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path: root/llvm/lib/CodeGen/VirtRegMap.cpp
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2025-08-15[VirtRegMap] Use TRI member variable. NFCCraig Topper1-1/+1
2025-07-14[CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (#148107)Vikram Hegde1-0/+2
same as https://github.com/llvm/llvm-project/pull/138660, Co-authored-by : Oke, Akshat <[Akshat.Oke@amd.com](mailto:Akshat.Oke@amd.com)>
2025-05-22[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties ↵users/pcc/spr/main.elf-add-branch-to-branch-optimizationRahul Joshi1-2/+1
(#140002) Add per-property has<Prop>/set<Prop>/reset<Prop> functions to MachineFunctionProperties.
2025-04-30[CodeGen] Remove unused variable 'ID' (NFC)Jie Fu1-1/+0
/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp:225:15: error: unused variable 'ID' [-Werror,-Wunused-variable] static char ID; ^ 1 error generated.
2025-04-30[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)Akshat Oke1-16/+69
2025-02-26RegAlloc: Use new approach to handling failed allocations (#128469)Matt Arsenault1-16/+3
This fixes an assert after allocation failure. Rather than collecting failed virtual registers and hacking on the uses after the fact, directly hack on the uses and rewrite the registers to the dummy assignment immediately. Previously we were bypassing LiveRegMatrix and directly assigning in the VirtRegMap. This resulted in inconsistencies where illegal overlapping assignments were missing. Rather than try to hack in some system to manage these in LiveRegMatrix (i.e. hacking around cases with invalid iterators), avoid this by directly using the physreg. This should also allow removal of special casing in virtregrewriter for failed allocations.
2025-02-26VirtRegRewriter: Fix verifier errors after regalloc failures (#128280)Matt Arsenault1-4/+12
2025-01-18[CodeGen] Use MCRegister instead of MCPhysReg in VirtRegMap. NFCCraig Topper1-4/+4
The callers of these methods already use MCRegister.
2025-01-14[CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)Jay Foad1-3/+3
2024-12-16RegAlloc: Do not fatal error if there are no registers in the alloc order ↵Matt Arsenault1-2/+7
(#119640) Try to use DiagnosticInfo if every register in the class is reserved by forcing assignment to a reserved register. Also reduces the number of redundant errors emitted, particularly with fast. This is still broken in the case of undef uses. There are additional complications in greedy and fast, so leave it for a separate fix.
2024-12-06[CodeGen][PM] Initialize analyses with isAnalysis=true (#118779)Akshat Oke1-1/+1
Analyses should be marked as analyses. Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.
2024-12-06[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)Akshat Oke1-3/+3
2024-12-04[CodeGen][NewPM] Port LiveDebugVariables to NPM (#115468)Akshat Oke1-4/+4
The existing analysis was already a pimpl wrapper. I have extracted legacy pass logic to a LDVImpl wrapper named `LiveDebugVariables` which is the analysis::Result now. This controls whether to activate the LDV (depending on `-live-debug-variables` and DIsubprogram) itself. The legacy and new analysis only construct the LiveDebugVariables. VirtRegRewriter will test this.
2024-10-28VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)Matt Arsenault1-0/+68
If an undef subregister def is live into another block, we need to maintain a physreg def to track the liveness of those lanes. This would manifest a verifier error after branch folding, when the cloned tail block use no longer had a def. We need to detect interference with other assigned intervals to avoid clobbering the undef lanes defined in other intervals, since the undef def didn't count as interference. This is pretty ugly and adds a new dependency on LiveRegMatrix, keeping it live for one more pass. It also adds a lot of implicit operand spam (we really should have a better representation for this). There is a missing verifier check for this situation. Added an xfailed test that demonstrates this. We may also be able to revert the changes in 47d3cbcf842a036c20c3f1c74255cdfc213f41c2. It might be better to insert an IMPLICIT_DEF before the instruction rather than using the implicit-def operand. Fixes #98474
2024-10-22[NewPM][CodeGen] Port VirtRegMap to NPM (#109936)Akshat Oke1-7/+23
2024-09-15[VirtRegMap] Store MCRegister in Virt2PhysMap. (#108775)Craig Topper1-5/+5
Remove NO_PHYS_REG in favor of MCRegister() and converting MCRegister to bool.
2024-09-15[VirtRegMap] Remove unnecessary calls to Register::id() accessing IndexMaps.Craig Topper1-6/+6
VirtReg2IndexFunctor already takes a Register.
2024-07-10[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)paperchalice1-4/+4
- Add `LiveIntervalsAnalysis`. - Add `LiveIntervalsPrinterPass`. - Use `LiveIntervalsWrapperPass` in legacy pass manager. - Use `std::unique_ptr` instead of raw pointer for `LICalc`, so destructor and default move constructor can handle it correctly. This would be the last analysis required by `PHIElimination`.
2024-07-09[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)paperchalice1-4/+4
- Add `SlotIndexesAnalysis`. - Add `SlotIndexesPrinterPass`. - Use `SlotIndexesWrapperPass` in legacy pass.
2024-04-15[NFC][LLVM][CodeGen] Move LiveDebugVariables.h into ↵Piyou Chen1-1/+1
llvm/include/llvm/CodeGen (#88374) This patch make `LiveDebugVariables` can be used by passes outside of `lib/CodeGen`. If we run a pass that occurs between the split register allocation pass without preserving this pass, it will be freed and recomputed until it encounters the next pass that needs LiveDebugVariables. However, `LiveDebugVariables` will raise an assertion due to the pass being freed without emitting a debug value. This is reason we need `LiveDebugVariables` to be available for passes outside of lib/Codegen.
2023-10-11[SlotIndexes] Use upper/lower bound terminology for MBB searches. NFC. (#68802)Jay Foad1-2/+2
Rename advanceMBBIndex and findMBBIndex to getMBBLowerBound and add getMBBUpperBound. The motivations are: - Make it clear what kind of search is being done, using names inspired by std::upper/lower_bound. - Simplify getMBBFromIndex which really wants an upper bound search and previously had to work hard to get the result it wanted from a lower bound search.
2023-10-11[VirtRegMap] Simplify condition after #65729Jay Foad1-1/+1
2023-10-11Clean up strange uses of getAnalysisIfAvailable (#65729)Jay Foad1-1/+1
After a pass calls addRequired<X>() it is strange to call getAnalysisIfAvailable<X>() because analysis X should always be available. Use getAnalysis<X>() instead.
2023-08-15Fix typos in commentsJay Foad1-1/+1
2023-06-16[MC] Add MCRegisterInfo::regunits for iteration over register unitsSergei Barannikov1-5/+4
Reviewed By: foad Differential Revision: https://reviews.llvm.org/D152098
2023-04-17Fix uninitialized pointer members in CodeGenAkshay Khadse1-8/+8
This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D148303
2023-03-22[CodeGen] Fix type of MachineRegisterInfo::RegAllocHints. NFC.Jay Foad1-3/+3
The first member of the pair should be unsigned instead of Register because it is the hint type, 0 for simple (target independent) hints and other values for target dependent hints. Differential Revision: https://reviews.llvm.org/D146646
2023-01-05Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ partserge-sans-paille1-1/+1
Use deduction guides instead of helper functions. The only non-automatic changes have been: 1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*)) 2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase. 3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated. 4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that). Per reviewers' comment, some useless makeArrayRef have been removed in the process. This is a follow-up to https://reviews.llvm.org/D140896 that introduced the deduction guides. Differential Revision: https://reviews.llvm.org/D140955
2022-12-07[NFC] Use Register instead of unsigned for variables that receive a Register ↵Gregory Alfonso1-2/+2
object Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D139451
2021-11-11[CodeGen] Use MachineInstr::operands (NFC)Kazu Hirata1-5/+1
2021-11-08[llvm] Use make_early_inc_range (NFC)Kazu Hirata1-14/+11
2021-06-11[CodeGen][regalloc] Don't align stack slots if the stack can't be realignedTomas Matheson1-0/+7
Register allocation may spill virtual registers to the stack, which can increase alignment requirements of the stack frame. If the the function did not require stack realignment before register allocation, the registers required to do so may not be reserved/available. This results in a stack frame that requires realignment but can not be realigned. Instead, only increase the alignment of the stack if we are still able to realign. The register SpillAlignment will be ignored if we can't realign, and the backend will be responsible for emitting the correct unaligned loads and stores. This seems to be the assumed behaviour already, e.g. ARMBaseInstrInfo::storeRegToStackSlot and X86InstrInfo::storeRegToStackSlot are both `canRealignStack` aware. Differential Revision: https://reviews.llvm.org/D103602
2021-05-27VirtRegMap: Preserve LiveDebugVariablesMatt Arsenault1-3/+12
This avoids recomputing it between regalloc runs when allocation is split, and also avoids a debug info test regression.
2021-04-29VirtRegMap: Support partially allocated virtual registersMatt Arsenault1-7/+40
Don't assert if there are unassigned virtual registers. Maintain LiveIntervals by removing the RegUnits for allocated registers, since they should not longer be necessary. One part I find somewhat questionable is the special handling necessary for handleIdentityCopy. The LiveIntervals for the relevant regunits needs to be removed.
2021-04-29VirtRegMap: Add pass option to not clear virt regsMatt Arsenault1-7/+20
In a future change it will be possible to run register allocation with a specific set of register classes, so some of the remaining virtual registers will still be meaningful.
2021-02-26[NFC] Const-ed 2 APIs in VirtRegMapMircea Trofin1-2/+2
2020-12-10[X86] AMX programming model.Luo, Yuanke1-0/+1
This patch implements amx programming model that discussed in llvm-dev (http://lists.llvm.org/pipermail/llvm-dev/2020-August/144302.html). Thank Hal for the good suggestion in the RA. The fast RA is not in the patch yet. This patch implemeted 7 components. 1. The c interface to end user. 2. The AMX intrinsics in LLVM IR. 3. Transform load/store <256 x i32> to AMX intrinsics or split the type into two <128 x i32>. 4. The Lowering from AMX intrinsics to AMX pseudo instruction. 5. Insert psuedo ldtilecfg and build the def-use between ldtilecfg to amx intruction. 6. The register allocation for tile register. 7. Morph AMX pseudo instruction to AMX real instruction. Change-Id: I935e1080916ffcb72af54c2c83faa8b2e97d5cb0 Differential Revision: https://reviews.llvm.org/D87981
2020-11-02[NFC][regalloc] Use MCRegister appropriatelyMircea Trofin1-3/+3
Differential Revision: https://reviews.llvm.org/D90506
2020-10-08[NFC][MC] MCRegister API typing.Mircea Trofin1-1/+1
Mostly LiveIntervals, with their effects (users). Differential Revision: https://reviews.llvm.org/D89018
2020-10-06Fix reordering of instructions during VirtRegRewriter unbundlingCarl Ritson1-1/+1
When unbundling COPY bundles in VirtRegRewriter the start of the bundle is not correctly referenced in the unbundling loop. The effect of this is that unbundled instructions are sometimes inserted out-of-order, particular in cases where multiple reordering have been applied to avoid clobbering dependencies. The resulting instruction sequence clobbers dependencies. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D88821
2020-08-10Unbundle KILL bundles in VirtRegRewriterStanislav Mekhanoshin1-3/+3
SplitKit forms invalid COPY subreg bundles without a leading BUNDLE instruction. That manifests itself in post-RA scheduler counting instruction and asserting on "Instruction count mismatch". The bundle shall be undone by VirtRegRewriter::expandCopyBundle(), but it does not because VirtRegRewriter::handleIdentityCopy() can turn COPY bundle into a KILL bundle. Process KILLs as well. Differential Revision: https://reviews.llvm.org/D85484
2020-04-02[Alignment][NFC] Use more Align versions of various functionsGuillaume Chatelet1-2/+2
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, arsenm, sdardis, jvesely, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77291
2019-08-13Eliminate implicit Register->unsigned conversions in VirtRegMap. NFCDaniel Sanders1-32/+31
Summary: This was mostly an experiment to assess the feasibility of completely eliminating a problematic implicit conversion case in D61321 in advance of landing that* but it also happens to align with the goal of propagating the use of Register/MCRegister instead of unsigned so I believe it makes sense to commit it. The overall process for eliminating the implicit conversions from Register/MCRegister -> unsigned was to: 1. Add an explicit conversion to support genuinely required conversions to unsigned. For example, using them as an index for IndexedMap. Sadly it's not possible to have an explicit and implicit conversion to the same type and only deprecate the implicit one so I called the explicit conversion get(). 2. Temporarily annotate the implicit conversion to unsigned with LLVM_ATTRIBUTE_DEPRECATED to make them visible 3. Eliminate implicit conversions by propagating Register/MCRegister/ explicit-conversions appropriately 4. Remove the deprecation added in 2. * My conclusion is that it isn't feasible as there's too much code to update in one go. Depends on D65678 Reviewers: arsenm Subscribers: MatzeB, wdng, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65685 llvm-svn: 368643
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders1-11/+11
llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-05-20RegAlloc: Fix verifier error with undef identity copiesMatt Arsenault1-1/+1
The code did not match the example in the comment, and was checking the undef flag on the copy dest instead of source. The existing tests were only hitting the > 2 operands case. llvm-svn: 361156
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-08-15[RegAlloc] Check that subreg liveness tracking applies to given virtual regKrzysztof Parzyszek1-1/+1
Subregister liveness applies selectively to register classes with certain properties. Make sure that when it's enabled, it applies to a given virtual register (in virtual register rewriter). llvm-svn: 339784
2018-06-14Re-apply "[VirtRegRewriter] Avoid clobbering registers when expanding copy ↵Justin Bogner1-7/+46
bundles" This is r334750 (which was reverted in r334754) with a fix for an uninitialized variable that was caught by msan. Original commit message: > If a copy bundle happens to involve overlapping registers, we can end > up with emitting the copies in an order that ends up clobbering some > of the subregisters. Since instructions in the copy bundle > semantically happen at the same time, this is incorrect and we need to > make sure we order the copies such that this doesn't happen. llvm-svn: 334756
2018-06-14Revert "[VirtRegRewriter] Avoid clobbering registers when expanding copy ↵Justin Bogner1-46/+7
bundles" There's an msan failure: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19549 This reverts r334750. llvm-svn: 334754
2018-06-14[VirtRegRewriter] Avoid clobbering registers when expanding copy bundlesJustin Bogner1-7/+46
If a copy bundle happens to involve overlapping registers, we can end up with emitting the copies in an order that ends up clobbering some of the subregisters. Since instructions in the copy bundle semantically happen at the same time, this is incorrect and we need to make sure we order the copies such that this doesn't happen. Differential Revision: https://reviews.llvm.org/D48154 llvm-svn: 334750
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