aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2019-08-28[FPEnv] Add fptosi and fptoui constrained intrinsics.Kevin P. Neal1-9/+39
2019-08-28[TargetLowering] Add buildLegalVectorShuffle facility to help build legal shu...Amaury Sechet1-5/+24
2019-08-23[SelectionDAG][X86] Enable iX SimplifyDemandedBits to vXi1 SimplifyDemandedVe...Craig Topper1-3/+1
2019-08-22[TargetLowering] Remove optional arguments passing to makeLibCallShiva Chen1-20/+18
2019-08-19[TargetLowering] x s% C == 0 fold: vector divisor with INT_MIN handlingRoman Lebedev1-13/+66
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-1/+1
2019-08-15Remove BitVector.h include. NFCI.Simon Pilgrim1-1/+0
2019-08-13[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)Roman Lebedev1-5/+221
2019-08-13[TargetLowering][NFC] prepareUREMEqFold(): fixup commentRoman Lebedev1-1/+1
2019-08-13Revert r368276 "[TargetLowering] SimplifyDemandedBits - call SimplifyMultiple...Hans Wennborg1-11/+0
2019-08-12[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim1-0/+5
2019-08-08[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim1-0/+11
2019-08-07[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim1-4/+19
2019-08-06[GISel]: Add GISelKnownBits analysisAditya Nandakumar1-0/+6
2019-08-06[TargetLowering] SimplifyMultipleUseDemandedBits - return UNDEF for undemande...Simon Pilgrim1-1/+10
2019-08-04[TargetLowering][X86] Teach SimplifyDemandedVectorElts to replace the base ve...Craig Topper1-0/+9
2019-08-03Emit diagnostic if an inline asm constraint requires an immediateBill Wendling1-7/+11
2019-08-02[TargetLowering] SimplifyMultipleUseDemandedBits - don't assume INSERT_VECTOR...Simon Pilgrim1-1/+1
2019-08-01[TargetLowering] SimplifyMultipleUseDemandedBits - Add ISD::INSERT_VECTOR_ELT...Simon Pilgrim1-0/+10
2019-07-27[TargetLowering] SimplifyMultipleUseDemandedBits - add BITCAST pass through s...Simon Pilgrim1-2/+59
2019-07-27[SelectionDAG] Check for any recursion depth greater than or equal to limit i...Simon Pilgrim1-2/+2
2019-07-27[TargetLowering] Add depth limit to SimplifyMultipleUseDemandedBitsSimon Pilgrim1-0/+3
2019-07-26Revert r367091, it caused PR42777.Nico Weber1-59/+2
2019-07-26[TargetLowering] SimplifyMultipleUseDemandedBits - add SIGN_EXTEND_INREG supp...Simon Pilgrim1-0/+7
2019-07-26[TargetLowering] SimplifyMultipleUseDemandedBits - add BITCAST pass through s...Simon Pilgrim1-2/+59
2019-07-24[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 foldRoman Lebedev1-0/+79
2019-07-24[SDAG] convert (sub x, 1) to (add x, -1) in ctpop expansion; NFCSanjay Patel1-3/+3
2019-07-23[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.Simon Pilgrim1-0/+23
2019-07-23[TargetLowering] Add SimplifyMultipleUseDemandedBitsSimon Pilgrim1-1/+128
2019-07-20[Codegen][SelectionDAG] X u% C == 0 fold: non-splat vector improvementsRoman Lebedev1-35/+132
2019-07-10[SDAG] commute setcc operands to match a subtractSanjay Patel1-0/+11
2019-07-10[TargetLowering] support BlockAddress as "i" inline asm constraintNick Desaulniers1-0/+7
2019-07-08[TargetLowering] SimplifyDemandedBits - just call computeKnownBits for BUILD_...Simon Pilgrim1-23/+3
2019-07-02[NFC][TargetLowering] Some preparatory cleanups around 'prepareUREMEqFold()' ...Roman Lebedev1-17/+18
2019-07-01[SelectionDAG] Do minnum->minimum at legalization time instead of building timeBenjamin Kramer1-0/+11
2019-06-27[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)Roman Lebedev1-0/+109
2019-06-27Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM cas...Roman Lebedev1-107/+0
2019-06-27[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)Roman Lebedev1-0/+107
2019-06-27[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.Simon Pilgrim1-0/+18
2019-06-27[TargetLowering] SimplifyDemandedBits - use DemandedElts to better identify p...Simon Pilgrim1-11/+21
2019-06-25[SDAG] expand ctpop != 1Sanjay Patel1-11/+11
2019-06-25[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG supportSimon Pilgrim1-2/+18
2019-06-25[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_...Simon Pilgrim1-6/+4
2019-06-25[SDAG] improve expansion of ctpop+setccSanjay Patel1-11/+14
2019-06-25[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EX...Simon Pilgrim1-6/+6
2019-06-25[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ...Simon Pilgrim1-6/+15
2019-06-25[Codegen] TargetLowering::SimplifySetCC(): omit urem when possibleRoman Lebedev1-0/+12
2019-06-25Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."Craig Topper1-26/+20
2019-06-19[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG supportSimon Pilgrim1-11/+12
2019-06-19[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_...Simon Pilgrim1-3/+4
generated by cgit v1.1 at 2025-10-09 02:20:59 +0000