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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-27 14:25:54 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-27 14:25:54 +0000 |
commit | 83e1a1e79b51f54700b304a230d10df0b5c8d8e6 (patch) | |
tree | 9b8470823757d2e237537cfb90a9e7392fab56fb /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
parent | d44cb7a65673796927cbb651685044d7e3ed0691 (diff) | |
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[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
llvm-svn: 364548
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 50cd8cd..0acac2b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2232,6 +2232,24 @@ bool TargetLowering::SimplifyDemandedVectorElts( KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS); break; } + case ISD::SHL: + case ISD::SRL: + case ISD::SRA: + case ISD::ROTL: + case ISD::ROTR: { + APInt UndefRHS, ZeroRHS; + if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS, + ZeroRHS, TLO, Depth + 1)) + return true; + APInt UndefLHS, ZeroLHS; + if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS, + ZeroLHS, TLO, Depth + 1)) + return true; + + KnownZero = ZeroLHS; + KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop? + break; + } case ISD::MUL: case ISD::AND: { APInt SrcUndef, SrcZero; |