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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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2018-03-29[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper1-1/+1
2018-03-23Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie1-1/+1
2018-03-23Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie1-1/+1
2018-02-20[VectorLegalizer] Fix uint64_t typo in ExpandUINT_TO_FLOAT (PR36391)Simon Pilgrim1-1/+1
2018-01-20[SelectionDAG] Fix codegen of vector stores with non byte-sized elements.Jonas Paulsson1-1/+0
2018-01-11[VectorLegalizer] Remove broken code in ExpandStore.Jonas Paulsson1-28/+0
2018-01-01[SelectionDAG][X86][AArch64] Require targets to specify the promotion type wh...Craig Topper1-37/+21
2017-12-28[SelectionDAG] Add some debug print messages to LegalizeVectorOps.Craig Topper1-2/+15
2017-11-29[SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to...Craig Topper1-3/+11
2017-11-29DAG: Add nuw when splitting loads and storesMatt Arsenault1-4/+2
2017-11-28[X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of le...Craig Topper1-2/+2
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-1/+1
2017-09-21[CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What Yo...Eugene Zelenko1-9/+27
2017-06-03Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova1-0/+1
2017-02-15DAG: Do not scalarize fsub if fneg is legalMatt Arsenault1-0/+15
2017-01-30Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where p...Simon Pilgrim1-7/+3
2016-12-08[SelectionDAG] Add expansion and promotion of [US]MUL_LOHINicolai Haehnle1-0/+2
2016-11-21[VectorLegalizer] Remove EVT::getSizeInBits code duplications. NFCI.Simon Pilgrim1-8/+6
2016-11-08[VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim1-6/+50
2016-09-14getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel1-2/+2
2016-09-14getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel1-1/+1
2016-09-14getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel1-3/+3
2016-08-17Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner1-1/+1
2016-07-15[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore,...Justin Lebar1-19/+14
2016-07-01[CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a poin...Craig Topper1-3/+2
2016-05-12[SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and...Simon Pilgrim1-5/+32
2016-05-04[SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED)Simon Pilgrim1-2/+2
2016-05-04Revert r268504Simon Pilgrim1-2/+2
2016-05-04[SelectionDAG] BITREVERSE vector legalization of bit operationsSimon Pilgrim1-2/+2
2016-04-21[SelectionDAG] Teach LegalizeVectorOps to directly Expand CTTZ_ZERO_UNDEF/CTL...Craig Topper1-3/+5
2016-03-30LegalizeDAG: Don't replace vector store with integer if not legalMatt Arsenault1-41/+27
2016-03-30LegalizeDAG: Don't replace vector load with integer unless legalMatt Arsenault1-28/+21
2016-03-10[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_...Simon Pilgrim1-1/+1
2016-02-15[CodeGen] Document and use getConstant's splat-building feature. NFC.Ahmed Bougacha1-4/+1
2016-02-09[CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha1-2/+1
2015-12-27[SelectionDAG] Teach LegalizeVectorOps to not unroll CTLZ_ZERO_UNDEF and CTTZ...Craig Topper1-0/+14
2015-12-14AMDGPU: Use generic bitreverse intrinsicMatt Arsenault1-1/+24
2015-12-11Revert r248483, r242546, r242545, and r242409 - absdiff intrinsicsHal Finkel1-34/+0
2015-12-07AVX-512: Fixed masked load / store instruction selection for KNL.Elena Demikhovsky1-1/+4
2015-11-25Fix some places where we were assuming that memory type had been legalizedEric Christopher1-1/+1
2015-10-27Do not use "else" when both branches return (NFC)Mehdi Amini1-2/+1
2015-10-20Two switch blocks in VectorLegalizer::LegalizeOp already have aArtyom Skrobov1-0/+1
2015-10-20Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into DA...Artyom Skrobov1-0/+2
2015-10-13SelectionDAG: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith1-1/+1
2015-09-24Codegen: Fix llvm.*absdiff semantic.Mohammad Shahid1-16/+22
2015-09-16propagate fast-math-flags on DAG nodesSanjay Patel1-2/+4
2015-08-11Add new ISD nodes: ISD::FMINNAN and ISD::FMAXNANJames Molloy1-0/+2
2015-07-16[Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute dif...James Molloy1-0/+28
2015-07-09Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini1-5/+8
2015-07-09Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini1-8/+12