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| author | Sanjay Patel <spatel@rotateright.com> | 2016-09-14 15:21:00 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-09-14 15:21:00 +0000 |
| commit | bd6fca14190e9693933d96361a9fef5a19fc0981 (patch) | |
| tree | 941a026af5476382aa96b7b6ace5534f59d4fb21 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | fa5f767a38be412f75e4b1426356263c65291ec6 (diff) | |
| download | llvm-bd6fca14190e9693933d96361a9fef5a19fc0981.zip llvm-bd6fca14190e9693933d96361a9fef5a19fc0981.tar.gz llvm-bd6fca14190e9693933d96361a9fef5a19fc0981.tar.bz2 | |
getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI
llvm-svn: 281489
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 709c2ce..49f830b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -770,8 +770,8 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) { SDLoc DL(Op); EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT(); - unsigned BW = VT.getScalarType().getSizeInBits(); - unsigned OrigBW = OrigTy.getScalarType().getSizeInBits(); + unsigned BW = VT.getScalarSizeInBits(); + unsigned OrigBW = OrigTy.getScalarSizeInBits(); SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); Op = Op.getOperand(0); @@ -961,7 +961,7 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); SDValue AllOnes = DAG.getConstant( - APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT); + APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT); SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); |