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2025-09-12CodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault1-2/+1
This is a low level utility to parse the MCInstrInfo and should not depend on the state of the function.
2025-08-15[CodeGen] Give ArgListEntry a proper constructor (NFC) (#153817)Nikita Popov1-10/+3
This ensures that the required fields are set, and also makes the construction more convenient.
2025-08-13[CodeGen] Remove default ctors for InputArg and OutputArg (#153205)Nikita Popov1-8/+7
These make it easy to forget to initialize some members, like the newly added OrigTy. Force these to always go through the ctor instead.
2025-08-12[win][arm64ec] Fix duplicate errors with the dontcall attribute (#152810)Daniel Paoliello1-2/+5
Since the `dontcall-*` attributes are checked both by `FastISel`/`GlobalISel` and `SelectionDAGBuilder`, and both `FastISel` and `GlobalISel` bail for calls on Arm64EC for AFTER doing the check, we ended up emitting duplicate copies of this error. This change moves the checking for `dontcall-*` in `FastISel` and `GlobalISel` to after it has been successfully lowered.
2025-06-18[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel ↵Orlando Cazalet-Hyams1-45/+0
(#144702)
2025-06-11Reapply 76197ea6f91f after removing an assertionJeremy Morse1-3/+0
Specifically this is the assertion in BasicBlock.cpp. Now that we're not examining or setting that flag consistently (because it'll be deleted in about an hour) there's no need to keep this assertion. Original commit title: [DebugInfo][RemoveDIs] Remove some debug intrinsic-only codepaths (#143451)
2025-06-11Revert "[DebugInfo][RemoveDIs] Remove some debug intrinsic-only codepaths ↵Jeremy Morse1-0/+3
(#143451)" This reverts commit c71a2e688828ab3ede4fb54168a674ff68396f61. /me squints -- this is hitting an assertion I thought had been deleted, will revert and investigate for a bit.
2025-06-11[DebugInfo][RemoveDIs] Remove some debug intrinsic-only codepaths (#143451)Jeremy Morse1-3/+0
These are opportunistic deletions as more places that make use of the IsNewDbgInfoFormat flag are removed. It should (TM)(R) all be dead code now that `IsNewDbgInfoFormat` should be true everywhere. FastISel: we don't need to do debug-aware instruction counting any more, because there are no debug instructions, Autoupgrade: you can no-longer avoid autoupgrading of intrinsics to records DIBuilder: Delete the code for creating debug intrinsics (!) LoopUtils: No need to handle debug instructions, they don't exist
2025-05-10[IR] Teach getAsmString to return StringRef (NFC) (#139406)Kazu Hirata1-1/+1
This is for consistency with #139401.
2025-03-20[SelectionDAG] Not issue TRAP node if naked function (#132147)yonghong-song1-10/+5
In [1], Nikita Popov suggested that during lowering 'unreachable' insn should not generate extra code for naked functions, and this applies to all architectures. Note that for naked functions, 'unreachable' insn is necessary in IR since the basic block needs a terminator to end. This patch checked whether a function is naked function or not. If it is a naked function, 'unreachable' insn will not generate ISD::TRAP. [1] https://github.com/llvm/llvm-project/pull/131731 Co-authored-by: Yonghong Song <yonghong.song@linux.dev>
2025-03-05[FastISel] Use Register. NFCCraig Topper1-15/+16
This focuses on the common interfaces and tablegen. More changes are needed to individual targets.
2025-03-02[SelectionDAG] Use Register and MCRegister. NFCCraig Topper1-1/+1
Add operators to Register to supporting adding an offset to get another Register.
2025-03-02[FastISel] Use Register. NFCCraig Topper1-2/+3
2025-03-02[FastISel] Use Register. NFCCraig Topper1-18/+17
2025-02-20Revert "[CodeGen] Remove static member function Register::isVirtualRegister. ↵Christopher Di Bella1-1/+2
NFC (#127968)" This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
2025-02-20[CodeGen] Remove static member function Register::isVirtualRegister. NFC ↵Craig Topper1-2/+1
(#127968) Use nonstatic member instead. This requires explicit conversions, but many will go away as we continue converting unsigned to Register. In a few places where it was simple, I changed unsigned to Register.
2025-01-20[Mips] Fix compiler crash when returning fp128 after calling a functi… ↵yingopq1-1/+1
(#117525) …on returning { i8, i128 } Fixes https://github.com/llvm/llvm-project/issues/96432.
2024-12-16[NFC] Remove some unnecessary semicolonsDavid Green1-1/+1
All inside LLVM_DEBUG, some of which have been cleaned up by adding block scopes to allow them to format more nicely.
2024-12-09[TargetLowering] Return Align from getByValTypeAlignment (NFC) (#119233)Sergei Barannikov1-1/+1
2024-12-03[FastISel] Support unreachable with NoTrapAfterNoReturn (#118296)Nikita Popov1-4/+12
Currently FastISel triggers a fallback if there is an unreachable terminator and the TrapUnreachable option is enabled (the ISD::TRAP selection does not actually work). Add handling for NoTrapAfterNoReturn, in which case we don't actually need to emit a trap. The test is just there to make sure there is no FastISel fallback (which is why I'm not testing the case without noreturn). We have other tests that check the actual unreachable codegen variations.
2024-11-26[SelectionDAG] Add generic implementation for @llvm.expect.with.probability ↵antangelo1-1/+2
when optimizations are disabled (#117459) Handle \@llvm.expect.with.probability in SelectionDAGBuilder, FastISel, and IntrinsicLowering in the same way \@llvm.expect is handled, where the value is passed through as-is. This can be reached if the intrinsic is used without optimizations, where it would otherwise be properly transformed out. Fixes #115411 for SelectionDAG. A similar patch is likely needed for GlobalISel.
2024-11-03[SelectionDAG] Remove unused includes (NFC) (#114697)Kazu Hirata1-1/+0
Identified with misc-include-cleaner.
2024-09-30FastISel: Fix incorrectly using getPointerTy (#110465)Matt Arsenault1-4/+4
This was using the default address space instead of the correct one. Fixes #56055
2024-08-29[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)Stephen Tozer1-0/+3
This patch is part of a set of patches that add an `-fextend-lifetimes` flag to clang, which extends the lifetimes of local variables and parameters for improved debuggability. In addition to that flag, the patch series adds a pragma to selectively disable `-fextend-lifetimes`, and an `-fextend-this-ptr` flag which functions as `-fextend-lifetimes` for this pointers only. All changes and tests in these patches were written by Wolfgang Pieb (@wolfy1961), while Stephen Tozer (@SLTozer) has handled review and merging. The extend lifetimes flag is intended to eventually be set on by `-Og`, as discussed in the RFC here: https://discourse.llvm.org/t/rfc-redefine-og-o1-and-add-a-new-level-of-og/72850 This patch implements a new intrinsic instruction in LLVM, `llvm.fake.use` in IR and `FAKE_USE` in MIR, that takes a single operand and has no effect other than "using" its operand, to ensure that its operand remains live until after the fake use. This patch does not emit fake uses anywhere; the next patch in this sequence causes them to be emitted from the clang frontend, such that for each variable (or this) a fake.use operand is inserted at the end of that variable's scope, using that variable's value. This patch covers everything post-frontend, which is largely just the basic plumbing for a new intrinsic/instruction, along with a few steps to preserve the fake uses through optimizations (such as moving them ahead of a tail call or translating them through SROA). Co-authored-by: Stephen Tozer <stephen.tozer@sony.com>
2024-08-04[CodeGen][NFC] Add wrapper method for MBBMap (#101893)Alexis Engelke1-3/+3
This is a preparation for changing the data structure of MBBMap.
2024-08-02[FastISel] Don't use sizeWithoutDebug() for debug records (#101648)Alexis Engelke1-2/+7
sizeWithoutDebug() iterates over the entire block, but all we do is to check whether the number is not equal to one. In times of debug records, simply check whether the first and last instructions are equal.
2024-07-26FastISel: Do not check for module debug info (#100353)Matt Arsenault1-16/+0
I don't see the point of this check and SelectionDAG does not perform it. In the normal usecase, if there's no debug info the debug intrinsics would not be there in the first place.
2024-04-25LLVM_FALLTHROUGH => [[fallthrough]]. NFCFangrui Song1-1/+1
2024-03-31[CodeGen] llvm.allow.{runtime,ubsan}.check() in FastISelVitaly Buka1-2/+7
Follow up to #86049. clang-armv8-quick build bot can trigger this branch.
2024-03-31[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)Vitaly Buka1-0/+4
RFC: https://discourse.llvm.org/t/rfc-add-llvm-experimental-hot-intrinsic-or-llvm-hot/77641
2024-03-26[Intrinsics] Make `patchpoint.i64` generic on its return type (#85911)Il-Capitano1-8/+17
Currently patchpoints can only have two result types, `void` and `i64`. This limits the result to general purpose registers. This patch makes `patchpoint.i64` an overloadable intrinsic, allowing result values that can fit in a single register (e.g. integers, pointers, floats).
2024-03-20[RemoveDIs][NFC] Rename DPLabel->DbgLabelRecord (#85918)Stephen Tozer1-5/+5
This patch renames DPLabel to DbgLabelRecord, in accordance with the ongoing DbgRecord rename. This rename was fairly trivial, since DPLabel isn't as widely used as DPValue and has no real conflicts in either its full or abbreviated name. As usual, the entire replacement was done automatically, with `s/DPLabel/DbgLabelRecord/` and `s/DPL/DLR/`.
2024-03-19[RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)Stephen Tozer1-12/+12
This is the major rename patch that prior patches have built towards. The DPValue class is being renamed to DbgVariableRecord, which reflects the updated terminology for the "final" implementation of the RemoveDI feature. This is a pure string substitution + clang-format patch. The only manual component of this patch was determining where to perform these string substitutions: `DPValue` and `DPV` are almost exclusively used for DbgRecords, *except* for: - llvm/lib/target, where 'DP' is used to mean double-precision, and so appears as part of .td files and in variable names. NB: There is a single existing use of `DPValue` here that refers to debug info, which I've manually updated. - llvm/tools/gold, where 'LDPV' is used as a prefix for symbol visibility enums. Outside of these places, I've applied several basic string substitutions, with the intent that they only affect DbgRecord-related identifiers; I've checked them as I went through to verify this, with reasonable confidence that there are no unintended changes that slipped through the cracks. The substitutions applied are all case-sensitive, and are applied in the order shown: ``` DPValue -> DbgVariableRecord DPVal -> DbgVarRec DPV -> DVR ``` Following the previous rename patches, it should be the case that there are no instances of any of these strings that are meant to refer to the general case of DbgRecords, or anything other than the DPValue class. The idea behind this patch is therefore that pure string substitution is correct in all cases as long as these assumptions hold.
2024-03-12[RemoveDIs][NFC] Rename common interface functions for DPValues->DbgRecords ↵Stephen Tozer1-2/+2
(#84793) As part of the effort to rename the DbgRecord classes, this patch renames the widely-used functions that operate on DbgRecords but refer to DbgValues or DPValues in their names to refer to DbgRecords instead; all such functions are defined in one of `BasicBlock.h`, `Instruction.h`, and `DebugProgramInstruction.h`. This patch explicitly does not change the names of any comments or variables, except for where they use the exact name of one of the renamed functions. The reason for this is reviewability; this patch can be trivially examined to determine that the only changes are direct string substitutions and any results from clang-format responding to the changed line lengths. Future patches will cover renaming variables and comments, and then renaming the classes themselves.
2024-02-23[RemoveDIs] Add DPLabels support [3a/3] (#82633)Orlando Cazalet-Hyams1-2/+15
Patch 2 of 3 to add llvm.dbg.label support to the RemoveDIs project. The patch stack adds the DPLabel class, which is the RemoveDIs llvm.dbg.label equivalent. 1. Add DbgRecord base class for DPValue and the not-yet-added DPLabel class. 2. Add the DPLabel class. -> 3. Add support to passes. The next patch, #82639, will enable conversion between dbg.labels and DPLabels. AssignemntTrackingAnalysis support could have gone two ways: 1. Have the analysis store a DPLabel representation in its results - SelectionDAGBuilder reads the analysis results and ignores all DbgRecord kinds. 2. Ignore DPLabels in the analysis - SelectionDAGBuilder reads the analysis results but still needs to iterate over DPLabels from the IR. I went with option 2 because it's less work and is no less correct than 1. It's worth noting that causes labels to sink to the bottom of packs of debug records. e.g., [value, label, value] becomes [value, value, label]. This shouldn't be a problem because labels and variable locations don't have an ordering requirement. The ordering between variable locations is maintained and the label movement is deterministic
2024-02-20[RemoveDIs][NFC] Introduce DbgRecord base class [1/3] (#78252)Orlando Cazalet-Hyams1-1/+3
Patch 1 of 3 to add llvm.dbg.label support to the RemoveDIs project. The patch stack adds a new base class -> 1. Add DbgRecord base class for DPValue and the not-yet-added DPLabel class. 2. Add the DPLabel class. 3. Enable dbg.label conversion and add support to passes. Patches 1 and 2 are NFC. In the near future we also will rename DPValue to DbgVariableRecord and DPLabel to DbgLabelRecord, at which point we'll overhaul the function names too. The name DPLabel keeps things consistent for now.
2024-02-08[DebugInfo] Handle dbg.assigns in FastISel (#80734)Jeremy Morse1-1/+9
There are some rare circumstances where dbg.assign intrinsics can reach FastISel. They are a more specialised kind of dbg.value intrinsic with more information about the originating alloca. They only occur during optimisation, but might reach FastISel through always_inlining an optimised function into an optnone function. This is a slight problem as it's not safe (for debug-info accuracy) to ignore any intrinsics, and for RemoveDIs (the intrinsic-replacement project) it causes a crash through an unhandled switch case. To get around this, we can just treat the dbg.assign as a dbg.value (it's an actual subclass) and use the variable location information from the dbg.value fields. This loses a small amount of debug-info about stack locations, but is more accurate than just ignoring the intrinsic. (This has popped up deep in an LTO build of a large codebase while testing RemoveDIs, I figured it'd be good to fix it for the intrinsic-form at the same time, just to demonstrate the correct behaviour).
2024-01-25[llvm] Move CodeGenTypes library to its own directory (#79444)Nico Weber1-1/+1
Finally addresses https://reviews.llvm.org/D148769#4311232 :) No behavior change.
2024-01-14[CodeGen] Use a range-based for loop (NFC)Kazu Hirata1-4/+1
2024-01-05[RemoveDIs] Handle DPValues in FastISel (#76952)Orlando Cazalet-Hyams1-135/+188
The change is fairly mechanical: 1. Factor code from `FastISel::selectIntrinsicCall`, which converts debug intrinsics into debug instructions, into functions (NFC). 2. Call those functions for DPValues attached to instructions too. The test updates look the same as other RemoveDIs changes: re-run the tests with `--try-experimental-debuginfo-iterators`, which checks the output is identical using the new debug info format (if it has been enabled in the cmake configuration). Depends on #76941 (otherwise some modified tests spuriously fail).
2024-01-04[IR] Fix GEP offset computations for vector GEPs (#75448)Jannik Silvanus1-4/+2
Vectors are always bit-packed and don't respect the elements' alignment requirements. This is different from arrays. This means offsets of vector GEPs need to be computed differently than offsets of array GEPs. This PR fixes many places that rely on an incorrect pattern that always relies on `DL.getTypeAllocSize(GTI.getIndexedType())`. We replace these by usages of `GTI.getSequentialElementStride(DL)`, which is a new helper function added in this PR. This changes behavior for GEPs into vectors with element types for which the (bit) size and alloc size is different. This includes two cases: * Types with a bit size that is not a multiple of a byte, e.g. i1. GEPs into such vectors are questionable to begin with, as some elements are not even addressable. * Overaligned types, e.g. i16 with 32-bit alignment. Existing tests are unaffected, but a miscompilation of a new test is fixed. --------- Co-authored-by: Nikita Popov <github@npopov.com>
2023-12-24[CodeGen] Use range-based for loops (NFC)Kazu Hirata1-2/+1
2023-10-02[FastISel][DebugInfo] Handle dbg.value targeting allocas (#67187)Felipe de Azevedo Piovezan1-0/+8
FastISel currently drops dbg.values targeting allocas. It may seem surprising that a simple case would fail to be lowered, but dbg.values targeting allocas are not common; we usually have dbg.declares doing that, and those are handled by the common code between FastISel and SelectionDAGISel. This patch addresses the issue by querying the static alloca map from FuncInfo. If we have a frame index for it, we create a DBG_VALUE intrinsic from it.
2023-06-23[XRay][AArch64] Suppport __xray_customevent/__xray_typedeventFangrui Song1-2/+2
`__xray_customevent` and `__xray_typedevent` are built-in functions in Clang. With -fxray-instrument, they are lowered to intrinsics llvm.xray.customevent and llvm.xray.typedevent, respectively. These intrinsics are then lowered to TargetOpcode::{PATCHABLE_EVENT_CALL,PATCHABLE_TYPED_EVENT_CALL}. The target is responsible for generating a code sequence that calls either `__xray_CustomEvent` (with 2 arguments) or `__xray_TypedEvent` (with 3 arguments). Before patching, the code sequence is prefixed by a branch instruction that skips the rest of the code sequence. After patching (compiler-rt/lib/xray/xray_AArch64.cpp), the branch instruction becomes a NOP and the function call will take effects. This patch implements the lowering process for {PATCHABLE_EVENT_CALL,PATCHABLE_TYPED_EVENT_CALL} and implements the runtime. ``` // Lowering of PATCHABLE_EVENT_CALL .Lxray_sled_N: b #24 stp x0, x1, [sp, #-16]! x0 = reg of op0 x1 = reg of op1 bl __xray_CustomEvent ldrp x0, x1, [sp], #16 ``` As a result, two updated tests in compiler-rt/test/xray/TestCases/Posix/ now pass on AArch64. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D153320
2023-05-26[FastISel] Implement translation of entry_value dbg.value intrinsicsFelipe de Azevedo Piovezan1-0/+18
For dbg.value intrinsics targeting an llvm::Argument address whose expression starts with an entry value, we lower this to a DEBUG_VALUE targeting the livein physical register corresponding to that Argument. Depends on D151332 Differential Revision: https://reviews.llvm.org/D151333
2023-05-26[FastISel][NFC] Remove repeated calls to get{Variable,Expr}Felipe de Azevedo Piovezan1-10/+11
This will make it easy to reuse these values in subsequent commits. Depends on D151331 Differential Revision: https://reviews.llvm.org/D151332
2023-05-26[FastISel][NFC] Refactor if/else chain into early returnsFelipe de Azevedo Piovezan1-19/+25
This will make it easier to add more cases in a subsequent commit and also better conforms to the coding guidelines. Depends on D151330 Differential Revision: https://reviews.llvm.org/D151331
2023-05-03[SelectionDAG][NFCI] Use common logic for identifying MMI varsFelipe de Azevedo Piovezan1-7/+3
After function argument lowering, but prior to instruction selection, dbg declares pointing to function arguments are lowered using special logic. Later, during instruction selection (both "fast" and regular ISel), this logic is "repeated" in order to identify which intrinsics have already been lowered. This is bad for two reasons: 1. The logic is not _really_ repeated, the code is different, which could lead to duplicate lowering of the intrinsic. 2. Even if the logic were repeated properly, this is still code duplication. This patch addresses these issues by storing all preprocessed dbg.declare intrinsics in a set inside FuncInfo; the set is queried upon instruction selection. Differential Revision: https://reviews.llvm.org/D149682
2023-05-03Restore CodeGen/MachineValueType.h from `Support`NAKAMURA Takumi1-1/+1
This is rework of; - rG13e77db2df94 (r328395; MVT) Since `LowLevelType.h` has been restored to `CodeGen`, `MachinveValueType.h` can be restored as well. Depends on D148767 Differential Revision: https://reviews.llvm.org/D149024
2023-03-13[DAG] Use ISD::isBitwiseLogicOp in AND/OR/XOR checks. NFCI.Simon Pilgrim1-2/+1
There's additional cases we can cleanup (mainly in target code), but this tries to cleanup generic code and PPC which had an equivalent helper.