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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-09-12 19:22:02 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-12 19:22:02 +0900 |
| commit | 7289f2cd0c371b2539faa628ec0eea58fa61892c (patch) | |
| tree | d5b7335a9d5f0f6dfceaf6791f4f0bcadca02142 /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | 83b48b13f3a70bf56053e92593270c519859cfd7 (diff) | |
| download | llvm-7289f2cd0c371b2539faa628ec0eea58fa61892c.zip llvm-7289f2cd0c371b2539faa628ec0eea58fa61892c.tar.gz llvm-7289f2cd0c371b2539faa628ec0eea58fa61892c.tar.bz2 | |
CodeGen: Remove MachineFunction argument from getRegClass (#158188)
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 9467ba1..851d445 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1964,8 +1964,7 @@ Register FastISel::createResultReg(const TargetRegisterClass *RC) { Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, unsigned OpNum) { if (Op.isVirtual()) { - const TargetRegisterClass *RegClass = - TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF); + const TargetRegisterClass *RegClass = TII.getRegClass(II, OpNum, &TRI); if (!MRI.constrainRegClass(Op, RegClass)) { // If it's not legal to COPY between the register classes, something // has gone very wrong before we got here. |