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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
AgeCommit message (Expand)AuthorFilesLines
2024-04-15[mi-sched] Suppress register pressure with i64. (#88256)laichunfeng1-2/+4
2024-04-02MachineScheduler: Simplify usage of TargetInstrInfoMatt Arsenault1-12/+4
2024-03-25[CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (#77138)Michael Maitland1-12/+101
2024-03-06[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)David Green1-6/+7
2024-02-27[CodeGen][MISched] Add misched post-regalloc bottom-up schedulingMichael Maitland1-33/+95
2024-02-27[CodeGen][MISched] dumpSched direction depends on field in DAG.Michael Maitland1-3/+21
2024-02-07[Sched] Add MacroFusion mutation if fusions are not empty (#72227)Wang Pengcheng1-2/+15
2024-01-25[llvm] Move CodeGenTypes library to its own directory (#79444)Nico Weber1-1/+1
2024-01-24[CodeGen][MISched] Rename instance of Cycle -> ReleaseAtCycleMichael Maitland1-1/+1
2024-01-24[CodeGen][MISched] Handle empty sized resource usage. (#75951)Michael Maitland1-1/+15
2024-01-17[CodeGen][MISched][NFC] Rename some instances of Cycle -> ReleaseAtCycleMichael Maitland1-3/+3
2024-01-16[MachineScheduler] Add option to control reordering for store/load clustering...Alex Bradbury1-11/+20
2023-12-11[CodeGen][MachineScheduler][NFC]Update some comments of scheduler (#74705)Ningning Shi(史宁宁)1-6/+6
2023-12-06[MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldCluste...Alex Bradbury1-5/+9
2023-09-01[llvm] Fix duplicate word typos. NFCFangrui Song1-1/+1
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland1-52/+61
2023-08-24Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"Michael Maitland1-61/+52
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland1-52/+61
2023-08-24Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"Michael Maitland1-61/+52
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland1-52/+61
2023-08-01[MISched] Do not erase resource booking history for subunits.Francesco Petrogalli1-10/+14
2023-06-28[MISched] Fix bug(s) in bottom-up scheduling.Francesco Petrogalli1-3/+3
2023-06-20[llc][MISched] Add `-misched-detail-resource-booking` to llc.Francesco Petrogalli1-1/+17
2023-06-20Revert "[llc][MISched] Add `-misched-detail-resource-booking` to llc."Francesco Petrogalli1-17/+1
2023-06-20[llc][MISched] Add `-misched-detail-resource-booking` to llc.Francesco Petrogalli1-1/+17
2023-06-13[MISched][scheduleDump] Use stable_sort to prevent test failures.Francesco Petrogalli1-14/+14
2023-06-12[MISched] Use StartAtCycle in trace dumps.Francesco Petrogalli1-14/+46
2023-06-09[CodeGen] Fix a warning in release buildsKazu Hirata1-2/+1
2023-06-09[MISched][rework] Introduce and use ResourceSegments.Francesco Petrogalli1-21/+166
2023-06-09Revert "[MISched] Introduce and use ResourceSegments."Francesco Petrogalli1-166/+21
2023-06-09[MISched] Introduce and use ResourceSegments.Francesco Petrogalli1-21/+166
2023-06-01[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.Jay Foad1-2/+2
2023-05-03Restore CodeGen/MachineValueType.h from `Support`NAKAMURA Takumi1-1/+1
2023-03-30[MachineScheduler] Rename postprocessDAG to postProcessDAG. NFCjacquesguan1-3/+3
2023-01-26[MISched] Dump the execution trace of the schedule.Francesco Petrogalli1-0/+160
2023-01-14MachineScheduler.cpp: Fixup D141707, suppress `MISchedDumpReservedCycles` con...NAKAMURA Takumi1-0/+2
2023-01-13[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFCCraig Topper1-8/+8
2023-01-13[CodeGen] Fix build failure due to missing declaration.Francesco Petrogalli1-0/+1
2023-01-13Recommit [SchedBoundary] Add dump method for resource usage.Francesco Petrogalli1-0/+27
2023-01-13Revert "[SchedBoundary] Add dump method for resource usage."Francesco Petrogalli1-27/+0
2023-01-13[SchedBoundary] Add dump method for resource usage.Francesco Petrogalli1-0/+27
2022-07-30[CodeGen] Fixed undeclared MISchedCutoff in case of NDEBUG and LLVM_ENABLE_AB...Dmitry Vassiliev1-1/+1
2022-07-17[CodeGen] Qualify auto variables in for loops (NFC)Kazu Hirata1-1/+1
2022-07-14[AMDGPU] SIMachineScheduler: Add support for several MachineScheduler featuresJannik Silvanus1-4/+3
2022-03-24[CodeGen] Define ABI breaking class members correctlyDaniil Kovalev1-4/+4
2022-03-16Cleanup codegen includesserge-sans-paille1-1/+0
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-0/+1
2022-03-10Cleanup codegen includesserge-sans-paille1-1/+0
2022-02-07[AMDGPU] Fix debug values in scheduler not placed correctly when revertingVang Thao1-4/+2
2021-12-06[llvm][Hexagon] Generalize VLIWResourceModel, VLIWMachineScheduler, and Conve...James Nagurne1-4/+8
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