diff options
Diffstat (limited to 'llvm/test')
157 files changed, 7957 insertions, 2903 deletions
diff --git a/llvm/test/Analysis/CostModel/ARM/add-cast-vect.ll b/llvm/test/Analysis/CostModel/ARM/add-cast-vect.ll index 1e9a5f7..c0410cf 100644 --- a/llvm/test/Analysis/CostModel/ARM/add-cast-vect.ll +++ b/llvm/test/Analysis/CostModel/ARM/add-cast-vect.ll @@ -1,4 +1,6 @@ -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s + ; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s ; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM @@ -15,13 +17,18 @@ target triple = "armv7--linux-gnueabihf" %T464 = type <4 x i64> define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { -; COST: function 'direct' +; COST-LABEL: 'direct' +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = add <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 %v1 = load %T432, ptr %loadaddr2 ; ASM: vld1.64 - %r3 = add %T432 %v0, %v1 -; COST: cost of 1 for instruction: {{.*}} add <4 x i32> + %r3 = add %T432 %v0, %v1 ; ASM: vadd.i32 store %T432 %r3, ptr %storeaddr ; ASM: vst1.64 @@ -29,16 +36,22 @@ define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { } define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { -; COST: function 'ups1632' +; COST-LABEL: 'ups1632' +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = sext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = sext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = add <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T416, ptr %loadaddr ; ASM: vldr %v1 = load %T416, ptr %loadaddr2 ; ASM: vldr %r1 = sext %T416 %v0 to %T432 %r2 = sext %T416 %v1 to %T432 -; COST: cost of 0 for instruction: {{.*}} sext <4 x i16> {{.*}} to <4 x i32> - %r3 = add %T432 %r1, %r2 -; COST: cost of 1 for instruction: {{.*}} add <4 x i32> + %r3 = add %T432 %r1, %r2 ; ASM: vaddl.s16 store %T432 %r3, ptr %storeaddr ; ASM: vst1.64 @@ -46,16 +59,22 @@ define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { } define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { -; COST: function 'upu1632' +; COST-LABEL: 'upu1632' +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = zext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = zext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = add <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T416, ptr %loadaddr ; ASM: vldr %v1 = load %T416, ptr %loadaddr2 ; ASM: vldr %r1 = zext %T416 %v0 to %T432 %r2 = zext %T416 %v1 to %T432 -; COST: cost of 0 for instruction: {{.*}} zext <4 x i16> {{.*}} to <4 x i32> - %r3 = add %T432 %r1, %r2 -; COST: cost of 1 for instruction: {{.*}} add <4 x i32> + %r3 = add %T432 %r1, %r2 ; ASM: vaddl.u16 store %T432 %r3, ptr %storeaddr ; ASM: vst1.64 @@ -63,51 +82,66 @@ define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { } define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { -; COST: function 'ups3264' +; COST-LABEL: 'ups3264' +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = add <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = sext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T232, ptr %loadaddr ; ASM: vldr %v1 = load %T232, ptr %loadaddr2 ; ASM: vldr - %r3 = add %T232 %v0, %v1 + %r3 = add %T232 %v0, %v1 ; ASM: vadd.i32 -; COST: cost of 1 for instruction: {{.*}} add <2 x i32> %st = sext %T232 %r3 to %T264 ; ASM: vmovl.s32 -; COST: cost of 1 for instruction: {{.*}} sext <2 x i32> {{.*}} to <2 x i64> store %T264 %st, ptr %storeaddr ; ASM: vst1.64 ret void } define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { -; COST: function 'upu3264' +; COST-LABEL: 'upu3264' +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = add <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = zext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T232, ptr %loadaddr ; ASM: vldr %v1 = load %T232, ptr %loadaddr2 ; ASM: vldr - %r3 = add %T232 %v0, %v1 + %r3 = add %T232 %v0, %v1 ; ASM: vadd.i32 -; COST: cost of 1 for instruction: {{.*}} add <2 x i32> %st = zext %T232 %r3 to %T264 ; ASM: vmovl.u32 -; COST: cost of 1 for instruction: {{.*}} zext <2 x i32> {{.*}} to <2 x i64> store %T264 %st, ptr %storeaddr ; ASM: vst1.64 ret void } define void @dn3216(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { -; COST: function 'dn3216' +; COST-LABEL: 'dn3216' +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = add <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = trunc <4 x i32> %r3 to <4 x i16> +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 %v1 = load %T432, ptr %loadaddr2 ; ASM: vld1.64 - %r3 = add %T432 %v0, %v1 + %r3 = add %T432 %v0, %v1 ; ASM: vadd.i32 -; COST: cost of 1 for instruction: {{.*}} add <4 x i32> %st = trunc %T432 %r3 to %T416 ; ASM: vmovn.i32 -; COST: cost of 1 for instruction: {{.*}} trunc <4 x i32> {{.*}} to <4 x i16> store %T416 %st, ptr %storeaddr ; ASM: vstr ret void diff --git a/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll b/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll index c2248c2..e5bbac6 100644 --- a/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll +++ b/llvm/test/Analysis/CostModel/ARM/cast_ldst.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 < %s | FileCheck %s --check-prefix=CHECK-NEON -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK-V8R +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 < %s | FileCheck %s --check-prefix=CHECK-NEON +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK-V8R target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" diff --git a/llvm/test/Analysis/CostModel/ARM/freeshift.ll b/llvm/test/Analysis/CostModel/ARM/freeshift.ll index 51e87b5..cd5c8c5 100644 --- a/llvm/test/Analysis/CostModel/ARM/freeshift.ll +++ b/llvm/test/Analysis/CostModel/ARM/freeshift.ll @@ -1,23 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi < %s | FileCheck %s +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define void @shl(i32 %a, i32 %b) { ; CHECK-LABEL: 'shl' -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = shl i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ac = add i32 %b, %as -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ss = shl i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sc = sub i32 %b, %ss -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %xs = shl i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xc = xor i32 %b, %xs -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ns = shl i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nc = and i32 %b, %ns -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %os = shl i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %oc = or i32 %b, %os -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %is = shl i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ic = icmp eq i32 %b, %is -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NEXT: Cost Model: Found costs of 0 for: %as = shl i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ac = add i32 %b, %as +; CHECK-NEXT: Cost Model: Found costs of 0 for: %ss = shl i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %sc = sub i32 %b, %ss +; CHECK-NEXT: Cost Model: Found costs of 0 for: %xs = shl i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %xc = xor i32 %b, %xs +; CHECK-NEXT: Cost Model: Found costs of 0 for: %ns = shl i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %nc = and i32 %b, %ns +; CHECK-NEXT: Cost Model: Found costs of 0 for: %os = shl i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %oc = or i32 %b, %os +; CHECK-NEXT: Cost Model: Found costs of 0 for: %is = shl i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ic = icmp eq i32 %b, %is +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret void ; %as = shl i32 %a, 3 %ac = add i32 %b, %as @@ -36,19 +36,19 @@ define void @shl(i32 %a, i32 %b) { define void @ashr(i32 %a, i32 %b) { ; CHECK-LABEL: 'ashr' -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = ashr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ac = add i32 %b, %as -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ss = ashr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sc = sub i32 %b, %ss -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %xs = ashr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xc = xor i32 %b, %xs -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ns = ashr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nc = and i32 %b, %ns -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %os = ashr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %oc = or i32 %b, %os -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %is = ashr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ic = icmp eq i32 %b, %is -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NEXT: Cost Model: Found costs of 0 for: %as = ashr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ac = add i32 %b, %as +; CHECK-NEXT: Cost Model: Found costs of 0 for: %ss = ashr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %sc = sub i32 %b, %ss +; CHECK-NEXT: Cost Model: Found costs of 0 for: %xs = ashr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %xc = xor i32 %b, %xs +; CHECK-NEXT: Cost Model: Found costs of 0 for: %ns = ashr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %nc = and i32 %b, %ns +; CHECK-NEXT: Cost Model: Found costs of 0 for: %os = ashr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %oc = or i32 %b, %os +; CHECK-NEXT: Cost Model: Found costs of 0 for: %is = ashr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ic = icmp eq i32 %b, %is +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret void ; %as = ashr i32 %a, 3 %ac = add i32 %b, %as @@ -67,19 +67,19 @@ define void @ashr(i32 %a, i32 %b) { define void @lshr(i32 %a, i32 %b) { ; CHECK-LABEL: 'lshr' -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = lshr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ac = add i32 %b, %as -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ss = lshr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sc = sub i32 %b, %ss -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %xs = lshr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xc = xor i32 %b, %xs -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ns = lshr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nc = and i32 %b, %ns -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %os = lshr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %oc = or i32 %b, %os -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %is = lshr i32 %a, 3 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ic = icmp eq i32 %b, %is -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NEXT: Cost Model: Found costs of 0 for: %as = lshr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ac = add i32 %b, %as +; CHECK-NEXT: Cost Model: Found costs of 0 for: %ss = lshr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %sc = sub i32 %b, %ss +; CHECK-NEXT: Cost Model: Found costs of 0 for: %xs = lshr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %xc = xor i32 %b, %xs +; CHECK-NEXT: Cost Model: Found costs of 0 for: %ns = lshr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %nc = and i32 %b, %ns +; CHECK-NEXT: Cost Model: Found costs of 0 for: %os = lshr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %oc = or i32 %b, %os +; CHECK-NEXT: Cost Model: Found costs of 0 for: %is = lshr i32 %a, 3 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ic = icmp eq i32 %b, %is +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret void ; %as = lshr i32 %a, 3 %ac = add i32 %b, %as diff --git a/llvm/test/Analysis/CostModel/ARM/gep.ll b/llvm/test/Analysis/CostModel/ARM/gep.ll index 48de193..cce87a5 100644 --- a/llvm/test/Analysis/CostModel/ARM/gep.ll +++ b/llvm/test/Analysis/CostModel/ARM/gep.ll @@ -1,98 +1,98 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V6M -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-V7M-NOFP -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-V7M-FP -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVEFP -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-T32 -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=arm-none-eabi -mcpu=cortex-a53 < %s | FileCheck %s --check-prefix=CHECK-A32 +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V6M +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-V7M-NOFP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-V7M-FP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVEFP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-T32 +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=arm-none-eabi -mcpu=cortex-a53 < %s | FileCheck %s --check-prefix=CHECK-A32 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define void @testi8(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testi8' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testi8' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testi8' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testi8' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testi8' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testi8' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testi8' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i8, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i8, ptr %a, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i8, ptr %a, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i8, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i8, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i8, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i8, ptr %a, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i8, ptr %a, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i8, ptr %a, i32 4095 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i8, ptr %a, i32 4096 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i8, ptr %a, i32 -255 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i8, ptr %a, i32 -256 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i8, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds i8, ptr %a, i32 1 %am4 = getelementptr inbounds i8, ptr %a, i32 -1 @@ -109,88 +109,88 @@ define void @testi8(ptr %a, i32 %i) { define void @testi16(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testi16' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testi16' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testi16' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testi16' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testi16' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testi16' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testi16' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i16, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i16, ptr %a, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i16, ptr %a, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i16, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i16, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i16, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i16, ptr %a, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i16, ptr %a, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i16, ptr %a, i32 2046 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i16, ptr %a, i32 2048 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i16, ptr %a, i32 -127 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i16, ptr %a, i32 -128 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i16, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds i16, ptr %a, i32 1 %am4 = getelementptr inbounds i16, ptr %a, i32 -1 @@ -207,88 +207,88 @@ define void @testi16(ptr %a, i32 %i) { define void @testi32(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testi32' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testi32' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testi32' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testi32' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testi32' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testi32' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testi32' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i32, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i32, ptr %a, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i32, ptr %a, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %ai = getelementptr inbounds i32, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i32, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i32, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i32, ptr %a, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i32, ptr %a, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds i32, ptr %a, i32 1023 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds i32, ptr %a, i32 1024 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i32, ptr %a, i32 -63 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i32, ptr %a, i32 -64 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %ai = getelementptr inbounds i32, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds i32, ptr %a, i32 1 %am4 = getelementptr inbounds i32, ptr %a, i32 -1 @@ -305,102 +305,102 @@ define void @testi32(ptr %a, i32 %i) { define void @testi64(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testi64' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testi64' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testi64' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testi64' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testi64' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testi64' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testi64' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1 = getelementptr inbounds i64, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a15 = getelementptr inbounds i64, ptr %a, i32 15 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a16 = getelementptr inbounds i64, ptr %a, i32 16 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a31 = getelementptr inbounds i64, ptr %a, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a32 = getelementptr inbounds i64, ptr %a, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds i64, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1 = getelementptr inbounds i64, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am4 = getelementptr inbounds i64, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a15 = getelementptr inbounds i64, ptr %a, i32 15 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a16 = getelementptr inbounds i64, ptr %a, i32 16 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a31 = getelementptr inbounds i64, ptr %a, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a32 = getelementptr inbounds i64, ptr %a, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a4095 = getelementptr inbounds i64, ptr %a, i32 1023 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a4096 = getelementptr inbounds i64, ptr %a, i32 1024 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds i64, ptr %a, i32 -63 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds i64, ptr %a, i32 -64 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds i64, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds i64, ptr %a, i32 1 %am4 = getelementptr inbounds i64, ptr %a, i32 -1 @@ -419,102 +419,102 @@ define void @testi64(ptr %a, i32 %i) { define void @testhalf(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testhalf' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testhalf' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testhalf' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testhalf' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testhalf' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testhalf' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testhalf' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1 = getelementptr inbounds half, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am1 = getelementptr inbounds half, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a255 = getelementptr inbounds half, ptr %a, i32 255 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds half, ptr %a, i32 256 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds half, ptr %a, i32 -255 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds half, ptr %a, i32 -256 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am63 = getelementptr inbounds half, ptr %a, i32 -63 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am64 = getelementptr inbounds half, ptr %a, i32 -64 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds half, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1 = getelementptr inbounds half, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am1 = getelementptr inbounds half, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a255 = getelementptr inbounds half, ptr %a, i32 255 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds half, ptr %a, i32 256 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds half, ptr %a, i32 -255 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds half, ptr %a, i32 -256 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds half, ptr %a, i32 1023 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds half, ptr %a, i32 1024 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am63 = getelementptr inbounds half, ptr %a, i32 -63 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am64 = getelementptr inbounds half, ptr %a, i32 -64 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds half, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds half, ptr %a, i32 1 %am1 = getelementptr inbounds half, ptr %a, i32 -1 @@ -533,102 +533,102 @@ define void @testhalf(ptr %a, i32 %i) { define void @testfloat(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testfloat' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testfloat' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testfloat' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testfloat' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testfloat' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testfloat' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testfloat' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds float, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds float, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds float, ptr %a, i32 255 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds float, ptr %a, i32 256 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds float, ptr %a, i32 -255 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds float, ptr %a, i32 -256 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds float, ptr %a, i32 -63 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds float, ptr %a, i32 -64 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds float, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds float, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds float, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds float, ptr %a, i32 255 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds float, ptr %a, i32 256 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds float, ptr %a, i32 -255 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds float, ptr %a, i32 -256 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds float, ptr %a, i32 1023 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds float, ptr %a, i32 1024 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds float, ptr %a, i32 -63 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds float, ptr %a, i32 -64 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds float, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds float, ptr %a, i32 1 %am1 = getelementptr inbounds float, ptr %a, i32 -1 @@ -647,102 +647,102 @@ define void @testfloat(ptr %a, i32 %i) { define void @testdouble(ptr %a, i32 %i) { ; CHECK-V6M-LABEL: 'testdouble' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testdouble' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testdouble' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testdouble' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testdouble' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testdouble' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testdouble' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a1 = getelementptr inbounds double, ptr %a, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am1 = getelementptr inbounds double, ptr %a, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a255 = getelementptr inbounds double, ptr %a, i32 127 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a256 = getelementptr inbounds double, ptr %a, i32 128 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am255 = getelementptr inbounds double, ptr %a, i32 -127 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %am256 = getelementptr inbounds double, ptr %a, i32 -128 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1023 = getelementptr inbounds double, ptr %a, i32 511 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a1024 = getelementptr inbounds double, ptr %a, i32 512 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am63 = getelementptr inbounds double, ptr %a, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %am64 = getelementptr inbounds double, ptr %a, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ai = getelementptr inbounds double, ptr %a, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a1 = getelementptr inbounds double, ptr %a, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am1 = getelementptr inbounds double, ptr %a, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %a255 = getelementptr inbounds double, ptr %a, i32 127 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a256 = getelementptr inbounds double, ptr %a, i32 128 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am255 = getelementptr inbounds double, ptr %a, i32 -127 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %am256 = getelementptr inbounds double, ptr %a, i32 -128 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1023 = getelementptr inbounds double, ptr %a, i32 511 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %a1024 = getelementptr inbounds double, ptr %a, i32 512 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am63 = getelementptr inbounds double, ptr %a, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %am64 = getelementptr inbounds double, ptr %a, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %ai = getelementptr inbounds double, ptr %a, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %a1 = getelementptr inbounds double, ptr %a, i32 1 %am1 = getelementptr inbounds double, ptr %a, i32 -1 @@ -761,375 +761,375 @@ define void @testdouble(ptr %a, i32 %i) { define void @testvecs(i32 %i) { ; CHECK-V6M-LABEL: 'testvecs' -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-V6M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-V6M-NEXT: Cost Model: Found costs of 0 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-V6M-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-NOFP-LABEL: 'testvecs' -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-V7M-NOFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 0 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-V7M-NOFP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-V7M-FP-LABEL: 'testvecs' -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-V7M-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 0 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-V7M-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'testvecs' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-MVE-NEXT: Cost Model: Found costs of 0 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-MVEFP-LABEL: 'testvecs' -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-MVEFP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-MVEFP-NEXT: Cost Model: Found costs of 0 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-T32-LABEL: 'testvecs' -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-T32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-T32-NEXT: Cost Model: Found costs of 0 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-T32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-A32-LABEL: 'testvecs' -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 -; CHECK-A32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b8 = getelementptr inbounds <4 x i16>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b9 = getelementptr inbounds <4 x i32>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b10 = getelementptr inbounds <4 x i64>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b11 = getelementptr inbounds <4 x half>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b12 = getelementptr inbounds <4 x float>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %b13 = getelementptr inbounds <4 x double>, ptr undef, i32 1 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o7 = getelementptr inbounds <4 x i8>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o8 = getelementptr inbounds <4 x i16>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o9 = getelementptr inbounds <4 x i32>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o10 = getelementptr inbounds <4 x i64>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o11 = getelementptr inbounds <4 x half>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o12 = getelementptr inbounds <4 x float>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %o13 = getelementptr inbounds <4 x double>, ptr undef, i32 4 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p7 = getelementptr inbounds <4 x i8>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p8 = getelementptr inbounds <4 x i16>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p9 = getelementptr inbounds <4 x i32>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p10 = getelementptr inbounds <4 x i64>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p11 = getelementptr inbounds <4 x half>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p12 = getelementptr inbounds <4 x float>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %p13 = getelementptr inbounds <4 x double>, ptr undef, i32 31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q7 = getelementptr inbounds <4 x i8>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q8 = getelementptr inbounds <4 x i16>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q9 = getelementptr inbounds <4 x i32>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q10 = getelementptr inbounds <4 x i64>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q11 = getelementptr inbounds <4 x half>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q12 = getelementptr inbounds <4 x float>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %q13 = getelementptr inbounds <4 x double>, ptr undef, i32 32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r11 = getelementptr inbounds <4 x half>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r12 = getelementptr inbounds <4 x float>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %r13 = getelementptr inbounds <4 x double>, ptr undef, i32 -31 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s7 = getelementptr inbounds <4 x i8>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s8 = getelementptr inbounds <4 x i16>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s9 = getelementptr inbounds <4 x i32>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s10 = getelementptr inbounds <4 x i64>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s11 = getelementptr inbounds <4 x half>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s12 = getelementptr inbounds <4 x float>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %s13 = getelementptr inbounds <4 x double>, ptr undef, i32 -32 +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c7 = getelementptr inbounds <4 x i8>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c8 = getelementptr inbounds <4 x i16>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c9 = getelementptr inbounds <4 x i32>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c10 = getelementptr inbounds <4 x i64>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c11 = getelementptr inbounds <4 x half>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c12 = getelementptr inbounds <4 x float>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 1 for: %c13 = getelementptr inbounds <4 x double>, ptr undef, i32 %i +; CHECK-A32-NEXT: Cost Model: Found costs of 0 for: %d0 = getelementptr inbounds i8, ptr undef, i32 -1 +; CHECK-A32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %b7 = getelementptr inbounds <4 x i8>, ptr undef, i32 1 diff --git a/llvm/test/Analysis/CostModel/ARM/immediates.ll b/llvm/test/Analysis/CostModel/ARM/immediates.ll index ed13636..cd42313 100644 --- a/llvm/test/Analysis/CostModel/ARM/immediates.ll +++ b/llvm/test/Analysis/CostModel/ARM/immediates.ll @@ -1,145 +1,53 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-T1-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-T2-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=latency -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-T1-LATENCY -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=latency -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-T2-LATENCY -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=throughput -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-T1-THROUGHPUT -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=throughput -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-T2-THROUGHPUT +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-T1 +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-T2 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define i32 @const_costs() { -; CHECK-T1-SIZE-LABEL: 'const_costs' -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_1 = add i32 undef, 1 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_32767 = add i32 undef, 32767 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_1 = sub i32 undef, 1 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_32768 = sub i32 undef, 32768 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_2 = mul i32 undef, 2 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_3 = mul i32 undef, 3 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_27 = mul i32 undef, 27 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_255 = and i32 undef, 255 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_65535 = and i32 undef, 65535 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_1 = and i32 undef, 1 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_1 = xor i32 undef, 1 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_7 = xor i32 undef, 7 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_1 = getelementptr i32, ptr undef, i32 1 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_16 = getelementptr i32, ptr undef, i32 16 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_244 = icmp ne i32 undef, 244 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_256 = icmp uge i32 undef, 256 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_1024 = icmp ult i32 undef, 1024 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %select_1_0 = select i1 undef, i32 1, i32 0 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %select_7_255 = select i1 undef, i32 7, i32 255 -; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 1 +; CHECK-T1-LABEL: 'const_costs' +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %add_1 = add i32 undef, 1 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %add_32767 = add i32 undef, 32767 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %sub_1 = sub i32 undef, 1 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %sub_32768 = sub i32 undef, 32768 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %mul_2 = mul i32 undef, 2 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %mul_3 = mul i32 undef, 3 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %mul_27 = mul i32 undef, 27 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %and_255 = and i32 undef, 255 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %and_65535 = and i32 undef, 65535 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %and_1 = and i32 undef, 1 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %xor_1 = xor i32 undef, 1 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %xor_7 = xor i32 undef, 7 +; CHECK-T1-NEXT: Cost Model: Found costs of 0 for: %gep_1 = getelementptr i32, ptr undef, i32 1 +; CHECK-T1-NEXT: Cost Model: Found costs of 0 for: %gep_16 = getelementptr i32, ptr undef, i32 16 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %cmp_244 = icmp ne i32 undef, 244 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %cmp_256 = icmp uge i32 undef, 256 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: %cmp_1024 = icmp ult i32 undef, 1024 +; CHECK-T1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %select_1_0 = select i1 undef, i32 1, i32 0 +; CHECK-T1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %select_7_255 = select i1 undef, i32 7, i32 255 +; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: ret i32 1 ; -; CHECK-T2-SIZE-LABEL: 'const_costs' -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_1 = add i32 undef, 1 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_32767 = add i32 undef, 32767 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_1 = sub i32 undef, 1 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_32768 = sub i32 undef, 32768 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_2 = mul i32 undef, 2 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_3 = mul i32 undef, 3 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_27 = mul i32 undef, 27 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_255 = and i32 undef, 255 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_65535 = and i32 undef, 65535 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_1 = and i32 undef, 1 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_1 = xor i32 undef, 1 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_7 = xor i32 undef, 7 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_1 = getelementptr i32, ptr undef, i32 1 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_16 = getelementptr i32, ptr undef, i32 16 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_244 = icmp ne i32 undef, 244 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_256 = icmp uge i32 undef, 256 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_1024 = icmp ult i32 undef, 1024 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %select_1_0 = select i1 undef, i32 1, i32 0 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %select_7_255 = select i1 undef, i32 7, i32 255 -; CHECK-T2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 1 -; -; CHECK-T1-LATENCY-LABEL: 'const_costs' -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_1 = add i32 undef, 1 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_32767 = add i32 undef, 32767 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_1 = sub i32 undef, 1 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_32768 = sub i32 undef, 32768 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_2 = mul i32 undef, 2 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_3 = mul i32 undef, 3 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_27 = mul i32 undef, 27 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_255 = and i32 undef, 255 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_65535 = and i32 undef, 65535 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_1 = and i32 undef, 1 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_1 = xor i32 undef, 1 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_7 = xor i32 undef, 7 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_1 = getelementptr i32, ptr undef, i32 1 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_16 = getelementptr i32, ptr undef, i32 16 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_244 = icmp ne i32 undef, 244 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_256 = icmp uge i32 undef, 256 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_1024 = icmp ult i32 undef, 1024 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_1_0 = select i1 undef, i32 1, i32 0 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_7_255 = select i1 undef, i32 7, i32 255 -; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 1 -; -; CHECK-T2-LATENCY-LABEL: 'const_costs' -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_1 = add i32 undef, 1 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_32767 = add i32 undef, 32767 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_1 = sub i32 undef, 1 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_32768 = sub i32 undef, 32768 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_2 = mul i32 undef, 2 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_3 = mul i32 undef, 3 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_27 = mul i32 undef, 27 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_255 = and i32 undef, 255 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_65535 = and i32 undef, 65535 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_1 = and i32 undef, 1 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_1 = xor i32 undef, 1 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_7 = xor i32 undef, 7 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_1 = getelementptr i32, ptr undef, i32 1 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_16 = getelementptr i32, ptr undef, i32 16 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_244 = icmp ne i32 undef, 244 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_256 = icmp uge i32 undef, 256 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_1024 = icmp ult i32 undef, 1024 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_1_0 = select i1 undef, i32 1, i32 0 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_7_255 = select i1 undef, i32 7, i32 255 -; CHECK-T2-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 1 -; -; CHECK-T1-THROUGHPUT-LABEL: 'const_costs' -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_1 = add i32 undef, 1 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_32767 = add i32 undef, 32767 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_1 = sub i32 undef, 1 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_32768 = sub i32 undef, 32768 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_2 = mul i32 undef, 2 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_3 = mul i32 undef, 3 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_27 = mul i32 undef, 27 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_255 = and i32 undef, 255 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_65535 = and i32 undef, 65535 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_1 = and i32 undef, 1 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_1 = xor i32 undef, 1 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_7 = xor i32 undef, 7 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_1 = getelementptr i32, ptr undef, i32 1 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_16 = getelementptr i32, ptr undef, i32 16 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_244 = icmp ne i32 undef, 244 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_256 = icmp uge i32 undef, 256 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_1024 = icmp ult i32 undef, 1024 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_1_0 = select i1 undef, i32 1, i32 0 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_7_255 = select i1 undef, i32 7, i32 255 -; CHECK-T1-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 1 -; -; CHECK-T2-THROUGHPUT-LABEL: 'const_costs' -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_1 = add i32 undef, 1 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add_32767 = add i32 undef, 32767 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_1 = sub i32 undef, 1 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub_32768 = sub i32 undef, 32768 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_2 = mul i32 undef, 2 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_3 = mul i32 undef, 3 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mul_27 = mul i32 undef, 27 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_255 = and i32 undef, 255 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_65535 = and i32 undef, 65535 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and_1 = and i32 undef, 1 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_1 = xor i32 undef, 1 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %xor_7 = xor i32 undef, 7 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_1 = getelementptr i32, ptr undef, i32 1 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep_16 = getelementptr i32, ptr undef, i32 16 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_244 = icmp ne i32 undef, 244 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_256 = icmp uge i32 undef, 256 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp_1024 = icmp ult i32 undef, 1024 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_1_0 = select i1 undef, i32 1, i32 0 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %select_7_255 = select i1 undef, i32 7, i32 255 -; CHECK-T2-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 1 +; CHECK-T2-LABEL: 'const_costs' +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %add_1 = add i32 undef, 1 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %add_32767 = add i32 undef, 32767 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %sub_1 = sub i32 undef, 1 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %sub_32768 = sub i32 undef, 32768 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %mul_2 = mul i32 undef, 2 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %mul_3 = mul i32 undef, 3 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %mul_27 = mul i32 undef, 27 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %and_255 = and i32 undef, 255 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %and_65535 = and i32 undef, 65535 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %and_1 = and i32 undef, 1 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %xor_1 = xor i32 undef, 1 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %xor_7 = xor i32 undef, 7 +; CHECK-T2-NEXT: Cost Model: Found costs of 0 for: %gep_1 = getelementptr i32, ptr undef, i32 1 +; CHECK-T2-NEXT: Cost Model: Found costs of 0 for: %gep_16 = getelementptr i32, ptr undef, i32 16 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %cmp_244 = icmp ne i32 undef, 244 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %cmp_256 = icmp uge i32 undef, 256 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: %cmp_1024 = icmp ult i32 undef, 1024 +; CHECK-T2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %select_1_0 = select i1 undef, i32 1, i32 0 +; CHECK-T2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %select_7_255 = select i1 undef, i32 7, i32 255 +; CHECK-T2-NEXT: Cost Model: Found costs of 1 for: ret i32 1 ; %add_1 = add i32 undef, 1 %add_32767 = add i32 undef, 32767 diff --git a/llvm/test/Analysis/CostModel/ARM/insertelement.ll b/llvm/test/Analysis/CostModel/ARM/insertelement.ll index 5a922dd..f14b200 100644 --- a/llvm/test/Analysis/CostModel/ARM/insertelement.ll +++ b/llvm/test/Analysis/CostModel/ARM/insertelement.ll @@ -1,4 +1,5 @@ -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios6.0.0" @@ -7,12 +8,16 @@ target triple = "thumbv7-apple-ios6.0.0" ; due to renaming constraints. %T_i8v = type <8 x i8> %T_i8 = type i8 -; CHECK: insertelement_i8 -define void @insertelement_i8(ptr %saddr, - ptr %vaddr) { +define void @insertelement_i8(ptr %saddr, ptr %vaddr) { +; CHECK-LABEL: 'insertelement_i8' +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <8 x i8>, ptr %vaddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i8, ptr %saddr, align 1 +; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <8 x i8> %v0, i8 %v1, i32 1 +; CHECK-NEXT: Cost Model: Found costs of 1 for: store <8 x i8> %v2, ptr %vaddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T_i8v, ptr %vaddr %v1 = load %T_i8, ptr %saddr -;CHECK: estimated cost of 3 for {{.*}} insertelement <8 x i8> %v2 = insertelement %T_i8v %v0, %T_i8 %v1, i32 1 store %T_i8v %v2, ptr %vaddr ret void @@ -21,12 +26,16 @@ define void @insertelement_i8(ptr %saddr, %T_i16v = type <4 x i16> %T_i16 = type i16 -; CHECK: insertelement_i16 -define void @insertelement_i16(ptr %saddr, - ptr %vaddr) { +define void @insertelement_i16(ptr %saddr, ptr %vaddr) { +; CHECK-LABEL: 'insertelement_i16' +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %vaddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i16, ptr %saddr, align 2 +; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <4 x i16> %v0, i16 %v1, i32 1 +; CHECK-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %v2, ptr %vaddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T_i16v, ptr %vaddr %v1 = load %T_i16, ptr %saddr -;CHECK: estimated cost of 3 for {{.*}} insertelement <4 x i16> %v2 = insertelement %T_i16v %v0, %T_i16 %v1, i32 1 store %T_i16v %v2, ptr %vaddr ret void @@ -34,12 +43,16 @@ define void @insertelement_i16(ptr %saddr, %T_i32v = type <2 x i32> %T_i32 = type i32 -; CHECK: insertelement_i32 -define void @insertelement_i32(ptr %saddr, - ptr %vaddr) { +define void @insertelement_i32(ptr %saddr, ptr %vaddr) { +; CHECK-LABEL: 'insertelement_i32' +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %vaddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i32, ptr %saddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <2 x i32> %v0, i32 %v1, i32 1 +; CHECK-NEXT: Cost Model: Found costs of 1 for: store <2 x i32> %v2, ptr %vaddr, align 4 +; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; %v0 = load %T_i32v, ptr %vaddr %v1 = load %T_i32, ptr %saddr -;CHECK: estimated cost of 3 for {{.*}} insertelement <2 x i32> %v2 = insertelement %T_i32v %v0, %T_i32 %v1, i32 1 store %T_i32v %v2, ptr %vaddr ret void diff --git a/llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll b/llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll index 4404209..c98601f 100644 --- a/llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll +++ b/llvm/test/Analysis/CostModel/ARM/load-to-trunc.ll @@ -1,17 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=armv8r-none-eabi < %s | FileCheck %s + ; Check memory cost model action for a load of an unusually sized integer ; follow by and a trunc to a register sized integer gives a cost of 1 rather ; than the expanded cost if it is not. Currently, this target does not have ; that expansion. -; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK - ; Check that cost is 1 for unusual load to register sized load. define i32 @loadUnusualIntegerWithTrunc(ptr %ptr) { ; CHECK-LABEL: 'loadUnusualIntegerWithTrunc' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %out = load i128, ptr %ptr, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %trunc = trunc i128 %out to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %trunc +; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %out = load i128, ptr %ptr, align 8 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %trunc = trunc i128 %out to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i32 %trunc ; %out = load i128, ptr %ptr %trunc = trunc i128 %out to i32 @@ -20,8 +20,8 @@ define i32 @loadUnusualIntegerWithTrunc(ptr %ptr) { define i128 @loadUnusualInteger(ptr %ptr) { ; CHECK-LABEL: 'loadUnusualInteger' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %out = load i128, ptr %ptr, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i128 %out +; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %out = load i128, ptr %ptr, align 8 +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i128 %out ; %out = load i128, ptr %ptr ret i128 %out diff --git a/llvm/test/Analysis/CostModel/ARM/load_store.ll b/llvm/test/Analysis/CostModel/ARM/load_store.ll index 4c322e9..dd2eaae 100644 --- a/llvm/test/Analysis/CostModel/ARM/load_store.ll +++ b/llvm/test/Analysis/CostModel/ARM/load_store.ll @@ -1,171 +1,117 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECK-NOVEC -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-NOVEC -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-FP -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-NEON -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=arm-none-eabi -mcpu=cortex-a53 < %s | FileCheck %s --check-prefix=CHECK-NEON -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8a-linux-gnueabihf < %s | FileCheck %s --check-prefix=CHECK-V8-SIZE -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE-SIZE +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECK-NOVEC +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-NOVEC +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-FP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-NEON +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=arm-none-eabi -mcpu=cortex-a53 < %s | FileCheck %s --check-prefix=CHECK-NEON target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define void @stores() { ; CHECK-NOVEC-LABEL: 'stores' -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store i64 undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store i128 undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store double undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i8> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i16> undef, ptr undef, align 2 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i32> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x i64> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i16> undef, ptr undef, align 2 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <16 x i8> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x float> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <4 x double> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x float> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x double> undef, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x i64> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i16> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x float> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x double> undef, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NOVEC-NEXT: Cost Model: Found costs of 1 for: store i8 undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of 1 for: store i16 undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of 1 for: store i32 undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store i64 undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store i128 undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of 1 for: store float undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store double undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i8> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i16> undef, ptr undef, align 2 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i32> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 2 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:16 CodeSize:1 Lat:1 SizeLat:1 for: store <16 x i8> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x double> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x float> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-FP-LABEL: 'stores' -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store i64 undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store i128 undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store double undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i8> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i16> undef, ptr undef, align 2 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i32> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x i64> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i16> undef, ptr undef, align 2 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <16 x i8> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x float> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x double> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x float> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x double> undef, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x i64> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i16> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x float> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x double> undef, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: store i8 undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: store i16 undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: store i32 undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store i64 undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store i128 undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: store float undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: store double undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i8> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i16> undef, ptr undef, align 2 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i32> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 2 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:16 CodeSize:1 Lat:1 SizeLat:1 for: store <16 x i8> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x double> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x float> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'stores' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store i64 undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store i128 undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store double undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: store <2 x i8> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: store <2 x i16> undef, ptr undef, align 2 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: store <2 x i32> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i64> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i32> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i16> undef, ptr undef, align 2 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i8> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x float> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x double> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: store <2 x float> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x double> undef, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x i64> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i32> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i16> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x float> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <2 x double> undef, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: store i8 undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: store i16 undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: store i32 undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store i64 undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store i128 undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: store float undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: store double undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:18 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i8> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:18 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i16> undef, ptr undef, align 2 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:18 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i32> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 2 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <16 x i8> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x double> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x float> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'stores' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store i64 undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store i128 undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store double undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 7 for instruction: store <2 x i8> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 7 for instruction: store <2 x i16> undef, ptr undef, align 2 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i32> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> undef, ptr undef, align 2 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <4 x double> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x float> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x double> undef, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x double> undef, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; CHECK-V8-SIZE-LABEL: 'stores' -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i64 undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i128 undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store double undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i8> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i16> undef, ptr undef, align 2 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i32> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> undef, ptr undef, align 2 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x double> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x float> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x double> undef, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x double> undef, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-MVE-SIZE-LABEL: 'stores' -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i64 undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i128 undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store double undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i8> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i16> undef, ptr undef, align 2 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i32> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> undef, ptr undef, align 2 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x double> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x float> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x double> undef, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x double> undef, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store i8 undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store i16 undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store i32 undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store i64 undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store i128 undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store float undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store double undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:7 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i8> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:7 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i16> undef, ptr undef, align 2 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <2 x i32> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <8 x i16> undef, ptr undef, align 2 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <16 x i8> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <4 x float> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x double> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <2 x float> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <8 x i16> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: store <4 x float> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; store i8 undef, ptr undef, align 4 store i16 undef, ptr undef, align 4 @@ -199,160 +145,108 @@ define void @stores() { define void @loads() { ; CHECK-NOVEC-LABEL: 'loads' -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = load i8, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = load i16, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = load i32, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = load i64, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = load i128, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = load float, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %7 = load double, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %8 = load <2 x i8>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = load <2 x i16>, ptr undef, align 2 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = load <2 x i32>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = load <2 x i64>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = load <4 x i32>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %13 = load <8 x i16>, ptr undef, align 2 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %14 = load <16 x i8>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %15 = load <4 x float>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %16 = load <4 x double>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %17 = load <2 x float>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %18 = load <2 x double>, ptr undef, align 4 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %19 = load <2 x i64>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = load <4 x i32>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = load <8 x i16>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %22 = load <4 x float>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %23 = load <2 x double>, ptr undef, align 1 -; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %1 = load i8, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %2 = load i16, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %3 = load i32, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %4 = load i64, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %5 = load i128, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %6 = load float, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %7 = load double, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %8 = load <2 x i8>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %9 = load <2 x i16>, ptr undef, align 2 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %10 = load <2 x i32>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %11 = load <2 x i64>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %12 = load <4 x i32>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %13 = load <8 x i16>, ptr undef, align 2 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:16 CodeSize:1 Lat:4 SizeLat:1 for: %14 = load <16 x i8>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %15 = load <4 x float>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %16 = load <4 x double>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %17 = load <2 x float>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %18 = load <2 x double>, ptr undef, align 4 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %19 = load <2 x i64>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %20 = load <4 x i32>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %21 = load <8 x i16>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %22 = load <4 x float>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %23 = load <2 x double>, ptr undef, align 1 +; CHECK-NOVEC-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-FP-LABEL: 'loads' -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = load i8, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = load i16, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = load i32, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = load i64, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = load i128, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = load float, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = load double, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %8 = load <2 x i8>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = load <2 x i16>, ptr undef, align 2 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = load <2 x i32>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = load <2 x i64>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = load <4 x i32>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %13 = load <8 x i16>, ptr undef, align 2 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %14 = load <16 x i8>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %15 = load <4 x float>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %16 = load <4 x double>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %17 = load <2 x float>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %18 = load <2 x double>, ptr undef, align 4 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %19 = load <2 x i64>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = load <4 x i32>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = load <8 x i16>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %22 = load <4 x float>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %23 = load <2 x double>, ptr undef, align 1 -; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %1 = load i8, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %2 = load i16, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %3 = load i32, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %4 = load i64, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %5 = load i128, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %6 = load float, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %7 = load double, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %8 = load <2 x i8>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %9 = load <2 x i16>, ptr undef, align 2 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %10 = load <2 x i32>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %11 = load <2 x i64>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %12 = load <4 x i32>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %13 = load <8 x i16>, ptr undef, align 2 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:16 CodeSize:1 Lat:4 SizeLat:1 for: %14 = load <16 x i8>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %15 = load <4 x float>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %16 = load <4 x double>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %17 = load <2 x float>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %18 = load <2 x double>, ptr undef, align 4 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %19 = load <2 x i64>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %20 = load <4 x i32>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %21 = load <8 x i16>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %22 = load <4 x float>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %23 = load <2 x double>, ptr undef, align 1 +; CHECK-FP-NEXT: Cost Model: Found costs of 1 for: ret void ; ; CHECK-MVE-LABEL: 'loads' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = load i8, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = load i16, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = load i32, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = load i64, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = load i128, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = load float, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = load double, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %8 = load <2 x i8>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %9 = load <2 x i16>, ptr undef, align 2 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %10 = load <2 x i32>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = load <2 x i64>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %12 = load <4 x i32>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %13 = load <8 x i16>, ptr undef, align 2 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = load <16 x i8>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %15 = load <4 x float>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %16 = load <4 x double>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %17 = load <2 x float>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %18 = load <2 x double>, ptr undef, align 4 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %19 = load <2 x i64>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %20 = load <4 x i32>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %21 = load <8 x i16>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %22 = load <4 x float>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %23 = load <2 x double>, ptr undef, align 1 -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %1 = load i8, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %2 = load i16, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %3 = load i32, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %4 = load i64, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %5 = load i128, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %6 = load float, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %7 = load double, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:18 CodeSize:1 Lat:4 SizeLat:1 for: %8 = load <2 x i8>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:18 CodeSize:1 Lat:4 SizeLat:1 for: %9 = load <2 x i16>, ptr undef, align 2 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:18 CodeSize:1 Lat:4 SizeLat:1 for: %10 = load <2 x i32>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %11 = load <2 x i64>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %12 = load <4 x i32>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %13 = load <8 x i16>, ptr undef, align 2 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %14 = load <16 x i8>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %15 = load <4 x float>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %16 = load <4 x double>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:1 Lat:4 SizeLat:1 for: %17 = load <2 x float>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %18 = load <2 x double>, ptr undef, align 4 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %19 = load <2 x i64>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %20 = load <4 x i32>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %21 = load <8 x i16>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %22 = load <4 x float>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %23 = load <2 x double>, ptr undef, align 1 +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'loads' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = load i8, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = load i16, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = load i32, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = load i64, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = load i128, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = load float, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = load double, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = load <2 x i8>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = load <2 x i16>, ptr undef, align 2 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = load <2 x i32>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = load <2 x i64>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = load <4 x i32>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = load <8 x i16>, ptr undef, align 2 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %14 = load <16 x i8>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %15 = load <4 x float>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %16 = load <4 x double>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %17 = load <2 x float>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %18 = load <2 x double>, ptr undef, align 4 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = load <2 x i64>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %20 = load <4 x i32>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %21 = load <8 x i16>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = load <4 x float>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %23 = load <2 x double>, ptr undef, align 1 -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; CHECK-V8-SIZE-LABEL: 'loads' -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = load i8, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = load i16, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = load i32, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = load i64, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = load i128, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = load float, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = load double, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = load <2 x i8>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = load <2 x i16>, ptr undef, align 2 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = load <2 x i32>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = load <2 x i64>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = load <4 x i32>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = load <8 x i16>, ptr undef, align 2 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %14 = load <16 x i8>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %15 = load <4 x float>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %16 = load <4 x double>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %17 = load <2 x float>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %18 = load <2 x double>, ptr undef, align 4 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = load <2 x i64>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %20 = load <4 x i32>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %21 = load <8 x i16>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = load <4 x float>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = load <2 x double>, ptr undef, align 1 -; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-MVE-SIZE-LABEL: 'loads' -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = load i8, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = load i16, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = load i32, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = load i64, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = load i128, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = load float, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = load double, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = load <2 x i8>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = load <2 x i16>, ptr undef, align 2 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = load <2 x i32>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = load <2 x i64>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = load <4 x i32>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = load <8 x i16>, ptr undef, align 2 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %14 = load <16 x i8>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %15 = load <4 x float>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %16 = load <4 x double>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %17 = load <2 x float>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %18 = load <2 x double>, ptr undef, align 4 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = load <2 x i64>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %20 = load <4 x i32>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %21 = load <8 x i16>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = load <4 x float>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = load <2 x double>, ptr undef, align 1 -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %1 = load i8, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %2 = load i16, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %3 = load i32, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %4 = load i64, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %5 = load i128, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %6 = load float, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %7 = load double, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %8 = load <2 x i8>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %9 = load <2 x i16>, ptr undef, align 2 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %10 = load <2 x i32>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %11 = load <2 x i64>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %12 = load <4 x i32>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %13 = load <8 x i16>, ptr undef, align 2 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %14 = load <16 x i8>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %15 = load <4 x float>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %16 = load <4 x double>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %17 = load <2 x float>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %18 = load <2 x double>, ptr undef, align 4 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %19 = load <2 x i64>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %20 = load <4 x i32>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %21 = load <8 x i16>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %22 = load <4 x float>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %23 = load <2 x double>, ptr undef, align 1 +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; load i8, ptr undef, align 4 load i16, ptr undef, align 4 diff --git a/llvm/test/Analysis/CostModel/ARM/logicalop.ll b/llvm/test/Analysis/CostModel/ARM/logicalop.ll index 967426c..82eb716 100644 --- a/llvm/test/Analysis/CostModel/ARM/logicalop.ll +++ b/llvm/test/Analysis/CostModel/ARM/logicalop.ll @@ -1,72 +1,40 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2-SIZE +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1 +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define void @op() { ; Logical and/or - select's cost must be equivalent to that of binop -; CHECK-MVE-RECIP-LABEL: 'op' -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; CHECK-NEON-RECIP-LABEL: 'op' -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; CHECK-THUMB1-RECIP-LABEL: 'op' -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB2-RECIP-LABEL: 'op' -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-MVE-SIZE-LABEL: 'op' -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-NEON-SIZE-LABEL: 'op' -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB1-SIZE-LABEL: 'op' -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB2-SIZE-LABEL: 'op' -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-MVE-LABEL: 'op' +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %sand = select i1 undef, i1 undef, i1 false +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %band = and i1 undef, undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %sor = select i1 undef, i1 true, i1 undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %bor = or i1 undef, undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; +; CHECK-NEON-LABEL: 'op' +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %sand = select i1 undef, i1 undef, i1 false +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %band = and i1 undef, undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %sor = select i1 undef, i1 true, i1 undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %bor = or i1 undef, undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; +; CHECK-THUMB1-LABEL: 'op' +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %sand = select i1 undef, i1 undef, i1 false +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %band = and i1 undef, undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %sor = select i1 undef, i1 true, i1 undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %bor = or i1 undef, undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 1 for: ret void +; +; CHECK-THUMB2-LABEL: 'op' +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %sand = select i1 undef, i1 undef, i1 false +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %band = and i1 undef, undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %sor = select i1 undef, i1 true, i1 undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %bor = or i1 undef, undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 1 for: ret void ; %sand = select i1 undef, i1 undef, i1 false %band = and i1 undef, undef @@ -77,61 +45,33 @@ define void @op() { } define void @vecop() { -; CHECK-MVE-RECIP-LABEL: 'vecop' -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and <4 x i1> undef, undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; CHECK-NEON-RECIP-LABEL: 'vecop' -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and <4 x i1> undef, undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; CHECK-THUMB1-RECIP-LABEL: 'vecop' -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %band = and <4 x i1> undef, undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB2-RECIP-LABEL: 'vecop' -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %band = and <4 x i1> undef, undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-MVE-SIZE-LABEL: 'vecop' -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and <4 x i1> undef, undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-NEON-SIZE-LABEL: 'vecop' -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and <4 x i1> undef, undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB1-SIZE-LABEL: 'vecop' -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %band = and <4 x i1> undef, undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB2-SIZE-LABEL: 'vecop' -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %band = and <4 x i1> undef, undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %bor = or <4 x i1> undef, undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-MVE-LABEL: 'vecop' +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %band = and <4 x i1> undef, undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %bor = or <4 x i1> undef, undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; +; CHECK-NEON-LABEL: 'vecop' +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %band = and <4 x i1> undef, undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %bor = or <4 x i1> undef, undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void +; +; CHECK-THUMB1-LABEL: 'vecop' +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 4 for: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 4 for: %band = and <4 x i1> undef, undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 4 for: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 4 for: %bor = or <4 x i1> undef, undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 1 for: ret void +; +; CHECK-THUMB2-LABEL: 'vecop' +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 4 for: %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> zeroinitializer +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 4 for: %band = and <4 x i1> undef, undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 4 for: %sor = select <4 x i1> undef, <4 x i1> splat (i1 true), <4 x i1> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 4 for: %bor = or <4 x i1> undef, undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 1 for: ret void ; %sand = select <4 x i1> undef, <4 x i1> undef, <4 x i1> <i1 false, i1 false, i1 false, i1 false> %band = and <4 x i1> undef, undef diff --git a/llvm/test/Analysis/CostModel/ARM/mul-cast-vect.ll b/llvm/test/Analysis/CostModel/ARM/mul-cast-vect.ll index 17d4263..07d2bd0 100644 --- a/llvm/test/Analysis/CostModel/ARM/mul-cast-vect.ll +++ b/llvm/test/Analysis/CostModel/ARM/mul-cast-vect.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s + ; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s ; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM @@ -17,11 +18,11 @@ target triple = "armv7--linux-gnueabihf" define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'direct' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = mul <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 @@ -36,13 +37,13 @@ define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'ups1632' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = sext <4 x i16> %v0 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext <4 x i16> %v1 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %r1, %r2 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = sext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = sext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = mul <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T416, ptr %loadaddr ; ASM: vldr @@ -59,13 +60,13 @@ define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'upu1632' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext <4 x i16> %v0 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = zext <4 x i16> %v1 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %r1, %r2 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = zext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = zext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = mul <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T416, ptr %loadaddr ; ASM: vldr @@ -82,12 +83,12 @@ define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'ups3264' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = mul <2 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = sext <2 x i32> %r3 to <2 x i64> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = mul <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = sext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T232, ptr %loadaddr ; ASM: vldr @@ -104,12 +105,12 @@ define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'upu3264' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = mul <2 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = zext <2 x i32> %r3 to <2 x i64> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = mul <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = zext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T232, ptr %loadaddr ; ASM: vldr @@ -126,12 +127,12 @@ define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @dn3216(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'dn3216' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = mul <4 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = trunc <4 x i32> %r3 to <4 x i16> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = mul <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = trunc <4 x i32> %r3 to <4 x i16> +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 diff --git a/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll b/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll index 7de2799..3ae02cd 100644 --- a/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll +++ b/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll @@ -1,21 +1,21 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP define i64 @test(i16 %a, i16 %b) { ; CHECK-LABEL: 'test' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = sext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = sext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: %as = sext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %bs = sext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %ms ; ; CHECK-NO-DSP-LABEL: 'test' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = sext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = sext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %as = sext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %bs = sext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %ms ; %as = sext i16 %a to i32 %bs = sext i16 %b to i32 @@ -26,20 +26,20 @@ define i64 @test(i16 %a, i16 %b) { define i64 @withadd(i16 %a, i16 %b, i64 %c) { ; CHECK-LABEL: 'withadd' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = sext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = sext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NEXT: Cost Model: Found costs of 1 for: %as = sext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %bs = sext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; ; CHECK-NO-DSP-LABEL: 'withadd' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = sext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = sext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %as = sext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %bs = sext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; %as = sext i16 %a to i32 %bs = sext i16 %b to i32 @@ -51,24 +51,24 @@ define i64 @withadd(i16 %a, i16 %b, i64 %c) { define i64 @withloads(ptr %pa, ptr %pb, i64 %c) { ; CHECK-LABEL: 'withloads' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = load i16, ptr %pa, align 2 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = load i16, ptr %pb, align 2 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = sext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %bs = sext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %a = load i16, ptr %pa, align 2 +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %b = load i16, ptr %pb, align 2 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %as = sext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %bs = sext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; ; CHECK-NO-DSP-LABEL: 'withloads' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = load i16, ptr %pa, align 2 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = load i16, ptr %pb, align 2 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = sext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %bs = sext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %a = load i16, ptr %pa, align 2 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %b = load i16, ptr %pb, align 2 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 0 for: %as = sext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 0 for: %bs = sext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; %a = load i16, ptr %pa %b = load i16, ptr %pb @@ -82,18 +82,18 @@ define i64 @withloads(ptr %pa, ptr %pb, i64 %c) { define i64 @different_extend_ops(i16 %a, i16 %b) { ; CHECK-LABEL: 'different_extend_ops' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = sext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = zext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: %as = sext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %bs = zext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %ms ; ; CHECK-NO-DSP-LABEL: 'different_extend_ops' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = sext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = zext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = sext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %as = sext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %bs = zext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = sext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %ms ; %as = sext i16 %a to i32 %bs = zext i16 %b to i32 diff --git a/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll b/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll index 521816d13..04a9520 100644 --- a/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll +++ b/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll @@ -1,20 +1,21 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s -; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP + define i64 @test(i16 %a, i16 %b) { ; CHECK-LABEL: 'test' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = zext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = zext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = zext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: %as = zext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %bs = zext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = zext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %ms ; ; CHECK-NO-DSP-LABEL: 'test' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = zext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = zext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = zext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %as = zext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %bs = zext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = zext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %ms ; %as = zext i16 %a to i32 %bs = zext i16 %b to i32 @@ -25,20 +26,20 @@ define i64 @test(i16 %a, i16 %b) { define i64 @withadd(i16 %a, i16 %b, i64 %c) { ; CHECK-LABEL: 'withadd' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = zext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = zext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = zext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NEXT: Cost Model: Found costs of 1 for: %as = zext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 1 for: %bs = zext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = zext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; ; CHECK-NO-DSP-LABEL: 'withadd' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %as = zext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bs = zext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = zext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %as = zext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %bs = zext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = zext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; %as = zext i16 %a to i32 %bs = zext i16 %b to i32 @@ -50,24 +51,24 @@ define i64 @withadd(i16 %a, i16 %b, i64 %c) { define i64 @withloads(ptr %pa, ptr %pb, i64 %c) { ; CHECK-LABEL: 'withloads' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = load i16, ptr %pa, align 2 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = load i16, ptr %pb, align 2 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = zext i16 %a to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %bs = zext i16 %b to i32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %m = mul i32 %as, %bs -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = zext i32 %m to i64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %a = load i16, ptr %pa, align 2 +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %b = load i16, ptr %pb, align 2 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %as = zext i16 %a to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %bs = zext i16 %b to i32 +; CHECK-NEXT: Cost Model: Found costs of 0 for: %m = mul i32 %as, %bs +; CHECK-NEXT: Cost Model: Found costs of 1 for: %ms = zext i32 %m to i64 +; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; ; CHECK-NO-DSP-LABEL: 'withloads' -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = load i16, ptr %pa, align 2 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = load i16, ptr %pb, align 2 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %as = zext i16 %a to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %bs = zext i16 %b to i32 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %m = mul i32 %as, %bs -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %ms = zext i32 %m to i64 -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = add i64 %c, %ms -; CHECK-NO-DSP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i64 %r +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %a = load i16, ptr %pa, align 2 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %b = load i16, ptr %pb, align 2 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 0 for: %as = zext i16 %a to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 0 for: %bs = zext i16 %b to i32 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %m = mul i32 %as, %bs +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: %ms = zext i32 %m to i64 +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 2 for: %r = add i64 %c, %ms +; CHECK-NO-DSP-NEXT: Cost Model: Found costs of 1 for: ret i64 %r ; %a = load i16, ptr %pa %b = load i16, ptr %pb diff --git a/llvm/test/Analysis/CostModel/ARM/select.ll b/llvm/test/Analysis/CostModel/ARM/select.ll index f626901..de429fd2 100644 --- a/llvm/test/Analysis/CostModel/ARM/select.ll +++ b/llvm/test/Analysis/CostModel/ARM/select.ll @@ -1,272 +1,140 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2-RECIP -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1-SIZE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2-SIZE +; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON +; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1 +; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define void @selects() { ; Scalar values -; CHECK-MVE-RECIP-LABEL: 'selects' -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-LABEL: 'selects' +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %v0 = select i1 undef, i1 undef, i1 undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v1 = select i1 undef, i8 undef, i8 undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v2 = select i1 undef, i16 undef, i16 undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v3 = select i1 undef, i32 undef, i32 undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v4 = select i1 undef, i64 undef, i64 undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v5 = select i1 undef, float undef, float undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v6 = select i1 undef, double undef, double undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:6 Lat:10 SizeLat:10 for: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; -; CHECK-NEON-RECIP-LABEL: 'selects' -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 100 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-LABEL: 'selects' +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %v0 = select i1 undef, i1 undef, i1 undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v1 = select i1 undef, i8 undef, i8 undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v2 = select i1 undef, i16 undef, i16 undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v3 = select i1 undef, i32 undef, i32 undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v4 = select i1 undef, i64 undef, i64 undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v5 = select i1 undef, float undef, float undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v6 = select i1 undef, double undef, double undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 19 for: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 50 for: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 100 for: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; -; CHECK-THUMB1-RECIP-LABEL: 'selects' -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-THUMB1-LABEL: 'selects' +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %v0 = select i1 undef, i1 undef, i1 undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v1 = select i1 undef, i8 undef, i8 undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v2 = select i1 undef, i16 undef, i16 undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v3 = select i1 undef, i32 undef, i32 undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v4 = select i1 undef, i64 undef, i64 undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v5 = select i1 undef, float undef, float undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v6 = select i1 undef, double undef, double undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:16 SizeLat:16 for: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:48 Lat:32 SizeLat:32 for: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:16 SizeLat:16 for: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:48 Lat:32 SizeLat:32 for: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:16 SizeLat:16 for: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:48 Lat:32 SizeLat:32 for: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:16 SizeLat:16 for: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:40 Lat:32 SizeLat:32 for: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:64 CodeSize:80 Lat:64 SizeLat:64 for: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:6 SizeLat:6 for: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:25 Lat:20 SizeLat:20 for: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef +; CHECK-THUMB1-NEXT: Cost Model: Found costs of 1 for: ret void ; -; CHECK-THUMB2-RECIP-LABEL: 'selects' -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-MVE-SIZE-LABEL: 'selects' -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-NEON-SIZE-LABEL: 'selects' -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 100 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB1-SIZE-LABEL: 'selects' -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void -; -; CHECK-THUMB2-SIZE-LABEL: 'selects' -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v0 = select i1 undef, i1 undef, i1 undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = select i1 undef, i8 undef, i8 undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2 = select i1 undef, i16 undef, i16 undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3 = select i1 undef, i32 undef, i32 undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4 = select i1 undef, i64 undef, i64 undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v5 = select i1 undef, float undef, float undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v6 = select i1 undef, double undef, double undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef -; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; CHECK-THUMB2-LABEL: 'selects' +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:3 Lat:1 SizeLat:1 for: %v0 = select i1 undef, i1 undef, i1 undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v1 = select i1 undef, i8 undef, i8 undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v2 = select i1 undef, i16 undef, i16 undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v3 = select i1 undef, i32 undef, i32 undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v4 = select i1 undef, i64 undef, i64 undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:1 SizeLat:1 for: %v5 = select i1 undef, float undef, float undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v6 = select i1 undef, double undef, double undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:16 SizeLat:16 for: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:48 Lat:32 SizeLat:32 for: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:16 SizeLat:16 for: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:48 Lat:32 SizeLat:32 for: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:16 SizeLat:16 for: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:48 Lat:32 SizeLat:32 for: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:16 SizeLat:16 for: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:40 Lat:32 SizeLat:32 for: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:64 CodeSize:80 Lat:64 SizeLat:64 for: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:6 Lat:4 SizeLat:4 for: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:8 SizeLat:8 for: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:9 Lat:6 SizeLat:6 for: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of RThru:20 CodeSize:25 Lat:20 SizeLat:20 for: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef +; CHECK-THUMB2-NEXT: Cost Model: Found costs of 1 for: ret void ; %v0 = select i1 undef, i1 undef, i1 undef %v1 = select i1 undef, i8 undef, i8 undef diff --git a/llvm/test/Analysis/CostModel/ARM/shl-cast-vect.ll b/llvm/test/Analysis/CostModel/ARM/shl-cast-vect.ll index 465611d..5ef869e 100644 --- a/llvm/test/Analysis/CostModel/ARM/shl-cast-vect.ll +++ b/llvm/test/Analysis/CostModel/ARM/shl-cast-vect.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s + ; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s ; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM @@ -17,11 +18,11 @@ target triple = "armv7--linux-gnueabihf" define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'direct' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = shl <4 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = shl <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 @@ -36,13 +37,13 @@ define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'ups1632' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = sext <4 x i16> %v0 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext <4 x i16> %v1 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = shl <4 x i32> %r1, %r2 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = sext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = sext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = shl <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T416, ptr %loadaddr ; ASM: vldr @@ -59,13 +60,13 @@ define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'upu1632' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext <4 x i16> %v0 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = zext <4 x i16> %v1 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = shl <4 x i32> %r1, %r2 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = zext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = zext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = shl <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T416, ptr %loadaddr ; ASM: vldr @@ -82,12 +83,12 @@ define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'ups3264' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = shl <2 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = sext <2 x i32> %r3 to <2 x i64> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = shl <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = sext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T232, ptr %loadaddr ; ASM: vldr @@ -104,12 +105,12 @@ define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'upu3264' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = shl <2 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = zext <2 x i32> %r3 to <2 x i64> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = shl <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = zext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T232, ptr %loadaddr ; ASM: vldr @@ -126,12 +127,12 @@ define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @dn3216(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'dn3216' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r3 = shl <4 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = trunc <4 x i32> %r3 to <4 x i16> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %r3 = shl <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = trunc <4 x i32> %r3 to <4 x i16> +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 diff --git a/llvm/test/Analysis/CostModel/ARM/shuffle.ll b/llvm/test/Analysis/CostModel/ARM/shuffle.ll index a17bbab..0fd1456 100644 --- a/llvm/test/Analysis/CostModel/ARM/shuffle.ll +++ b/llvm/test/Analysis/CostModel/ARM/shuffle.ll @@ -1,59 +1,59 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" define void @broadcast() { ; CHECK-MVE-LABEL: 'broadcast' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> zeroinitializer -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:12 Lat:24 SizeLat:24 for: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:12 Lat:24 SizeLat:24 for: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:12 Lat:24 SizeLat:24 for: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:48 CodeSize:24 Lat:48 SizeLat:48 for: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:40 Lat:80 SizeLat:80 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:3 Lat:6 SizeLat:6 for: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:10 SizeLat:10 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> zeroinitializer +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'broadcast' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> zeroinitializer -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 8 for: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 14 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 26 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 50 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> zeroinitializer +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> zeroinitializer %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer @@ -90,58 +90,58 @@ define void @broadcast() { ;; Reverse shuffles should be lowered to vrev and possibly a vext (for quadwords, on neon) define void @reverse() { ; CHECK-MVE-LABEL: 'reverse' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v3i24 = shufflevector <3 x i24> undef, <3 x i24> undef, <3 x i32> <i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v3i124 = shufflevector <3 x i124> undef, <3 x i124> undef, <3 x i32> <i32 2, i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:256 CodeSize:128 Lat:256 SizeLat:256 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:256 CodeSize:128 Lat:256 SizeLat:256 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:48 CodeSize:24 Lat:48 SizeLat:48 for: %v3i24 = shufflevector <3 x i24> undef, <3 x i24> undef, <3 x i32> <i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:192 CodeSize:96 Lat:192 SizeLat:192 for: %v3i124 = shufflevector <3 x i124> undef, <3 x i124> undef, <3 x i32> <i32 2, i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'reverse' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i24 = shufflevector <3 x i24> undef, <3 x i24> undef, <3 x i32> <i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v3i124 = shufflevector <3 x i124> undef, <3 x i124> undef, <3 x i32> <i32 2, i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 10 for: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 20 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 80 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v3i24 = shufflevector <3 x i24> undef, <3 x i24> undef, <3 x i32> <i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 18 for: %v3i124 = shufflevector <3 x i124> undef, <3 x i124> undef, <3 x i32> <i32 2, i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 1, i32 0> %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> @@ -179,40 +179,40 @@ define void @reverse() { define void @concat() { ; CHECK-MVE-LABEL: 'concat' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = shufflevector <2 x half> undef, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f16 = shufflevector <4 x half> undef, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f16 = shufflevector <8 x half> undef, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f32 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f32 = shufflevector <4 x float> undef, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f64 = shufflevector <2 x double> undef, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v4f16 = shufflevector <2 x half> undef, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v8f16 = shufflevector <4 x half> undef, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v16f16 = shufflevector <8 x half> undef, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v4f32 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v8f32 = shufflevector <4 x float> undef, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v4f64 = shufflevector <2 x double> undef, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'concat' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v4f16 = shufflevector <2 x half> undef, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v8f16 = shufflevector <4 x half> undef, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v16f16 = shufflevector <8 x half> undef, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v4f32 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v8f32 = shufflevector <4 x float> undef, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4f64 = shufflevector <2 x double> undef, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 12 for: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 12 for: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 12 for: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 12 for: %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 10 for: %v4f16 = shufflevector <2 x half> undef, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 20 for: %v8f16 = shufflevector <4 x half> undef, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v16f16 = shufflevector <8 x half> undef, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 10 for: %v4f32 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 20 for: %v8f32 = shufflevector <4 x float> undef, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v4f64 = shufflevector <2 x double> undef, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -241,54 +241,54 @@ define void @concat() { define void @select() { ; CHECK-MVE-LABEL: 'select' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 0, i32 3> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 0, i32 3> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:256 CodeSize:128 Lat:256 SizeLat:256 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:256 CodeSize:128 Lat:256 SizeLat:256 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'select' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 0, i32 3> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 6 for: %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 0, i32 3> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 32 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 16 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 32 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 10 for: %v2f16 = shufflevector <2 x half> undef, <2 x half> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 20 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 80 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2f32 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 15> +; CHECK-NEON-NEXT: Cost Model: Found costs of 1 for: %v2f64 = shufflevector <2 x double> undef, <2 x double> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEON-NEXT: Cost Model: Found costs of 2 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 0, i32 3> %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7> @@ -324,40 +324,40 @@ define void @select() { define void @vrev2() { ; CHECK-MVE-LABEL: 'vrev2' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:256 CodeSize:128 Lat:256 SizeLat:256 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:16 SizeLat:16 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'vrev2' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-NEON-NEXT: Cost Model: Found costs of 96 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-NEON-NEXT: Cost Model: Found costs of 96 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-NEON-NEXT: Cost Model: Found costs of 24 for: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of 20 for: %v4f16 = shufflevector <4 x half> undef, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-NEON-NEXT: Cost Model: Found costs of 80 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> +; CHECK-NEON-NEXT: Cost Model: Found costs of 20 for: %v4f32 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> +; CHECK-NEON-NEXT: Cost Model: Found costs of 8 for: %v4f64 = shufflevector <4 x double> undef, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> @@ -386,26 +386,26 @@ define void @vrev2() { define void @vrev4() { ; CHECK-MVE-LABEL: 'vrev4' -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:256 CodeSize:128 Lat:256 SizeLat:256 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:128 CodeSize:64 Lat:128 SizeLat:128 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:32 Lat:64 SizeLat:64 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:16 Lat:32 SizeLat:32 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; CHECK-NEON-LABEL: 'vrev4' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-NEON-NEXT: Cost Model: Found costs of 96 for: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-NEON-NEXT: Cost Model: Found costs of 96 for: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> +; CHECK-NEON-NEXT: Cost Model: Found costs of 48 for: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v8f16 = shufflevector <8 x half> undef, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-NEON-NEXT: Cost Model: Found costs of 80 for: %v16f16 = shufflevector <16 x half> undef, <16 x half> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> +; CHECK-NEON-NEXT: Cost Model: Found costs of 40 for: %v8f32 = shufflevector <8 x float> undef, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> +; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> diff --git a/llvm/test/Analysis/CostModel/ARM/sub-cast-vect.ll b/llvm/test/Analysis/CostModel/ARM/sub-cast-vect.ll index df26121..924a629 100644 --- a/llvm/test/Analysis/CostModel/ARM/sub-cast-vect.ll +++ b/llvm/test/Analysis/CostModel/ARM/sub-cast-vect.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s +; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s + ; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s ; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM @@ -17,11 +18,11 @@ target triple = "armv7--linux-gnueabihf" define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'direct' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = sub <4 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = sub <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 @@ -36,13 +37,13 @@ define void @direct(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'ups1632' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = sext <4 x i16> %v0 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext <4 x i16> %v1 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = sub <4 x i32> %r1, %r2 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = sext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = sext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = sub <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T416, ptr %loadaddr ; ASM: vldr @@ -59,13 +60,13 @@ define void @ups1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'upu1632' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i16>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext <4 x i16> %v0 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = zext <4 x i16> %v1 to <4 x i32> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = sub <4 x i32> %r1, %r2 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %r3, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i16>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 0 for: %r1 = zext <4 x i16> %v0 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 0 for: %r2 = zext <4 x i16> %v1 to <4 x i32> +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = sub <4 x i32> %r1, %r2 +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> %r3, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T416, ptr %loadaddr ; ASM: vldr @@ -82,12 +83,12 @@ define void @upu1632(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'ups3264' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = sub <2 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = sext <2 x i32> %r3 to <2 x i64> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = sub <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = sext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T232, ptr %loadaddr ; ASM: vldr @@ -104,12 +105,12 @@ define void @ups3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'upu3264' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <2 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = sub <2 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = zext <2 x i32> %r3 to <2 x i64> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x i64> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <2 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = sub <2 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = zext <2 x i32> %r3 to <2 x i64> +; COST-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T232, ptr %loadaddr ; ASM: vldr @@ -126,12 +127,12 @@ define void @upu3264(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { define void @dn3216(ptr %loadaddr, ptr %loadaddr2, ptr %storeaddr) { ; COST-LABEL: 'dn3216' -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = load <4 x i32>, ptr %loadaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = sub <4 x i32> %v0, %v1 -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %st = trunc <4 x i32> %r3 to <4 x i16> -; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %st, ptr %storeaddr, align 8 -; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i32>, ptr %loadaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load <4 x i32>, ptr %loadaddr2, align 8 +; COST-NEXT: Cost Model: Found costs of 1 for: %r3 = sub <4 x i32> %v0, %v1 +; COST-NEXT: Cost Model: Found costs of 1 for: %st = trunc <4 x i32> %r3 to <4 x i16> +; COST-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %st, ptr %storeaddr, align 8 +; COST-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v0 = load %T432, ptr %loadaddr ; ASM: vld1.64 diff --git a/llvm/test/CodeGen/AMDGPU/add-max.ll b/llvm/test/CodeGen/AMDGPU/add-max.ll index b3a7057..c551375 100644 --- a/llvm/test/CodeGen/AMDGPU/add-max.ll +++ b/llvm/test/CodeGen/AMDGPU/add-max.ll @@ -7,7 +7,7 @@ define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_max_u32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret @@ -18,39 +18,38 @@ define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_max_u32 v0, s0, v0, v1 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret } define amdgpu_ps float @add_max_u32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) { -; SDAG-LABEL: add_max_u32_ssv: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_add_max_u32 v0, s0, s1, v0 -; SDAG-NEXT: ; return to shader part epilog -; -; GISEL-LABEL: add_max_u32_ssv: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_add_co_i32 s0, s0, s1 -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_max_u32_e32 v0, s0, v0 -; GISEL-NEXT: ; return to shader part epilog - %add = add i32 %a, %b +; GCN-LABEL: add_max_u32_ssv: +; GCN: ; %bb.0: +; GCN-NEXT: v_add_max_u32 v0, s0, s1, v0 +; GCN-NEXT: ; return to shader part epilog + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret } define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) { -; GCN-LABEL: add_max_u32_sss: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_co_i32 s0, s0, s1 -; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GCN-NEXT: s_max_u32 s0, s0, s2 -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b +; SDAG-LABEL: add_max_u32_sss: +; SDAG: ; %bb.0: +; SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp +; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-NEXT: v_max_u32_e32 v0, s2, v0 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: add_max_u32_sss: +; GISEL: ; %bb.0: +; GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-NEXT: v_add_max_u32 v0, s0, s1, v0 +; GISEL-NEXT: ; return to shader part epilog + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret @@ -61,7 +60,7 @@ define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_max_u32 v0, v0, s0, 4 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umax.i32(i32 %add, i32 4) %ret = bitcast i32 %max to float ret float %ret @@ -72,26 +71,19 @@ define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_max_u32 v0, s0, v0, 0x64 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umax.i32(i32 %add, i32 100) %ret = bitcast i32 %max to float ret float %ret } -define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b) { -; SDAG-LABEL: add_max_u32_slv: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_add_max_u32 v0, 0x64, s0, v0 -; SDAG-NEXT: ; return to shader part epilog -; -; GISEL-LABEL: add_max_u32_slv: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_addk_co_i32 s0, 0x64 -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_max_u32_e32 v0, s0, v0 -; GISEL-NEXT: ; return to shader part epilog - %add = add i32 %a, 100 - %max = call i32 @llvm.umax.i32(i32 %add, i32 %b) +define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b, i32 %c) { +; GCN-LABEL: add_max_u32_slv: +; GCN: ; %bb.0: +; GCN-NEXT: v_add_max_u32 v0, s0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) + %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret } @@ -101,7 +93,7 @@ define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_max_i32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.sadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.smax.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret @@ -112,7 +104,7 @@ define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_min_u32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.umin.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret @@ -123,7 +115,7 @@ define amdgpu_ps float @add_min_i32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN: ; %bb.0: ; GCN-NEXT: v_add_min_i32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add i32 %a, %b + %add = call i32 @llvm.sadd.sat.i32(i32 %a, i32 %b) %max = call i32 @llvm.smin.i32(i32 %add, i32 %c) %ret = bitcast i32 %max to float ret float %ret @@ -134,7 +126,7 @@ define amdgpu_ps float @add_max_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_max_u16 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -145,29 +137,18 @@ define amdgpu_ps float @add_max_v2u16_svv(<2 x i16> inreg %a, <2 x i16> %b, <2 x ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, v1 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret } define amdgpu_ps float @add_max_v2u16_ssv(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> %c) { -; SDAG-LABEL: add_max_v2u16_ssv: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_pk_add_max_u16 v0, s0, s1, v0 -; SDAG-NEXT: ; return to shader part epilog -; -; GISEL-LABEL: add_max_v2u16_ssv: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_lshr_b32 s2, s0, 16 -; GISEL-NEXT: s_lshr_b32 s3, s1, 16 -; GISEL-NEXT: s_add_co_i32 s0, s0, s1 -; GISEL-NEXT: s_add_co_i32 s2, s2, s3 -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GISEL-NEXT: v_pk_max_u16 v0, s0, v0 -; GISEL-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b +; GCN-LABEL: add_max_v2u16_ssv: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_add_max_u16 v0, s0, s1, v0 +; GCN-NEXT: ; return to shader part epilog + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -176,30 +157,18 @@ define amdgpu_ps float @add_max_v2u16_ssv(<2 x i16> inreg %a, <2 x i16> inreg %b define amdgpu_ps float @add_max_v2u16_sss(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> inreg %c) { ; SDAG-LABEL: add_max_v2u16_sss: ; SDAG: ; %bb.0: -; SDAG-NEXT: v_pk_add_u16 v0, s0, s1 +; SDAG-NEXT: v_pk_add_u16 v0, s0, s1 clamp ; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; SDAG-NEXT: v_pk_max_u16 v0, v0, s2 ; SDAG-NEXT: ; return to shader part epilog ; ; GISEL-LABEL: add_max_v2u16_sss: ; GISEL: ; %bb.0: -; GISEL-NEXT: s_lshr_b32 s3, s0, 16 -; GISEL-NEXT: s_lshr_b32 s4, s1, 16 -; GISEL-NEXT: s_add_co_i32 s0, s0, s1 -; GISEL-NEXT: s_add_co_i32 s3, s3, s4 -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s3 -; GISEL-NEXT: s_and_b32 s3, s2, 0xffff -; GISEL-NEXT: s_lshr_b32 s1, s0, 16 -; GISEL-NEXT: s_and_b32 s0, s0, 0xffff -; GISEL-NEXT: s_lshr_b32 s2, s2, 16 -; GISEL-NEXT: s_max_u32 s0, s0, s3 -; GISEL-NEXT: s_max_u32 s1, s1, s2 -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1 -; GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-NEXT: v_pk_add_max_u16 v0, s0, s1, v0 ; GISEL-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -210,7 +179,7 @@ define amdgpu_ps float @add_max_v2u16_vsi(<2 x i16> %a, <2 x i16> inreg %b) { ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_max_u16 v0, v0, s0, 4 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> <i16 4, i16 0>) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -221,28 +190,18 @@ define amdgpu_ps float @add_max_v2u16_svl(<2 x i16> inreg %a, <2 x i16> %b) { ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, 0x650064 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> <i16 100, i16 101>) %ret = bitcast <2 x i16> %max to float ret float %ret } define amdgpu_ps float @add_max_v2u16_slv(<2 x i16> inreg %a, <2 x i16> %b) { -; SDAG-LABEL: add_max_v2u16_slv: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_pk_add_max_u16 v0, 0x640064, s0, v0 -; SDAG-NEXT: ; return to shader part epilog -; -; GISEL-LABEL: add_max_v2u16_slv: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_lshr_b32 s1, s0, 16 -; GISEL-NEXT: s_add_co_i32 s0, s0, 0x640064 -; GISEL-NEXT: s_addk_co_i32 s1, 0x64 -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1 -; GISEL-NEXT: v_pk_max_u16 v0, s0, v0 -; GISEL-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, <i16 100, i16 100> +; GCN-LABEL: add_max_v2u16_slv: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_add_max_u16 v0, 0x640064, s0, v0 +; GCN-NEXT: ; return to shader part epilog + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> <i16 100, i16 100>) %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %b) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -253,7 +212,7 @@ define amdgpu_ps float @add_max_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_max_i16 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.sadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.smax.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -264,7 +223,7 @@ define amdgpu_ps float @add_min_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_min_u16 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.umin.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret @@ -275,7 +234,7 @@ define amdgpu_ps float @add_min_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> ; GCN: ; %bb.0: ; GCN-NEXT: v_pk_add_min_i16 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog - %add = add <2 x i16> %a, %b + %add = call <2 x i16> @llvm.sadd.sat.i32(<2 x i16> %a, <2 x i16> %b) %max = call <2 x i16> @llvm.smin.v216(<2 x i16> %add, <2 x i16> %c) %ret = bitcast <2 x i16> %max to float ret float %ret diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index 711d57b..30ad46d9 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -39131,21 +39131,21 @@ define bfloat @v_sitofp_i64_to_bf16(i64 %x) { ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_xor_b32_e32 v2, v0, v1 ; GFX1250-NEXT: v_cls_i32_e32 v3, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: v_dual_add_nc_u32 v3, -1, v3 :: v_dual_bitop2_b32 v2, v0, v1 bitop3:0x14 ; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v2 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_add_nc_u32_e32 v2, 32, v2 +; GFX1250-NEXT: v_min_u32_e32 v2, v3, v2 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_min_u32 v2, v3, -1, v2 ; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v2, v[0:1] -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_min_u32_e32 v0, 1, v0 -; GFX1250-NEXT: v_dual_sub_nc_u32 v1, 32, v2 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: v_dual_sub_nc_u32 v1, 32, v2 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 ; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250-NEXT: s_set_pc_i64 s[30:31] %op = sitofp i64 %x to bfloat @@ -39483,29 +39483,30 @@ define <2 x bfloat> @v_sitofp_v2i64_to_v2bf16(<2 x i64> %x) { ; GFX1250-NEXT: v_xor_b32_e32 v4, v2, v3 ; GFX1250-NEXT: v_cls_i32_e32 v6, v3 ; GFX1250-NEXT: v_cls_i32_e32 v7, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-NEXT: v_dual_ashrrev_i32 v5, 31, v5 :: v_dual_ashrrev_i32 v4, 31, v4 +; GFX1250-NEXT: v_dual_add_nc_u32 v6, -1, v6 :: v_dual_add_nc_u32 v7, -1, v7 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_dual_add_nc_u32 v5, 32, v5 :: v_dual_add_nc_u32 v4, 32, v4 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_min_u32 v5, v7, -1, v5 -; GFX1250-NEXT: v_add_min_u32 v4, v6, -1, v4 +; GFX1250-NEXT: v_min_u32_e32 v5, v7, v5 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250-NEXT: v_min_u32_e32 v4, v6, v4 ; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v5, v[0:1] -; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v4, v[2:3] ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v4, v[2:3] ; GFX1250-NEXT: v_min_u32_e32 v0, 1, v0 -; GFX1250-NEXT: v_min_u32_e32 v2, 1, v2 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250-NEXT: v_min_u32_e32 v2, 1, v2 ; GFX1250-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX1250-NEXT: v_dual_sub_nc_u32 v1, 32, v4 :: v_dual_bitop2_b32 v2, v3, v2 bitop3:0x54 ; GFX1250-NEXT: v_sub_nc_u32_e32 v3, 32, v5 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-NEXT: v_ldexp_f32 v0, v0, v3 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_ldexp_f32 v1, v2, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 ; GFX1250-NEXT: s_set_pc_i64 s[30:31] %op = sitofp <2 x i64> %x to <2 x bfloat> @@ -39968,41 +39969,42 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX1250TRUE16: ; %bb.0: ; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_xor_b32_e32 v7, v2, v3 -; GFX1250TRUE16-NEXT: v_xor_b32_e32 v6, v4, v5 +; GFX1250TRUE16-NEXT: v_cls_i32_e32 v6, v5 +; GFX1250TRUE16-NEXT: v_xor_b32_e32 v7, v4, v5 ; GFX1250TRUE16-NEXT: v_cls_i32_e32 v10, v3 -; GFX1250TRUE16-NEXT: v_cls_i32_e32 v9, v5 ; GFX1250TRUE16-NEXT: v_cls_i32_e32 v11, v1 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_dual_ashrrev_i32 v7, 31, v7 :: v_dual_ashrrev_i32 v6, 31, v6 -; GFX1250TRUE16-NEXT: v_xor_b32_e32 v8, v0, v1 -; GFX1250TRUE16-NEXT: v_dual_add_nc_u32 v7, 32, v7 :: v_dual_add_nc_u32 v6, 32, v6 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8 -; GFX1250TRUE16-NEXT: v_add_min_u32 v7, v10, -1, v7 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_add_min_u32 v6, v9, -1, v6 -; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[2:3], v7, v[2:3] -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[4:5], v6, v[4:5] -; GFX1250TRUE16-NEXT: v_min_u32_e32 v2, 1, v2 -; GFX1250TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_dual_add_nc_u32 v6, -1, v6 :: v_dual_bitop2_b32 v9, v0, v1 bitop3:0x14 +; GFX1250TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_dual_ashrrev_i32 v9, 31, v9 :: v_dual_bitop2_b32 v8, v2, v3 bitop3:0x14 +; GFX1250TRUE16-NEXT: v_dual_add_nc_u32 v7, 32, v7 :: v_dual_ashrrev_i32 v8, 31, v8 +; GFX1250TRUE16-NEXT: v_dual_add_nc_u32 v10, -1, v10 :: v_dual_add_nc_u32 v11, -1, v11 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_add_nc_u32_e32 v9, 32, v9 +; GFX1250TRUE16-NEXT: v_min_u32_e32 v6, v6, v7 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8 +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[4:5], v6, v[4:5] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v7, v10, v8 +; GFX1250TRUE16-NEXT: v_min_u32_e32 v8, v11, v9 +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[2:3], v7, v[2:3] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[0:1], v8, v[0:1] ; GFX1250TRUE16-NEXT: v_min_u32_e32 v4, 1, v4 -; GFX1250TRUE16-NEXT: v_or_b32_e32 v2, v3, v2 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250TRUE16-NEXT: v_add_min_u32 v8, v11, -1, v8 -; GFX1250TRUE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v4, v5, v4 bitop3:0x54 +; GFX1250TRUE16-NEXT: v_min_u32_e32 v2, 1, v2 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[0:1], v8, v[0:1] -; GFX1250TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_min_u32_e32 v0, 1, v0 -; GFX1250TRUE16-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX1250TRUE16-NEXT: v_or_b32_e32 v4, v5, v4 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_dual_sub_nc_u32 v5, 32, v8 :: v_dual_bitop2_b32 v2, v3, v2 bitop3:0x54 +; GFX1250TRUE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v4 ; GFX1250TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v7 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0 ; GFX1250TRUE16-NEXT: v_ldexp_f32 v1, v1, v3 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) @@ -40017,44 +40019,47 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX1250FAKE16: ; %bb.0: ; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_xor_b32_e32 v8, v4, v5 -; GFX1250FAKE16-NEXT: v_xor_b32_e32 v6, v2, v3 +; GFX1250FAKE16-NEXT: v_cls_i32_e32 v6, v5 +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v7, v2, v3 ; GFX1250FAKE16-NEXT: v_cls_i32_e32 v10, v3 -; GFX1250FAKE16-NEXT: v_cls_i32_e32 v9, v5 ; GFX1250FAKE16-NEXT: v_cls_i32_e32 v11, v1 -; GFX1250FAKE16-NEXT: v_dual_ashrrev_i32 v8, 31, v8 :: v_dual_bitop2_b32 v7, v0, v1 bitop3:0x14 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_dual_ashrrev_i32 v6, 31, v6 :: v_dual_ashrrev_i32 v7, 31, v7 -; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v6, 32, v6 :: v_dual_add_nc_u32 v7, 32, v7 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_add_min_u32 v6, v10, -1, v6 -; GFX1250FAKE16-NEXT: v_add_min_u32 v7, v11, -1, v7 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v6, -1, v6 :: v_dual_bitop2_b32 v8, v4, v5 bitop3:0x14 +; GFX1250FAKE16-NEXT: v_dual_ashrrev_i32 v7, 31, v7 :: v_dual_bitop2_b32 v9, v0, v1 bitop3:0x14 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[2:3], v6, v[2:3] -; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[0:1], v7, v[0:1] -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1250FAKE16-NEXT: v_min_u32_e32 v2, 1, v2 -; GFX1250FAKE16-NEXT: v_add_nc_u32_e32 v8, 32, v8 -; GFX1250FAKE16-NEXT: v_min_u32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v10, -1, v10 :: v_dual_ashrrev_i32 v8, 31, v8 +; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v11, -1, v11 :: v_dual_ashrrev_i32 v9, 31, v9 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v7, 32, v7 :: v_dual_add_nc_u32 v8, 32, v8 +; GFX1250FAKE16-NEXT: v_add_nc_u32_e32 v9, 32, v9 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v7, v10, v7 +; GFX1250FAKE16-NEXT: v_min_u32_e32 v6, v6, v8 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250FAKE16-NEXT: v_or_b32_e32 v2, v3, v2 -; GFX1250FAKE16-NEXT: v_add_min_u32 v8, v9, -1, v8 +; GFX1250FAKE16-NEXT: v_min_u32_e32 v9, v11, v9 +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[2:3], v7, v[2:3] ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 -; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[4:5], v8, v[4:5] -; GFX1250FAKE16-NEXT: v_sub_nc_u32_e32 v8, 32, v8 -; GFX1250FAKE16-NEXT: v_ldexp_f32 v2, v2, v3 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[4:5], v6, v[4:5] +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[0:1], v9, v[0:1] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v2, 1, v2 ; GFX1250FAKE16-NEXT: v_min_u32_e32 v4, 1, v4 -; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v4, 32, v7 :: v_dual_bitop2_b32 v1, v5, v4 bitop3:0x54 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: v_sub_nc_u32_e32 v6, 32, v6 +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v3, 32, v7 :: v_dual_bitop2_b32 v2, v3, v2 bitop3:0x54 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v4, 32, v9 :: v_dual_bitop2_b32 v1, v5, v4 bitop3:0x54 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v2, v2, v3 ; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v4 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_ldexp_f32 v1, v1, v8 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v1, v1, v6 ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 @@ -40644,51 +40649,54 @@ define <4 x bfloat> @v_sitofp_v4i64_to_v4bf16(<4 x i64> %x) { ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_xor_b32_e32 v9, v4, v5 +; GFX1250-NEXT: v_cls_i32_e32 v9, v7 ; GFX1250-NEXT: v_xor_b32_e32 v8, v6, v7 -; GFX1250-NEXT: v_cls_i32_e32 v12, v7 -; GFX1250-NEXT: v_cls_i32_e32 v13, v5 -; GFX1250-NEXT: v_cls_i32_e32 v14, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_dual_ashrrev_i32 v9, 31, v9 :: v_dual_ashrrev_i32 v8, 31, v8 -; GFX1250-NEXT: v_xor_b32_e32 v10, v2, v3 -; GFX1250-NEXT: v_cls_i32_e32 v15, v1 -; GFX1250-NEXT: v_dual_add_nc_u32 v9, 32, v9 :: v_dual_add_nc_u32 v8, 32, v8 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_dual_ashrrev_i32 v10, 31, v10 :: v_dual_bitop2_b32 v11, v0, v1 bitop3:0x14 -; GFX1250-NEXT: v_add_min_u32 v9, v13, -1, v9 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_add_min_u32 v8, v12, -1, v8 -; GFX1250-NEXT: v_dual_ashrrev_i32 v11, 31, v11 :: v_dual_add_nc_u32 v10, 32, v10 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_lshlrev_b64_e32 v[4:5], v9, v[4:5] -; GFX1250-NEXT: v_lshlrev_b64_e32 v[6:7], v8, v[6:7] -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_add_nc_u32_e32 v11, 32, v11 -; GFX1250-NEXT: v_add_min_u32 v10, v14, -1, v10 +; GFX1250-NEXT: v_cls_i32_e32 v10, v5 +; GFX1250-NEXT: v_xor_b32_e32 v14, v0, v1 +; GFX1250-NEXT: v_cls_i32_e32 v12, v3 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250-NEXT: v_dual_add_nc_u32 v9, -1, v9 :: v_dual_ashrrev_i32 v8, 31, v8 +; GFX1250-NEXT: v_dual_add_nc_u32 v10, -1, v10 :: v_dual_bitop2_b32 v11, v4, v5 bitop3:0x14 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_min_u32 v11, v15, -1, v11 -; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v10, v[2:3] -; GFX1250-NEXT: v_min_u32_e32 v6, 1, v6 -; GFX1250-NEXT: v_min_u32_e32 v4, 1, v4 +; GFX1250-NEXT: v_dual_add_nc_u32 v8, 32, v8 :: v_dual_bitop2_b32 v13, v2, v3 bitop3:0x14 +; GFX1250-NEXT: v_ashrrev_i32_e32 v11, 31, v11 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250-NEXT: v_min_u32_e32 v8, v9, v8 +; GFX1250-NEXT: v_ashrrev_i32_e32 v9, 31, v13 +; GFX1250-NEXT: v_cls_i32_e32 v13, v1 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250-NEXT: v_dual_ashrrev_i32 v14, 31, v14 :: v_dual_add_nc_u32 v11, 32, v11 +; GFX1250-NEXT: v_dual_add_nc_u32 v12, -1, v12 :: v_dual_add_nc_u32 v9, 32, v9 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250-NEXT: v_dual_add_nc_u32 v13, -1, v13 :: v_dual_add_nc_u32 v14, 32, v14 +; GFX1250-NEXT: v_min_u32_e32 v10, v10, v11 +; GFX1250-NEXT: v_lshlrev_b64_e32 v[6:7], v8, v[6:7] +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250-NEXT: v_min_u32_e32 v9, v12, v9 +; GFX1250-NEXT: v_min_u32_e32 v11, v13, v14 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250-NEXT: v_lshlrev_b64_e32 v[4:5], v10, v[4:5] +; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v9, v[2:3] +; GFX1250-NEXT: v_min_u32_e32 v6, 1, v6 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v11, v[0:1] +; GFX1250-NEXT: v_min_u32_e32 v4, 1, v4 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX1250-NEXT: v_or_b32_e32 v6, v7, v6 ; GFX1250-NEXT: v_min_u32_e32 v2, 1, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_dual_sub_nc_u32 v5, 32, v10 :: v_dual_bitop2_b32 v4, v5, v4 bitop3:0x54 -; GFX1250-NEXT: v_sub_nc_u32_e32 v7, 32, v9 +; GFX1250-NEXT: v_sub_nc_u32_e32 v7, 32, v10 ; GFX1250-NEXT: v_min_u32_e32 v0, 1, v0 -; GFX1250-NEXT: v_dual_sub_nc_u32 v3, 32, v8 :: v_dual_bitop2_b32 v2, v3, v2 bitop3:0x54 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cvt_f32_i32_e32 v4, v4 +; GFX1250-NEXT: v_dual_sub_nc_u32 v5, 32, v9 :: v_dual_bitop2_b32 v4, v5, v4 bitop3:0x54 +; GFX1250-NEXT: v_or_b32_e32 v2, v3, v2 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX1250-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v6 +; GFX1250-NEXT: v_sub_nc_u32_e32 v1, 32, v8 +; GFX1250-NEXT: v_cvt_f32_i32_e32 v3, v6 +; GFX1250-NEXT: v_cvt_f32_i32_e32 v4, v4 ; GFX1250-NEXT: v_sub_nc_u32_e32 v6, 32, v11 ; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GFX1250-NEXT: v_ldexp_f32 v1, v1, v3 +; GFX1250-NEXT: v_ldexp_f32 v1, v3, v1 ; GFX1250-NEXT: v_ldexp_f32 v3, v4, v7 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-NEXT: v_ldexp_f32 v2, v2, v5 diff --git a/llvm/test/CodeGen/AVR/dynalloca.ll b/llvm/test/CodeGen/AVR/dynalloca.ll index 3face71..b32910b 100644 --- a/llvm/test/CodeGen/AVR/dynalloca.ll +++ b/llvm/test/CodeGen/AVR/dynalloca.ll @@ -64,16 +64,16 @@ define void @dynalloca2(i16 %x) { ; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 61, {{.*}} ; Store values on the stack -; CHECK: ldi r20, 0 -; CHECK: ldi r21, 0 -; CHECK: std Z+8, r21 -; CHECK: std Z+7, r20 -; CHECK: std Z+6, r21 -; CHECK: std Z+5, r20 -; CHECK: std Z+4, r21 -; CHECK: std Z+3, r20 -; CHECK: std Z+2, r21 -; CHECK: std Z+1, r20 +; CHECK: ldi [[REG1:r[0-9]+]], 0 +; CHECK: ldi [[REG2:r[0-9]+]], 0 +; CHECK: std Z+8, [[REG2]] +; CHECK: std Z+7, [[REG1]] +; CHECK: std Z+6, [[REG2]] +; CHECK: std Z+5, [[REG1]] +; CHECK: std Z+4, [[REG2]] +; CHECK: std Z+3, [[REG1]] +; CHECK: std Z+2, [[REG2]] +; CHECK: std Z+1, [[REG1]] ; CHECK: call ; Call frame restore ; CHECK-NEXT: in r30, 61 diff --git a/llvm/test/CodeGen/AVR/issue-163015.ll b/llvm/test/CodeGen/AVR/issue-163015.ll new file mode 100644 index 0000000..6c4dc51 --- /dev/null +++ b/llvm/test/CodeGen/AVR/issue-163015.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -mtriple=avr | FileCheck %s + +@ui1 = protected local_unnamed_addr global i64 zeroinitializer, align 8 +@ui2 = protected local_unnamed_addr global i64 zeroinitializer, align 8 +@failed = private unnamed_addr addrspace(1) constant [12 x i8] c"test failed\00" +@stats2 = external protected global i16, align 1 + +; CHECK-LABEL: main: +define i32 @main() addrspace(1) { +entry: + store i64 94, ptr @ui1, align 8 + store i64 53, ptr @ui2, align 8 + tail call addrspace(1) void @foo(i16 ptrtoint (ptr addrspace(1) @failed to i16), i16 11, i8 2, i16 32, ptr @stats2) + %11 = load i64, ptr @ui1, align 8 + %12 = load i64, ptr @ui2, align 8 + +; COM: CHECK: call __udivdi3 + %15 = udiv i64 %11, %12 + +; look for the buggy pattern where r30/r31 are being clobbered, corrupting the stack pointer +; CHECK-NOT: std Z+{{[1-9]+}}, r30 +; CHECK-NOT: std Z+{{[1-9]+}}, r31 + +; CHECK: call expect + tail call addrspace(1) void @expect(i64 %15, i64 1, i16 ptrtoint (ptr addrspace(1) @failed to i16), i16 11, i8 2, i16 33) + +; CHECK: ret + ret i32 0 +} + +declare protected void @expect(i64, i64, i16, i16, i8, i16) local_unnamed_addr addrspace(1) #0 +declare protected void @foo(i16, i16, i8, i16, i16) local_unnamed_addr addrspace(1) #0 diff --git a/llvm/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll b/llvm/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll index f82cd11..f12fc4a8 100644 --- a/llvm/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll +++ b/llvm/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll @@ -23,6 +23,6 @@ entry: declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) #1 -attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir index 64e569c..3d40240 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir @@ -63,7 +63,7 @@ ret double %conv } - attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } !llvm.module.flags = !{!0} !llvm.ident = !{!1} diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir index 0bb6061..8f76ad5 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir @@ -35,7 +35,7 @@ ret double %conv } - attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } !llvm.module.flags = !{!0} !llvm.ident = !{!1} diff --git a/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir b/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir index a992222..1612485 100644 --- a/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir +++ b/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir @@ -64,9 +64,9 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #3 - attributes #0 = { ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="64" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="64" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind willreturn } - attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "use-soft-float"="false" } attributes #3 = { nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/X86/atom-fixup-lea4.ll b/llvm/test/CodeGen/X86/atom-fixup-lea4.ll index 8e7a463..69689f0 100644 --- a/llvm/test/CodeGen/X86/atom-fixup-lea4.ll +++ b/llvm/test/CodeGen/X86/atom-fixup-lea4.ll @@ -18,5 +18,5 @@ entry: ; Function Attrs: uwtable declare void @_ZN12ValueWrapperIS_IS_IdEEEC2Ev(ptr) unnamed_addr #0 align 2 -attributes #0 = { uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll b/llvm/test/CodeGen/X86/atomic-load-store.ll index 9fab8b9..3e7b73a 100644 --- a/llvm/test/CodeGen/X86/atomic-load-store.ll +++ b/llvm/test/CodeGen/X86/atomic-load-store.ll @@ -270,6 +270,82 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind { ret <1 x i64> %ret } +define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec1_ptr: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: pushq %rax +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $8, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movq (%rsp), %rax +; CHECK-O3-NEXT: popq %rcx +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec1_ptr: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: pushq %rax +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $8, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movq (%rsp), %rax +; CHECK-SSE-O3-NEXT: popq %rcx +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec1_ptr: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: pushq %rax +; CHECK-AVX-O3-NEXT: movq %rdi, %rsi +; CHECK-AVX-O3-NEXT: movq %rsp, %rdx +; CHECK-AVX-O3-NEXT: movl $8, %edi +; CHECK-AVX-O3-NEXT: movl $2, %ecx +; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O3-NEXT: movq (%rsp), %rax +; CHECK-AVX-O3-NEXT: popq %rcx +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec1_ptr: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: pushq %rax +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $8, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movq (%rsp), %rax +; CHECK-O0-NEXT: popq %rcx +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec1_ptr: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: pushq %rax +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $8, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movq (%rsp), %rax +; CHECK-SSE-O0-NEXT: popq %rcx +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec1_ptr: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: pushq %rax +; CHECK-AVX-O0-NEXT: movq %rdi, %rsi +; CHECK-AVX-O0-NEXT: movl $8, %edi +; CHECK-AVX-O0-NEXT: movq %rsp, %rdx +; CHECK-AVX-O0-NEXT: movl $2, %ecx +; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O0-NEXT: movq (%rsp), %rax +; CHECK-AVX-O0-NEXT: popq %rcx +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <1 x ptr>, ptr %x acquire, align 4 + ret <1 x ptr> %ret +} + define <1 x half> @atomic_vec1_half(ptr %x) { ; CHECK-O3-LABEL: atomic_vec1_half: ; CHECK-O3: # %bb.0: @@ -386,3 +462,515 @@ define <1 x double> @atomic_vec1_double_align(ptr %x) nounwind { %ret = load atomic <1 x double>, ptr %x acquire, align 8 ret <1 x double> %ret } + +define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec1_i64: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: pushq %rax +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $8, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movq (%rsp), %rax +; CHECK-O3-NEXT: popq %rcx +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec1_i64: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: pushq %rax +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $8, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movq (%rsp), %rax +; CHECK-SSE-O3-NEXT: popq %rcx +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec1_i64: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: pushq %rax +; CHECK-AVX-O3-NEXT: movq %rdi, %rsi +; CHECK-AVX-O3-NEXT: movq %rsp, %rdx +; CHECK-AVX-O3-NEXT: movl $8, %edi +; CHECK-AVX-O3-NEXT: movl $2, %ecx +; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O3-NEXT: movq (%rsp), %rax +; CHECK-AVX-O3-NEXT: popq %rcx +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec1_i64: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: pushq %rax +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $8, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movq (%rsp), %rax +; CHECK-O0-NEXT: popq %rcx +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec1_i64: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: pushq %rax +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $8, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movq (%rsp), %rax +; CHECK-SSE-O0-NEXT: popq %rcx +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec1_i64: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: pushq %rax +; CHECK-AVX-O0-NEXT: movq %rdi, %rsi +; CHECK-AVX-O0-NEXT: movl $8, %edi +; CHECK-AVX-O0-NEXT: movq %rsp, %rdx +; CHECK-AVX-O0-NEXT: movl $2, %ecx +; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O0-NEXT: movq (%rsp), %rax +; CHECK-AVX-O0-NEXT: popq %rcx +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <1 x i64>, ptr %x acquire, align 4 + ret <1 x i64> %ret +} + +define <1 x double> @atomic_vec1_double(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec1_double: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: pushq %rax +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $8, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-O3-NEXT: popq %rax +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec1_double: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: pushq %rax +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $8, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-SSE-O3-NEXT: popq %rax +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec1_double: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: pushq %rax +; CHECK-AVX-O3-NEXT: movq %rdi, %rsi +; CHECK-AVX-O3-NEXT: movq %rsp, %rdx +; CHECK-AVX-O3-NEXT: movl $8, %edi +; CHECK-AVX-O3-NEXT: movl $2, %ecx +; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O3-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-AVX-O3-NEXT: popq %rax +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec1_double: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: pushq %rax +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $8, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-O0-NEXT: popq %rax +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec1_double: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: pushq %rax +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $8, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-SSE-O0-NEXT: popq %rax +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec1_double: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: pushq %rax +; CHECK-AVX-O0-NEXT: movq %rdi, %rsi +; CHECK-AVX-O0-NEXT: movl $8, %edi +; CHECK-AVX-O0-NEXT: movq %rsp, %rdx +; CHECK-AVX-O0-NEXT: movl $2, %ecx +; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-AVX-O0-NEXT: popq %rax +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <1 x double>, ptr %x acquire, align 4 + ret <1 x double> %ret +} + +define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec2_i32: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: pushq %rax +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $8, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-O3-NEXT: popq %rax +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec2_i32: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: pushq %rax +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $8, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-SSE-O3-NEXT: popq %rax +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec2_i32: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: pushq %rax +; CHECK-AVX-O3-NEXT: movq %rdi, %rsi +; CHECK-AVX-O3-NEXT: movq %rsp, %rdx +; CHECK-AVX-O3-NEXT: movl $8, %edi +; CHECK-AVX-O3-NEXT: movl $2, %ecx +; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O3-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-AVX-O3-NEXT: popq %rax +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec2_i32: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: pushq %rax +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $8, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; CHECK-O0-NEXT: popq %rax +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec2_i32: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: pushq %rax +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $8, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; CHECK-SSE-O0-NEXT: popq %rax +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec2_i32: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: pushq %rax +; CHECK-AVX-O0-NEXT: movq %rdi, %rsi +; CHECK-AVX-O0-NEXT: movl $8, %edi +; CHECK-AVX-O0-NEXT: movq %rsp, %rdx +; CHECK-AVX-O0-NEXT: movl $2, %ecx +; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O0-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; CHECK-AVX-O0-NEXT: popq %rax +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <2 x i32>, ptr %x acquire, align 4 + ret <2 x i32> %ret +} + +define <4 x float> @atomic_vec4_float(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec4_float: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: subq $24, %rsp +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $16, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-O3-NEXT: addq $24, %rsp +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec4_float: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: subq $24, %rsp +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $16, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O3-NEXT: addq $24, %rsp +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec4_float: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: subq $24, %rsp +; CHECK-AVX-O3-NEXT: movq %rdi, %rsi +; CHECK-AVX-O3-NEXT: movq %rsp, %rdx +; CHECK-AVX-O3-NEXT: movl $16, %edi +; CHECK-AVX-O3-NEXT: movl $2, %ecx +; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O3-NEXT: vmovaps (%rsp), %xmm0 +; CHECK-AVX-O3-NEXT: addq $24, %rsp +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec4_float: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: subq $24, %rsp +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $16, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movaps (%rsp), %xmm0 +; CHECK-O0-NEXT: addq $24, %rsp +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec4_float: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: subq $24, %rsp +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $16, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O0-NEXT: addq $24, %rsp +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec4_float: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: subq $24, %rsp +; CHECK-AVX-O0-NEXT: movq %rdi, %rsi +; CHECK-AVX-O0-NEXT: movl $16, %edi +; CHECK-AVX-O0-NEXT: movq %rsp, %rdx +; CHECK-AVX-O0-NEXT: movl $2, %ecx +; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O0-NEXT: vmovaps (%rsp), %xmm0 +; CHECK-AVX-O0-NEXT: addq $24, %rsp +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <4 x float>, ptr %x acquire, align 4 + ret <4 x float> %ret +} + +define <8 x double> @atomic_vec8_double(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec8_double: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: subq $72, %rsp +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $64, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-O3-NEXT: addq $72, %rsp +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec8_double: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: subq $72, %rsp +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $64, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE-O3-NEXT: addq $72, %rsp +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec8_double: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: subq $72, %rsp +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $64, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movapd (%rsp), %xmm0 +; CHECK-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm1 +; CHECK-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm2 +; CHECK-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3 +; CHECK-O0-NEXT: addq $72, %rsp +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec8_double: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: subq $72, %rsp +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $64, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movapd (%rsp), %xmm0 +; CHECK-SSE-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE-O0-NEXT: addq $72, %rsp +; CHECK-SSE-O0-NEXT: retq + %ret = load atomic <8 x double>, ptr %x acquire, align 4 + ret <8 x double> %ret +} + +define <16 x bfloat> @atomic_vec16_bfloat(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec16_bfloat: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: subq $40, %rsp +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $32, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-O3-NEXT: addq $40, %rsp +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec16_bfloat: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: subq $40, %rsp +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $32, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE-O3-NEXT: addq $40, %rsp +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec16_bfloat: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: subq $40, %rsp +; CHECK-AVX-O3-NEXT: movq %rdi, %rsi +; CHECK-AVX-O3-NEXT: movq %rsp, %rdx +; CHECK-AVX-O3-NEXT: movl $32, %edi +; CHECK-AVX-O3-NEXT: movl $2, %ecx +; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O3-NEXT: vmovups (%rsp), %ymm0 +; CHECK-AVX-O3-NEXT: addq $40, %rsp +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec16_bfloat: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: subq $40, %rsp +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $32, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movaps (%rsp), %xmm0 +; CHECK-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-O0-NEXT: addq $40, %rsp +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec16_bfloat: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: subq $40, %rsp +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $32, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE-O0-NEXT: addq $40, %rsp +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec16_bfloat: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: subq $40, %rsp +; CHECK-AVX-O0-NEXT: movq %rdi, %rsi +; CHECK-AVX-O0-NEXT: movl $32, %edi +; CHECK-AVX-O0-NEXT: movq %rsp, %rdx +; CHECK-AVX-O0-NEXT: movl $2, %ecx +; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT +; CHECK-AVX-O0-NEXT: vmovups (%rsp), %ymm0 +; CHECK-AVX-O0-NEXT: addq $40, %rsp +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <16 x bfloat>, ptr %x acquire, align 4 + ret <16 x bfloat> %ret +} + +define <32 x half> @atomic_vec32_half(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec32_half: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: subq $72, %rsp +; CHECK-O3-NEXT: movq %rdi, %rsi +; CHECK-O3-NEXT: movq %rsp, %rdx +; CHECK-O3-NEXT: movl $64, %edi +; CHECK-O3-NEXT: movl $2, %ecx +; CHECK-O3-NEXT: callq __atomic_load@PLT +; CHECK-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-O3-NEXT: addq $72, %rsp +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec32_half: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: subq $72, %rsp +; CHECK-SSE-O3-NEXT: movq %rdi, %rsi +; CHECK-SSE-O3-NEXT: movq %rsp, %rdx +; CHECK-SSE-O3-NEXT: movl $64, %edi +; CHECK-SSE-O3-NEXT: movl $2, %ecx +; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE-O3-NEXT: addq $72, %rsp +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec32_half: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: subq $72, %rsp +; CHECK-O0-NEXT: movq %rdi, %rsi +; CHECK-O0-NEXT: movl $64, %edi +; CHECK-O0-NEXT: movq %rsp, %rdx +; CHECK-O0-NEXT: movl $2, %ecx +; CHECK-O0-NEXT: callq __atomic_load@PLT +; CHECK-O0-NEXT: movaps (%rsp), %xmm0 +; CHECK-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-O0-NEXT: addq $72, %rsp +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec32_half: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: subq $72, %rsp +; CHECK-SSE-O0-NEXT: movq %rdi, %rsi +; CHECK-SSE-O0-NEXT: movl $64, %edi +; CHECK-SSE-O0-NEXT: movq %rsp, %rdx +; CHECK-SSE-O0-NEXT: movl $2, %ecx +; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT +; CHECK-SSE-O0-NEXT: movaps (%rsp), %xmm0 +; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 +; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3 +; CHECK-SSE-O0-NEXT: addq $72, %rsp +; CHECK-SSE-O0-NEXT: retq + %ret = load atomic <32 x half>, ptr %x acquire, align 4 + ret <32 x half> %ret +} diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir index 99fee27..88d7682 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir @@ -52,7 +52,7 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #2 - attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir index 50b2433..8dbd4e2 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir @@ -63,7 +63,7 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #2 - attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir index 7a4b993..c0924ea 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir @@ -73,7 +73,7 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #2 - attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-overlaps.ll b/llvm/test/CodeGen/X86/avoid-sfb-overlaps.ll index da9d16c..f074390 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-overlaps.ll +++ b/llvm/test/CodeGen/X86/avoid-sfb-overlaps.ll @@ -502,6 +502,6 @@ entry: ret void } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } diff --git a/llvm/test/CodeGen/X86/avx512-cmp-kor-sequence.ll b/llvm/test/CodeGen/X86/avx512-cmp-kor-sequence.ll index b4ba239..7fd4f59 100644 --- a/llvm/test/CodeGen/X86/avx512-cmp-kor-sequence.ll +++ b/llvm/test/CodeGen/X86/avx512-cmp-kor-sequence.ll @@ -48,5 +48,5 @@ entry: ; Function Attrs: nounwind readnone declare <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, <16 x i1>, i32) #1 -attributes #0 = { nounwind readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="broadwell" "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512f,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+evex512,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-vzeroupper" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="broadwell" "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512f,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+evex512,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-vzeroupper" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/X86/bit-piece-comment.ll b/llvm/test/CodeGen/X86/bit-piece-comment.ll index d74863f..85c64a7 100644 --- a/llvm/test/CodeGen/X86/bit-piece-comment.ll +++ b/llvm/test/CodeGen/X86/bit-piece-comment.ll @@ -32,7 +32,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { norecurse nounwind optsize readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind optsize readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/X86/catchpad-regmask.ll b/llvm/test/CodeGen/X86/catchpad-regmask.ll index 9dba897..713d015 100644 --- a/llvm/test/CodeGen/X86/catchpad-regmask.ll +++ b/llvm/test/CodeGen/X86/catchpad-regmask.ll @@ -130,7 +130,7 @@ unreachable: ; preds = %entry ; CHECK: retq # CATCHRET -attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #1 = { noreturn } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/X86/catchpad-weight.ll b/llvm/test/CodeGen/X86/catchpad-weight.ll index e97f358..699243d 100644 --- a/llvm/test/CodeGen/X86/catchpad-weight.ll +++ b/llvm/test/CodeGen/X86/catchpad-weight.ll @@ -74,8 +74,8 @@ declare void @"\01??1HasDtor@@QEAA@XZ"(ptr) #3 ; Function Attrs: nounwind argmemonly declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 -attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #1 = { nounwind argmemonly } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" "use-soft-float"="false" } +attributes #3 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #4 = { nounwind } diff --git a/llvm/test/CodeGen/X86/clang-section-coff.ll b/llvm/test/CodeGen/X86/clang-section-coff.ll index 02381fd..6b76bb6 100644 --- a/llvm/test/CodeGen/X86/clang-section-coff.ll +++ b/llvm/test/CodeGen/X86/clang-section-coff.ll @@ -37,8 +37,8 @@ attributes #0 = { "bss-section"="my_bss.1" "data-section"="my_data.1" "rodata-se attributes #1 = { "data-section"="my_data.1" "rodata-section"="my_rodata.1" } attributes #2 = { "bss-section"="my_bss.2" "rodata-section"="my_rodata.1" } attributes #3 = { "bss-section"="my_bss.2" "data-section"="my_data.2" "rodata-section"="my_rodata.2" } -attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/llvm/test/CodeGen/X86/cleanuppad-inalloca.ll b/llvm/test/CodeGen/X86/cleanuppad-inalloca.ll index 01e7019..863f580 100644 --- a/llvm/test/CodeGen/X86/cleanuppad-inalloca.ll +++ b/llvm/test/CodeGen/X86/cleanuppad-inalloca.ll @@ -65,4 +65,4 @@ declare i32 @__CxxFrameHandler3(...) declare x86_thiscallcc void @"\01??1A@@QAE@XZ"(ptr) #0 -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/complex-fastmath.ll b/llvm/test/CodeGen/X86/complex-fastmath.ll index 29a37a1..21bb64a 100644 --- a/llvm/test/CodeGen/X86/complex-fastmath.ll +++ b/llvm/test/CodeGen/X86/complex-fastmath.ll @@ -212,4 +212,4 @@ define <2 x double> @complex_mul_f64(<2 x double>, <2 x double>) #0 { ret <2 x double> %14 } -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "less-precise-fpmad"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "unsafe-fp-math"="true" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "less-precise-fpmad"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" } diff --git a/llvm/test/CodeGen/X86/crash-lre-eliminate-dead-def.ll b/llvm/test/CodeGen/X86/crash-lre-eliminate-dead-def.ll index ddddcfa..9f51fa4 100644 --- a/llvm/test/CodeGen/X86/crash-lre-eliminate-dead-def.ll +++ b/llvm/test/CodeGen/X86/crash-lre-eliminate-dead-def.ll @@ -264,5 +264,5 @@ unreachable: ; preds = %cleanup100 ; Function Attrs: nounwind declare void @printf(ptr nocapture readonly, ...) #1 -attributes #0 = { noreturn nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noreturn nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/dag-optnone.ll b/llvm/test/CodeGen/X86/dag-optnone.ll index 66e4c1d..022694e 100644 --- a/llvm/test/CodeGen/X86/dag-optnone.ll +++ b/llvm/test/CodeGen/X86/dag-optnone.ll @@ -28,7 +28,7 @@ ; a repeated fadd that can be combined into an fmul. We show that this ; happens in both the non-optnone function and the optnone function. -define float @foo(float %x, ...) #0 { +define float @foo(float %x, ...) { entry: %add = fadd fast float %x, %x %add1 = fadd fast float %add, %x @@ -68,5 +68,4 @@ entry: ret void } -attributes #0 = { "unsafe-fp-math"="true" } -attributes #1 = { noinline optnone "unsafe-fp-math"="true" } +attributes #1 = { noinline optnone } diff --git a/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll b/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll index deba5a8..18e5490 100644 --- a/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll +++ b/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll @@ -112,9 +112,9 @@ declare void @_Z3fooPcjPKc(ptr, i32, ptr) #2 ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #3 -attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #3 = { nounwind readnone } attributes #4 = { nounwind } diff --git a/llvm/test/CodeGen/X86/dbg-changes-codegen.ll b/llvm/test/CodeGen/X86/dbg-changes-codegen.ll index fabdbbb..c688895 100644 --- a/llvm/test/CodeGen/X86/dbg-changes-codegen.ll +++ b/llvm/test/CodeGen/X86/dbg-changes-codegen.ll @@ -68,8 +68,8 @@ _ZN7Flibble3barEP6Wibble.exit: ; preds = %entry, %if.then.i ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 -attributes #0 = { nounwind readonly uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readonly uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind readnone } !1 = distinct !DISubprogram() diff --git a/llvm/test/CodeGen/X86/dbg-combine.ll b/llvm/test/CodeGen/X86/dbg-combine.ll index b3d2213..3ff5a26 100644 --- a/llvm/test/CodeGen/X86/dbg-combine.ll +++ b/llvm/test/CodeGen/X86/dbg-combine.ll @@ -63,7 +63,7 @@ declare ptr @llvm.stacksave() #2 ; Function Attrs: nounwind declare void @llvm.stackrestore(ptr) #2 -attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/debug-loclists-lto.ll b/llvm/test/CodeGen/X86/debug-loclists-lto.ll index fde8e00..2bd927f 100644 --- a/llvm/test/CodeGen/X86/debug-loclists-lto.ll +++ b/llvm/test/CodeGen/X86/debug-loclists-lto.ll @@ -34,8 +34,8 @@ entry: ret void, !dbg !29 } -attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind readnone speculatable willreturn } !llvm.dbg.cu = !{!0, !7} diff --git a/llvm/test/CodeGen/X86/debugloc-argsize.ll b/llvm/test/CodeGen/X86/debugloc-argsize.ll index 3cfeb6e..f4527c5 100644 --- a/llvm/test/CodeGen/X86/debugloc-argsize.ll +++ b/llvm/test/CodeGen/X86/debugloc-argsize.ll @@ -30,7 +30,7 @@ declare ptr @__cxa_begin_catch(ptr) declare void @__cxa_end_catch() -attributes #0 = { optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+sse,+sse2" "use-soft-float"="false" } attributes #1 = { optsize } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/early-cfi-sections.ll b/llvm/test/CodeGen/X86/early-cfi-sections.ll index 3a9e62a..8ab0340 100644 --- a/llvm/test/CodeGen/X86/early-cfi-sections.ll +++ b/llvm/test/CodeGen/X86/early-cfi-sections.ll @@ -12,7 +12,7 @@ entry: ret void, !dbg !8 } -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4} diff --git a/llvm/test/CodeGen/X86/fadd-combines.ll b/llvm/test/CodeGen/X86/fadd-combines.ll index 2c06c53..a44671c 100644 --- a/llvm/test/CodeGen/X86/fadd-combines.ll +++ b/llvm/test/CodeGen/X86/fadd-combines.ll @@ -275,4 +275,4 @@ define <2 x double> @fmul2_negated_vec(<2 x double> %a, <2 x double> %b, <2 x do ret <2 x double> %sub } -attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" } +attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll b/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll index 5afa12c..1bc94b1 100644 --- a/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll +++ b/llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll @@ -65,5 +65,5 @@ entry: declare i16 @llvm.convert.to.fp16.f64(double) declare i16 @llvm.convert.to.fp16.f80(x86_fp80) -attributes #0 = { nounwind readnone "unsafe-fp-math"="true" "use-soft-float"="false" } -attributes #1 = { nounwind readnone "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone "use-soft-float"="false" } +attributes #1 = { nounwind readnone "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/fdiv.ll b/llvm/test/CodeGen/X86/fdiv.ll index 67bad09..859f54e 100644 --- a/llvm/test/CodeGen/X86/fdiv.ll +++ b/llvm/test/CodeGen/X86/fdiv.ll @@ -54,7 +54,7 @@ define double @denormal2(double %x) { ; Deleting the negates does not require unsafe-fp-math. -define float @double_negative(float %x, float %y) #0 { +define float @double_negative(float %x, float %y) { ; CHECK-LABEL: double_negative: ; CHECK: # %bb.0: ; CHECK-NEXT: divss %xmm1, %xmm0 @@ -65,7 +65,7 @@ define float @double_negative(float %x, float %y) #0 { ret float %div } -define <4 x float> @double_negative_vector(<4 x float> %x, <4 x float> %y) #0 { +define <4 x float> @double_negative_vector(<4 x float> %x, <4 x float> %y) { ; CHECK-LABEL: double_negative_vector: ; CHECK: # %bb.0: ; CHECK-NEXT: divps %xmm1, %xmm0 @@ -80,7 +80,7 @@ define <4 x float> @double_negative_vector(<4 x float> %x, <4 x float> %y) #0 { ; clang/gcc), due to order of argument evaluation not being well defined. We ; ended up hitting llvm_unreachable in getNegatedExpression when building with ; gcc. Just make sure that we get a deterministic result. -define float @fdiv_fneg_combine(float %a0, float %a1, float %a2) #0 { +define float @fdiv_fneg_combine(float %a0, float %a1, float %a2) { ; CHECK-LABEL: fdiv_fneg_combine: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm0, %xmm3 @@ -99,6 +99,3 @@ define float @fdiv_fneg_combine(float %a0, float %a1, float %a2) #0 { %div5 = fdiv fast float %mul2, %sub4 ret float %div5 } - -attributes #0 = { "unsafe-fp-math"="false" } - diff --git a/llvm/test/CodeGen/X86/fma_patterns_wide.ll b/llvm/test/CodeGen/X86/fma_patterns_wide.ll index 4c16cf9..0c3ec8d 100644 --- a/llvm/test/CodeGen/X86/fma_patterns_wide.ll +++ b/llvm/test/CodeGen/X86/fma_patterns_wide.ll @@ -1021,7 +1021,7 @@ define <8 x double> @test_v8f64_interp_ninf(<8 x double> %x, <8 x double> %y, <8 ; Pattern: (fneg (fma x, y, z)) -> (fma x, -y, -z) ; -define <16 x float> @test_v16f32_fneg_fmadd(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) #0 { +define <16 x float> @test_v16f32_fneg_fmadd(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; FMA-LABEL: test_v16f32_fneg_fmadd: ; FMA: # %bb.0: ; FMA-NEXT: vfnmsub213ps {{.*#+}} ymm0 = -(ymm2 * ymm0) - ymm4 @@ -1044,7 +1044,7 @@ define <16 x float> @test_v16f32_fneg_fmadd(<16 x float> %a0, <16 x float> %a1, ret <16 x float> %neg } -define <8 x double> @test_v8f64_fneg_fmsub(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) #0 { +define <8 x double> @test_v8f64_fneg_fmsub(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; FMA-LABEL: test_v8f64_fneg_fmsub: ; FMA: # %bb.0: ; FMA-NEXT: vfnmadd213pd {{.*#+}} ymm0 = -(ymm2 * ymm0) + ymm4 @@ -1067,7 +1067,7 @@ define <8 x double> @test_v8f64_fneg_fmsub(<8 x double> %a0, <8 x double> %a1, < ret <8 x double> %neg } -define <16 x float> @test_v16f32_fneg_fnmadd(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) #0 { +define <16 x float> @test_v16f32_fneg_fnmadd(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; FMA-LABEL: test_v16f32_fneg_fnmadd: ; FMA: # %bb.0: ; FMA-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) - ymm4 @@ -1091,7 +1091,7 @@ define <16 x float> @test_v16f32_fneg_fnmadd(<16 x float> %a0, <16 x float> %a1, ret <16 x float> %neg1 } -define <8 x double> @test_v8f64_fneg_fnmsub(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) #0 { +define <8 x double> @test_v8f64_fneg_fnmsub(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; FMA-LABEL: test_v8f64_fneg_fnmsub: ; FMA: # %bb.0: ; FMA-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm2 * ymm0) + ymm4 @@ -1119,7 +1119,7 @@ define <8 x double> @test_v8f64_fneg_fnmsub(<8 x double> %a0, <8 x double> %a1, ; Pattern: (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) ; -define <16 x float> @test_v16f32_fma_x_c1_fmul_x_c2(<16 x float> %x) #0 { +define <16 x float> @test_v16f32_fma_x_c1_fmul_x_c2(<16 x float> %x) { ; FMA-LABEL: test_v16f32_fma_x_c1_fmul_x_c2: ; FMA: # %bb.0: ; FMA-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 @@ -1146,7 +1146,7 @@ define <16 x float> @test_v16f32_fma_x_c1_fmul_x_c2(<16 x float> %x) #0 { ; Pattern: (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) ; -define <16 x float> @test_v16f32_fma_fmul_x_c1_c2_y(<16 x float> %x, <16 x float> %y) #0 { +define <16 x float> @test_v16f32_fma_fmul_x_c1_c2_y(<16 x float> %x, <16 x float> %y) { ; FMA-LABEL: test_v16f32_fma_fmul_x_c1_c2_y: ; FMA: # %bb.0: ; FMA-NEXT: vfmadd132ps {{.*#+}} ymm0 = (ymm0 * mem) + ymm2 @@ -1171,7 +1171,7 @@ define <16 x float> @test_v16f32_fma_fmul_x_c1_c2_y(<16 x float> %x, <16 x float ; Pattern: (fneg (fmul x, y)) -> (fnmsub x, y, 0) -define <16 x float> @test_v16f32_fneg_fmul(<16 x float> %x, <16 x float> %y) #0 { +define <16 x float> @test_v16f32_fneg_fmul(<16 x float> %x, <16 x float> %y) { ; FMA-LABEL: test_v16f32_fneg_fmul: ; FMA: # %bb.0: ; FMA-NEXT: vxorps %xmm4, %xmm4, %xmm4 @@ -1196,7 +1196,7 @@ define <16 x float> @test_v16f32_fneg_fmul(<16 x float> %x, <16 x float> %y) #0 ret <16 x float> %n } -define <8 x double> @test_v8f64_fneg_fmul(<8 x double> %x, <8 x double> %y) #0 { +define <8 x double> @test_v8f64_fneg_fmul(<8 x double> %x, <8 x double> %y) { ; FMA-LABEL: test_v8f64_fneg_fmul: ; FMA: # %bb.0: ; FMA-NEXT: vxorpd %xmm4, %xmm4, %xmm4 @@ -1221,7 +1221,7 @@ define <8 x double> @test_v8f64_fneg_fmul(<8 x double> %x, <8 x double> %y) #0 { ret <8 x double> %n } -define <8 x double> @test_v8f64_fneg_fmul_no_nsz(<8 x double> %x, <8 x double> %y) #0 { +define <8 x double> @test_v8f64_fneg_fmul_no_nsz(<8 x double> %x, <8 x double> %y) { ; FMA-LABEL: test_v8f64_fneg_fmul_no_nsz: ; FMA: # %bb.0: ; FMA-NEXT: vmulpd %ymm3, %ymm1, %ymm1 @@ -1250,7 +1250,6 @@ define <8 x double> @test_v8f64_fneg_fmul_no_nsz(<8 x double> %x, <8 x double> % ret <8 x double> %n } -attributes #0 = { "unsafe-fp-math"="true" } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; AVX512-INFS: {{.*}} ; FMA-INFS: {{.*}} diff --git a/llvm/test/CodeGen/X86/fold-tied-op.ll b/llvm/test/CodeGen/X86/fold-tied-op.ll index 5ea2964..d60d397 100644 --- a/llvm/test/CodeGen/X86/fold-tied-op.ll +++ b/llvm/test/CodeGen/X86/fold-tied-op.ll @@ -158,7 +158,7 @@ if.end: ; preds = %if.else, %if.then ret i64 undef } -attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll index bd32430..fc5279d0 100644 --- a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll +++ b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll @@ -100,40 +100,52 @@ entry: ret i32 %result } -; These 2 divs only differ in their exception behavior and will be CSEd. Make -; sure the nofpexcept flag is not set on the combined node. +; These 4 divs only differ in their exception behavior. They form two groups, +; whithin each the constrained functions have the same exception hehavior and +; may be CSE'd. Instructions with different exception behavior belong to +; different groups, they have different chain argument and cannot be CSE'd. define void @binop_cse(double %a, double %b, ptr %x, ptr %y) #0 { entry: ; CHECK-LABEL: name: binop_cse -; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.0) -; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.1, align 16) -; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.3, align 16) -; CHECK: %3:fr64 = DIVSDrm [[MOVSDrm_alt]], %fixed-stack.2, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load (s64) from %fixed-stack.2) -; CHECK: MOVSDmr killed [[MOV32rm1]], 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.x, align 4) -; CHECK: MOVSDmr killed [[MOV32rm]], 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.y, align 4) +; CHECK: [[Y:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.0) +; CHECK: [[X:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.1, align 16) +; CHECK: [[B:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.2) +; CHECK: [[A:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.3, align 16) +; CHECK: [[DIV0:%[0-9]+]]:fr64 = DIVSDrr [[A]], [[B]], implicit $mxcsr +; CHECK: [[DIV1:%[0-9]+]]:fr64 = nofpexcept DIVSDrr [[A]], [[B]], implicit $mxcsr +; CHECK: MOVSDmr killed [[X]], 1, $noreg, 0, $noreg, [[DIV1]] :: (store (s64) into %ir.x, align 4) +; CHECK: MOVSDmr killed [[Y]], 1, $noreg, 0, $noreg, [[DIV1]] :: (store (s64) into %ir.y, align 4) ; CHECK: RET 0 %div = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 + %div1 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %div2 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0 - store double %div, ptr %x - store double %div2, ptr %y + %div3 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0 + store double %div2, ptr %x + store double %div3, ptr %y ret void } -; These 2 sitofps only differ in their exception behavior and will be CSEd. Make -; sure the nofpexcept flag is not set on the combined node. +; These 4 divs only differ in their exception behavior. They form two groups, +; whithin each the constrained functions have the same exception hehavior and +; may be CSE'd. Instructions with different exception behavior belong to +; different groups, they have different chain argument and cannot be CSE'd. define void @sitofp_cse(i32 %a, ptr %x, ptr %y) #0 { entry: ; CHECK-LABEL: name: sitofp_cse -; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.0, align 8) -; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.1) -; CHECK: %2:fr64 = CVTSI2SDrm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.2, align 16) -; CHECK: MOVSDmr killed [[MOV32rm1]], 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.x, align 4) -; CHECK: MOVSDmr killed [[MOV32rm]], 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.y, align 4) +; CHECK: [[Y:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.0, align 8) +; CHECK: [[X:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.1) +; CHECK: [[A:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.2, align 16) +; CHECK: [[CVT0:%[0-9]+]]:fr64 = CVTSI2SDrr [[A]] +; CHECK: [[CVT1:%[0-9]+]]:fr64 = nofpexcept CVTSI2SDrr [[A]] +; CHECK: MOVSDmr killed [[X]], 1, $noreg, 0, $noreg, [[CVT1]] :: (store (s64) into %ir.x, align 4) +; CHECK: MOVSDmr killed [[Y]], 1, $noreg, 0, $noreg, [[CVT1]] :: (store (s64) into %ir.y, align 4) ; CHECK: RET 0 %result = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 + %result1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %result2 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0 - store double %result, ptr %x - store double %result2, ptr %y + %result3 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0 + store double %result2, ptr %x + store double %result3, ptr %y ret void } diff --git a/llvm/test/CodeGen/X86/fp128-g.ll b/llvm/test/CodeGen/X86/fp128-g.ll index 58a57d3..d2b956f 100644 --- a/llvm/test/CodeGen/X86/fp128-g.ll +++ b/llvm/test/CodeGen/X86/fp128-g.ll @@ -106,8 +106,8 @@ entry: ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 -attributes #0 = { nounwind readonly uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { norecurse nounwind readonly uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readonly uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "use-soft-float"="false" } +attributes #1 = { norecurse nounwind readonly uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "use-soft-float"="false" } attributes #2 = { nounwind readnone } !llvm.dbg.cu = !{!2} diff --git a/llvm/test/CodeGen/X86/fp128-i128.ll b/llvm/test/CodeGen/X86/fp128-i128.ll index f176a29..ef616ca 100644 --- a/llvm/test/CodeGen/X86/fp128-i128.ll +++ b/llvm/test/CodeGen/X86/fp128-i128.ll @@ -526,6 +526,6 @@ cleanup: ; preds = %entry, %if.then } -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+ssse3,+sse3,+popcnt,+sse,+sse2,+sse4.1,+sse4.2" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+ssse3,+sse3,+popcnt,+sse,+sse2,+sse4.1,+sse4.2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+ssse3,+sse3,+popcnt,+sse,+sse2,+sse4.1,+sse4.2" "use-soft-float"="false" } +attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+ssse3,+sse3,+popcnt,+sse,+sse2,+sse4.1,+sse4.2" "use-soft-float"="false" } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/X86/frame-order.ll b/llvm/test/CodeGen/X86/frame-order.ll index dcbcb48..f410acf 100644 --- a/llvm/test/CodeGen/X86/frame-order.ll +++ b/llvm/test/CodeGen/X86/frame-order.ll @@ -74,9 +74,9 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 declare void @capture(ptr) #2 -attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #1 = { nounwind readnone } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/X86/fsafdo_test2.ll b/llvm/test/CodeGen/X86/fsafdo_test2.ll index d83e241..fc4c1e8 100644 --- a/llvm/test/CodeGen/X86/fsafdo_test2.ll +++ b/llvm/test/CodeGen/X86/fsafdo_test2.ll @@ -196,10 +196,10 @@ if.end9.3: } -attributes #0 = { noinline nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind willreturn } -attributes #2 = { nofree noinline norecurse nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nofree noinline norecurse nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } +attributes #3 = { nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5} diff --git a/llvm/test/CodeGen/X86/i386-shrink-wrapping.ll b/llvm/test/CodeGen/X86/i386-shrink-wrapping.ll index 7bb3bf42..4347d62 100644 --- a/llvm/test/CodeGen/X86/i386-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/i386-shrink-wrapping.ll @@ -130,5 +130,5 @@ for.end: ; preds = %for.cond.preheader ; Function Attrs: nounwind declare i32 @varfunc(ptr nocapture readonly, ...) #0 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+mmx,+sse" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+mmx,+sse" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll b/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll index f982196..11a1f39 100644 --- a/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll +++ b/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll @@ -23,7 +23,7 @@ entry: ; CHECK: lock ; CHECK-NEXT: cmpxchg16b -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/X86/label-annotation.ll b/llvm/test/CodeGen/X86/label-annotation.ll index 626040c..05e4e87 100644 --- a/llvm/test/CodeGen/X86/label-annotation.ll +++ b/llvm/test/CodeGen/X86/label-annotation.ll @@ -77,8 +77,8 @@ entry: -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { inaccessiblememonly noduplicate nounwind } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/X86/label-heapallocsite.ll b/llvm/test/CodeGen/X86/label-heapallocsite.ll index 31bca25..72834be6c 100644 --- a/llvm/test/CodeGen/X86/label-heapallocsite.ll +++ b/llvm/test/CodeGen/X86/label-heapallocsite.ll @@ -98,8 +98,8 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) #2 ; CHECK-NEXT: .short [[LABEL5]]-[[LABEL4]] ; CHECK-NEXT: .long 4096 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind readnone speculatable willreturn } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/X86/late-remat-update.mir b/llvm/test/CodeGen/X86/late-remat-update.mir index 3212312..9108002 100644 --- a/llvm/test/CodeGen/X86/late-remat-update.mir +++ b/llvm/test/CodeGen/X86/late-remat-update.mir @@ -39,8 +39,8 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #2 - attributes #0 = { noreturn uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { noreturn uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } + attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/X86/lea-opt-memop-check-1.ll b/llvm/test/CodeGen/X86/lea-opt-memop-check-1.ll index 5199b15..96780af0 100644 --- a/llvm/test/CodeGen/X86/lea-opt-memop-check-1.ll +++ b/llvm/test/CodeGen/X86/lea-opt-memop-check-1.ll @@ -92,4 +92,4 @@ if.end: ; CHECK: pushl ([[REG3]]) } -attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/lifetime-alias.ll b/llvm/test/CodeGen/X86/lifetime-alias.ll index 3efaccb..22e350c 100644 --- a/llvm/test/CodeGen/X86/lifetime-alias.ll +++ b/llvm/test/CodeGen/X86/lifetime-alias.ll @@ -140,10 +140,10 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado ; Function Attrs: argmemonly nounwind declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1 -attributes #0 = { norecurse uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { nobuiltin nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #3 = { nobuiltin nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #4 = { nounwind } attributes #5 = { noreturn nounwind } attributes #6 = { builtin nounwind } diff --git a/llvm/test/CodeGen/X86/limit-split-cost.mir b/llvm/test/CodeGen/X86/limit-split-cost.mir index 5b8bb98..8e4e786 100644 --- a/llvm/test/CodeGen/X86/limit-split-cost.mir +++ b/llvm/test/CodeGen/X86/limit-split-cost.mir @@ -53,8 +53,8 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #2 - attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } + attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll b/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll index 3dba5eb..206d453 100644 --- a/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll +++ b/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll @@ -41,5 +41,5 @@ if.end: ; preds = %entry declare <4 x float> @_Z1bv() local_unnamed_addr -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/misched-copy.ll b/llvm/test/CodeGen/X86/misched-copy.ll index fa6cd15..e3ceddf 100644 --- a/llvm/test/CodeGen/X86/misched-copy.ll +++ b/llvm/test/CodeGen/X86/misched-copy.ll @@ -42,7 +42,7 @@ end: ret i64 %add } -attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } !0 = !{!"float", !1} !1 = !{!"omnipotent char", !2} diff --git a/llvm/test/CodeGen/X86/misched-matmul.ll b/llvm/test/CodeGen/X86/misched-matmul.ll index a6c489d..9029167 100644 --- a/llvm/test/CodeGen/X86/misched-matmul.ll +++ b/llvm/test/CodeGen/X86/misched-matmul.ll @@ -222,4 +222,4 @@ entry: ret void } -attributes #0 = { noinline nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/movpc32-check.ll b/llvm/test/CodeGen/X86/movpc32-check.ll index e3730d0..4585dcb 100644 --- a/llvm/test/CodeGen/X86/movpc32-check.ll +++ b/llvm/test/CodeGen/X86/movpc32-check.ll @@ -12,8 +12,8 @@ entry: declare void @bar(...) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="i686" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="i686" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="i686" "use-soft-float"="false" } +attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="i686" "use-soft-float"="false" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!7, !8, !9} diff --git a/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll b/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll index ec17b1d..04db25b 100644 --- a/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll +++ b/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll @@ -20,5 +20,5 @@ entry: ; CHECK: movq %rax, 7(%rsp) ; CHECK: retq -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/X86/nocf_check.ll b/llvm/test/CodeGen/X86/nocf_check.ll index 7b184ed..742b07d 100644 --- a/llvm/test/CodeGen/X86/nocf_check.ll +++ b/llvm/test/CodeGen/X86/nocf_check.ll @@ -66,8 +66,8 @@ bb2: ret void } -attributes #0 = { nocf_check noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nocf_check noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } +attributes #1 = { noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } attributes #2 = { nocf_check } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/X86/pr15705.ll b/llvm/test/CodeGen/X86/pr15705.ll index 3dd4aab..2de9a34 100644 --- a/llvm/test/CodeGen/X86/pr15705.ll +++ b/llvm/test/CodeGen/X86/pr15705.ll @@ -45,4 +45,4 @@ return: ret i32 %retval.0 } -attributes #0 = { nounwind readnone ssp "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone ssp "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/pr18846.ll b/llvm/test/CodeGen/X86/pr18846.ll index 93a9a5d..4239f46 100644 --- a/llvm/test/CodeGen/X86/pr18846.ll +++ b/llvm/test/CodeGen/X86/pr18846.ll @@ -122,7 +122,7 @@ for.body65: ; preds = %for.body29 ; Function Attrs: nounwind declare void @llvm.x86.avx.storeu.ps.256(ptr, <8 x float>) #1 -attributes #0 = { uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/X86/pr31045.ll b/llvm/test/CodeGen/X86/pr31045.ll index 4aa73d7..78ba7cc 100644 --- a/llvm/test/CodeGen/X86/pr31045.ll +++ b/llvm/test/CodeGen/X86/pr31045.ll @@ -73,4 +73,4 @@ entry: ret void } -attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/pr32610.ll b/llvm/test/CodeGen/X86/pr32610.ll index dc11ba8..6f3602d 100644 --- a/llvm/test/CodeGen/X86/pr32610.ll +++ b/llvm/test/CodeGen/X86/pr32610.ll @@ -50,7 +50,7 @@ entry: ret void } -attributes #0 = { norecurse nounwind optsize ssp "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+fxsr,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind optsize ssp "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+fxsr,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "use-soft-float"="false" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/X86/pr34080-2.ll b/llvm/test/CodeGen/X86/pr34080-2.ll index de34bfb1..279373a 100644 --- a/llvm/test/CodeGen/X86/pr34080-2.ll +++ b/llvm/test/CodeGen/X86/pr34080-2.ll @@ -132,4 +132,4 @@ define void @computeJD(ptr) nounwind { ret void } -attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="i486" "target-features"="+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="i486" "target-features"="+x87" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/pr34080.ll b/llvm/test/CodeGen/X86/pr34080.ll index d07d1aa..3b46bd3 100644 --- a/llvm/test/CodeGen/X86/pr34080.ll +++ b/llvm/test/CodeGen/X86/pr34080.ll @@ -162,4 +162,4 @@ entry: ret void } -attributes #0 = { noinline uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/pr34629.ll b/llvm/test/CodeGen/X86/pr34629.ll index eeb61d2..f7747b1 100644 --- a/llvm/test/CodeGen/X86/pr34629.ll +++ b/llvm/test/CodeGen/X86/pr34629.ll @@ -38,7 +38,7 @@ if.end: ; preds = %entry, %if.then ret void } -attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } !llvm.module.flags = !{!0} !llvm.ident = !{!1} diff --git a/llvm/test/CodeGen/X86/pr34634.ll b/llvm/test/CodeGen/X86/pr34634.ll index a374112..980961a 100644 --- a/llvm/test/CodeGen/X86/pr34634.ll +++ b/llvm/test/CodeGen/X86/pr34634.ll @@ -54,7 +54,7 @@ entry: ret i32 0 } -attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } !llvm.module.flags = !{!0} !llvm.ident = !{!1} diff --git a/llvm/test/CodeGen/X86/pr42727.ll b/llvm/test/CodeGen/X86/pr42727.ll index cf1fa5a..18e884b 100644 --- a/llvm/test/CodeGen/X86/pr42727.ll +++ b/llvm/test/CodeGen/X86/pr42727.ll @@ -29,5 +29,5 @@ entry: ret void } -attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+avx,+avx2,+cx8,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+avx,+avx2,+cx8,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/pr48064.mir b/llvm/test/CodeGen/X86/pr48064.mir index eb74edd..d2eaea7 100644 --- a/llvm/test/CodeGen/X86/pr48064.mir +++ b/llvm/test/CodeGen/X86/pr48064.mir @@ -185,8 +185,8 @@ ; Function Attrs: nounwind declare void @llvm.x86.seh.ehregnode(ptr) #7 - attributes #0 = { noinline nounwind sspstrong "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { norecurse sspstrong "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { noinline nounwind sspstrong "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } + attributes #1 = { norecurse sspstrong "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } attributes #2 = { argmemonly nofree nosync nounwind willreturn } attributes #3 = { nofree } attributes #4 = { nofree nosync nounwind willreturn } diff --git a/llvm/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll b/llvm/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll index 0d5d822..e497575 100644 --- a/llvm/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll +++ b/llvm/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll @@ -178,4 +178,4 @@ bb439: ; preds = %bb222, %bb85 ret void } -attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/recip-fastmath.ll b/llvm/test/CodeGen/X86/recip-fastmath.ll index dab7a6a..f8d28ae 100644 --- a/llvm/test/CodeGen/X86/recip-fastmath.ll +++ b/llvm/test/CodeGen/X86/recip-fastmath.ll @@ -1400,7 +1400,7 @@ define <16 x float> @v16f32_two_step(<16 x float> %x) #2 { ret <16 x float> %div } -attributes #0 = { "unsafe-fp-math"="true" "reciprocal-estimates"="!divf,!vec-divf" } -attributes #1 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf,vec-divf" } -attributes #2 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf:2,vec-divf:2" } +attributes #0 = { "reciprocal-estimates"="!divf,!vec-divf" } +attributes #1 = { "reciprocal-estimates"="divf,vec-divf" } +attributes #2 = { "reciprocal-estimates"="divf:2,vec-divf:2" } diff --git a/llvm/test/CodeGen/X86/recip-fastmath2.ll b/llvm/test/CodeGen/X86/recip-fastmath2.ll index 77ccaff..7fa13cb 100644 --- a/llvm/test/CodeGen/X86/recip-fastmath2.ll +++ b/llvm/test/CodeGen/X86/recip-fastmath2.ll @@ -1841,8 +1841,8 @@ define <16 x float> @v16f32_no_step2(<16 x float> %x) #3 { ret <16 x float> %div } -attributes #0 = { "unsafe-fp-math"="true" "reciprocal-estimates"="!divf,!vec-divf" } -attributes #1 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf,vec-divf" } -attributes #2 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf:2,vec-divf:2" } -attributes #3 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf:0,vec-divf:0" } +attributes #0 = { "reciprocal-estimates"="!divf,!vec-divf" } +attributes #1 = { "reciprocal-estimates"="divf,vec-divf" } +attributes #2 = { "reciprocal-estimates"="divf:2,vec-divf:2" } +attributes #3 = { "reciprocal-estimates"="divf:0,vec-divf:0" } diff --git a/llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll b/llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll index 50422a8..ea1ca51 100644 --- a/llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll +++ b/llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll @@ -72,7 +72,7 @@ if.end: ; preds = %if.else, %if.then ret i32 %add } -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+x87" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/X86/regparm.ll b/llvm/test/CodeGen/X86/regparm.ll index 6d6802e..95009b5 100644 --- a/llvm/test/CodeGen/X86/regparm.ll +++ b/llvm/test/CodeGen/X86/regparm.ll @@ -38,7 +38,7 @@ entry: declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/X86/seh-catchpad.ll b/llvm/test/CodeGen/X86/seh-catchpad.ll index cb85f39..85e465b 100644 --- a/llvm/test/CodeGen/X86/seh-catchpad.ll +++ b/llvm/test/CodeGen/X86/seh-catchpad.ll @@ -189,9 +189,9 @@ entry: ; Function Attrs: nounwind declare i32 @puts(ptr nocapture readonly) #3 -attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { noinline nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "use-soft-float"="false" } +attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "use-soft-float"="false" } +attributes #2 = { noinline nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "use-soft-float"="false" } +attributes #3 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "use-soft-float"="false" } attributes #4 = { noinline } attributes #5 = { nounwind } diff --git a/llvm/test/CodeGen/X86/seh-except-finally.ll b/llvm/test/CodeGen/X86/seh-except-finally.ll index 539d776..fedb0c4 100644 --- a/llvm/test/CodeGen/X86/seh-except-finally.ll +++ b/llvm/test/CodeGen/X86/seh-except-finally.ll @@ -136,10 +136,10 @@ declare ptr @llvm.localaddress() #4 ; Function Attrs: nounwind readnone declare i32 @llvm.eh.typeid.for(ptr) #4 -attributes #0 = { noinline nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "use-soft-float"="false" } +attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "use-soft-float"="false" } +attributes #2 = { noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "use-soft-float"="false" } +attributes #3 = { "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "use-soft-float"="false" } attributes #4 = { nounwind readnone } attributes #5 = { noinline } attributes #6 = { nounwind } diff --git a/llvm/test/CodeGen/X86/seh-no-invokes.ll b/llvm/test/CodeGen/X86/seh-no-invokes.ll index 63e91d3..112031c 100644 --- a/llvm/test/CodeGen/X86/seh-no-invokes.ll +++ b/llvm/test/CodeGen/X86/seh-no-invokes.ll @@ -63,8 +63,8 @@ declare i32 @_except_handler3(...) ; Function Attrs: nounwind declare void @llvm.localescape(...) #3 -attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/X86/shrinkwrap-hang.ll b/llvm/test/CodeGen/X86/shrinkwrap-hang.ll index fe42d31..7e98b8a 100644 --- a/llvm/test/CodeGen/X86/shrinkwrap-hang.ll +++ b/llvm/test/CodeGen/X86/shrinkwrap-hang.ll @@ -29,4 +29,4 @@ if.end3: ; preds = %if.end ret void } -attributes #0 = { norecurse nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath.ll b/llvm/test/CodeGen/X86/sqrt-fastmath.ll index a260b32..83bfcd7 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath.ll @@ -1012,15 +1012,15 @@ define double @sqrt_simplify_before_recip_order(double %x, ptr %p) nounwind { ret double %sqrt_fast } -attributes #0 = { "unsafe-fp-math"="true" "reciprocal-estimates"="!sqrtf,!vec-sqrtf,!divf,!vec-divf" } -attributes #1 = { "unsafe-fp-math"="true" "reciprocal-estimates"="sqrt,vec-sqrt" } +attributes #0 = { "reciprocal-estimates"="!sqrtf,!vec-sqrtf,!divf,!vec-divf" } +attributes #1 = { "reciprocal-estimates"="sqrt,vec-sqrt" } attributes #2 = { nounwind readnone } -attributes #3 = { "unsafe-fp-math"="true" "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,ieee" } -attributes #4 = { "unsafe-fp-math"="true" "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="ieee,preserve-sign" } -attributes #5 = { "unsafe-fp-math"="true" "reciprocal-estimates"="all:0" } -attributes #6 = { "unsafe-fp-math"="true" "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,dynamic" } +attributes #3 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,ieee" } +attributes #4 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="ieee,preserve-sign" } +attributes #5 = { "reciprocal-estimates"="all:0" } +attributes #6 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,dynamic" } -; Attributes without "unsafe-fp-math"="true" +; Attributes without ; TODO: Merge with previous attributes when this attribute can be deleted. attributes #7 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,ieee" } ; #3 attributes #8 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,dynamic" } ; #6 diff --git a/llvm/test/CodeGen/X86/sse1.ll b/llvm/test/CodeGen/X86/sse1.ll index 8ac86d1..5005752 100644 --- a/llvm/test/CodeGen/X86/sse1.ll +++ b/llvm/test/CodeGen/X86/sse1.ll @@ -251,5 +251,5 @@ define <2 x float> @PR31672() #0 { declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #1 -attributes #0 = { nounwind "unsafe-fp-math"="true" } +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll index 665a84a..d7c9438 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll @@ -1912,7 +1912,7 @@ define <4 x float> @stack_fold_insertps(<4 x float> %a0, <4 x float> %a1) { } declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone -define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1927,7 +1927,7 @@ define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) #0 { } declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone -define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> %a1) #1 { +define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1941,7 +1941,7 @@ define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> ret <2 x double> %2 } -define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 { +define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -1956,7 +1956,7 @@ define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 } declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwind readnone -define <4 x double> @stack_fold_maxpd_ymm_commutable(<4 x double> %a0, <4 x double> %a1) #1 { +define <4 x double> @stack_fold_maxpd_ymm_commutable(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -1970,7 +1970,7 @@ define <4 x double> @stack_fold_maxpd_ymm_commutable(<4 x double> %a0, <4 x doub ret <4 x double> %2 } -define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1985,7 +1985,7 @@ define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone -define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1) #1 { +define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1999,7 +1999,7 @@ define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1 ret <4 x float> %2 } -define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { +define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -2014,7 +2014,7 @@ define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { } declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind readnone -define <8 x float> @stack_fold_maxps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) #1 { +define <8 x float> @stack_fold_maxps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -2028,7 +2028,7 @@ define <8 x float> @stack_fold_maxps_ymm_commutable(<8 x float> %a0, <8 x float> ret <8 x float> %2 } -define double @stack_fold_maxsd(double %a0, double %a1) #0 { +define double @stack_fold_maxsd(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_maxsd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -2043,7 +2043,7 @@ define double @stack_fold_maxsd(double %a0, double %a1) #0 { ret double %3 } -define double @stack_fold_maxsd_commutable(double %a0, double %a1) #1 { +define double @stack_fold_maxsd_commutable(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_maxsd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -2058,7 +2058,7 @@ define double @stack_fold_maxsd_commutable(double %a0, double %a1) #1 { ret double %3 } -define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxsd_int: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2073,7 +2073,7 @@ define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) #0 } declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone -define float @stack_fold_maxss(float %a0, float %a1) #0 { +define float @stack_fold_maxss(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_maxss: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -2088,7 +2088,7 @@ define float @stack_fold_maxss(float %a0, float %a1) #0 { ret float %3 } -define float @stack_fold_maxss_commutable(float %a0, float %a1) #1 { +define float @stack_fold_maxss_commutable(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_maxss_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -2103,7 +2103,7 @@ define float @stack_fold_maxss_commutable(float %a0, float %a1) #1 { ret float %3 } -define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxss_int: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2118,7 +2118,7 @@ define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone -define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2133,7 +2133,7 @@ define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) #0 { } declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone -define <2 x double> @stack_fold_minpd_commutable(<2 x double> %a0, <2 x double> %a1) #1 { +define <2 x double> @stack_fold_minpd_commutable(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2147,7 +2147,7 @@ define <2 x double> @stack_fold_minpd_commutable(<2 x double> %a0, <2 x double> ret <2 x double> %2 } -define <4 x double> @stack_fold_minpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 { +define <4 x double> @stack_fold_minpd_ymm(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -2162,7 +2162,7 @@ define <4 x double> @stack_fold_minpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 } declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwind readnone -define <4 x double> @stack_fold_minpd_ymm_commutable(<4 x double> %a0, <4 x double> %a1) #1 { +define <4 x double> @stack_fold_minpd_ymm_commutable(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -2176,7 +2176,7 @@ define <4 x double> @stack_fold_minpd_ymm_commutable(<4 x double> %a0, <4 x doub ret <4 x double> %2 } -define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minps: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2191,7 +2191,7 @@ define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone -define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1) #1 { +define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2205,7 +2205,7 @@ define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1 ret <4 x float> %2 } -define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { +define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -2220,7 +2220,7 @@ define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { } declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone -define <8 x float> @stack_fold_minps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) #1 { +define <8 x float> @stack_fold_minps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -2234,7 +2234,7 @@ define <8 x float> @stack_fold_minps_ymm_commutable(<8 x float> %a0, <8 x float> ret <8 x float> %2 } -define double @stack_fold_minsd(double %a0, double %a1) #0 { +define double @stack_fold_minsd(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_minsd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -2249,7 +2249,7 @@ define double @stack_fold_minsd(double %a0, double %a1) #0 { ret double %3 } -define double @stack_fold_minsd_commutable(double %a0, double %a1) #1 { +define double @stack_fold_minsd_commutable(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_minsd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -2279,7 +2279,7 @@ define <2 x double> @stack_fold_minsd_int(<2 x double> %a0, <2 x double> %a1) { } declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone -define float @stack_fold_minss(float %a0, float %a1) #0 { +define float @stack_fold_minss(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_minss: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -2294,7 +2294,7 @@ define float @stack_fold_minss(float %a0, float %a1) #0 { ret float %3 } -define float @stack_fold_minss_commutable(float %a0, float %a1) #1 { +define float @stack_fold_minss_commutable(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_minss_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -2309,7 +2309,7 @@ define float @stack_fold_minss_commutable(float %a0, float %a1) #1 { ret float %3 } -define <4 x float> @stack_fold_minss_int(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_minss_int(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minss_int: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -3632,6 +3632,3 @@ define <8 x float> @stack_fold_xorps_ymm(<8 x float> %a0, <8 x float> %a1) { %6 = fadd <8 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0> ret <8 x float> %6 } - -attributes #0 = { "unsafe-fp-math"="false" } -attributes #1 = { "unsafe-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll index a75cdf9d..43743d5 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll @@ -609,7 +609,7 @@ define <4 x float> @stack_fold_insertps(<4 x float> %a0, <4 x float> %a1) { } declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone -define <8 x double> @stack_fold_maxpd_zmm(<8 x double> %a0, <8 x double> %a1) #0 { +define <8 x double> @stack_fold_maxpd_zmm(<8 x double> %a0, <8 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -695,7 +695,7 @@ define <8 x double> @stack_fold_maxpd_zmm_commutable_kz(<8 x double> %a0, <8 x d ret <8 x double> %4 } -define <16 x float> @stack_fold_maxps_zmm(<16 x float> %a0, <16 x float> %a1) #0 { +define <16 x float> @stack_fold_maxps_zmm(<16 x float> %a0, <16 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -781,7 +781,7 @@ define <16 x float> @stack_fold_maxps_zmm_commutable_kz(<16 x float> %a0, <16 x ret <16 x float> %4 } -define <8 x double> @stack_fold_minpd_zmm(<8 x double> %a0, <8 x double> %a1) #0 { +define <8 x double> @stack_fold_minpd_zmm(<8 x double> %a0, <8 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -867,7 +867,7 @@ define <8 x double> @stack_fold_minpd_zmm_commutable_kz(<8 x double> %a0, <8 x d ret <8 x double> %4 } -define <16 x float> @stack_fold_minps_zmm(<16 x float> %a0, <16 x float> %a1) #0 { +define <16 x float> @stack_fold_minps_zmm(<16 x float> %a0, <16 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -1157,7 +1157,7 @@ define <4 x float> @stack_fold_mulss_int(<4 x float> %a0, <4 x float> %a1) { ret <4 x float> %5 } -define <8 x double> @stack_fold_orpd_zmm(<8 x double> %a0, <8 x double> %a1) #0 { +define <8 x double> @stack_fold_orpd_zmm(<8 x double> %a0, <8 x double> %a1) { ; CHECK-LABEL: stack_fold_orpd_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -1178,7 +1178,7 @@ define <8 x double> @stack_fold_orpd_zmm(<8 x double> %a0, <8 x double> %a1) #0 ret <8 x double> %6 } -define <16 x float> @stack_fold_orps_zmm(<16 x float> %a0, <16 x float> %a1) #0 { +define <16 x float> @stack_fold_orps_zmm(<16 x float> %a0, <16 x float> %a1) { ; CHECK-LABEL: stack_fold_orps_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -1414,7 +1414,7 @@ define <4 x float> @stack_fold_subss_int(<4 x float> %a0, <4 x float> %a1) { ret <4 x float> %5 } -define <8 x double> @stack_fold_xorpd_zmm(<8 x double> %a0, <8 x double> %a1) #0 { +define <8 x double> @stack_fold_xorpd_zmm(<8 x double> %a0, <8 x double> %a1) { ; CHECK-LABEL: stack_fold_xorpd_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -1435,7 +1435,7 @@ define <8 x double> @stack_fold_xorpd_zmm(<8 x double> %a0, <8 x double> %a1) #0 ret <8 x double> %6 } -define <16 x float> @stack_fold_xorps_zmm(<16 x float> %a0, <16 x float> %a1) #0 { +define <16 x float> @stack_fold_xorps_zmm(<16 x float> %a0, <16 x float> %a1) { ; CHECK-LABEL: stack_fold_xorps_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -2058,5 +2058,4 @@ define <16 x float> @stack_fold_permilpsvar_zmm_maskz(<16 x float> %a0, <16 x i3 ret <16 x float> %4 } -attributes #0 = { "unsafe-fp-math"="false" } -attributes #1 = { "unsafe-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } +attributes #1 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll index 52d4d8b..b715df8 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll @@ -502,7 +502,7 @@ define <8 x half> @stack_fold_getmantsh_maskz(<8 x half> %a0, <8 x half> %a1, pt ret <8 x half> %3 } -define <32 x half> @stack_fold_maxph_zmm(<32 x half> %a0, <32 x half> %a1) #0 { +define <32 x half> @stack_fold_maxph_zmm(<32 x half> %a0, <32 x half> %a1) { ; CHECK-LABEL: stack_fold_maxph_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -517,7 +517,7 @@ define <32 x half> @stack_fold_maxph_zmm(<32 x half> %a0, <32 x half> %a1) #0 { } declare <32 x half> @llvm.x86.avx512fp16.max.ph.512(<32 x half>, <32 x half>, i32) nounwind readnone -define <32 x half> @stack_fold_maxph_zmm_commuted(<32 x half> %a0, <32 x half> %a1) #0 { +define <32 x half> @stack_fold_maxph_zmm_commuted(<32 x half> %a0, <32 x half> %a1) { ; CHECK-LABEL: stack_fold_maxph_zmm_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -532,7 +532,7 @@ define <32 x half> @stack_fold_maxph_zmm_commuted(<32 x half> %a0, <32 x half> % ret <32 x half> %2 } -define <32 x half> @stack_fold_maxph_zmm_k(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) #0 { +define <32 x half> @stack_fold_maxph_zmm_k(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) { ; CHECK-LABEL: stack_fold_maxph_zmm_k: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -552,7 +552,7 @@ define <32 x half> @stack_fold_maxph_zmm_k(<32 x half> %a0, <32 x half> %a1, i32 ret <32 x half> %5 } -define <32 x half> @stack_fold_maxph_zmm_k_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) #0 { +define <32 x half> @stack_fold_maxph_zmm_k_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) { ; CHECK-LABEL: stack_fold_maxph_zmm_k_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -573,7 +573,7 @@ define <32 x half> @stack_fold_maxph_zmm_k_commuted(<32 x half> %a0, <32 x half> ret <32 x half> %5 } -define <32 x half> @stack_fold_maxph_zmm_kz(<32 x half> %a0, <32 x half> %a1, i32 %mask) #0 { +define <32 x half> @stack_fold_maxph_zmm_kz(<32 x half> %a0, <32 x half> %a1, i32 %mask) { ; CHECK-LABEL: stack_fold_maxph_zmm_kz: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -590,7 +590,7 @@ define <32 x half> @stack_fold_maxph_zmm_kz(<32 x half> %a0, <32 x half> %a1, i3 ret <32 x half> %4 } -define <32 x half> @stack_fold_maxph_zmm_kz_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask) #0 { +define <32 x half> @stack_fold_maxph_zmm_kz_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask) { ; CHECK-LABEL: stack_fold_maxph_zmm_kz_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -710,7 +710,7 @@ define <32 x half> @stack_fold_maxph_zmm_commutable_kz_commuted(<32 x half> %a0, ret <32 x half> %4 } -define half @stack_fold_maxsh(half %a0, half %a1) #0 { +define half @stack_fold_maxsh(half %a0, half %a1) { ; CHECK-LABEL: stack_fold_maxsh: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsh %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -725,7 +725,7 @@ define half @stack_fold_maxsh(half %a0, half %a1) #0 { ret half %3 } -define half @stack_fold_maxsh_commuted(half %a0, half %a1) #0 { +define half @stack_fold_maxsh_commuted(half %a0, half %a1) { ; CHECK-LABEL: stack_fold_maxsh_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsh %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -772,7 +772,7 @@ define half @stack_fold_maxsh_commutable_commuted(half %a0, half %a1) #1 { ret half %3 } -define <8 x half> @stack_fold_maxsh_int(<8 x half> %a0, <8 x half> %a1) #0 { +define <8 x half> @stack_fold_maxsh_int(<8 x half> %a0, <8 x half> %a1) { ; CHECK-LABEL: stack_fold_maxsh_int: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -820,7 +820,7 @@ define <8 x half> @stack_fold_maxsh_maskz(<8 x half> %a0, <8 x half> %a1, i8 %ma ret <8 x half> %2 } -define <32 x half> @stack_fold_minph_zmm(<32 x half> %a0, <32 x half> %a1) #0 { +define <32 x half> @stack_fold_minph_zmm(<32 x half> %a0, <32 x half> %a1) { ; CHECK-LABEL: stack_fold_minph_zmm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -835,7 +835,7 @@ define <32 x half> @stack_fold_minph_zmm(<32 x half> %a0, <32 x half> %a1) #0 { } declare <32 x half> @llvm.x86.avx512fp16.min.ph.512(<32 x half>, <32 x half>, i32) nounwind readnone -define <32 x half> @stack_fold_minph_zmm_commuted(<32 x half> %a0, <32 x half> %a1) #0 { +define <32 x half> @stack_fold_minph_zmm_commuted(<32 x half> %a0, <32 x half> %a1) { ; CHECK-LABEL: stack_fold_minph_zmm_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -850,7 +850,7 @@ define <32 x half> @stack_fold_minph_zmm_commuted(<32 x half> %a0, <32 x half> % ret <32 x half> %2 } -define <32 x half> @stack_fold_minph_zmm_k(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) #0 { +define <32 x half> @stack_fold_minph_zmm_k(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) { ; CHECK-LABEL: stack_fold_minph_zmm_k: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -870,7 +870,7 @@ define <32 x half> @stack_fold_minph_zmm_k(<32 x half> %a0, <32 x half> %a1, i32 ret <32 x half> %5 } -define <32 x half> @stack_fold_minph_zmm_k_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) #0 { +define <32 x half> @stack_fold_minph_zmm_k_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask, ptr %passthru) { ; CHECK-LABEL: stack_fold_minph_zmm_k_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -891,7 +891,7 @@ define <32 x half> @stack_fold_minph_zmm_k_commuted(<32 x half> %a0, <32 x half> ret <32 x half> %5 } -define <32 x half> @stack_fold_minph_zmm_kz(<32 x half> %a0, <32 x half> %a1, i32 %mask) #0 { +define <32 x half> @stack_fold_minph_zmm_kz(<32 x half> %a0, <32 x half> %a1, i32 %mask) { ; CHECK-LABEL: stack_fold_minph_zmm_kz: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -908,7 +908,7 @@ define <32 x half> @stack_fold_minph_zmm_kz(<32 x half> %a0, <32 x half> %a1, i3 ret <32 x half> %4 } -define <32 x half> @stack_fold_minph_zmm_kz_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask) #0 { +define <32 x half> @stack_fold_minph_zmm_kz_commuted(<32 x half> %a0, <32 x half> %a1, i32 %mask) { ; CHECK-LABEL: stack_fold_minph_zmm_kz_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill @@ -1028,7 +1028,7 @@ define <32 x half> @stack_fold_minph_zmm_commutable_kz_commuted(<32 x half> %a0, ret <32 x half> %4 } -define half @stack_fold_minsh(half %a0, half %a1) #0 { +define half @stack_fold_minsh(half %a0, half %a1) { ; CHECK-LABEL: stack_fold_minsh: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsh %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -1043,7 +1043,7 @@ define half @stack_fold_minsh(half %a0, half %a1) #0 { ret half %3 } -define half @stack_fold_minsh_commuted(half %a0, half %a1) #0 { +define half @stack_fold_minsh_commuted(half %a0, half %a1) { ; CHECK-LABEL: stack_fold_minsh_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovsh %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -1090,7 +1090,7 @@ define half @stack_fold_minsh_commutable_commuted(half %a0, half %a1) #1 { ret half %3 } -define <8 x half> @stack_fold_minsh_int(<8 x half> %a0, <8 x half> %a1) #0 { +define <8 x half> @stack_fold_minsh_int(<8 x half> %a0, <8 x half> %a1) { ; CHECK-LABEL: stack_fold_minsh_int: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2316,5 +2316,4 @@ define <4 x float> @stack_fold_fcmaddcsh_maskz(<4 x float> %a0, <4 x float> %a1, } declare <4 x float> @llvm.x86.avx512fp16.maskz.vfcmadd.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32) -attributes #0 = { "unsafe-fp-math"="false" } -attributes #1 = { "unsafe-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } +attributes #1 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll index 4fed6bc..cd06f2d 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll @@ -381,7 +381,7 @@ define <16 x half> @stack_fold_getmantph_maskz_ymm(<16 x half> %a0, ptr %mask) { ret <16 x half> %3 } -define <8 x half> @stack_fold_maxph(<8 x half> %a0, <8 x half> %a1) #0 { +define <8 x half> @stack_fold_maxph(<8 x half> %a0, <8 x half> %a1) { ; CHECK-LABEL: stack_fold_maxph: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -396,7 +396,7 @@ define <8 x half> @stack_fold_maxph(<8 x half> %a0, <8 x half> %a1) #0 { } declare <8 x half> @llvm.x86.avx512fp16.max.ph.128(<8 x half>, <8 x half>) nounwind readnone -define <8 x half> @stack_fold_maxph_commutable(<8 x half> %a0, <8 x half> %a1) #1 { +define <8 x half> @stack_fold_maxph_commutable(<8 x half> %a0, <8 x half> %a1) { ; CHECK-LABEL: stack_fold_maxph_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -410,7 +410,7 @@ define <8 x half> @stack_fold_maxph_commutable(<8 x half> %a0, <8 x half> %a1) # ret <8 x half> %2 } -define <16 x half> @stack_fold_maxph_ymm(<16 x half> %a0, <16 x half> %a1) #0 { +define <16 x half> @stack_fold_maxph_ymm(<16 x half> %a0, <16 x half> %a1) { ; CHECK-LABEL: stack_fold_maxph_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -425,7 +425,7 @@ define <16 x half> @stack_fold_maxph_ymm(<16 x half> %a0, <16 x half> %a1) #0 { } declare <16 x half> @llvm.x86.avx512fp16.max.ph.256(<16 x half>, <16 x half>) nounwind readnone -define <16 x half> @stack_fold_maxph_ymm_commutable(<16 x half> %a0, <16 x half> %a1) #1 { +define <16 x half> @stack_fold_maxph_ymm_commutable(<16 x half> %a0, <16 x half> %a1) { ; CHECK-LABEL: stack_fold_maxph_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -439,7 +439,7 @@ define <16 x half> @stack_fold_maxph_ymm_commutable(<16 x half> %a0, <16 x half> ret <16 x half> %2 } -define <8 x half> @stack_fold_minph(<8 x half> %a0, <8 x half> %a1) #0 { +define <8 x half> @stack_fold_minph(<8 x half> %a0, <8 x half> %a1) { ; CHECK-LABEL: stack_fold_minph: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -454,7 +454,7 @@ define <8 x half> @stack_fold_minph(<8 x half> %a0, <8 x half> %a1) #0 { } declare <8 x half> @llvm.x86.avx512fp16.min.ph.128(<8 x half>, <8 x half>) nounwind readnone -define <8 x half> @stack_fold_minph_commutable(<8 x half> %a0, <8 x half> %a1) #1 { +define <8 x half> @stack_fold_minph_commutable(<8 x half> %a0, <8 x half> %a1) { ; CHECK-LABEL: stack_fold_minph_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -468,7 +468,7 @@ define <8 x half> @stack_fold_minph_commutable(<8 x half> %a0, <8 x half> %a1) # ret <8 x half> %2 } -define <16 x half> @stack_fold_minph_ymm(<16 x half> %a0, <16 x half> %a1) #0 { +define <16 x half> @stack_fold_minph_ymm(<16 x half> %a0, <16 x half> %a1) { ; CHECK-LABEL: stack_fold_minph_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -483,7 +483,7 @@ define <16 x half> @stack_fold_minph_ymm(<16 x half> %a0, <16 x half> %a1) #0 { } declare <16 x half> @llvm.x86.avx512fp16.min.ph.256(<16 x half>, <16 x half>) nounwind readnone -define <16 x half> @stack_fold_minph_ymm_commutable(<16 x half> %a0, <16 x half> %a1) #1 { +define <16 x half> @stack_fold_minph_ymm_commutable(<16 x half> %a0, <16 x half> %a1) { ; CHECK-LABEL: stack_fold_minph_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -1471,6 +1471,3 @@ define <8 x float> @stack_fold_fcmaddc_maskz_ymm(<8 x float> %a0, <8 x float> %a ret <8 x float> %3 } declare <8 x float> @llvm.x86.avx512fp16.maskz.vfcmadd.cph.256(<8 x float>, <8 x float>, <8 x float>, i8) - -attributes #0 = { "unsafe-fp-math"="false" } -attributes #1 = { "unsafe-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512vl.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512vl.ll index b370a80..bd56e61 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512vl.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512vl.ll @@ -457,7 +457,7 @@ define <4 x float> @stack_fold_cvtpd2ps_ymm(<4 x double> %a0) { ret <4 x float> %2 } -define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -472,7 +472,7 @@ define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) #0 { } declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone -define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> %a1) #1 { +define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -486,7 +486,7 @@ define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> ret <2 x double> %2 } -define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 { +define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -501,7 +501,7 @@ define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 } declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwind readnone -define <4 x double> @stack_fold_maxpd_ymm_commutable(<4 x double> %a0, <4 x double> %a1) #1 { +define <4 x double> @stack_fold_maxpd_ymm_commutable(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -515,7 +515,7 @@ define <4 x double> @stack_fold_maxpd_ymm_commutable(<4 x double> %a0, <4 x doub ret <4 x double> %2 } -define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -530,7 +530,7 @@ define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone -define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1) #1 { +define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -544,7 +544,7 @@ define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1 ret <4 x float> %2 } -define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { +define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -559,7 +559,7 @@ define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { } declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind readnone -define <8 x float> @stack_fold_maxps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) #1 { +define <8 x float> @stack_fold_maxps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -573,7 +573,7 @@ define <8 x float> @stack_fold_maxps_ymm_commutable(<8 x float> %a0, <8 x float> ret <8 x float> %2 } -define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minps: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -588,7 +588,7 @@ define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone -define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1) #1 { +define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -602,7 +602,7 @@ define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1 ret <4 x float> %2 } -define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { +define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -617,7 +617,7 @@ define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) #0 { } declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone -define <8 x float> @stack_fold_minps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) #1 { +define <8 x float> @stack_fold_minps_ymm_commutable(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_ymm_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -687,7 +687,7 @@ define <8 x float> @stack_fold_mulps_ymm(<8 x float> %a0, <8 x float> %a1) { ret <8 x float> %2 } -define <2 x double> @stack_fold_orpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_orpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_orpd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -708,7 +708,7 @@ define <2 x double> @stack_fold_orpd(<2 x double> %a0, <2 x double> %a1) #0 { ret <2 x double> %6 } -define <4 x double> @stack_fold_orpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 { +define <4 x double> @stack_fold_orpd_ymm(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_orpd_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -939,7 +939,7 @@ define <8 x float> @stack_fold_subps_ymm(<8 x float> %a0, <8 x float> %a1) { ret <8 x float> %2 } -define <2 x double> @stack_fold_xorpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_xorpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_xorpd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -960,7 +960,7 @@ define <2 x double> @stack_fold_xorpd(<2 x double> %a0, <2 x double> %a1) #0 { ret <2 x double> %6 } -define <4 x double> @stack_fold_xorpd_ymm(<4 x double> %a0, <4 x double> %a1) #0 { +define <4 x double> @stack_fold_xorpd_ymm(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: stack_fold_xorpd_ymm: ; CHECK: # %bb.0: ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill @@ -1391,6 +1391,3 @@ declare <4 x float> @llvm.x86.avx512.vpermi2var.ps.128(<4 x float>, <4 x i32>, < declare <2 x double> @llvm.x86.avx512.vpermi2var.pd.128(<2 x double>, <2 x i64>, <2 x double>) declare <8 x float> @llvm.x86.avx512.vpermi2var.ps.256(<8 x float>, <8 x i32>, <8 x float>) declare <4 x double> @llvm.x86.avx512.vpermi2var.pd.256(<4 x double>, <4 x i64>, <4 x double>) - -attributes #0 = { "unsafe-fp-math"="false" } -attributes #1 = { "unsafe-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-sse42.ll b/llvm/test/CodeGen/X86/stack-folding-fp-sse42.ll index 306ee31..9bc9a9c 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-sse42.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-sse42.ll @@ -1424,7 +1424,7 @@ define <4 x float> @stack_fold_insertps(<4 x float> %a0, <4 x float> %a1) { } declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone -define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1439,7 +1439,7 @@ define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) #0 { } declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone -define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> %a1) #1 { +define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxpd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1453,7 +1453,7 @@ define <2 x double> @stack_fold_maxpd_commutable(<2 x double> %a0, <2 x double> ret <2 x double> %2 } -define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1468,7 +1468,7 @@ define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone -define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1) #1 { +define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxps_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1482,7 +1482,7 @@ define <4 x float> @stack_fold_maxps_commutable(<4 x float> %a0, <4 x float> %a1 ret <4 x float> %2 } -define double @stack_fold_maxsd(double %a0, double %a1) #0 { +define double @stack_fold_maxsd(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_maxsd: ; CHECK: # %bb.0: ; CHECK-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -1497,7 +1497,7 @@ define double @stack_fold_maxsd(double %a0, double %a1) #0 { ret double %3 } -define double @stack_fold_maxsd_commutable(double %a0, double %a1) #1 { +define double @stack_fold_maxsd_commutable(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_maxsd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -1512,7 +1512,7 @@ define double @stack_fold_maxsd_commutable(double %a0, double %a1) #1 { ret double %3 } -define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_maxsd_int: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1527,7 +1527,7 @@ define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) #0 } declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone -define float @stack_fold_maxss(float %a0, float %a1) #0 { +define float @stack_fold_maxss(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_maxss: ; CHECK: # %bb.0: ; CHECK-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -1542,7 +1542,7 @@ define float @stack_fold_maxss(float %a0, float %a1) #0 { ret float %3 } -define float @stack_fold_maxss_commutable(float %a0, float %a1) #1 { +define float @stack_fold_maxss_commutable(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_maxss_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -1557,7 +1557,7 @@ define float @stack_fold_maxss_commutable(float %a0, float %a1) #1 { ret float %3 } -define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_maxss_int: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1572,7 +1572,7 @@ define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone -define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1587,7 +1587,7 @@ define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) #0 { } declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone -define <2 x double> @stack_fold_minpd_commutable(<2 x double> %a0, <2 x double> %a1) #1 { +define <2 x double> @stack_fold_minpd_commutable(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_minpd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1601,7 +1601,7 @@ define <2 x double> @stack_fold_minpd_commutable(<2 x double> %a0, <2 x double> ret <2 x double> %2 } -define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minps: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1616,7 +1616,7 @@ define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) #0 { } declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone -define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1) #1 { +define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minps_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1630,7 +1630,7 @@ define <4 x float> @stack_fold_minps_commutable(<4 x float> %a0, <4 x float> %a1 ret <4 x float> %2 } -define double @stack_fold_minsd(double %a0, double %a1) #0 { +define double @stack_fold_minsd(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_minsd: ; CHECK: # %bb.0: ; CHECK-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -1645,7 +1645,7 @@ define double @stack_fold_minsd(double %a0, double %a1) #0 { ret double %3 } -define double @stack_fold_minsd_commutable(double %a0, double %a1) #1 { +define double @stack_fold_minsd_commutable(double %a0, double %a1) { ; CHECK-LABEL: stack_fold_minsd_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -1660,7 +1660,7 @@ define double @stack_fold_minsd_commutable(double %a0, double %a1) #1 { ret double %3 } -define <2 x double> @stack_fold_minsd_int(<2 x double> %a0, <2 x double> %a1) #0 { +define <2 x double> @stack_fold_minsd_int(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: stack_fold_minsd_int: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -1675,7 +1675,7 @@ define <2 x double> @stack_fold_minsd_int(<2 x double> %a0, <2 x double> %a1) #0 } declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone -define float @stack_fold_minss(float %a0, float %a1) #0 { +define float @stack_fold_minss(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_minss: ; CHECK: # %bb.0: ; CHECK-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -1690,7 +1690,7 @@ define float @stack_fold_minss(float %a0, float %a1) #0 { ret float %3 } -define float @stack_fold_minss_commutable(float %a0, float %a1) #1 { +define float @stack_fold_minss_commutable(float %a0, float %a1) { ; CHECK-LABEL: stack_fold_minss_commutable: ; CHECK: # %bb.0: ; CHECK-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -1705,7 +1705,7 @@ define float @stack_fold_minss_commutable(float %a0, float %a1) #1 { ret float %3 } -define <4 x float> @stack_fold_minss_int(<4 x float> %a0, <4 x float> %a1) #0 { +define <4 x float> @stack_fold_minss_int(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: stack_fold_minss_int: ; CHECK: # %bb.0: ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill @@ -2490,6 +2490,3 @@ define <4 x float> @stack_fold_xorps(<4 x float> %a0, <4 x float> %a1) { declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) - -attributes #0 = { "unsafe-fp-math"="false" } -attributes #1 = { "unsafe-fp-math"="true" } diff --git a/llvm/test/CodeGen/X86/stack-protector-3.ll b/llvm/test/CodeGen/X86/stack-protector-3.ll index 59784af..8ca6a56 100644 --- a/llvm/test/CodeGen/X86/stack-protector-3.ll +++ b/llvm/test/CodeGen/X86/stack-protector-3.ll @@ -118,7 +118,7 @@ declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 ; Function Attrs: argmemonly nounwind willreturn declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1 -attributes #0 = { nounwind sspreq uwtable writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind sspreq uwtable writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind willreturn } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll b/llvm/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll index 63390e4..4bc91bf 100644 --- a/llvm/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll +++ b/llvm/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll @@ -55,6 +55,6 @@ entry: declare void @f(i32) #1 -attributes #0 = { nounwind sspreq "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind sspreq "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/stack_guard_remat.ll b/llvm/test/CodeGen/X86/stack_guard_remat.ll index f7a602c..f53fa0b4 100644 --- a/llvm/test/CodeGen/X86/stack_guard_remat.ll +++ b/llvm/test/CodeGen/X86/stack_guard_remat.ll @@ -23,4 +23,4 @@ declare void @foo3(ptr) ; Function Attrs: nounwind declare void @llvm.lifetime.end.p0(i64, ptr nocapture) -attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/tail-merge-wineh.ll b/llvm/test/CodeGen/X86/tail-merge-wineh.ll index 00bddc1..a208368 100644 --- a/llvm/test/CodeGen/X86/tail-merge-wineh.ll +++ b/llvm/test/CodeGen/X86/tail-merge-wineh.ll @@ -101,5 +101,5 @@ declare x86_stdcallcc void @_CxxThrowException(ptr, ptr) declare i32 @__CxxFrameHandler3(...) -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { noreturn } diff --git a/llvm/test/CodeGen/X86/tls-shrink-wrapping.ll b/llvm/test/CodeGen/X86/tls-shrink-wrapping.ll index 2749ebd..f0d5a16 100644 --- a/llvm/test/CodeGen/X86/tls-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/tls-shrink-wrapping.ll @@ -51,6 +51,6 @@ if.end: ; preds = %if.then, %entry declare void @f(...) #1 -attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } +attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/unused_stackslots.ll b/llvm/test/CodeGen/X86/unused_stackslots.ll index d909dd4..4d390bd 100644 --- a/llvm/test/CodeGen/X86/unused_stackslots.ll +++ b/llvm/test/CodeGen/X86/unused_stackslots.ll @@ -215,8 +215,8 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, ; Function Attrs: argmemonly nounwind declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 -attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "use-soft-float"="false" } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/X86/uwtables.ll b/llvm/test/CodeGen/X86/uwtables.ll index 1e2e1d9..68a5ff1 100644 --- a/llvm/test/CodeGen/X86/uwtables.ll +++ b/llvm/test/CodeGen/X86/uwtables.ll @@ -38,5 +38,5 @@ declare i32 @__gxx_personality_v0(...) declare void @__cxa_call_unexpected(ptr) local_unnamed_addr -attributes #0 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll index 910dd1e..5954e34 100644 --- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll +++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll @@ -5435,7 +5435,7 @@ define double @extract3_uitofp_v4i32_f64(<4 x i32> %x) nounwind { ret double %r } -define void @PR43609(ptr nocapture %x, <2 x i64> %y) #0 { +define void @PR43609(ptr nocapture %x, <2 x i64> %y) { ; SSE2-LABEL: PR43609: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,2] @@ -5643,6 +5643,3 @@ define void @PR43609(ptr nocapture %x, <2 x i64> %y) #0 { store <2 x double> %t23, ptr %t26, align 8 ret void } - -attributes #0 = { "unsafe-fp-math"="true" } - diff --git a/llvm/test/CodeGen/X86/vector-sqrt.ll b/llvm/test/CodeGen/X86/vector-sqrt.ll index b08784a..843f099a 100644 --- a/llvm/test/CodeGen/X86/vector-sqrt.ll +++ b/llvm/test/CodeGen/X86/vector-sqrt.ll @@ -63,6 +63,6 @@ entry: ; Function Attrs: nounwind readnone declare float @sqrtf(float) local_unnamed_addr #1 -attributes #0 = { nounwind readonly uwtable "target-features"="+avx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind readnone "target-features"="+avx2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readonly uwtable "target-features"="+avx" "use-soft-float"="false" } +attributes #1 = { nounwind readnone "target-features"="+avx2" "use-soft-float"="false" } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/X86/vector-width-store-merge.ll b/llvm/test/CodeGen/X86/vector-width-store-merge.ll index 50c7b01..9363348 100644 --- a/llvm/test/CodeGen/X86/vector-width-store-merge.ll +++ b/llvm/test/CodeGen/X86/vector-width-store-merge.ll @@ -85,8 +85,8 @@ entry: ; Function Attrs: argmemonly nounwind declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1 immarg) #1 -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "use-soft-float"="false" } !0 = !{i32 1, !"wchar_size", i32 4} diff --git a/llvm/test/CodeGen/X86/win-cleanuppad.ll b/llvm/test/CodeGen/X86/win-cleanuppad.ll index e9265a1..59dcccc 100644 --- a/llvm/test/CodeGen/X86/win-cleanuppad.ll +++ b/llvm/test/CodeGen/X86/win-cleanuppad.ll @@ -194,6 +194,6 @@ cleanup.outer: ; preds = %invoke.cont.1, %c ; X64-NEXT: .long .Ltmp7@IMGREL ; X64-NEXT: .long -1 -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/X86/win32-seh-catchpad.ll b/llvm/test/CodeGen/X86/win32-seh-catchpad.ll index 832ddca..0f51866 100644 --- a/llvm/test/CodeGen/X86/win32-seh-catchpad.ll +++ b/llvm/test/CodeGen/X86/win32-seh-catchpad.ll @@ -220,7 +220,7 @@ declare i32 @_except_handler3(...) ; Function Attrs: nounwind declare void @llvm.localescape(...) #2 -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } attributes #3 = { noinline } diff --git a/llvm/test/CodeGen/X86/win32-seh-nested-finally.ll b/llvm/test/CodeGen/X86/win32-seh-nested-finally.ll index 5b1f9b3..5095460 100644 --- a/llvm/test/CodeGen/X86/win32-seh-nested-finally.ll +++ b/llvm/test/CodeGen/X86/win32-seh-nested-finally.ll @@ -34,8 +34,8 @@ declare void @f(i32) #0 declare i32 @_except_handler3(...) -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { noinline nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { noinline nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { noinline } diff --git a/llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll b/llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll index 785c260..d4d4fe3 100644 --- a/llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll +++ b/llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll @@ -272,12 +272,12 @@ declare dso_local void @llvm.seh.try.end() #2 ; Function Attrs: nounwind readnone declare i32 @llvm.eh.exceptioncode(token) #3 -attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { noinline optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { noinline optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind willreturn } attributes #3 = { nounwind readnone } -attributes #4 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #5 = { noinline norecurse optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #4 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #5 = { noinline norecurse optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #6 = { nounwind } attributes #7 = { noreturn } attributes #8 = { noinline } diff --git a/llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll b/llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll index 6c6e9c3..b0baaac 100644 --- a/llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll +++ b/llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll @@ -240,12 +240,12 @@ declare i32 @llvm.eh.exceptioncode(token) #1 declare dso_local void @"?printf@@YAXZZ"(...) #5 -attributes #0 = { noinline optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #1 = { nounwind readnone } -attributes #2 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { noinline norecurse optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #3 = { noinline norecurse optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #4 = { nounwind willreturn } -attributes #5 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #5 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #6 = { nounwind } attributes #7 = { noinline } diff --git a/llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll b/llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll index 9e44299..d3da5f8 100644 --- a/llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll +++ b/llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll @@ -209,10 +209,10 @@ declare i32 @llvm.eh.exceptioncode(token) #4 ; Function Attrs: nounwind declare void @llvm.localescape(...) #5 -attributes #0 = { noinline norecurse optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline norecurse optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #2 = { nounwind willreturn } -attributes #3 = { noinline "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { noinline "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #4 = { nounwind readnone } attributes #5 = { nounwind } attributes #6 = { noinline } diff --git a/llvm/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll b/llvm/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll index cb12481..9f888f8 100644 --- a/llvm/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll +++ b/llvm/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll @@ -24,7 +24,7 @@ entry: ret i64 %or } -attributes #0 = { minsize nounwind readnone uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { minsize nounwind readnone uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } ; clang -Os -c test2.cpp -emit-llvm -S @@ -63,7 +63,7 @@ entry: ret i64 %or } -attributes #1 = { nounwind optsize readnone uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind optsize readnone uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } ; clang -O2 -c test2.cpp -emit-llvm -S ; Verify that we do not generate shld insruction when we are not optimizing @@ -89,7 +89,7 @@ entry: ret i64 %or } -attributes #2= { nounwind readnone uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2= { nounwind readnone uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } !llvm.module.flags = !{!0} !0 = !{i32 1, !"ProfileSummary", !1} diff --git a/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s b/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s index cf8d21658..15efbee 100644 --- a/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s +++ b/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s @@ -16,7 +16,7 @@ fmmla v0.4s, v1.4s, v2.4s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: fmmla v0.8h, v1.8h, v2.8h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: f16mm // CHECK-NEXT: fmmla v0.8h, v1.8h, v2.8h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s b/llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s new file mode 100644 index 0000000..c25ff66 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s @@ -0,0 +1,191 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +luti6 z0.h, zt0, z0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: luti6 z0.h, zt0, z0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 z0.s, zt0, z0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: luti6 z0.s, zt0, z0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 z0.d, zt0, z0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: luti6 z0.d, zt0, z0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 z0.b, zt0, z1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 z0.b, zt0, z1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 z0.b, zt0, z1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 z0.b, zt0, z1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vectors/mis-matched registers/invalid index + +luti6 { z0.h - z5.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: luti6 { z0.h - z5.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.b - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: luti6 { z0.b - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Wrong striding/registers/index + +luti6 { z0.h, z4.h, z8.h, z13.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride +// CHECK-NEXT: luti6 { z0.h, z4.h, z8.h, z13.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z1.h, z2.h, z3.h, z4.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: luti6 { z1.h, z2.h, z3.h, z4.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.b, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: luti6 { z0.b, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid registers + +luti6 { z0.b - z5.b }, zt0, { z2 - z4 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: luti6 { z0.b - z5.b }, zt0, { z2 - z4 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.b - z3.b }, zt0, { z1 - z1 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: luti6 { z0.b - z3.b }, zt0, { z1 - z1 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.b - z5.b }, zt0, { z7 - z11 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: luti6 { z0.b - z5.b }, zt0, { z7 - z11 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z0.b - z3.b }, zt1, { z1 - z3 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid lookup table, expected zt0 +// CHECK-NEXT: luti6 { z0.b - z3.b }, zt1, { z1 - z3 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z4.b, z8.b, z12.b, z16.b}, zt0, { z2 - z5 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: luti6 { z4.b, z8.b, z12.b, z16.b}, zt0, { z2 - z5 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z17.b, z21.b, z25.b, z29.b}, zt0, { z2 - z5 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: luti6 { z17.b, z21.b, z25.b, z29.b}, zt0, { z2 - z5 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 { z0.b - z3.b }, zt0, { z1 - z3 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.b - z3.b }, zt0, { z1 - z3 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 { z0.b - z3.b }, zt0, { z1 - z3 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.b - z3.b }, zt0, { z1 - z3 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Wrong striding/registers + +luti6 { z1.b, z5.b, z9.b, z14.b }, zt0, { z0 - z2 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride +// CHECK-NEXT: luti6 { z1.b, z5.b, z9.b, z14.b }, zt0, { z0 - z2 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z1.b, z2.b, z3.b, z4.b }, zt0, { z0 - z2 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: luti6 { z1.b, z2.b, z3.b, z4.b }, zt0, { z0 - z2 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z20.b, z24.b, z28.b, z32.b }, zt0, { z0 - z2 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: luti6 { z20.b, z24.b, z28.b, z32.b }, zt0, { z0 - z2 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 { z1.h, z5.h, z9.h, z13.h }, zt0, { z0 - z2 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: luti6 { z1.h, z5.h, z9.h, z13.h }, zt0, { z0 - z2 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z2 - z4 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z2 - z4 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z0 - z2 } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z0 - z2 } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2p3/luti6.s b/llvm/test/MC/AArch64/SME2p3/luti6.s new file mode 100644 index 0000000..7a7872f --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p3/luti6.s @@ -0,0 +1,472 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ---------------------------------------------------------- +// Lookup table read with 6-bit indices (single) + +luti6 z0.b, zt0, z0 +// CHECK-INST: luti6 z0.b, zt0, z0 +// CHECK-ENCODING: encoding: [0x00,0x40,0xc8,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c0c84000 <unknown> + +luti6 z31.b, zt0, z0 +// CHECK-INST: luti6 z31.b, zt0, z0 +// CHECK-ENCODING: encoding: [0x1f,0x40,0xc8,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c0c8401f <unknown> + +luti6 z0.b, zt0, z31 +// CHECK-INST: luti6 z0.b, zt0, z31 +// CHECK-ENCODING: encoding: [0xe0,0x43,0xc8,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c0c843e0 <unknown> + +luti6 z31.b, zt0, z31 +// CHECK-INST: luti6 z31.b, zt0, z31 +// CHECK-ENCODING: encoding: [0xff,0x43,0xc8,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c0c843ff <unknown> + +// ---------------------------------------------------------- +// Lookup table read with 6-bit indices (16-bit) - consecutive + +luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z0.h - z3.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x00,0xf4,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120f400 <unknown> + +luti6 { z8.h - z11.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z8.h - z11.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x08,0xf4,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120f408 <unknown> + +luti6 { z20.h - z23.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z20.h - z23.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x14,0xf4,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120f414 <unknown> + +luti6 { z28.h - z31.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z28.h - z31.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x1c,0xf4,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120f41c <unknown> + +luti6 { z0.h - z3.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z0.h - z3.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xe0,0xf7,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ff7e0 <unknown> + +luti6 { z8.h - z11.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z8.h - z11.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xe8,0xf7,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ff7e8 <unknown> + +luti6 { z20.h - z23.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z20.h - z23.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xf4,0xf7,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ff7f4 <unknown> + +luti6 { z28.h - z31.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z28.h - z31.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xfc,0xf7,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ff7fc <unknown> + +// ---------------------------------------------------------- +// Lookup table read with 6-bit indices (16-bit) - strided + +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x00,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc00 <unknown> + +luti6 { z1.h, z5.h, z9.h, z13.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z1.h, z5.h, z9.h, z13.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x01,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc01 <unknown> + +luti6 { z2.h, z6.h, z10.h, z14.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z2.h, z6.h, z10.h, z14.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x02,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc02 <unknown> + +luti6 { z3.h, z7.h, z11.h, z15.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z3.h, z7.h, z11.h, z15.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x03,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc03 <unknown> + +luti6 { z16.h, z20.h, z24.h, z28.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z16.h, z20.h, z24.h, z28.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x10,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc10 <unknown> + +luti6 { z17.h, z21.h, z25.h, z29.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z17.h, z21.h, z25.h, z29.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x11,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc11 <unknown> + +luti6 { z18.h, z22.h, z26.h, z30.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z18.h, z22.h, z26.h, z30.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x12,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc12 <unknown> + +luti6 { z19.h, z23.h, z27.h, z31.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-INST: luti6 { z19.h, z23.h, z27.h, z31.h }, { z0.h, z1.h }, { z0, z1 }[0] +// CHECK-ENCODING: encoding: [0x13,0xfc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c120fc13 <unknown> + +luti6 { z0.h, z4.h, z8.h, z12.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z0.h, z4.h, z8.h, z12.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xe0,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17fffe0 <unknown> + +luti6 { z1.h, z5.h, z9.h, z13.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z1.h, z5.h, z9.h, z13.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xe1,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17fffe1 <unknown> + +luti6 { z2.h, z6.h, z10.h, z14.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z2.h, z6.h, z10.h, z14.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xe2,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17fffe2 <unknown> + +luti6 { z3.h, z7.h, z11.h, z15.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z3.h, z7.h, z11.h, z15.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xe3,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17fffe3 <unknown> + +luti6 { z16.h, z20.h, z24.h, z28.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z16.h, z20.h, z24.h, z28.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xf0,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ffff0 <unknown> + +luti6 { z17.h, z21.h, z25.h, z29.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z17.h, z21.h, z25.h, z29.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xf1,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ffff1 <unknown> + +luti6 { z18.h, z22.h, z26.h, z30.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z18.h, z22.h, z26.h, z30.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xf2,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ffff2 <unknown> + +luti6 { z19.h, z23.h, z27.h, z31.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-INST: luti6 { z19.h, z23.h, z27.h, z31.h }, { z31.h, z0.h }, { z31, z0 }[1] +// CHECK-ENCODING: encoding: [0xf3,0xff,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c17ffff3 <unknown> + +// ---------------------------------------------------------- +// Lookup table read with 6-bit indices (8-bit) - consecutive + +luti6 { z8.b - z11.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z8.b - z11.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x08,0x00,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0008 <unknown> + +luti6 { z20.b - z23.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z20.b - z23.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x14,0x00,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0014 <unknown> + +luti6 { z28.b - z31.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z28.b - z31.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x1c,0x00,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a001c <unknown> + +luti6 { z0.b - z3.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z0.b - z3.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x00,0x01,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0100 <unknown> + +luti6 { z8.b - z11.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z8.b - z11.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x08,0x01,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0108 <unknown> + +luti6 { z20.b - z23.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z20.b - z23.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x14,0x01,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0114 <unknown> + +luti6 { z28.b - z31.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z28.b - z31.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x1c,0x01,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a011c <unknown> + +luti6 { z0.b - z3.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z0.b - z3.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x80,0x02,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0280 <unknown> + +luti6 { z8.b - z11.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z8.b - z11.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x88,0x02,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0288 <unknown> + +luti6 { z20.b - z23.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z20.b - z23.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x94,0x02,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0294 <unknown> + +luti6 { z28.b - z31.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z28.b - z31.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x9c,0x02,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a029c <unknown> + +luti6 { z0.b - z3.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z0.b - z3.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x80,0x03,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0380 <unknown> + +luti6 { z8.b - z11.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z8.b - z11.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x88,0x03,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0388 <unknown> + +luti6 { z20.b - z23.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z20.b - z23.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x94,0x03,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a0394 <unknown> + +luti6 { z28.b - z31.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z28.b - z31.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x9c,0x03,0x8a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c08a039c <unknown> + +// ---------------------------------------------------------- +// Lookup table read with 6-bit indices (8-bit) - strided + +luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x01,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0001 <unknown> + +luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x02,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0002 <unknown> + +luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x03,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0003 <unknown> + +luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x10,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0010 <unknown> + +luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x11,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0011 <unknown> + +luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x12,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0012 <unknown> + +luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z0 - z2 } +// CHECK-INST: luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z0 - z2 } +// CHECK-ENCODING: encoding: [0x13,0x00,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0013 <unknown> + +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x00,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0100 <unknown> + +luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x01,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0101 <unknown> + +luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x02,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0102 <unknown> + +luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x03,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0103 <unknown> + +luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x10,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0110 <unknown> + +luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x11,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0111 <unknown> + +luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x12,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0112 <unknown> + +luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z2 - z4 } +// CHECK-INST: luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z2 - z4 } +// CHECK-ENCODING: encoding: [0x13,0x01,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0113 <unknown> + +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x80,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0280 <unknown> + +luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x81,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0281 <unknown> + +luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x82,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0282 <unknown> + +luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x83,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0283 <unknown> + +luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x90,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0290 <unknown> + +luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x91,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0291 <unknown> + +luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x92,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0292 <unknown> + +luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z5 - z7 } +// CHECK-INST: luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z5 - z7 } +// CHECK-ENCODING: encoding: [0x93,0x02,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0293 <unknown> + +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x80,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0380 <unknown> + +luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z1.b, z5.b, z9.b, z13.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x81,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0381 <unknown> + +luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z2.b, z6.b, z10.b, z14.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x82,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0382 <unknown> + +luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z3.b, z7.b, z11.b, z15.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x83,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0383 <unknown> + +luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z16.b, z20.b, z24.b, z28.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x90,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0390 <unknown> + +luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z17.b, z21.b, z25.b, z29.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x91,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0391 <unknown> + +luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z18.b, z22.b, z26.b, z30.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x92,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0392 <unknown> + +luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z7 - z9 } +// CHECK-INST: luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z7 - z9 } +// CHECK-ENCODING: encoding: [0x93,0x03,0x9a,0xc0] +// CHECK-ERROR: instruction requires: sme2p3 +// CHECK-UNKNOWN: c09a0393 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s b/llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s index 409c2c5..4695b05 100644 --- a/llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s @@ -5,11 +5,6 @@ bfmmla z0.s, z1.s, z2.h // CHECK-NEXT: bfmmla z0.s, z1.s, z2.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -bfmmla z0.h, z1.h, z2.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: bfmmla z0.h, z1.h, z2.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - bfmmla z0.s, z1.h, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: bfmmla z0.s, z1.h, z2.s diff --git a/llvm/test/MC/AArch64/SVE2p1/sdot-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/sdot-diagnostics.s index 344abb1..42c6ae7 100644 --- a/llvm/test/MC/AArch64/SVE2p1/sdot-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/sdot-diagnostics.s @@ -29,7 +29,7 @@ sdot z0.s, z0.h, z0.h[-1] // Invalid vector suffix sdot z0.h, z0.s, z0.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: sdot z0.h, z0.s, z0.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/udot-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/udot-diagnostics.s index 0debddf..aa2ec7f 100644 --- a/llvm/test/MC/AArch64/SVE2p1/udot-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/udot-diagnostics.s @@ -29,11 +29,11 @@ udot z0.s, z0.h, z0.h[-1] // Invalid vector suffix udot z0.h, z0.s, z0.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: udot z0.h, z0.s, z0.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: udot z0.h, z0.s, z0.s[1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: udot z0.h, z0.s, z0.s[1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/fmmla-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/fmmla-diagnostics.s new file mode 100644 index 0000000..e88fcce --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fmmla-diagnostics.s @@ -0,0 +1,15 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2,+f16mm 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +fmmla z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmmla z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z6.d +fmmla z0.h, z2.h, z3.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmmla z0.h, z2.h, z3.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/fmmla.s b/llvm/test/MC/AArch64/SVE2p2/fmmla.s new file mode 100644 index 0000000..19929a9 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fmmla.s @@ -0,0 +1,45 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2,+f16mm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2,+f16mm < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2,+f16mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2,+f16mm < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2,-f16mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2,+f16mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2,+f16mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +fmmla z0.h, z0.h, z0.h +// CHECK-INST: fmmla z0.h, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0xe0,0xa0,0x64] +// CHECK-ERROR: instruction requires: f16mm sve2p2 +// CHECK-UNKNOWN: 64a0e000 <unknown> + +fmmla z10.h, z10.h, z10.h +// CHECK-INST: fmmla z10.h, z10.h, z10.h +// CHECK-ENCODING: encoding: [0x4a,0xe1,0xaa,0x64] +// CHECK-ERROR: instruction requires: f16mm sve2p2 +// CHECK-UNKNOWN: 64aae14a <unknown> + +fmmla z21.h, z21.h, z21.h +// CHECK-INST: fmmla z21.h, z21.h, z21.h +// CHECK-ENCODING: encoding: [0xb5,0xe2,0xb5,0x64] +// CHECK-ERROR: instruction requires: f16mm sve2p2 +// CHECK-UNKNOWN: 64b5e2b5 <unknown> + +fmmla z31.h, z31.h, z31.h +// CHECK-INST: fmmla z31.h, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0xe3,0xbf,0x64] +// CHECK-ERROR: instruction requires: f16mm sve2p2 +// CHECK-UNKNOWN: 64bfe3ff <unknown> + +movprfx z0, z7 +fmmla z0.h, z1.h, z2.h +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: fmmla z0.h, z1.h, z2.h +// CHECK-ENCODING: encoding: [0x20,0xe0,0xa2,0x64] +// CHECK-ERROR: instruction requires: f16mm sve2p2 +// CHECK-UNKNOWN: 64a2e020 <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/arithmetic-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/arithmetic-diagnostics.s new file mode 100644 index 0000000..2c0cf07 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/arithmetic-diagnostics.s @@ -0,0 +1,147 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Test addqp + +addqp z0.h, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addqp z0.h, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addqp z0.s, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addqp z0.s, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addqp z0.d, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addqp z0.d, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addqp z0.b, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addqp z0.b, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Test addsubp + +addsubp z0.h, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addsubp z0.h, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addsubp z0.s, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addsubp z0.s, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addsubp z0.d, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addsubp z0.d, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addsubp z0.b, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addsubp z0.b, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Test sabal + +sabal z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabal z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabal z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabal z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabal z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabal z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabal z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabal z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Test uabal + +uabal z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabal z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabal z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabal z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabal z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabal z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabal z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabal z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Test subp + +subp z0.h, p0/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subp z0.h, p0/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subp z0.s, p0/m, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subp z0.s, p0/m, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subp z0.d, p0/m, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subp z0.d, p0/m, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subp z0.b, p0/m, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subp z0.b, p0/m, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +subp z0.h, p8/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: subp z0.h, p8/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Operand must match destination register + +subp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: subp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +addqp z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: addqp z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +addsubp z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: addsubp z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/arithmetic.s b/llvm/test/MC/AArch64/SVE2p3/arithmetic.s new file mode 100644 index 0000000..12df18d --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/arithmetic.s @@ -0,0 +1,275 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +addqp z0.b, z0.b, z0.b +// CHECK-INST: addqp z0.b, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0x78,0x20,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04207800 <unknown> + +addqp z31.b, z31.b, z31.b +// CHECK-INST: addqp z31.b, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0x7b,0x3f,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 043f7bff <unknown> + +addqp z0.h, z0.h, z0.h +// CHECK-INST: addqp z0.h, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0x78,0x60,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04607800 <unknown> + +addqp z31.h, z31.h, z31.h +// CHECK-INST: addqp z31.h, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0x7b,0x7f,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 047f7bff <unknown> + +addqp z0.s, z0.s, z0.s +// CHECK-INST: addqp z0.s, z0.s, z0.s +// CHECK-ENCODING: encoding: [0x00,0x78,0xa0,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04a07800 <unknown> + +addqp z31.s, z31.s, z31.s +// CHECK-INST: addqp z31.s, z31.s, z31.s +// CHECK-ENCODING: encoding: [0xff,0x7b,0xbf,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04bf7bff <unknown> + +addqp z0.d, z0.d, z0.d +// CHECK-INST: addqp z0.d, z0.d, z0.d +// CHECK-ENCODING: encoding: [0x00,0x78,0xe0,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04e07800 <unknown> + +addqp z31.d, z31.d, z31.d +// CHECK-INST: addqp z31.d, z31.d, z31.d +// CHECK-ENCODING: encoding: [0xff,0x7b,0xff,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04ff7bff <unknown> + +// --------------------------------------------------------------------------// +// Test addsubp + +addsubp z0.b, z0.b, z0.b +// CHECK-INST: addsubp z0.b, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0x7c,0x20,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04207c00 <unknown> + +addsubp z31.b, z31.b, z31.b +// CHECK-INST: addsubp z31.b, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0x7f,0x3f,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 043f7fff <unknown> + +addsubp z0.h, z0.h, z0.h +// CHECK-INST: addsubp z0.h, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0x7c,0x60,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04607c00 <unknown> + +addsubp z31.h, z31.h, z31.h +// CHECK-INST: addsubp z31.h, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0x7f,0x7f,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 047f7fff <unknown> + +addsubp z0.s, z0.s, z0.s +// CHECK-INST: addsubp z0.s, z0.s, z0.s +// CHECK-ENCODING: encoding: [0x00,0x7c,0xa0,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04a07c00 <unknown> + +addsubp z31.s, z31.s, z31.s +// CHECK-INST: addsubp z31.s, z31.s, z31.s +// CHECK-ENCODING: encoding: [0xff,0x7f,0xbf,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04bf7fff <unknown> + +addsubp z0.d, z0.d, z0.d +// CHECK-INST: addsubp z0.d, z0.d, z0.d +// CHECK-ENCODING: encoding: [0x00,0x7c,0xe0,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04e07c00 <unknown> + +addsubp z31.d, z31.d, z31.d +// CHECK-INST: addsubp z31.d, z31.d, z31.d +// CHECK-ENCODING: encoding: [0xff,0x7f,0xff,0x04] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 04ff7fff <unknown> + +// --------------------------------------------------------------------------// +// Test sabal + +sabal z0.h, z0.b, z0.b +// CHECK-INST: sabal z0.h, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0xd4,0x40,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4440d400 <unknown> + +sabal z31.h, z31.b, z31.b +// CHECK-INST: sabal z31.h, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0xd7,0x5f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 445fd7ff <unknown> + +sabal z0.s, z0.h, z0.h +// CHECK-INST: sabal z0.s, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0xd4,0x80,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4480d400 <unknown> + +sabal z31.s, z31.h, z31.h +// CHECK-INST: sabal z31.s, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0xd7,0x9f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 449fd7ff <unknown> + +sabal z0.d, z0.s, z0.s +// CHECK-INST: sabal z0.d, z0.s, z0.s +// CHECK-ENCODING: encoding: [0x00,0xd4,0xc0,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44c0d400 <unknown> + +sabal z31.d, z31.s, z31.s +// CHECK-INST: sabal z31.d, z31.s, z31.s +// CHECK-ENCODING: encoding: [0xff,0xd7,0xdf,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44dfd7ff <unknown> + +movprfx z0, z7 +sabal z0.h, z1.b, z2.b +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: sabal z0.h, z1.b, z2.b +// CHECK-ENCODING: encoding: [0x20,0xd4,0x42,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4442d420 <unknown> + +// --------------------------------------------------------------------------// +// Test uabal + +uabal z0.h, z0.b, z0.b +// CHECK-INST: uabal z0.h, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0xdc,0x40,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4440dc00 <unknown> + +uabal z31.h, z31.b, z31.b +// CHECK-INST: uabal z31.h, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0xdf,0x5f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 445fdfff <unknown> + +uabal z0.s, z0.h, z0.h +// CHECK-INST: uabal z0.s, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0xdc,0x80,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4480dc00 <unknown> + +uabal z31.s, z31.h, z31.h +// CHECK-INST: uabal z31.s, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0xdf,0x9f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 449fdfff <unknown> + +uabal z0.d, z0.s, z0.s +// CHECK-INST: uabal z0.d, z0.s, z0.s +// CHECK-ENCODING: encoding: [0x00,0xdc,0xc0,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44c0dc00 <unknown> + +uabal z31.d, z31.s, z31.s +// CHECK-INST: uabal z31.d, z31.s, z31.s +// CHECK-ENCODING: encoding: [0xff,0xdf,0xdf,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44dfdfff <unknown> + +movprfx z0, z7 +uabal z0.h, z1.b, z2.b +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: uabal z0.h, z1.b, z2.b +// CHECK-ENCODING: encoding: [0x20,0xdc,0x42,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4442dc20 <unknown> + +// --------------------------------------------------------------------------// +// Test subp + +subp z0.b, p0/m, z0.b, z0.b +// CHECK-INST: subp z0.b, p0/m, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0xa0,0x10,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4410a000 <unknown> + +subp z31.b, p7/m, z31.b, z31.b +// CHECK-INST: subp z31.b, p7/m, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0xbf,0x10,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4410bfff <unknown> + +subp z0.h, p0/m, z0.h, z0.h +// CHECK-INST: subp z0.h, p0/m, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0xa0,0x50,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4450a000 <unknown> + +subp z31.h, p7/m, z31.h, z31.h +// CHECK-INST: subp z31.h, p7/m, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0xbf,0x50,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4450bfff <unknown> + +subp z0.s, p0/m, z0.s, z0.s +// CHECK-INST: subp z0.s, p0/m, z0.s, z0.s +// CHECK-ENCODING: encoding: [0x00,0xa0,0x90,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4490a000 <unknown> + +subp z31.s, p7/m, z31.s, z31.s +// CHECK-INST: subp z31.s, p7/m, z31.s, z31.s +// CHECK-ENCODING: encoding: [0xff,0xbf,0x90,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4490bfff <unknown> + +subp z0.d, p0/m, z0.d, z0.d +// CHECK-INST: subp z0.d, p0/m, z0.d, z0.d +// CHECK-ENCODING: encoding: [0x00,0xa0,0xd0,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44d0a000 <unknown> + +subp z31.d, p7/m, z31.d, z31.d +// CHECK-INST: subp z31.d, p7/m, z31.d, z31.d +// CHECK-ENCODING: encoding: [0xff,0xbf,0xd0,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44d0bfff <unknown> + +movprfx z0.b, p0/m, z7.b +subp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: movprfx z0.b, p0/m, z7.b +// CHECK-INST: subp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: encoding: [0x20,0xa0,0x10,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4410a020 <unknown> + +movprfx z0, z7 +subp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: subp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: encoding: [0x20,0xa0,0x10,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4410a020 <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/bfmmla-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/bfmmla-diagnostics.s new file mode 100644 index 0000000..28ec78d --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/bfmmla-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-b16mm 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +bfmmla z0.h, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmmla z0.h, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmmla z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmmla z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmmla z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmmla z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/bfmmla.s b/llvm/test/MC/AArch64/SVE2p3/bfmmla.s new file mode 100644 index 0000000..77440ee --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/bfmmla.s @@ -0,0 +1,45 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-b16mm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-b16mm < %s \ +// RUN: | llvm-objdump -d --mattr=+sve-b16mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-b16mm < %s \ +// RUN: | llvm-objdump -d --mattr=-sve-b16mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-b16mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve-b16mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmmla z0.h, z0.h, z0.h +// CHECK-INST: bfmmla z0.h, z0.h, z0.h +// CHECK-ENCODING: encoding: [0x00,0xe0,0xe0,0x64] +// CHECK-ERROR: instruction requires: sve-b16mm +// CHECK-UNKNOWN: 64e0e000 <unknown> + +bfmmla z10.h, z10.h, z10.h +// CHECK-INST: bfmmla z10.h, z10.h, z10.h +// CHECK-ENCODING: encoding: [0x4a,0xe1,0xea,0x64] +// CHECK-ERROR: instruction requires: sve-b16mm +// CHECK-UNKNOWN: 64eae14a <unknown> + +bfmmla z21.h, z21.h, z21.h +// CHECK-INST: bfmmla z21.h, z21.h, z21.h +// CHECK-ENCODING: encoding: [0xb5,0xe2,0xf5,0x64] +// CHECK-ERROR: instruction requires: sve-b16mm +// CHECK-UNKNOWN: 64f5e2b5 <unknown> + +bfmmla z31.h, z31.h, z31.h +// CHECK-INST: bfmmla z31.h, z31.h, z31.h +// CHECK-ENCODING: encoding: [0xff,0xe3,0xff,0x64] +// CHECK-ERROR: instruction requires: sve-b16mm +// CHECK-UNKNOWN: 64ffe3ff <unknown> + +movprfx z0, z7 +bfmmla z0.h, z1.h, z2.h +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: bfmmla z0.h, z1.h, z2.h +// CHECK-ENCODING: encoding: [0x20,0xe0,0xe2,0x64] +// CHECK-ERROR: instruction requires: sve-b16mm +// CHECK-UNKNOWN: 64e2e020 <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s new file mode 100644 index 0000000..68a50ab --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s @@ -0,0 +1,193 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +fcvtzsn z0.b, { z0.b, z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.b, { z0.b, z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.h, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.h, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.s, { z0.s, z1.s } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.s, { z0.s, z1.s } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.b, { z1.h, z2.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: fcvtzsn z0.b, { z1.h, z2.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +fcvtzsn z0.b, { z2.h, z3.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtzsn z0.b, { z2.h, z3.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +fcvtzun z0.b, { z0.b, z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.b, { z0.b, z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.h, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.h, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.s, { z0.s, z1.s } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.s, { z0.s, z1.s } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.b, { z1.h, z2.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: fcvtzun z0.b, { z1.h, z2.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +fcvtzun z0.b, { z2.h, z3.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtzun z0.b, { z2.h, z3.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +scvtf z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +scvtf z0.h, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: scvtf z0.h, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +scvtflt z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +scvtflt z0.h, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: scvtflt z0.h, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +ucvtf z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ucvtf z0.h, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ucvtf z0.h, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +ucvtflt z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ucvtflt z0.h, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ucvtflt z0.h, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/cvt.s b/llvm/test/MC/AArch64/SVE2p3/cvt.s new file mode 100644 index 0000000..da9c463 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/cvt.s @@ -0,0 +1,321 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ------------------------------------------------------------- +// Floating-point convert, narrow and interleave to signed integer, rounding toward zero + +fcvtzsn z0.b, { z0.h, z1.h } +// CHECK-INST: fcvtzsn z0.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x00,0x30,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d3000 <unknown> + +fcvtzsn z31.b, { z0.h, z1.h } +// CHECK-INST: fcvtzsn z31.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x1f,0x30,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d301f <unknown> + +fcvtzsn z0.b, { z30.h, z31.h } +// CHECK-INST: fcvtzsn z0.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xc0,0x33,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d33c0 <unknown> + +fcvtzsn z31.b, { z30.h, z31.h } +// CHECK-INST: fcvtzsn z31.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xdf,0x33,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d33df <unknown> + +fcvtzsn z0.h, { z0.s, z1.s } +// CHECK-INST: fcvtzsn z0.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x00,0x30,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d3000 <unknown> + +fcvtzsn z31.h, { z0.s, z1.s } +// CHECK-INST: fcvtzsn z31.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x1f,0x30,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d301f <unknown> + +fcvtzsn z0.h, { z30.s, z31.s } +// CHECK-INST: fcvtzsn z0.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xc0,0x33,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d33c0 <unknown> + +fcvtzsn z31.h, { z30.s, z31.s } +// CHECK-INST: fcvtzsn z31.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xdf,0x33,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d33df <unknown> + +fcvtzsn z0.s, { z0.d, z1.d } +// CHECK-INST: fcvtzsn z0.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x00,0x30,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd3000 <unknown> + +fcvtzsn z31.s, { z0.d, z1.d } +// CHECK-INST: fcvtzsn z31.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x1f,0x30,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd301f <unknown> + +fcvtzsn z0.s, { z30.d, z31.d } +// CHECK-INST: fcvtzsn z0.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xc0,0x33,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd33c0 <unknown> + +fcvtzsn z31.s, { z30.d, z31.d } +// CHECK-INST: fcvtzsn z31.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xdf,0x33,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd33df <unknown> + +// ------------------------------------------------------------- +// Floating-point convert, narrow and interleave to unsigned integer, rounding toward zero + +fcvtzun z0.b, { z0.h, z1.h } +// CHECK-INST: fcvtzun z0.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x00,0x34,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d3400 <unknown> + +fcvtzun z31.b, { z0.h, z1.h } +// CHECK-INST: fcvtzun z31.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x1f,0x34,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d341f <unknown> + +fcvtzun z0.b, { z30.h, z31.h } +// CHECK-INST: fcvtzun z0.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xc0,0x37,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d37c0 <unknown> + +fcvtzun z31.b, { z30.h, z31.h } +// CHECK-INST: fcvtzun z31.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xdf,0x37,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d37df <unknown> + +fcvtzun z0.h, { z0.s, z1.s } +// CHECK-INST: fcvtzun z0.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x00,0x34,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d3400 <unknown> + +fcvtzun z31.h, { z0.s, z1.s } +// CHECK-INST: fcvtzun z31.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x1f,0x34,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d341f <unknown> + +fcvtzun z0.h, { z30.s, z31.s } +// CHECK-INST: fcvtzun z0.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xc0,0x37,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d37c0 <unknown> + +fcvtzun z31.h, { z30.s, z31.s } +// CHECK-INST: fcvtzun z31.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xdf,0x37,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d37df <unknown> + +fcvtzun z0.s, { z0.d, z1.d } +// CHECK-INST: fcvtzun z0.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x00,0x34,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd3400 <unknown> + +fcvtzun z31.s, { z0.d, z1.d } +// CHECK-INST: fcvtzun z31.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x1f,0x34,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd341f <unknown> + +fcvtzun z0.s, { z30.d, z31.d } +// CHECK-INST: fcvtzun z0.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xc0,0x37,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd37c0 <unknown> + +fcvtzun z31.s, { z30.d, z31.d } +// CHECK-INST: fcvtzun z31.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xdf,0x37,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd37df <unknown> + +// ----------------------------------------------------------------------- +// Signed integer convert to floating-point (bottom, unpredicated) + +scvtf z0.h, z0.b +// CHECK-INST: scvtf z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x30,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3000 <unknown> + +scvtf z31.h, z31.b +// CHECK-INST: scvtf z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x33,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c33ff <unknown> + +scvtf z0.s, z0.h +// CHECK-INST: scvtf z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x30,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3000 <unknown> + +scvtf z31.s, z31.h +// CHECK-INST: scvtf z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x33,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c33ff <unknown> + +scvtf z0.d, z0.s +// CHECK-INST: scvtf z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x30,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3000 <unknown> + +scvtf z31.d, z31.s +// CHECK-INST: scvtf z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x33,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc33ff <unknown> + +// ----------------------------------------------------------------------- +// Signed integer convert to floating-point (top, unpredicated) + +scvtflt z0.h, z0.b +// CHECK-INST: scvtflt z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x38,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3800 <unknown> + +scvtflt z31.h, z31.b +// CHECK-INST: scvtflt z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x3b,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3bff <unknown> + +scvtflt z0.s, z0.h +// CHECK-INST: scvtflt z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x38,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3800 <unknown> + +scvtflt z31.s, z31.h +// CHECK-INST: scvtflt z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x3b,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3bff <unknown> + +scvtflt z0.d, z0.s +// CHECK-INST: scvtflt z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x38,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3800 <unknown> + +scvtflt z31.d, z31.s +// CHECK-INST: scvtflt z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x3b,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3bff <unknown> + +// ----------------------------------------------------------------------- +// Unsigned integer convert to floating-point (bottom, unpredicated) + +ucvtf z0.h, z0.b +// CHECK-INST: ucvtf z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x34,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3400 <unknown> + +ucvtf z31.h, z31.b +// CHECK-INST: ucvtf z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x37,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c37ff <unknown> + +ucvtf z0.s, z0.h +// CHECK-INST: ucvtf z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x34,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3400 <unknown> + +ucvtf z31.s, z31.h +// CHECK-INST: ucvtf z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x37,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c37ff <unknown> + +ucvtf z0.d, z0.s +// CHECK-INST: ucvtf z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x34,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3400 <unknown> + +ucvtf z31.d, z31.s +// CHECK-INST: ucvtf z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x37,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc37ff <unknown> + +// ----------------------------------------------------------------------- +// Unsigned integer convert to floating-point (top, unpredicated) + +ucvtflt z0.h, z0.b +// CHECK-INST: ucvtflt z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x3c,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3c00 <unknown> + +ucvtflt z31.h, z31.b +// CHECK-INST: ucvtflt z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x3f,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3fff <unknown> + +ucvtflt z0.s, z0.h +// CHECK-INST: ucvtflt z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x3c,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3c00 <unknown> + +ucvtflt z31.s, z31.h +// CHECK-INST: ucvtflt z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x3f,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3fff <unknown> + +ucvtflt z0.d, z0.s +// CHECK-INST: ucvtflt z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x3c,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3c00 <unknown> + +ucvtflt z31.d, z31.s +// CHECK-INST: ucvtflt z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x3f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3fff <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2p3/directive-arch-negative.s new file mode 100644 index 0000000..0a12cf8 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/directive-arch-negative.s @@ -0,0 +1,7 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch armv9-a+sve2p3 +.arch armv9-a+nosve2p3 +addqp z0.b, z0.b, z0.b +// CHECK: error: instruction requires: sme2p3 or sve2p3 +// CHECK-NEXT: addqp z0.b, z0.b, z0.b diff --git a/llvm/test/MC/AArch64/SVE2p3/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2p3/directive-arch_extension-negative.s new file mode 100644 index 0000000..1af6245 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/directive-arch_extension-negative.s @@ -0,0 +1,7 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch_extension sve2p3 +.arch_extension nosve2p3 +addqp z0.b, z0.b, z0.b +// CHECK: error: instruction requires: sme2p3 or sve2p3 +// CHECK-NEXT: addqp z0.b, z0.b, z0.b diff --git a/llvm/test/MC/AArch64/SVE2p3/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2p3/directive-cpu-negative.s new file mode 100644 index 0000000..f3dac04 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/directive-cpu-negative.s @@ -0,0 +1,7 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.cpu generic+sve2p3 +.cpu generic+nosve2p3 +addqp z0.b, z0.b, z0.b +// CHECK: error: instruction requires: sme2p3 or sve2p3 +// CHECK-NEXT: addqp z0.b, z0.b, z0.b diff --git a/llvm/test/MC/AArch64/SVE2p3/dot-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/dot-diagnostics.s new file mode 100644 index 0000000..3eb3792 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/dot-diagnostics.s @@ -0,0 +1,137 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +sdot z0.b, z0.b, z0.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.b, z0.b, z0.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.h, z0.h, z0.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.h, z0.h, z0.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.s, z0.s, z0.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.s, z0.s, z0.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.d, z0.d, z0.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.d, z0.d, z0.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.d, z0.s, z0.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.d, z0.s, z0.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.d, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sdot z0.d, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.b, z0.b, z0.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.b, z0.b, z0.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.h, z0.h, z0.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.h, z0.h, z0.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.s, z0.s, z0.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.s, z0.s, z0.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.d, z0.d, z0.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.d, z0.d, z0.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.d, z0.s, z0.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.d, z0.s, z0.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.d, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: udot z0.d, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid register range and index + +sdot z0.h, z0.b, z8.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sdot z0.h, z0.b, z8.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.h, z0.b, z0.b[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sdot z0.h, z0.b, z0.b[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sdot z0.h, z0.b, z0.b[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sdot z0.h, z0.b, z0.b[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.h, z0.b, z8.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: udot z0.h, z0.b, z8.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.h, z0.b, z0.b[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: udot z0.h, z0.b, z0.b[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +udot z0.h, z0.b, z0.b[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: udot z0.h, z0.b, z0.b[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/dot.s b/llvm/test/MC/AArch64/SVE2p3/dot.s new file mode 100644 index 0000000..01021b38 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/dot.s @@ -0,0 +1,173 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sdot z0.h, z0.b, z0.b +// CHECK-INST: sdot z0.h, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0x00,0x40,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44400000 <unknown> + +sdot z10.h, z10.b, z10.b +// CHECK-INST: sdot z10.h, z10.b, z10.b +// CHECK-ENCODING: encoding: [0x4a,0x01,0x4a,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 444a014a <unknown> + +sdot z21.h, z21.b, z21.b +// CHECK-INST: sdot z21.h, z21.b, z21.b +// CHECK-ENCODING: encoding: [0xb5,0x02,0x55,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 445502b5 <unknown> + +sdot z31.h, z31.b, z31.b +// CHECK-INST: sdot z31.h, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0x03,0x5f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 445f03ff <unknown> + +movprfx z0, z7 +sdot z0.h, z1.b, z2.b +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: sdot z0.h, z1.b, z2.b +// CHECK-ENCODING: encoding: [0x20,0x00,0x42,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44420020 <unknown> + +// sdot indexed + +sdot z0.h, z0.b, z0.b[0] +// CHECK-INST: sdot z0.h, z0.b, z0.b[0] +// CHECK-ENCODING: encoding: [0x00,0x00,0x20,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44200000 <unknown> + +sdot z31.h, z31.b, z7.b[0] +// CHECK-INST: sdot z31.h, z31.b, z7.b[0] +// CHECK-ENCODING: encoding: [0xff,0x03,0x27,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 442703ff <unknown> + +sdot z0.h, z0.b, z0.b[1] +// CHECK-INST: sdot z0.h, z0.b, z0.b[1] +// CHECK-ENCODING: encoding: [0x00,0x00,0x28,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44280000 <unknown> + +sdot z31.h, z31.b, z7.b[1] +// CHECK-INST: sdot z31.h, z31.b, z7.b[1] +// CHECK-ENCODING: encoding: [0xff,0x03,0x2f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 442f03ff <unknown> + +sdot z0.h, z0.b, z0.b[7] +// CHECK-INST: sdot z0.h, z0.b, z0.b[7] +// CHECK-ENCODING: encoding: [0x00,0x00,0x78,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44780000 <unknown> + +sdot z31.h, z31.b, z7.b[7] +// CHECK-INST: sdot z31.h, z31.b, z7.b[7] +// CHECK-ENCODING: encoding: [0xff,0x03,0x7f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 447f03ff <unknown> + +movprfx z0, z7 +sdot z0.h, z1.b, z2.b[0] +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: sdot z0.h, z1.b, z2.b[0] +// CHECK-ENCODING: encoding: [0x20,0x00,0x22,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44220020 <unknown> + +// udot + +udot z0.h, z0.b, z0.b +// CHECK-INST: udot z0.h, z0.b, z0.b +// CHECK-ENCODING: encoding: [0x00,0x04,0x40,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44400400 <unknown> + +udot z10.h, z10.b, z10.b +// CHECK-INST: udot z10.h, z10.b, z10.b +// CHECK-ENCODING: encoding: [0x4a,0x05,0x4a,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 444a054a <unknown> + +udot z21.h, z21.b, z21.b +// CHECK-INST: udot z21.h, z21.b, z21.b +// CHECK-ENCODING: encoding: [0xb5,0x06,0x55,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 445506b5 <unknown> + +udot z31.h, z31.b, z31.b +// CHECK-INST: udot z31.h, z31.b, z31.b +// CHECK-ENCODING: encoding: [0xff,0x07,0x5f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 445f07ff <unknown> + +movprfx z0, z7 +udot z0.h, z1.b, z2.b +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: udot z0.h, z1.b, z2.b +// CHECK-ENCODING: encoding: [0x20,0x04,0x42,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44420420 <unknown> + +// udot indexed + +udot z0.h, z0.b, z0.b[0] +// CHECK-INST: udot z0.h, z0.b, z0.b[0] +// CHECK-ENCODING: encoding: [0x00,0x04,0x20,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44200400 <unknown> + +udot z31.h, z31.b, z7.b[0] +// CHECK-INST: udot z31.h, z31.b, z7.b[0] +// CHECK-ENCODING: encoding: [0xff,0x07,0x27,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 442707ff <unknown> + +udot z0.h, z0.b, z0.b[1] +// CHECK-INST: udot z0.h, z0.b, z0.b[1] +// CHECK-ENCODING: encoding: [0x00,0x04,0x28,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44280400 <unknown> + +udot z31.h, z31.b, z7.b[1] +// CHECK-INST: udot z31.h, z31.b, z7.b[1] +// CHECK-ENCODING: encoding: [0xff,0x07,0x2f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 442f07ff <unknown> + +udot z0.h, z0.b, z0.b[7] +// CHECK-INST: udot z0.h, z0.b, z0.b[7] +// CHECK-ENCODING: encoding: [0x00,0x04,0x78,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44780400 <unknown> + +udot z31.h, z31.b, z7.b[7] +// CHECK-INST: udot z31.h, z31.b, z7.b[7] +// CHECK-ENCODING: encoding: [0xff,0x07,0x7f,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 447f07ff <unknown> + +movprfx z0, z7 +udot z0.h, z1.b, z2.b[0] +// CHECK-INST: movprfx z0, z7 +// CHECK-INST: udot z0.h, z1.b, z2.b[0] +// CHECK-ENCODING: encoding: [0x20,0x04,0x22,0x44] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 44220420 <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/luti6-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/luti6-diagnostics.s new file mode 100644 index 0000000..21b4df9 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/luti6-diagnostics.s @@ -0,0 +1,70 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +luti6 z10.h, { z0.b, z1.b }, z0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: luti6 z10.h, { z0.b, z1.b }, z0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 z10.s, { z0.b, z1.b }, z0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: luti6 z10.s, { z0.b, z1.b }, z0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 z0.b, { z2.b, z3.b }, z4 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 z0.b, { z2.b, z3.b }, z4 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 z0.b, { z2.b, z3.b }, z4 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 z0.b, { z2.b, z3.b }, z4 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +luti6 z10.s, { z0.h, z1.h }, z0[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: luti6 z10.s, { z0.h, z1.h }, z0[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 z10.b, { z0.h, z1.h }, z0[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: luti6 z10.b, { z0.h, z1.h }, z0[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +luti6 z10.h, { z0.h, z1.h }, z0[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: luti6 z10.h, { z0.h, z1.h }, z0[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +luti6 z10.h, { z0.h, z1.h }, z0[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: luti6 z10.h, { z0.h, z1.h }, z0[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/m, z7.h +luti6 z0.h, { z2.h, z3.h }, z4[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 z0.h, { z2.h, z3.h }, z4[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +luti6 z0.h, { z2.h, z3.h }, z4[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: luti6 z0.h, { z2.h, z3.h }, z4[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/luti6.s b/llvm/test/MC/AArch64/SVE2p3/luti6.s new file mode 100644 index 0000000..848091c --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/luti6.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// --------------------------------------------------------------- +// Lookup table read with 6-bit indices (8-bit) + +luti6 z0.b, { z0.b, z1.b }, z0 +// CHECK-INST: luti6 z0.b, { z0.b, z1.b }, z0 +// CHECK-ENCODING: encoding: [0x00,0xac,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 4520ac00 <unknown> + +luti6 z10.b, { z0.b, z1.b }, z0 +// CHECK-INST: luti6 z10.b, { z0.b, z1.b }, z0 +// CHECK-ENCODING: encoding: [0x0a,0xac,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 4520ac0a <unknown> + +luti6 z21.b, { z0.b, z1.b }, z0 +// CHECK-INST: luti6 z21.b, { z0.b, z1.b }, z0 +// CHECK-ENCODING: encoding: [0x15,0xac,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 4520ac15 <unknown> + +luti6 z31.b, { z0.b, z1.b }, z0 +// CHECK-INST: luti6 z31.b, { z0.b, z1.b }, z0 +// CHECK-ENCODING: encoding: [0x1f,0xac,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 4520ac1f <unknown> + +luti6 z0.b, { z31.b, z0.b }, z31 +// CHECK-INST: luti6 z0.b, { z31.b, z0.b }, z31 +// CHECK-ENCODING: encoding: [0xe0,0xaf,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 453fafe0 <unknown> + +luti6 z10.b, { z31.b, z0.b }, z31 +// CHECK-INST: luti6 z10.b, { z31.b, z0.b }, z31 +// CHECK-ENCODING: encoding: [0xea,0xaf,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 453fafea <unknown> + +luti6 z21.b, { z31.b, z0.b }, z31 +// CHECK-INST: luti6 z21.b, { z31.b, z0.b }, z31 +// CHECK-ENCODING: encoding: [0xf5,0xaf,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 453faff5 <unknown> + +luti6 z31.b, { z31.b, z0.b }, z31 +// CHECK-INST: luti6 z31.b, { z31.b, z0.b }, z31 +// CHECK-ENCODING: encoding: [0xff,0xaf,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2p3 +// CHECK-UNKNOWN: 453fafff <unknown> + +// --------------------------------------------------------------- +// Lookup table read with 6-bit indices (16-bit) + +luti6 z0.h, { z0.h, z1.h }, z0[0] +// CHECK-INST: luti6 z0.h, { z0.h, z1.h }, z0[0] +// CHECK-ENCODING: encoding: [0x00,0xac,0x60,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4560ac00 <unknown> + +luti6 z10.h, { z0.h, z1.h }, z0[0] +// CHECK-INST: luti6 z10.h, { z0.h, z1.h }, z0[0] +// CHECK-ENCODING: encoding: [0x0a,0xac,0x60,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4560ac0a <unknown> + +luti6 z21.h, { z0.h, z1.h }, z0[0] +// CHECK-INST: luti6 z21.h, { z0.h, z1.h }, z0[0] +// CHECK-ENCODING: encoding: [0x15,0xac,0x60,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4560ac15 <unknown> + +luti6 z31.h, { z0.h, z1.h }, z0[0] +// CHECK-INST: luti6 z31.h, { z0.h, z1.h }, z0[0] +// CHECK-ENCODING: encoding: [0x1f,0xac,0x60,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 4560ac1f <unknown> + +luti6 z0.h, { z31.h, z0.h }, z31[1] +// CHECK-INST: luti6 z0.h, { z31.h, z0.h }, z31[1] +// CHECK-ENCODING: encoding: [0xe0,0xaf,0xff,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45ffafe0 <unknown> + +luti6 z10.h, { z31.h, z0.h }, z31[1] +// CHECK-INST: luti6 z10.h, { z31.h, z0.h }, z31[1] +// CHECK-ENCODING: encoding: [0xea,0xaf,0xff,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45ffafea <unknown> + +luti6 z21.h, { z31.h, z0.h }, z31[1] +// CHECK-INST: luti6 z21.h, { z31.h, z0.h }, z31[1] +// CHECK-ENCODING: encoding: [0xf5,0xaf,0xff,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45ffaff5 <unknown> + +luti6 z31.h, { z31.h, z0.h }, z31[1] +// CHECK-INST: luti6 z31.h, { z31.h, z0.h }, z31[1] +// CHECK-ENCODING: encoding: [0xff,0xaf,0xff,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45ffafff <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s new file mode 100644 index 0000000..a4dbae2 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s @@ -0,0 +1,343 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Mismatched register size suffix + +sqrshrn z0.b, { z0.h, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: sqrshrn z0.b, { z0.h, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +sqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqrshrn z0.b, { z2.h, z3.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrn z0.b, { z2.h, z3.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrun z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrun z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrun z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrun z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +sqrshrun z10.h, { z0.b, z1.b }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshrun z10.h, { z0.b, z1.b }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqrshrun z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrun z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrun z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqrshrun z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Mismatched register size suffix + +sqrshrun z0.b, { z0.h, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: sqrshrun z0.b, { z0.h, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqrshrun z0.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Mismatched register size suffix + +sqshrn z0.b, { z0.h, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: sqshrn z0.b, { z0.h, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrun z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrun z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrun z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Mismatched register size suffix + +sqshrun z0.b, { z0.h, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: sqshrun z0.b, { z0.h, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqshrun z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrun z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrun z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.h, { z0.s, z1.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrun z10.h, { z0.s, z1.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.h, { z0.s, z1.s }, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrun z10.h, { z0.s, z1.s }, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqshrun z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqshrun z0.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +uqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Mismatched register size suffix + +uqrshrn z0.b, { z0.h, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: uqrshrn z0.b, { z0.h, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +uqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +uqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: uqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +uqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +uqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Mismatched register size suffix + +uqshrn z0.b, { z0.h, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: uqshrn z0.b, { z0.h, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +uqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: uqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: uqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: uqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +uqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/qshrn.s b/llvm/test/MC/AArch64/SVE2p3/qshrn.s new file mode 100644 index 0000000..31c87cf --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/qshrn.s @@ -0,0 +1,255 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ----------------------------------------------------------------- +// Signed saturating rounding shift right narrow by immediate and interleave + +sqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x28,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af2800 <unknown> + +sqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x2b,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af2bdf <unknown> + +sqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x28,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a82800 <unknown> + +sqrshrn z31.b, { z30.h, z31.h }, #3 +// CHECK-INST: sqrshrn z31.b, { z30.h, z31.h }, #3 +// CHECK-ENCODING: encoding: [0xdf,0x2b,0xad,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45ad2bdf <unknown> + +// ----------------------------------------------------------------- +// Signed saturating rounding shift right unsigned narrow by immediate and interleave + +sqrshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqrshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x08,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af0800 <unknown> + +sqrshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqrshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x0b,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af0bdf <unknown> + +sqrshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqrshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x08,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a80800 <unknown> + +sqrshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: sqrshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x0b,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a80bdf <unknown> + +// ----------------------------------------------------------------- +// Signed saturating shift right narrow by immediate and interleave + +sqshrn z21.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqshrn z21.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xd5,0x03,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af03d5 <unknown> + +sqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af03df <unknown> + +sqshrn z10.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqshrn z10.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x0a,0x00,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a8000a <unknown> + +sqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: sqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a803df <unknown> + +sqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x00,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af0000 <unknown> + +sqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-INST: sqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-ENCODING: encoding: [0x00,0x00,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf0000 <unknown> + +sqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-INST: sqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf03df <unknown> + +sqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-INST: sqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: encoding: [0x00,0x00,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b00000 <unknown> + +sqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-INST: sqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b003df <unknown> + +// ----------------------------------------------------------------- +// Signed saturating shift right unsigned narrow by immediate and interleave + +sqshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x20,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af2000 <unknown> + +sqshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af23df <unknown> + +sqshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x20,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a82000 <unknown> + +sqshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: sqshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a823df <unknown> + +sqshrun z0.h, { z0.s, z1.s }, #1 +// CHECK-INST: sqshrun z0.h, { z0.s, z1.s }, #1 +// CHECK-ENCODING: encoding: [0x00,0x20,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf2000 <unknown> + +sqshrun z31.h, { z30.s, z31.s }, #1 +// CHECK-INST: sqshrun z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf23df <unknown> + +sqshrun z0.h, { z0.s, z1.s }, #16 +// CHECK-INST: sqshrun z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: encoding: [0x00,0x20,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b02000 <unknown> + +sqshrun z31.h, { z30.s, z31.s }, #16 +// CHECK-INST: sqshrun z31.h, { z30.s, z31.s }, #16 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b023df <unknown> + +// ----------------------------------------------------------------- +// Unsigned saturating rounding shift right narrow by immediate and interleave + +uqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: uqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x38,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af3800 <unknown> + +uqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: uqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x3b,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af3bdf <unknown> + +uqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: uqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x38,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a83800 <unknown> + +uqrshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: uqrshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x3b,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a83bdf <unknown> + +// ----------------------------------------------------------------- +// Unsigned saturating shift right narrow by immediate and interleave + +uqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: uqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x10,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af1000 <unknown> + +uqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: uqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af13df <unknown> + +uqshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: uqshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x10,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a81000 <unknown> + +uqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: uqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a813df <unknown> + +uqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-INST: uqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-ENCODING: encoding: [0x00,0x10,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf1000 <unknown> + +uqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-INST: uqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf13df <unknown> + +uqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-INST: uqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: encoding: [0x00,0x10,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b01000 <unknown> + +uqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-INST: uqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b013df <unknown> diff --git a/llvm/test/MC/AArch64/armv8.4a-mpam.s b/llvm/test/MC/AArch64/armv8.4a-mpam.s index 14787e6..7469227 100644 --- a/llvm/test/MC/AArch64/armv8.4a-mpam.s +++ b/llvm/test/MC/AArch64/armv8.4a-mpam.s @@ -1,6 +1,4 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK -// RUN: FileCheck --check-prefix=CHECK-RO < %t %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR //------------------------------------------------------------------------------ // ARMV8.4-A MPAM Extensions @@ -56,9 +54,6 @@ mrs x0, MPAMIDR_EL1 //CHECK: msr MPAMVPM6_EL2, x0 // encoding: [0xc0,0xa6,0x1c,0xd5] //CHECK: msr MPAMVPM7_EL2, x0 // encoding: [0xe0,0xa6,0x1c,0xd5] -//CHECK-RO: error: expected writable system register or pstate -//CHECK-RO: msr MPAMIDR_EL1, x0 -//CHECK-RO: ^ //CHECK: mrs x0, MPAM0_EL1 // encoding: [0x20,0xa5,0x38,0xd5] //CHECK: mrs x0, MPAM1_EL1 // encoding: [0x00,0xa5,0x38,0xd5] @@ -77,100 +72,4 @@ mrs x0, MPAMIDR_EL1 //CHECK: mrs x0, MPAMVPM7_EL2 // encoding: [0xe0,0xa6,0x3c,0xd5] //CHECK: mrs x0, MPAMIDR_EL1 // encoding: [0x80,0xa4,0x38,0xd5] -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAM0_EL1, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAM1_EL1, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAM2_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAM3_EL3, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAM1_EL12, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMHCR_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPMV_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM0_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM1_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM2_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM3_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM4_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM5_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM6_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMVPM7_EL2, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected writable system register or pstate -//CHECK-ERROR: msr MPAMIDR_EL1, x0 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAM0_EL1 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAM1_EL1 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAM2_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAM3_EL3 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAM1_EL12 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMHCR_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPMV_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM0_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM1_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM2_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM3_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM4_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM5_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM6_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMVPM7_EL2 -//CHECK-ERROR: ^ -//CHECK-ERROR: error: expected readable system register -//CHECK-ERROR: mrs x0, MPAMIDR_EL1 -//CHECK-ERROR: ^ diff --git a/llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s new file mode 100644 index 0000000..cffee7d --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-gcie-diagnostics.s @@ -0,0 +1,18 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+gcie -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +//------------------------------------------------------------------------------ +// FEAT_GCIE instructions +//------------------------------------------------------------------------------ + +gsb +// CHECK-ERROR: error: invalid operand for GSB instruction + +gicr +// CHECK-ERROR: error: expected register operand + +gicr x3, foo +// CHECK-ERROR: error: invalid operand for GICR instruction + +gic cdaff +// CHECK-ERROR: error: specified gic op requires a register diff --git a/llvm/test/MC/AArch64/armv9.7a-gcie.s b/llvm/test/MC/AArch64/armv9.7a-gcie.s new file mode 100644 index 0000000..4fd5d25 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-gcie.s @@ -0,0 +1,985 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcie < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcie < %s \ +// RUN: | llvm-objdump -d --mattr=+gcie --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcie < %s \ +// RUN: | llvm-objdump -d --mattr=-gcie --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcie < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+gcie -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +//------------------------------------------------------------------------------ +// Armv9.7-A FEAT_GCIE Extensions +//------------------------------------------------------------------------------ + +// CPU Interface Registers MRS Instruction - Encodings Checked +MRS x3, ICC_APR_EL1 +// CHECK-INST: mrs x3, ICC_APR_EL1 +// CHECK-ENCODING: [0x03,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c003 + +MRS x3, ICC_APR_EL3 +// CHECK-INST: mrs x3, ICC_APR_EL3 +// CHECK-ENCODING: [0x03,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec803 + +MRS x3, ICC_CR0_EL1 +// CHECK-INST: mrs x3, ICC_CR0_EL1 +// CHECK-ENCODING: [0x23,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c023 + +MRS x3, ICC_CR0_EL3 +// CHECK-INST: mrs x3, ICC_CR0_EL3 +// CHECK-ENCODING: [0x03,0xc9,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec903 + +MRS x3, ICC_DOMHPPIR_EL3 +// CHECK-INST: mrs x3, ICC_DOMHPPIR_EL3 +// CHECK-ENCODING: [0x43,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec843 + +MRS x3, ICC_HAPR_EL1 +// CHECK-INST: mrs x3, ICC_HAPR_EL1 +// CHECK-ENCODING: [0x63,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c063 + +MRS x3, ICC_HPPIR_EL1 +// CHECK-INST: mrs x3, ICC_HPPIR_EL1 +// CHECK-ENCODING: [0x63,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca63 + +MRS x3, ICC_HPPIR_EL3 +// CHECK-INST: mrs x3, ICC_HPPIR_EL3 +// CHECK-ENCODING: [0x23,0xc9,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec923 + +MRS x3, ICC_IAFFIDR_EL1 +// CHECK-INST: mrs x3, ICC_IAFFIDR_EL1 +// CHECK-ENCODING: [0xa3,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538caa3 + +MRS x3, ICC_ICSR_EL1 +// CHECK-INST: mrs x3, ICC_ICSR_EL1 +// CHECK-ENCODING: [0x83,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca83 + +MRS x3, ICC_IDR0_EL1 +// CHECK-INST: mrs x3, ICC_IDR0_EL1 +// CHECK-ENCODING: [0x43,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca43 + +MRS x3, ICC_PCR_EL1 +// CHECK-INST: mrs x3, ICC_PCR_EL1 +// CHECK-ENCODING: [0x43,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c043 + +MRS x3, ICC_PCR_EL3 +// CHECK-INST: mrs x3, ICC_PCR_EL3 +// CHECK-ENCODING: [0x23,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec823 + +MRS x3, ICC_SRE_EL1 +// CHECK-INST: mrs x3, ICC_SRE_EL1 +// CHECK-ENCODING: [0xa3,0xcc,0x38,0xd5] +// CHECK-UNKNOWN: d538cca3 + +// ----------------------------------------------- +MSR ICC_APR_EL1, x3 +// CHECK-INST: msr ICC_APR_EL1, x3 +// CHECK-ENCODING: [0x03,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c003 + +MSR ICC_APR_EL3, x3 +// CHECK-INST: msr ICC_APR_EL3, x3 +// CHECK-ENCODING: [0x03,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec803 + +MSR ICC_CR0_EL1, x3 +// CHECK-INST: msr ICC_CR0_EL1, x3 +// CHECK-ENCODING: [0x23,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c023 + +MSR ICC_CR0_EL3, x3 +// CHECK-INST: msr ICC_CR0_EL3, x3 +// CHECK-ENCODING: [0x03,0xc9,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec903 + +MSR ICC_ICSR_EL1, x3 +// CHECK-INST: msr ICC_ICSR_EL1, x3 +// CHECK-ENCODING: [0x83,0xca,0x18,0xd5] +// CHECK-UNKNOWN: d518ca83 + +MSR ICC_PCR_EL1, x3 +// CHECK-INST: msr ICC_PCR_EL1, x3 +// CHECK-ENCODING: [0x43,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c043 + +MSR ICC_PCR_EL3, x3 +// CHECK-INST: msr ICC_PCR_EL3, x3 +// CHECK-ENCODING: [0x23,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec823 + + +// ----------------------------------------------- +// Virtual CPU Registers MRS Instructions + +// The specification says: +// "Each ICC_system register that is accessible at EL1 and higher and whose state +// is specific to the Virtual Interrupt Domain, has a corresponding virtual +// ICV_register. The ICV_registers are accessed using the same system register +// encodings as their ICC_counterparts." +// +// So expect ICC_* encodings here, not ICV_* encodings + +MRS x3, ICV_APR_EL1 +// CHECK-INST: mrs x3, ICC_APR_EL1 +// CHECK-ENCODING: [0x03,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c003 + +MRS x3, ICV_CR0_EL1 +// CHECK-INST: mrs x3, ICC_CR0_EL1 +// CHECK-ENCODING: [0x23,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c023 + +MRS x3, ICV_HAPR_EL1 +// CHECK-INST: mrs x3, ICC_HAPR_EL1 +// CHECK-ENCODING: [0x63,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c063 + +MRS x3, ICV_HPPIR_EL1 +// CHECK-INST: mrs x3, ICC_HPPIR_EL1 +// CHECK-ENCODING: [0x63,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca63 + +MRS x3, ICV_PCR_EL1 +// CHECK-INST: mrs x3, ICC_PCR_EL1 +// CHECK-ENCODING: [0x43,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c043 + + +// ----------------------------------------------- +// Likewise here, expect ICC_* encodings here, not ICV_* encodings +MSR ICV_APR_EL1, x3 +// CHECK-INST: msr ICC_APR_EL1, x3 +// CHECK-ENCODING: [0x03,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c003 + +MSR ICV_CR0_EL1, x3 +// CHECK-INST: msr ICC_CR0_EL1, x3 +// CHECK-ENCODING: [0x23,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c023 + +MSR ICV_PCR_EL1, x3 +// CHECK-INST: msr ICC_PCR_EL1, x3 +// CHECK-ENCODING: [0x43,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c043 + +// ----------------------------------------------- +// PPI Registers MRS Instructions - Encodings Checked +MRS x3, ICC_PPI_CACTIVER0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CACTIVER0_EL1 +// CHECK-ENCODING: [0x03,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd03 + +MRS x3, ICC_PPI_CACTIVER1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CACTIVER1_EL1 +// CHECK-ENCODING: [0x23,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd23 + +MRS x3, ICC_PPI_CPENDR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CPENDR0_EL1 +// CHECK-ENCODING: [0x83,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd83 + +MRS x3, ICC_PPI_CPENDR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CPENDR1_EL1 +// CHECK-ENCODING: [0xa3,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cda3 + +MRS x3, ICC_PPI_DOMAINR0_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR0_EL3 +// CHECK-ENCODING: [0x83,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec883 + +MRS x3, ICC_PPI_DOMAINR1_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR1_EL3 +// CHECK-ENCODING: [0xa3,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec8a3 + +MRS x3, ICC_PPI_DOMAINR2_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR2_EL3 +// CHECK-ENCODING: [0xc3,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec8c3 + +MRS x3, ICC_PPI_DOMAINR3_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR3_EL3 +// CHECK-ENCODING: [0xe3,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec8e3 + +MRS x3, ICC_PPI_ENABLER0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_ENABLER0_EL1 +// CHECK-ENCODING: [0xc3,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538cac3 + +MRS x3, ICC_PPI_ENABLER1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_ENABLER1_EL1 +// CHECK-ENCODING: [0xe3,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538cae3 + +MRS x3, ICC_PPI_PRIORITYR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR0_EL1 +// CHECK-ENCODING: [0x03,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce03 + +MRS x3, ICC_PPI_PRIORITYR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR1_EL1 +// CHECK-ENCODING: [0x23,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce23 + +MRS x3, ICC_PPI_PRIORITYR2_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR2_EL1 +// CHECK-ENCODING: [0x43,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce43 + +MRS x3, ICC_PPI_PRIORITYR3_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR3_EL1 +// CHECK-ENCODING: [0x63,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce63 + +MRS x3, ICC_PPI_PRIORITYR4_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR4_EL1 +// CHECK-ENCODING: [0x83,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce83 + +MRS x3, ICC_PPI_PRIORITYR5_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR5_EL1 +// CHECK-ENCODING: [0xa3,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538cea3 + +MRS x3, ICC_PPI_PRIORITYR6_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR6_EL1 +// CHECK-ENCODING: [0xc3,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538cec3 + +MRS x3, ICC_PPI_PRIORITYR7_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR7_EL1 +// CHECK-ENCODING: [0xe3,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538cee3 + +MRS x3, ICC_PPI_PRIORITYR8_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR8_EL1 +// CHECK-ENCODING: [0x03,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf03 + +MRS x3, ICC_PPI_PRIORITYR9_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR9_EL1 +// CHECK-ENCODING: [0x23,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf23 + +MRS x3, ICC_PPI_PRIORITYR10_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR10_EL1 +// CHECK-ENCODING: [0x43,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf43 + +MRS x3, ICC_PPI_PRIORITYR11_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR11_EL1 +// CHECK-ENCODING: [0x63,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf63 + +MRS x3, ICC_PPI_PRIORITYR12_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR12_EL1 +// CHECK-ENCODING: [0x83,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf83 + +MRS x3, ICC_PPI_PRIORITYR13_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR13_EL1 +// CHECK-ENCODING: [0xa3,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cfa3 + +MRS x3, ICC_PPI_PRIORITYR14_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR14_EL1 +// CHECK-ENCODING: [0xc3,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cfc3 + +MRS x3, ICC_PPI_PRIORITYR15_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR15_EL1 +// CHECK-ENCODING: [0xe3,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cfe3 + +MRS x3, ICC_PPI_SACTIVER0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SACTIVER0_EL1 +// CHECK-ENCODING: [0x43,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd43 + +MRS x3, ICC_PPI_SACTIVER1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SACTIVER1_EL1 +// CHECK-ENCODING: [0x63,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd63 + +MRS x3, ICC_PPI_SPENDR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SPENDR0_EL1 +// CHECK-ENCODING: [0xc3,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cdc3 + +MRS x3, ICC_PPI_SPENDR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SPENDR1_EL1 +// CHECK-ENCODING: [0xe3,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cde3 + +MRS x3, ICC_PPI_HMR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_HMR0_EL1 +// CHECK-ENCODING: [0x03,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca03 + +MRS x3, ICC_PPI_HMR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_HMR1_EL1 +// CHECK-ENCODING: [0x23,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca23 + +// ----------------------------------------------- +// MSR PPI Registers Instructions +MSR ICC_PPI_CACTIVER0_EL1, x3 +// CHECK-INST: msr ICC_PPI_CACTIVER0_EL1, x3 +// CHECK-ENCODING: [0x03,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd03 + +MSR ICC_PPI_CACTIVER1_EL1, x3 +// CHECK-INST: msr ICC_PPI_CACTIVER1_EL1, x3 +// CHECK-ENCODING: [0x23,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd23 + +MSR ICC_PPI_CPENDR0_EL1, x3 +// CHECK-INST: msr ICC_PPI_CPENDR0_EL1, x3 +// CHECK-ENCODING: [0x83,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd83 + +MSR ICC_PPI_CPENDR1_EL1, x3 +// CHECK-INST: msr ICC_PPI_CPENDR1_EL1, x3 +// CHECK-ENCODING: [0xa3,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cda3 + +MSR ICC_PPI_DOMAINR0_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR0_EL3, x3 +// CHECK-ENCODING: [0x83,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec883 + +MSR ICC_PPI_DOMAINR1_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR1_EL3, x3 +// CHECK-ENCODING: [0xa3,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec8a3 + +MSR ICC_PPI_DOMAINR2_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR2_EL3, x3 +// CHECK-ENCODING: [0xc3,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec8c3 + +MSR ICC_PPI_DOMAINR3_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR3_EL3, x3 +// CHECK-ENCODING: [0xe3,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec8e3 + +MSR ICC_PPI_ENABLER0_EL1, x3 +// CHECK-INST: msr ICC_PPI_ENABLER0_EL1, x3 +// CHECK-ENCODING: [0xc3,0xca,0x18,0xd5] +// CHECK-UNKNOWN: d518cac3 + +MSR ICC_PPI_ENABLER1_EL1, x3 +// CHECK-INST: msr ICC_PPI_ENABLER1_EL1, x3 +// CHECK-ENCODING: [0xe3,0xca,0x18,0xd5] +// CHECK-UNKNOWN: d518cae3 + +MSR ICC_PPI_PRIORITYR0_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR0_EL1, x3 +// CHECK-ENCODING: [0x03,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce03 + +MSR ICC_PPI_PRIORITYR1_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR1_EL1, x3 +// CHECK-ENCODING: [0x23,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce23 + +MSR ICC_PPI_PRIORITYR2_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR2_EL1, x3 +// CHECK-ENCODING: [0x43,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce43 + +MSR ICC_PPI_PRIORITYR3_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR3_EL1, x3 +// CHECK-ENCODING: [0x63,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce63 + +MSR ICC_PPI_PRIORITYR4_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR4_EL1, x3 +// CHECK-ENCODING: [0x83,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce83 + +MSR ICC_PPI_PRIORITYR5_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR5_EL1, x3 +// CHECK-ENCODING: [0xa3,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518cea3 + +MSR ICC_PPI_PRIORITYR6_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR6_EL1, x3 +// CHECK-ENCODING: [0xc3,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518cec3 + +MSR ICC_PPI_PRIORITYR7_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR7_EL1, x3 +// CHECK-ENCODING: [0xe3,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518cee3 + +MSR ICC_PPI_PRIORITYR8_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR8_EL1, x3 +// CHECK-ENCODING: [0x03,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf03 + +MSR ICC_PPI_PRIORITYR9_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR9_EL1, x3 +// CHECK-ENCODING: [0x23,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf23 + +MSR ICC_PPI_PRIORITYR10_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR10_EL1, x3 +// CHECK-ENCODING: [0x43,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf43 + +MSR ICC_PPI_PRIORITYR11_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR11_EL1, x3 +// CHECK-ENCODING: [0x63,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf63 + +MSR ICC_PPI_PRIORITYR12_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR12_EL1, x3 +// CHECK-ENCODING: [0x83,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf83 + +MSR ICC_PPI_PRIORITYR13_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR13_EL1, x3 +// CHECK-ENCODING: [0xa3,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cfa3 + +MSR ICC_PPI_PRIORITYR14_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR14_EL1, x3 +// CHECK-ENCODING: [0xc3,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cfc3 + +MSR ICC_PPI_PRIORITYR15_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR15_EL1, x3 +// CHECK-ENCODING: [0xe3,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cfe3 + +MSR ICC_PPI_SACTIVER0_EL1, x3 +// CHECK-INST: msr ICC_PPI_SACTIVER0_EL1, x3 +// CHECK-ENCODING: [0x43,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd43 + +MSR ICC_PPI_SACTIVER1_EL1, x3 +// CHECK-INST: msr ICC_PPI_SACTIVER1_EL1, x3 +// CHECK-ENCODING: [0x63,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd63 + +MSR ICC_PPI_SPENDR0_EL1, x3 +// CHECK-INST: msr ICC_PPI_SPENDR0_EL1, x3 +// CHECK-ENCODING: [0xc3,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cdc3 + +MSR ICC_PPI_SPENDR1_EL1, x3 +// CHECK-INST: msr ICC_PPI_SPENDR1_EL1, x3 +// CHECK-ENCODING: [0xe3,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cde3 + +// ----------------------------------------------- +// Hypervisor Control Register MRS Instructions +MRS x3, ICH_APR_EL2 +// CHECK-INST: mrs x3, ICH_APR_EL2 +// CHECK-ENCODING: [0x83,0xc8,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc883 + +MRS x3, ICH_CONTEXTR_EL2 +// CHECK-INST: mrs x3, ICH_CONTEXTR_EL2 +// CHECK-ENCODING: [0xc3,0xcb,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccbc3 + +MRS x3, ICH_HFGITR_EL2 +// CHECK-INST: mrs x3, ICH_HFGITR_EL2 +// CHECK-ENCODING: [0xe3,0xc9,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc9e3 + +MRS x3, ICH_HFGRTR_EL2 +// CHECK-INST: mrs x3, ICH_HFGRTR_EL2 +// CHECK-ENCODING: [0x83,0xc9,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc983 + +MRS x3, ICH_HFGWTR_EL2 +// CHECK-INST: mrs x3, ICH_HFGWTR_EL2 +// CHECK-ENCODING: [0xc3,0xc9,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc9c3 + +MRS x3, ICH_HPPIR_EL2 +// CHECK-INST: mrs x3, ICH_HPPIR_EL2 +// CHECK-ENCODING: [0xa3,0xc8,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc8a3 + +MRS x3, ICH_PPI_ACTIVER0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ACTIVER0_EL2 +// CHECK-ENCODING: [0xc3,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccac3 + +MRS x3, ICH_PPI_ACTIVER1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ACTIVER1_EL2 +// CHECK-ENCODING: [0xe3,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccae3 + +MRS x3, ICH_PPI_DVIR0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_DVIR0_EL2 +// CHECK-ENCODING: [0x03,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca03 + +MRS x3, ICH_PPI_DVIR1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_DVIR1_EL2 +// CHECK-ENCODING: [0x23,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca23 + +MRS x3, ICH_PPI_ENABLER0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ENABLER0_EL2 +// CHECK-ENCODING: [0x43,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca43 + +MRS x3, ICH_PPI_ENABLER1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ENABLER1_EL2 +// CHECK-ENCODING: [0x63,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca63 + +MRS x3, ICH_PPI_PENDR0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PENDR0_EL2 +// CHECK-ENCODING: [0x83,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca83 + +MRS x3, ICH_PPI_PENDR1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PENDR1_EL2 +// CHECK-ENCODING: [0xa3,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccaa3 + +MRS x3, ICH_PPI_PRIORITYR0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR0_EL2 +// CHECK-ENCODING: [0x03,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce03 + +MRS x3, ICH_PPI_PRIORITYR1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR1_EL2 +// CHECK-ENCODING: [0x23,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce23 + +MRS x3, ICH_PPI_PRIORITYR2_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR2_EL2 +// CHECK-ENCODING: [0x43,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce43 + +MRS x3, ICH_PPI_PRIORITYR3_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR3_EL2 +// CHECK-ENCODING: [0x63,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce63 + +MRS x3, ICH_PPI_PRIORITYR4_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR4_EL2 +// CHECK-ENCODING: [0x83,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce83 + +MRS x3, ICH_PPI_PRIORITYR5_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR5_EL2 +// CHECK-ENCODING: [0xa3,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccea3 + +MRS x3, ICH_PPI_PRIORITYR6_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR6_EL2 +// CHECK-ENCODING: [0xc3,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccec3 + +MRS x3, ICH_PPI_PRIORITYR7_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR7_EL2 +// CHECK-ENCODING: [0xe3,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccee3 + +MRS x3, ICH_PPI_PRIORITYR8_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR8_EL2 +// CHECK-ENCODING: [0x03,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf03 + +MRS x3, ICH_PPI_PRIORITYR9_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR9_EL2 +// CHECK-ENCODING: [0x23,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf23 + +MRS x3, ICH_PPI_PRIORITYR10_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR10_EL2 +// CHECK-ENCODING: [0x43,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf43 + +MRS x3, ICH_PPI_PRIORITYR11_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR11_EL2 +// CHECK-ENCODING: [0x63,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf63 + +MRS x3, ICH_PPI_PRIORITYR12_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR12_EL2 +// CHECK-ENCODING: [0x83,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf83 + +MRS x3, ICH_PPI_PRIORITYR13_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR13_EL2 +// CHECK-ENCODING: [0xa3,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccfa3 + +MRS x3, ICH_PPI_PRIORITYR14_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR14_EL2 +// CHECK-ENCODING: [0xc3,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccfc3 + +MRS x3, ICH_PPI_PRIORITYR15_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR15_EL2 +// CHECK-ENCODING: [0xe3,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccfe3 + +MRS x3, ICH_VCTLR_EL2 +// CHECK-INST: mrs x3, ICH_VCTLR_EL2 +// CHECK-ENCODING: [0x83,0xcb,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccb83 + +// ----------------------------------------------- +// Hypervisor Control Register MSR Instructions +MSR ICH_APR_EL2, x3 +// CHECK-INST: msr ICH_APR_EL2, x3 +// CHECK-ENCODING: [0x83,0xc8,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc883 + +MSR ICH_CONTEXTR_EL2, x3 +// CHECK-INST: msr ICH_CONTEXTR_EL2, x3 +// CHECK-ENCODING: [0xc3,0xcb,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccbc3 + +MSR ICH_HFGITR_EL2, x3 +// CHECK-INST: msr ICH_HFGITR_EL2, x3 +// CHECK-ENCODING: [0xe3,0xc9,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc9e3 + +MSR ICH_HFGRTR_EL2, x3 +// CHECK-INST: msr ICH_HFGRTR_EL2, x3 +// CHECK-ENCODING: [0x83,0xc9,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc983 + +MSR ICH_HFGWTR_EL2, x3 +// CHECK-INST: msr ICH_HFGWTR_EL2, x3 +// CHECK-ENCODING: [0xc3,0xc9,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc9c3 + +MSR ICH_PPI_ACTIVER0_EL2, x3 +// CHECK-INST: msr ICH_PPI_ACTIVER0_EL2, x3 +// CHECK-ENCODING: [0xc3,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccac3 + +MSR ICH_PPI_ACTIVER1_EL2, x3 +// CHECK-INST: msr ICH_PPI_ACTIVER1_EL2, x3 +// CHECK-ENCODING: [0xe3,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccae3 + +MSR ICH_PPI_DVIR0_EL2, x3 +// CHECK-INST: msr ICH_PPI_DVIR0_EL2, x3 +// CHECK-ENCODING: [0x03,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca03 + +MSR ICH_PPI_DVIR1_EL2, x3 +// CHECK-INST: msr ICH_PPI_DVIR1_EL2, x3 +// CHECK-ENCODING: [0x23,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca23 + +MSR ICH_PPI_ENABLER0_EL2, x3 +// CHECK-INST: msr ICH_PPI_ENABLER0_EL2, x3 +// CHECK-ENCODING: [0x43,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca43 + +MSR ICH_PPI_ENABLER1_EL2, x3 +// CHECK-INST: msr ICH_PPI_ENABLER1_EL2, x3 +// CHECK-ENCODING: [0x63,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca63 + +MSR ICH_PPI_PENDR0_EL2, x3 +// CHECK-INST: msr ICH_PPI_PENDR0_EL2, x3 +// CHECK-ENCODING: [0x83,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca83 + +MSR ICH_PPI_PENDR1_EL2, x3 +// CHECK-INST: msr ICH_PPI_PENDR1_EL2, x3 +// CHECK-ENCODING: [0xa3,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccaa3 + +MSR ICH_PPI_PRIORITYR0_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR0_EL2, x3 +// CHECK-ENCODING: [0x03,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce03 + +MSR ICH_PPI_PRIORITYR1_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR1_EL2, x3 +// CHECK-ENCODING: [0x23,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce23 + +MSR ICH_PPI_PRIORITYR2_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR2_EL2, x3 +// CHECK-ENCODING: [0x43,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce43 + +MSR ICH_PPI_PRIORITYR3_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR3_EL2, x3 +// CHECK-ENCODING: [0x63,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce63 + +MSR ICH_PPI_PRIORITYR4_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR4_EL2, x3 +// CHECK-ENCODING: [0x83,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce83 + +MSR ICH_PPI_PRIORITYR5_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR5_EL2, x3 +// CHECK-ENCODING: [0xa3,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccea3 + +MSR ICH_PPI_PRIORITYR6_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR6_EL2, x3 +// CHECK-ENCODING: [0xc3,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccec3 + +MSR ICH_PPI_PRIORITYR7_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR7_EL2, x3 +// CHECK-ENCODING: [0xe3,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccee3 + +MSR ICH_PPI_PRIORITYR8_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR8_EL2, x3 +// CHECK-ENCODING: [0x03,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf03 + +MSR ICH_PPI_PRIORITYR9_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR9_EL2, x3 +// CHECK-ENCODING: [0x23,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf23 + +MSR ICH_PPI_PRIORITYR10_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR10_EL2, x3 +// CHECK-ENCODING: [0x43,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf43 + +MSR ICH_PPI_PRIORITYR11_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR11_EL2, x3 +// CHECK-ENCODING: [0x63,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf63 + +MSR ICH_PPI_PRIORITYR12_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR12_EL2, x3 +// CHECK-ENCODING: [0x83,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf83 + +MSR ICH_PPI_PRIORITYR13_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR13_EL2, x3 +// CHECK-ENCODING: [0xa3,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccfa3 + +MSR ICH_PPI_PRIORITYR14_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR14_EL2, x3 +// CHECK-ENCODING: [0xc3,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccfc3 + +MSR ICH_PPI_PRIORITYR15_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR15_EL2, x3 +// CHECK-ENCODING: [0xe3,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccfe3 + +MSR ICH_VCTLR_EL2, x3 +// CHECK-INST: msr ICH_VCTLR_EL2, x3 +// CHECK-ENCODING: [0x83,0xcb,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccb83 + +// ----------------------------------------------- +// FEAT_GCIE Instructions +// Current Interrupt Domain +GIC CDAFF, x3 +// CHECK-INST: gic cdaff, x3 +// CHECK-ENCODING: [0x63,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c163 sys #0, c12, c1, #3, x3 +// CHECK-ERROR: error: GIC cdaff requires: gcie + +GIC CDDI, x3 +// CHECK-INST: gic cddi, x3 +// CHECK-ENCODING: [0x03,0xc2,0x08,0xd5] +// CHECK-UNKNOWN: d508c203 sys #0, c12, c2, #0, x3 +// CHECK-ERROR: error: GIC cddi requires: gcie + +GIC CDDIS, x3 +// CHECK-INST: gic cddis, x3 +// CHECK-ENCODING: [0x03,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c103 sys #0, c12, c1, #0, x3 +// CHECK-ERROR: error: GIC cddis requires: gcie + +GIC CDEN, x3 +// CHECK-INST: gic cden, x3 +// CHECK-ENCODING: [0x23,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c123 sys #0, c12, c1, #1, x3 +// CHECK-ERROR: error: GIC cden requires: gcie + +GIC CDEOI, x3 +// CHECK-INST: gic cdeoi, x3 +// CHECK-ENCODING: [0xe3,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c1e3 sys #0, c12, c1, #7, x3 +// CHECK-ERROR: error: GIC cdeoi requires: gcie + +GIC CDHM, x3 +// CHECK-INST: gic cdhm, x3 +// CHECK-ENCODING: [0x23,0xc2,0x08,0xd5] +// CHECK-UNKNOWN: d508c223 sys #0, c12, c2, #1, x3 +// CHECK-ERROR: error: GIC cdhm requires: gcie + +GIC CDPEND, x3 +// CHECK-INST: gic cdpend, x3 +// CHECK-ENCODING: [0x83,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c183 sys #0, c12, c1, #4, x3 +// CHECK-ERROR: error: GIC cdpend requires: gcie + +GIC CDPRI, x3 +// CHECK-INST: gic cdpri, x3 +// CHECK-ENCODING: [0x43,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c143 sys #0, c12, c1, #2, x3 +// CHECK-ERROR: error: GIC cdpri requires: gcie + +GIC CDRCFG, x3 +// CHECK-INST: gic cdrcfg, x3 +// CHECK-ENCODING: [0xa3,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c1a3 sys #0, c12, c1, #5, x3 +// CHECK-ERROR: error: GIC cdrcfg requires: gcie + +GICR x3, CDIA +// CHECK-INST: gicr x3, cdia +// CHECK-ENCODING: [0x03,0xc3,0x28,0xd5] +// CHECK-UNKNOWN: d528c303 sysl x3, #0, c12, c3, #0 +// CHECK-ERROR: error: GICR cdia requires: gcie + +GICR x3, CDNMIA +// CHECK-INST: gicr x3, cdnmia +// CHECK-ENCODING: [0x23,0xc3,0x28,0xd5] +// CHECK-UNKNOWN: d528c323 sysl x3, #0, c12, c3, #1 +// CHECK-ERROR: error: GICR cdnmia requires: gcie + +// ----------------------------------------------- +// Virtual Interrupt Domain +GIC VDAFF, x3 +// CHECK-INST: gic vdaff, x3 +// CHECK-ENCODING: [0x63,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc163 sys #4, c12, c1, #3, x3 +// CHECK-ERROR: error: GIC vdaff requires: gcie + +GIC VDDI, x3 +// CHECK-INST: gic vddi, x3 +// CHECK-ENCODING: [0x03,0xc2,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc203 sys #4, c12, c2, #0, x3 +// CHECK-ERROR: error: GIC vddi requires: gcie + +GIC VDDIS, x3 +// CHECK-INST: gic vddis, x3 +// CHECK-ENCODING: [0x03,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc103 sys #4, c12, c1, #0, x3 +// CHECK-ERROR: error: GIC vddis requires: gcie + +GIC VDEN, x3 +// CHECK-INST: gic vden, x3 +// CHECK-ENCODING: [0x23,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc123 sys #4, c12, c1, #1, x3 +// CHECK-ERROR: error: GIC vden requires: gcie + +GIC VDHM, x3 +// CHECK-INST: gic vdhm, x3 +// CHECK-ENCODING: [0x23,0xc2,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc223 sys #4, c12, c2, #1, x3 +// CHECK-ERROR: error: GIC vdhm requires: gcie + +GIC VDPEND, x3 +// CHECK-INST: gic vdpend, x3 +// CHECK-ENCODING: [0x83,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc183 sys #4, c12, c1, #4, x3 +// CHECK-ERROR: error: GIC vdpend requires: gcie + +GIC VDPRI, x3 +// CHECK-INST: gic vdpri, x3 +// CHECK-ENCODING: [0x43,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc143 sys #4, c12, c1, #2, x3 +// CHECK-ERROR: error: GIC vdpri requires: gcie + +GIC VDRCFG, x3 +// CHECK-INST: gic vdrcfg, x3 +// CHECK-ENCODING: [0xa3,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc1a3 sys #4, c12, c1, #5, x3 +// CHECK-ERROR: error: GIC vdrcfg requires: gcie + +// ----------------------------------------------- +// Logical Interrupt Domain +GIC LDAFF, x3 +// CHECK-INST: gic ldaff, x3 +// CHECK-ENCODING: [0x63,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec163 sys #6, c12, c1, #3, x3 +// CHECK-ERROR: error: GIC ldaff requires: gcie + +GIC LDDI, x3 +// CHECK-INST: gic lddi, x3 +// CHECK-ENCODING: [0x03,0xc2,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec203 sys #6, c12, c2, #0, x3 +// CHECK-ERROR: error: GIC lddi requires: gcie + +GIC LDDIS, x3 +// CHECK-INST: gic lddis, x3 +// CHECK-ENCODING: [0x03,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec103 sys #6, c12, c1, #0, x3 +// CHECK-ERROR: error: GIC lddis requires: gcie + +GIC LDEN, x3 +// CHECK-INST: gic lden, x3 +// CHECK-ENCODING: [0x23,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec123 sys #6, c12, c1, #1, x3 +// CHECK-ERROR: error: GIC lden requires: gcie + +GIC LDHM, x3 +// CHECK-INST: gic ldhm, x3 +// CHECK-ENCODING: [0x23,0xc2,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec223 sys #6, c12, c2, #1, x3 +// CHECK-ERROR: error: GIC ldhm requires: gcie + +GIC LDPEND, x3 +// CHECK-INST: gic ldpend, x3 +// CHECK-ENCODING: [0x83,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec183 sys #6, c12, c1, #4, x3 +// CHECK-ERROR: error: GIC ldpend requires: gcie + +GIC LDPRI, x3 +// CHECK-INST: gic ldpri, x3 +// CHECK-ENCODING: [0x43,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec143 sys #6, c12, c1, #2, x3 +// CHECK-ERROR: error: GIC ldpri requires: gcie + +GIC LDRCFG, x3 +// CHECK-INST: gic ldrcfg, x3 +// CHECK-ENCODING: [0xa3,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec1a3 sys #6, c12, c1, #5, x3 +// CHECK-ERROR: error: GIC ldrcfg requires: gcie + +// ----------------------------------------------- +// GIC Synchronization Barrier Instructions +GSB SYS +// CHECK-INST: gsb sys +// CHECK-ENCODING: [0x1f,0xc0,0x08,0xd5] +// CHECK-UNKNOWN: d508c01f sys #0, c12, c0, #0 +// CHECK-ERROR: error: GSB sys requires: gcie + +GSB ACK +// CHECK-INST: gsb ack +// CHECK-ENCODING: [0x3f,0xc0,0x08,0xd5] +// CHECK-UNKNOWN: d508c03f sys #0, c12, c0, #1 +// CHECK-ERROR: error: GSB ack requires: gcie diff --git a/llvm/test/MC/AArch64/armv9.7a-memsys.s b/llvm/test/MC/AArch64/armv9.7a-memsys.s new file mode 100644 index 0000000..228c71e --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-memsys.s @@ -0,0 +1,140 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+cmh,+lscp < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+cmh,+lscp < %s \ +// RUN: | llvm-objdump -d --mattr=+cmh,+lscp --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+cmh,+lscp < %s \ +// RUN: | llvm-objdump -d --mattr=-cmh,-lscp --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+cmh,+lscp < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+cmh,+lscp -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// Armv9.7-A Contention Management Hints (FEAT_CMH). + +shuh +// CHECK-INST: shuh +// CHECK-ENCODING: encoding: [0x5f,0x26,0x03,0xd5] +// CHECK-ERROR: error: instruction requires: cmh +// CHECK-UNKNOWN: d503265f hint #50 + +shuh ph +// CHECK-INST: shuh ph +// CHECK-ENCODING: encoding: [0x7f,0x26,0x03,0xd5] +// CHECK-ERROR: error: instruction requires: cmh +// CHECK-UNKNOWN: d503267f hint #51 + +stcph +// CHECK-INST: stcph +// CHECK-ENCODING: [0x9f,0x26,0x03,0xd5] +// CHECK-ERROR: error: instruction requires: cmh +// CHECK-UNKNOWN: d503269f hint #52 + +ldap x0, x1, [x2] +// CHECK-INST: ldap x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x40,0x58,0x41,0xd9] +// CHECK-ERROR: error: instruction requires: lscp +// CHECK-UNKNOWN: d9415840 <unknown> + +ldap x0, x1, [x2, #0] +// CHECK-INST: ldap x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x40,0x58,0x41,0xd9] +// CHECK-ERROR: error: instruction requires: lscp +// CHECK-UNKNOWN: d9415840 <unknown> + +ldapp x0, x1, [x2] +// CHECK-INST: ldapp x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x40,0x78,0x41,0xd9] +// CHECK-ERROR: error: instruction requires: lscp +// CHECK-UNKNOWN: d9417840 <unknown> + +ldapp x0, x1, [x2, #0] +// CHECK-INST: ldapp x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x40,0x78,0x41,0xd9] +// CHECK-ERROR: error: instruction requires: lscp +// CHECK-UNKNOWN: d9417840 <unknown> + +stlp x0, x1, [x2, #0] +// CHECK-INST: stlp x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x40,0x58,0x01,0xd9] +// CHECK-ERROR: error: instruction requires: lscp +// CHECK-UNKNOWN: d9015840 <unknown> + +stlp x0, x1, [x2] +// CHECK-INST: stlp x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x40,0x58,0x01,0xd9] +// CHECK-ERROR: error: instruction requires: lscp +// CHECK-UNKNOWN: d9015840 <unknown> + +mrs x3, VTLBID0_EL2 +// CHECK-INST: mrs x3, VTLBID0_EL2 +// CHECK-ENCODING: encoding: [0x03,0x28,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2803 +mrs x3, VTLBID1_EL2 +// CHECK-INST: mrs x3, VTLBID1_EL2 +// CHECK-ENCODING: encoding: [0x23,0x28,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2823 +mrs x3, VTLBID2_EL2 +// CHECK-INST: mrs x3, VTLBID2_EL2 +// CHECK-ENCODING: encoding: [0x43,0x28,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2843 +mrs x3, VTLBID3_EL2 +// CHECK-INST: mrs x3, VTLBID3_EL2 +// CHECK-ENCODING: encoding: [0x63,0x28,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2863 +mrs x3, VTLBIDOS0_EL2 +// CHECK-INST: mrs x3, VTLBIDOS0_EL2 +// CHECK-ENCODING: encoding: [0x03,0x29,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2903 +mrs x3, VTLBIDOS1_EL2 +// CHECK-INST: mrs x3, VTLBIDOS1_EL2 +// CHECK-ENCODING: encoding: [0x23,0x29,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2923 +mrs x3, VTLBIDOS2_EL2 +// CHECK-INST: mrs x3, VTLBIDOS2_EL2 +// CHECK-ENCODING: encoding: [0x43,0x29,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2943 +mrs x3, VTLBIDOS3_EL2 +// CHECK-INST: mrs x3, VTLBIDOS3_EL2 +// CHECK-ENCODING: encoding: [0x63,0x29,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2963 +mrs x3, TLBIDIDR_EL1 +// CHECK-INST: mrs x3, TLBIDIDR_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xa4,0x38,0xd5] +// CHECK-UNKNOWN: d538a4c3 + +msr VTLBID0_EL2, x3 +// CHECK-INST: msr VTLBID0_EL2, x3 +// CHECK-ENCODING: encoding: [0x03,0x28,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2803 +msr VTLBID1_EL2, x3 +// CHECK-INST: msr VTLBID1_EL2, x3 +// CHECK-ENCODING: encoding: [0x23,0x28,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2823 +msr VTLBID2_EL2, x3 +// CHECK-INST: msr VTLBID2_EL2, x3 +// CHECK-ENCODING: encoding: [0x43,0x28,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2843 +msr VTLBID3_EL2, x3 +// CHECK-INST: msr VTLBID3_EL2, x3 +// CHECK-ENCODING: encoding: [0x63,0x28,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2863 +msr VTLBIDOS0_EL2, x3 +// CHECK-INST: msr VTLBIDOS0_EL2, x3 +// CHECK-ENCODING: encoding: [0x03,0x29,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2903 +msr VTLBIDOS1_EL2, x3 +// CHECK-INST: msr VTLBIDOS1_EL2, x3 +// CHECK-ENCODING: encoding: [0x23,0x29,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2923 +msr VTLBIDOS2_EL2, x3 +// CHECK-INST: msr VTLBIDOS2_EL2, x3 +// CHECK-ENCODING: encoding: [0x43,0x29,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2943 +msr VTLBIDOS3_EL2, x3 +// CHECK-INST: msr VTLBIDOS3_EL2, x3 +// CHECK-ENCODING: encoding: [0x63,0x29,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2963 + diff --git a/llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s new file mode 100644 index 0000000..54fdc23 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s @@ -0,0 +1,18 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+mpamv2 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +//------------------------------------------------------------------------------ +// Armv9.7-A FEAT_MPAMV2 Extensions +//------------------------------------------------------------------------------ + +mlbi alle1, x30 +// CHECK-ERROR: error: specified mlbi op does not use a register + +mlbi vmalle1, x30 +// CHECK-ERROR: error: specified mlbi op does not use a register + +mlbi vpide1 +// CHECK-ERROR: error: specified mlbi op requires a register + +mlbi vpmge1 +// CHECK-ERROR: error: specified mlbi op requires a register diff --git a/llvm/test/MC/AArch64/armv9.7a-mpamv2.s b/llvm/test/MC/AArch64/armv9.7a-mpamv2.s new file mode 100644 index 0000000..b8b21e96 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-mpamv2.s @@ -0,0 +1,126 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mpamv2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mpamv2 < %s \ +// RUN: | llvm-objdump -d --mattr=+mpamv2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mpamv2 < %s \ +// RUN: | llvm-objdump -d --mattr=-mpamv2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mpamv2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+mpamv2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +//------------------------------------------------------------------------------ +// Armv9.7-A FEAT_MPAMV2 Extensions +//------------------------------------------------------------------------------ + +msr MPAMCTL_EL1, x0 +// CHECK-INST: msr MPAMCTL_EL1, x0 +// CHECK-ENCODING: [0x40,0xa5,0x18,0xd5] +// CHECK-UNKNOWN: d518a540 + +msr MPAMCTL_EL12, x0 +// CHECK-INST: msr MPAMCTL_EL12, x0 +// CHECK-ENCODING: [0x40,0xa5,0x1d,0xd5] +// CHECK-UNKNOWN: d51da540 + +msr MPAMCTL_EL2, x0 +// CHECK-INST: msr MPAMCTL_EL2, x0 +// CHECK-ENCODING: [0x40,0xa5,0x1c,0xd5] +// CHECK-UNKNOWN: d51ca540 + +msr MPAMCTL_EL3, x0 +// CHECK-INST: msr MPAMCTL_EL3, x0 +// CHECK-ENCODING: [0x40,0xa5,0x1e,0xd5] +// CHECK-UNKNOWN: d51ea540 + +msr MPAMVIDCR_EL2, x0 +// CHECK-INST: msr MPAMVIDCR_EL2, x0 +// CHECK-ENCODING: [0x00,0xa7,0x1c,0xd5] +// CHECK-UNKNOWN: d51ca700 + +msr MPAMVIDSR_EL2, x0 +// CHECK-INST: msr MPAMVIDSR_EL2, x0 +// CHECK-ENCODING: [0x20,0xa7,0x1c,0xd5] +// CHECK-UNKNOWN: d51ca720 + +msr MPAMVIDSR_EL3, x0 +// CHECK-INST: msr MPAMVIDSR_EL3, x0 +// CHECK-ENCODING: [0x20,0xa7,0x1e,0xd5] +// CHECK-UNKNOWN: d51ea720 + + +mrs x0, MPAMCTL_EL1 +// CHECK-INST: mrs x0, MPAMCTL_EL1 +// CHECK-ENCODING: [0x40,0xa5,0x38,0xd5] +// CHECK-UNKNOWN: d538a540 + +mrs x0, MPAMCTL_EL12 +// CHECK-INST: mrs x0, MPAMCTL_EL12 +// CHECK-ENCODING: [0x40,0xa5,0x3d,0xd5] +// CHECK-UNKNOWN: d53da540 + +mrs x0, MPAMCTL_EL2 +// CHECK-INST: mrs x0, MPAMCTL_EL2 +// CHECK-ENCODING: [0x40,0xa5,0x3c,0xd5] +// CHECK-UNKNOWN: d53ca540 + +mrs x0, MPAMCTL_EL3 +// CHECK-INST: mrs x0, MPAMCTL_EL3 +// CHECK-ENCODING: [0x40,0xa5,0x3e,0xd5] +// CHECK-UNKNOWN: d53ea540 + +mrs x0, MPAMVIDCR_EL2 +// CHECK-INST: mrs x0, MPAMVIDCR_EL2 +// CHECK-ENCODING: [0x00,0xa7,0x3c,0xd5] +// CHECK-UNKNOWN: d53ca700 + +mrs x0, MPAMVIDSR_EL2 +// CHECK-INST: mrs x0, MPAMVIDSR_EL2 +// CHECK-ENCODING: [0x20,0xa7,0x3c,0xd5] +// CHECK-UNKNOWN: d53ca720 + +mrs x0, MPAMVIDSR_EL3 +// CHECK-INST: mrs x0, MPAMVIDSR_EL3 +// CHECK-ENCODING: [0x20,0xa7,0x3e,0xd5] +// CHECK-UNKNOWN: d53ea720 + + +//------------------------------------------------------------------------------ +// Armv9.7-A FEAT_MPAMV2_VID Extensions +//------------------------------------------------------------------------------ + +mlbi vmalle1 +// CHECK-INST: mlbi vmalle1 +// CHECK-ENCODING: [0xbf,0x70,0x0c,0xd5] +// CHECK-UNKNOWN: d50c70bf sys #4, c7, c0, #5 +// CHECK-ERROR: error: MLBI VMALLE1 requires: mpamv2 + +mlbi vpide1, x0 +// CHECK-INST: mlbi vpide1, x0 +// CHECK-ENCODING: [0xc0,0x70,0x0c,0xd5] +// CHECK-UNKNOWN: d50c70c0 sys #4, c7, c0, #6, x0 +// CHECK-ERROR: error: MLBI VPIDE1 requires: mpamv2 + +mlbi vpmge1, x0 +// CHECK-INST: mlbi vpmge1, x0 +// CHECK-ENCODING: [0xe0,0x70,0x0c,0xd5] +// CHECK-UNKNOWN: d50c70e0 sys #4, c7, c0, #7, x0 +// CHECK-ERROR: error: MLBI VPMGE1 requires: mpamv2 + +// Check that invalid encodings are rendered as SYS aliases +// [0x9f,0x70,0x0c,0xd5] -> mlbi alle1 +// [0x9e,0x70,0x0c,0xd5] -> sys #4, c7, c0, #4, x30 + +mlbi alle1 +// CHECK-INST: mlbi alle1 +// CHECK-ENCODING: [0x9f,0x70,0x0c,0xd5] +// CHECK-UNKNOWN: d50c709f sys #4, c7, c0, #4 +// CHECK-ERROR: error: MLBI ALLE1 requires: mpamv2 + +sys #4, c7, c0, #4, x30 +// CHECK-INST: sys #4, c7, c0, #4, x30 +// CHECK-ENCODING: [0x9e,0x70,0x0c,0xd5] +// CHECK-UNKNOWN: d50c709e sys #4, c7, c0, #4, x30 diff --git a/llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s new file mode 100644 index 0000000..dc2a290 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s @@ -0,0 +1,16 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+mtetc -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-REQUIRES-MTETC + +//------------------------------------------------------------------------------ +// FEAT_MTETC Extension instructions +//------------------------------------------------------------------------------ + +dc zgbva +// CHECK-ERROR: error: specified dc op requires a register +// CHECK-REQUIRES-MTETC: DC ZGBVA requires: mtetc + +dc gbva +// CHECK-ERROR: error: specified dc op requires a register +// CHECK-REQUIRES-MTETC: DC GBVA requires: mtetc diff --git a/llvm/test/MC/AArch64/armv9.7a-mtetc.s b/llvm/test/MC/AArch64/armv9.7a-mtetc.s new file mode 100644 index 0000000..087b23b --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-mtetc.s @@ -0,0 +1,29 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mtetc < %s \ +// RUN: | llvm-objdump -d --mattr=+mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mtetc < %s \ +// RUN: | llvm-objdump -d --mattr=-mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+mtetc -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +//------------------------------------------------------------------------------ +// FEAT_MTETC Extension instructions +//------------------------------------------------------------------------------ + +dc zgbva, x0 +// CHECK-INST: dc zgbva, x0 +// CHECK-ENCODING: [0xa0,0x74,0x0b,0xd5] +// CHECK-UNKNOWN: d50b74a0 sys #3, c7, c4, #5, x0 +// CHECK-ERROR: DC ZGBVA requires: mtetc + +dc gbva, x0 +// CHECK-INST: dc gbva, x0 +// CHECK-ENCODING: [0xe0,0x74,0x0b,0xd5] +// CHECK-UNKNOWN: d50b74e0 sys #3, c7, c4, #7, x0 +// CHECK-ERROR: DC GBVA requires: mtetc diff --git a/llvm/test/MC/AArch64/armv9.7a-tlbid-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-tlbid-diagnostics.s new file mode 100644 index 0000000..2440fd3 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-tlbid-diagnostics.s @@ -0,0 +1,64 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi,+tlbiw,+rme < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi,+tlbiw,+tlbid,+rme < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-NO-REGISTER + +// Test without using +tlbid - no optional register operand allowed + +tlbi vmalle1is, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmalle1is, x5 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmalle1os, x5 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmalls12e1os, x5 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi alle1is, x5 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi alle2is, x5 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi alle3is, x5 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmallws2e1os, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmalls12e1is, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmallws2e1is, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register + +tlbi vmalle1, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register + +tlbi alle1, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register + +tlbi alle2, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register + +tlbi alle3, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register + +tlbi vmalls12e1, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register + +tlbi paallos, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register + +tlbi paall, x1 +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-NO-REGISTER: error: specified tlbi op does not use a register diff --git a/llvm/test/MC/AArch64/armv9.7a-tlbid.s b/llvm/test/MC/AArch64/armv9.7a-tlbid.s new file mode 100644 index 0000000..1362bd3 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-tlbid.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbid,+tlb-rmi,+tlbiw < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi,+tlbiw < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbid,+tlb-rmi,+tlbiw < %s \ +// RUN: | llvm-objdump -d --mattr=+tlbid,+tlb-rmi,+tlbiw --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbid,+tlb-rmi,+tlbiw < %s \ +// RUN: | llvm-objdump -d --mattr=-tlbid --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbid,+tlb-rmi,+tlbiw < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+tlbid,+tlb-rmi,+tlbiw -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// Armv9.7-A TLBI Domains (FEAT_TLBID) + +tlbi vmalle1is +// CHECK-INST: tlbi vmalle1is +// CHECK-ENCODING: encoding: [0x1f,0x83,0x08,0xd5] +// CHECK-UNKNOWN: d508831f tlbi vmalle1is + +tlbi vmalle1is, xzr +// CHECK-INST: tlbi vmalle1is +// CHECK-ENCODING: encoding: [0x1f,0x83,0x08,0xd5] +// CHECK-UNKNOWN: d508831f tlbi vmalle1is + +tlbi vmalle1is, x31 +// CHECK-INST: tlbi vmalle1is +// CHECK-ENCODING: encoding: [0x1f,0x83,0x08,0xd5] +// CHECK-UNKNOWN: d508831f tlbi vmalle1is + +tlbi vmalle1is, x5 +// CHECK-INST: tlbi vmalle1is, x5 +// CHECK-ENCODING: encoding: [0x05,0x83,0x08,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d5088305 sys #0, c8, c3, #0, x5 + +tlbi vmalle1os, x5 +// CHECK-INST: tlbi vmalle1os, x5 +// CHECK-ENCODING: encoding: [0x05,0x81,0x08,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d5088105 sys #0, c8, c1, #0, x5 + +tlbi alle1is, x5 +// CHECK-INST: tlbi alle1is, x5 +// CHECK-ENCODING: encoding: [0x85,0x83,0x0c,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50c8385 sys #4, c8, c3, #4, x5 + +tlbi alle2is, x5 +// CHECK-INST: tlbi alle2is, x5 +// CHECK-ENCODING: encoding: [0x05,0x83,0x0c,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50c8305 sys #4, c8, c3, #0, x5 + +tlbi alle3is, x5 +// CHECK-INST: tlbi alle3is, x5 +// CHECK-ENCODING: encoding: [0x05,0x83,0x0e,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50e8305 sys #6, c8, c3, #0, x5 + +tlbi vmalls12e1is, x1 +// CHECK-INST: tlbi vmalls12e1is, x1 +// CHECK-ENCODING: encoding: [0xc1,0x83,0x0c,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50c83c1 sys #4, c8, c3, #6, x1 + +tlbi vmalls12e1os, x5 +// CHECK-INST: tlbi vmalls12e1os, x5 +// CHECK-ENCODING: encoding: [0xc5,0x81,0x0c,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50c81c5 sys #4, c8, c1, #6, x5 + +tlbi vmallws2e1is, x1 +// CHECK-INST: tlbi vmallws2e1is, x1 +// CHECK-ENCODING: encoding: [0x41,0x82,0x0c,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50c8241 sys #4, c8, c2, #2, x1 + +tlbi vmallws2e1os, x1 +// CHECK-INST: tlbi vmallws2e1os, x1 +// CHECK-ENCODING: encoding: [0x41,0x85,0x0c,0xd5] +// CHECK-ERROR: error: specified tlbi op does not use a register +// CHECK-UNKNOWN: d50c8541 sys #4, c8, c5, #2, x1 diff --git a/llvm/test/MC/AArch64/neon-fdot-diagnostics.s b/llvm/test/MC/AArch64/neon-fdot-diagnostics.s new file mode 100644 index 0000000..4f5f557 --- /dev/null +++ b/llvm/test/MC/AArch64/neon-fdot-diagnostics.s @@ -0,0 +1,59 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=f16f32dot 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand + +fdot v0.2s, v0.4b, v0.4b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2s, v0.4b, v0.4b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2b, v0.4b, v0.4b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2b, v0.4b, v0.4b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2s, v0.4s, v0.4s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2s, v0.4s, v0.4s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2h, v0.4h, v0.4h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2h, v0.4h, v0.4h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// fdot indexed + +fdot v0.2s, v0.4b, v0.4b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2s, v0.4b, v0.4b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2b, v0.4b, v0.4b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2b, v0.4b, v0.4b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2s, v0.4s, v0.4s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2s, v0.4s, v0.4s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2h, v0.4h, v0.4h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fdot v0.2h, v0.4h, v0.4h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +fdot v0.2s, v0.4h, v0.2h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fdot v0.2s, v0.4h, v0.2h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fdot v0.2s, v0.4h, v0.2h[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fdot v0.2s, v0.4h, v0.2h[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/neon-fdot.s b/llvm/test/MC/AArch64/neon-fdot.s new file mode 100644 index 0000000..c8a8e2f --- /dev/null +++ b/llvm/test/MC/AArch64/neon-fdot.s @@ -0,0 +1,147 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16f32dot < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16f32dot < %s \ +// RUN: | llvm-objdump -d --mattr=+f16f32dot --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16f32dot < %s \ +// RUN: | llvm-objdump -d --mattr=-f16f32dot --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16f32dot < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+f16f32dot -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +fdot v0.2s, v0.4h, v0.4h +// CHECK-INST: fdot v0.2s, v0.4h, v0.4h +// CHECK-ENCODING: encoding: [0x00,0xfc,0x80,0x0e] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0e80fc00 <unknown> + +fdot v10.2s, v10.4h, v10.4h +// CHECK-INST: fdot v10.2s, v10.4h, v10.4h +// CHECK-ENCODING: encoding: [0x4a,0xfd,0x8a,0x0e] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0e8afd4a <unknown> + +fdot v31.2s, v31.4h, v31.4h +// CHECK-INST: fdot v31.2s, v31.4h, v31.4h +// CHECK-ENCODING: encoding: [0xff,0xff,0x9f,0x0e] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0e9fffff <unknown> + +fdot v0.4s, v0.8h, v0.8h +// CHECK-INST: fdot v0.4s, v0.8h, v0.8h +// CHECK-ENCODING: encoding: [0x00,0xfc,0x80,0x4e] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4e80fc00 <unknown> + +fdot v10.4s, v10.8h, v10.8h +// CHECK-INST: fdot v10.4s, v10.8h, v10.8h +// CHECK-ENCODING: encoding: [0x4a,0xfd,0x8a,0x4e] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4e8afd4a <unknown> + +fdot v31.4s, v31.8h, v31.8h +// CHECK-INST: fdot v31.4s, v31.8h, v31.8h +// CHECK-ENCODING: encoding: [0xff,0xff,0x9f,0x4e] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4e9fffff <unknown> + +// fdot indexed + +fdot v0.2s, v0.4h, v0.2h[0] +// CHECK-INST: fdot v0.2s, v0.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x00,0x90,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f409000 <unknown> + +fdot v10.2s, v0.4h, v0.2h[0] +// CHECK-INST: fdot v10.2s, v0.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x0a,0x90,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f40900a <unknown> + +fdot v21.2s, v0.4h, v0.2h[0] +// CHECK-INST: fdot v21.2s, v0.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x15,0x90,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f409015 <unknown> + +fdot v31.2s, v0.4h, v0.2h[0] +// CHECK-INST: fdot v31.2s, v0.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x1f,0x90,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f40901f <unknown> + +fdot v0.2s, v10.4h, v0.2h[0] +// CHECK-INST: fdot v0.2s, v10.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x40,0x91,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f409140 <unknown> + +fdot v10.2s, v10.4h, v0.2h[0] +// CHECK-INST: fdot v10.2s, v10.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x4a,0x91,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f40914a <unknown> + +fdot v21.2s, v10.4h, v0.2h[0] +// CHECK-INST: fdot v21.2s, v10.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x55,0x91,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f409155 <unknown> + +fdot v31.2s, v10.4h, v0.2h[0] +// CHECK-INST: fdot v31.2s, v10.4h, v0.2h[0] +// CHECK-ENCODING: encoding: [0x5f,0x91,0x40,0x0f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 0f40915f <unknown> + +fdot v0.4s, v21.8h, v31.2h[3] +// CHECK-INST: fdot v0.4s, v21.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xa0,0x9a,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9aa0 <unknown> + +fdot v10.4s, v21.8h, v31.2h[3] +// CHECK-INST: fdot v10.4s, v21.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xaa,0x9a,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9aaa <unknown> + +fdot v21.4s, v21.8h, v31.2h[3] +// CHECK-INST: fdot v21.4s, v21.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xb5,0x9a,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9ab5 <unknown> + +fdot v31.4s, v21.8h, v31.2h[3] +// CHECK-INST: fdot v31.4s, v21.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xbf,0x9a,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9abf <unknown> + +fdot v0.4s, v31.8h, v31.2h[3] +// CHECK-INST: fdot v0.4s, v31.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xe0,0x9b,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9be0 <unknown> + +fdot v10.4s, v31.8h, v31.2h[3] +// CHECK-INST: fdot v10.4s, v31.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xea,0x9b,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9bea <unknown> + +fdot v21.4s, v31.8h, v31.2h[3] +// CHECK-INST: fdot v21.4s, v31.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xf5,0x9b,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9bf5 <unknown> + +fdot v31.4s, v31.8h, v31.2h[3] +// CHECK-INST: fdot v31.4s, v31.8h, v31.2h[3] +// CHECK-ENCODING: encoding: [0xff,0x9b,0x7f,0x4f] +// CHECK-ERROR: instruction requires: f16f32dot +// CHECK-UNKNOWN: 4f7f9bff <unknown> diff --git a/llvm/test/MC/AArch64/neon-fmmla-HtoS-diagnostics.s b/llvm/test/MC/AArch64/neon-fmmla-HtoS-diagnostics.s new file mode 100644 index 0000000..ccc0742 --- /dev/null +++ b/llvm/test/MC/AArch64/neon-fmmla-HtoS-diagnostics.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+f16f32mm 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand/vector + +fmmla v0.4b, v0.8b, v0.8b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmmla v0.4b, v0.8b, v0.8b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla v0.4h, v0.8h, v0.8h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmmla v0.4h, v0.8h, v0.8h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla v0.4s, v0.8s, v0.8s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: fmmla v0.4s, v0.8s, v0.8s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla v0.4d, v0.8d, v0.8d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: fmmla v0.4d, v0.8d, v0.8d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/neon-fmmla-HtoS.s b/llvm/test/MC/AArch64/neon-fmmla-HtoS.s new file mode 100644 index 0000000..6b3d352 --- /dev/null +++ b/llvm/test/MC/AArch64/neon-fmmla-HtoS.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16f32mm< %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16f32mm < %s \ +// RUN: | llvm-objdump -d --mattr=+f16f32mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16f32mm < %s \ +// RUN: | llvm-objdump -d --mattr=-f16f32mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16f32mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+f16f32mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +fmmla v0.4s, v0.8h, v0.8h +// CHECK-INST: fmmla v0.4s, v0.8h, v0.8h +// CHECK-ENCODING: encoding: [0x00,0xec,0x40,0x4e] +// CHECK-ERROR: instruction requires: f16f32mm +// CHECK-UNKNOWN: 4e40ec00 <unknown> + +fmmla v10.4s, v10.8h, v10.8h +// CHECK-INST: fmmla v10.4s, v10.8h, v10.8h +// CHECK-ENCODING: encoding: [0x4a,0xed,0x4a,0x4e] +// CHECK-ERROR: instruction requires: f16f32mm +// CHECK-UNKNOWN: 4e4aed4a <unknown> + +fmmla v21.4s, v21.8h, v21.8h +// CHECK-INST: fmmla v21.4s, v21.8h, v21.8h +// CHECK-ENCODING: encoding: [0xb5,0xee,0x55,0x4e] +// CHECK-ERROR: instruction requires: f16f32mm +// CHECK-UNKNOWN: 4e55eeb5 <unknown> + +fmmla v31.4s, v31.8h, v31.8h +// CHECK-INST: fmmla v31.4s, v31.8h, v31.8h +// CHECK-ENCODING: encoding: [0xff,0xef,0x5f,0x4e] +// CHECK-ERROR: instruction requires: f16f32mm +// CHECK-UNKNOWN: 4e5fefff <unknown> diff --git a/llvm/test/MC/AArch64/neon-fmmla-diagnostics.s b/llvm/test/MC/AArch64/neon-fmmla-diagnostics.s new file mode 100644 index 0000000..7fc5373 --- /dev/null +++ b/llvm/test/MC/AArch64/neon-fmmla-diagnostics.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+f16mm 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand/vector + +fmmla v0.8b, v0.8b, v0.8b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmmla v0.8b, v0.8b, v0.8b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla v0.8b, v0.8h, v0.8h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmmla v0.8b, v0.8h, v0.8h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla v0.8s, v0.8h, v0.8h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: fmmla v0.8s, v0.8h, v0.8h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla v0.8d, v0.8h, v0.8h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: fmmla v0.8d, v0.8h, v0.8h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/neon-fmmla.s b/llvm/test/MC/AArch64/neon-fmmla.s new file mode 100644 index 0000000..f35c2fb --- /dev/null +++ b/llvm/test/MC/AArch64/neon-fmmla.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16mm< %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16mm < %s \ +// RUN: | llvm-objdump -d --mattr=+f16mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16mm < %s \ +// RUN: | llvm-objdump -d --mattr=-f16mm --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+f16mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +fmmla v0.8h, v0.8h, v0.8h +// CHECK-INST: fmmla v0.8h, v0.8h, v0.8h +// CHECK-ENCODING: encoding: [0x00,0xec,0xc0,0x4e] +// CHECK-ERROR: instruction requires: f16mm +// CHECK-UNKNOWN: 4ec0ec00 <unknown> + +fmmla v10.8h, v10.8h, v10.8h +// CHECK-INST: fmmla v10.8h, v10.8h, v10.8h +// CHECK-ENCODING: encoding: [0x4a,0xed,0xca,0x4e] +// CHECK-ERROR: instruction requires: f16mm +// CHECK-UNKNOWN: 4ecaed4a <unknown> + +fmmla v21.8h, v21.8h, v21.8h +// CHECK-INST: fmmla v21.8h, v21.8h, v21.8h +// CHECK-ENCODING: encoding: [0xb5,0xee,0xd5,0x4e] +// CHECK-ERROR: instruction requires: f16mm +// CHECK-UNKNOWN: 4ed5eeb5 <unknown> + +fmmla v31.8h, v31.8h, v31.8h +// CHECK-INST: fmmla v31.8h, v31.8h, v31.8h +// CHECK-ENCODING: encoding: [0xff,0xef,0xdf,0x4e] +// CHECK-ERROR: instruction requires: f16mm +// CHECK-UNKNOWN: 4edfefff <unknown> diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s index 4f7ca47..358fe0b 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s @@ -45,6 +45,10 @@ s_set_vgpr_msb 255 // GFX1250: [0xff,0x00,0x86,0xbf] // GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +s_set_vgpr_msb 0xffff +// GFX1250: [0xff,0xff,0x86,0xbf] +// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU + s_monitor_sleep 1 // GFX1250: s_monitor_sleep 1 ; encoding: [0x01,0x00,0x84,0xbf] // GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/gfx1250_err.s b/llvm/test/MC/AMDGPU/gfx1250_err.s index 9d1131e..676eb48 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_err.s +++ b/llvm/test/MC/AMDGPU/gfx1250_err.s @@ -1,15 +1,5 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX1250-ERR --implicit-check-not=error: -strict-whitespace %s -s_set_vgpr_msb -1 -// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: s_set_vgpr_msb accepts values in range [0..255] -// GFX1250-ERR: s_set_vgpr_msb -1 -// GFX1250-ERR: ^ - -s_set_vgpr_msb 256 -// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: s_set_vgpr_msb accepts values in range [0..255] -// GFX1250-ERR: s_set_vgpr_msb 256 -// GFX1250-ERR: ^ - s_load_b32 s4, s[2:3], 10 th:TH_LOAD_NT th:TH_LOAD_NT // GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // GFX1250-ERR: s_load_b32 s4, s[2:3], 10 th:TH_LOAD_NT th:TH_LOAD_NT diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt index ad22000..16eba25 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt @@ -65,35 +65,39 @@ #CHECK: mrs x0, MPAMVPM7_EL2 #CHECK: mrs x0, MPAMIDR_EL1 -#CHECK-NOV84: msr S3_0_C10_C5_1, x0 -#CHECK-NOV84: msr S3_0_C10_C5_0, x0 -#CHECK-NOV84: msr S3_4_C10_C5_0, x0 -#CHECK-NOV84: msr S3_6_C10_C5_0, x0 -#CHECK-NOV84: msr S3_5_C10_C5_0, x0 -#CHECK-NOV84: msr S3_4_C10_C4_0, x0 -#CHECK-NOV84: msr S3_4_C10_C4_1, x0 -#CHECK-NOV84: msr S3_4_C10_C6_0, x0 -#CHECK-NOV84: msr S3_4_C10_C6_1, x0 -#CHECK-NOV84: msr S3_4_C10_C6_2, x0 -#CHECK-NOV84: msr S3_4_C10_C6_3, x0 -#CHECK-NOV84: msr S3_4_C10_C6_4, x0 -#CHECK-NOV84: msr S3_4_C10_C6_5, x0 -#CHECK-NOV84: msr S3_4_C10_C6_6, x0 -#CHECK-NOV84: msr S3_4_C10_C6_7, x0 -#CHECK-NOV84: mrs x0, S3_0_C10_C5_1 -#CHECK-NOV84: mrs x0, S3_0_C10_C5_0 -#CHECK-NOV84: mrs x0, S3_4_C10_C5_0 -#CHECK-NOV84: mrs x0, S3_6_C10_C5_0 -#CHECK-NOV84: mrs x0, S3_5_C10_C5_0 -#CHECK-NOV84: mrs x0, S3_4_C10_C4_0 -#CHECK-NOV84: mrs x0, S3_4_C10_C4_1 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_0 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_1 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_2 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_3 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_4 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_5 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_6 -#CHECK-NOV84: mrs x0, S3_4_C10_C6_7 -#CHECK-NOV84: mrs x0, S3_0_C10_C4_4 +// Available outside MPAM from Armv9.7 +#CHECK-NOV84: msr MPAM0_EL1, x0 +#CHECK-NOV84: msr MPAM1_EL1, x0 +#CHECK-NOV84: msr MPAM2_EL2, x0 +#CHECK-NOV84: msr MPAM3_EL3, x0 +#CHECK-NOV84: msr MPAM1_EL12, x0 +#CHECK-NOV84: msr MPAMHCR_EL2, x0 +#CHECK-NOV84: msr MPAMVPMV_EL2, x0 +#CHECK-NOV84: msr MPAMVPM0_EL2, x0 +#CHECK-NOV84: msr MPAMVPM1_EL2, x0 +#CHECK-NOV84: msr MPAMVPM2_EL2, x0 +#CHECK-NOV84: msr MPAMVPM3_EL2, x0 +#CHECK-NOV84: msr MPAMVPM4_EL2, x0 +#CHECK-NOV84: msr MPAMVPM5_EL2, x0 +#CHECK-NOV84: msr MPAMVPM6_EL2, x0 +#CHECK-NOV84: msr MPAMVPM7_EL2, x0 + +// Available outside MPAM from Armv9.7 +#CHECK-NOV84: mrs x0, MPAM0_EL1 +#CHECK-NOV84: mrs x0, MPAM1_EL1 +#CHECK-NOV84: mrs x0, MPAM2_EL2 +#CHECK-NOV84: mrs x0, MPAM3_EL3 +#CHECK-NOV84: mrs x0, MPAM1_EL12 +#CHECK-NOV84: mrs x0, MPAMHCR_EL2 + +#CHECK-NOV84: mrs x0, MPAMVPMV_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM0_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM1_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM2_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM3_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM4_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM5_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM6_EL2 +#CHECK-NOV84: mrs x0, MPAMVPM7_EL2 +#CHECK-NOV84: mrs x0, MPAMIDR_EL1 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt index a8627d6..b84324b 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt @@ -33,6 +33,9 @@ # GFX1250: s_set_vgpr_msb 0xff ; encoding: [0xff,0x00,0x86,0xbf] 0xff,0x00,0x86,0xbf +# GFX1250: s_set_vgpr_msb 0xffff ; encoding: [0xff,0xff,0x86,0xbf] +0xff,0xff,0x86,0xbf + # GFX1250: s_monitor_sleep 0 ; encoding: [0x00,0x00,0x84,0xbf] 0x00,0x00,0x84,0xbf diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll new file mode 100644 index 0000000..46b0ebd --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll @@ -0,0 +1,276 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 +; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF2IC1 %s +; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=VF2IC2 %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" +target triple = "arm64-apple-macosx" + +define void @load_store_interleave_group_block_invar_cond(ptr noalias %data, ptr noalias %dst.0, ptr noalias %dst.1, i1 %c) { +; VF2IC1-LABEL: define void @load_store_interleave_group_block_invar_cond( +; VF2IC1-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], i1 [[C:%.*]]) { +; VF2IC1-NEXT: [[ENTRY:.*:]] +; VF2IC1-NEXT: br label %[[VECTOR_PH:.*]] +; VF2IC1: [[VECTOR_PH]]: +; VF2IC1-NEXT: br label %[[VECTOR_BODY:.*]] +; VF2IC1: [[VECTOR_BODY]]: +; VF2IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE3:.*]] ] +; VF2IC1-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 +; VF2IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP0]] +; VF2IC1-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 +; VF2IC1-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> +; VF2IC1-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> +; VF2IC1-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; VF2IC1-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; VF2IC1-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8 +; VF2IC1-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] +; VF2IC1: [[PRED_STORE_IF]]: +; VF2IC1-NEXT: store i8 1, ptr [[DST_0]], align 1 +; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE]] +; VF2IC1: [[PRED_STORE_CONTINUE]]: +; VF2IC1-NEXT: br i1 [[C]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3]] +; VF2IC1: [[PRED_STORE_IF2]]: +; VF2IC1-NEXT: store i8 1, ptr [[DST_0]], align 1 +; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE3]] +; VF2IC1: [[PRED_STORE_CONTINUE3]]: +; VF2IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST_1]], i64 [[INDEX]] +; VF2IC1-NEXT: store <2 x i8> zeroinitializer, ptr [[TMP2]], align 1 +; VF2IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; VF2IC1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; VF2IC1-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; VF2IC1: [[MIDDLE_BLOCK]]: +; VF2IC1-NEXT: br label %[[EXIT:.*]] +; VF2IC1: [[EXIT]]: +; VF2IC1-NEXT: ret void +; +; VF2IC2-LABEL: define void @load_store_interleave_group_block_invar_cond( +; VF2IC2-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], i1 [[C:%.*]]) { +; VF2IC2-NEXT: [[ENTRY:.*:]] +; VF2IC2-NEXT: br label %[[VECTOR_PH:.*]] +; VF2IC2: [[VECTOR_PH]]: +; VF2IC2-NEXT: br label %[[VECTOR_BODY:.*]] +; VF2IC2: [[VECTOR_BODY]]: +; VF2IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE11:.*]] ] +; VF2IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 2 +; VF2IC2-NEXT: [[TMP1:%.*]] = shl nsw i64 [[INDEX]], 1 +; VF2IC2-NEXT: [[TMP2:%.*]] = shl nsw i64 [[TMP0]], 1 +; VF2IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP1]] +; VF2IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP2]] +; VF2IC2-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 +; VF2IC2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> +; VF2IC2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> +; VF2IC2-NEXT: [[WIDE_VEC2:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 +; VF2IC2-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> +; VF2IC2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> +; VF2IC2-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; VF2IC2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP8]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8 +; VF2IC2-NEXT: [[TMP9:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC3]], <2 x i64> [[STRIDED_VEC4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; VF2IC2-NEXT: [[INTERLEAVED_VEC5:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC5]], ptr [[TMP4]], align 8 +; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] +; VF2IC2: [[PRED_STORE_IF]]: +; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE]] +; VF2IC2: [[PRED_STORE_CONTINUE]]: +; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7:.*]] +; VF2IC2: [[PRED_STORE_IF6]]: +; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE7]] +; VF2IC2: [[PRED_STORE_CONTINUE7]]: +; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF8:.*]], label %[[PRED_STORE_CONTINUE9:.*]] +; VF2IC2: [[PRED_STORE_IF8]]: +; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE9]] +; VF2IC2: [[PRED_STORE_CONTINUE9]]: +; VF2IC2-NEXT: br i1 [[C]], label %[[PRED_STORE_IF10:.*]], label %[[PRED_STORE_CONTINUE11]] +; VF2IC2: [[PRED_STORE_IF10]]: +; VF2IC2-NEXT: store i8 1, ptr [[DST_0]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE11]] +; VF2IC2: [[PRED_STORE_CONTINUE11]]: +; VF2IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[DST_1]], i64 [[INDEX]] +; VF2IC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i32 2 +; VF2IC2-NEXT: store <2 x i8> zeroinitializer, ptr [[TMP5]], align 1 +; VF2IC2-NEXT: store <2 x i8> zeroinitializer, ptr [[TMP6]], align 1 +; VF2IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; VF2IC2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; VF2IC2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; VF2IC2: [[MIDDLE_BLOCK]]: +; VF2IC2-NEXT: br label %[[EXIT:.*]] +; VF2IC2: [[EXIT]]: +; VF2IC2-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] + %mul.2 = shl nsw i64 %iv, 1 + %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.2 + %l.0 = load i64, ptr %data.0, align 8 + store i64 %l.0, ptr %data.0, align 8 + %add.1 = or disjoint i64 %mul.2, 1 + %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.1 + %l.1 = load i64, ptr %data.1, align 8 + store i64 %l.1, ptr %data.1, align 8 + br i1 %c, label %then, label %loop.latch + +then: + store i8 1, ptr %dst.0 + br label %loop.latch + +loop.latch: + %gep.dst.1 = getelementptr inbounds i8, ptr %dst.1, i64 %iv + store i8 0, ptr %gep.dst.1 + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv.next, 100 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} + +define void @load_store_interleave_group_block_var_cond(ptr noalias %data, ptr %masks, ptr noalias %dst) { +; VF2IC1-LABEL: define void @load_store_interleave_group_block_var_cond( +; VF2IC1-SAME: ptr noalias [[DATA:%.*]], ptr [[MASKS:%.*]], ptr noalias [[DST:%.*]]) { +; VF2IC1-NEXT: [[ENTRY:.*:]] +; VF2IC1-NEXT: br label %[[VECTOR_PH:.*]] +; VF2IC1: [[VECTOR_PH]]: +; VF2IC1-NEXT: br label %[[VECTOR_BODY:.*]] +; VF2IC1: [[VECTOR_BODY]]: +; VF2IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE3:.*]] ] +; VF2IC1-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 +; VF2IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP0]] +; VF2IC1-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 +; VF2IC1-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> +; VF2IC1-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> +; VF2IC1-NEXT: [[TMP11:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; VF2IC1-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP11]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; VF2IC1-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8 +; VF2IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[INDEX]] +; VF2IC1-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 +; VF2IC1-NEXT: [[TMP3:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD1]], zeroinitializer +; VF2IC1-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0 +; VF2IC1-NEXT: br i1 [[TMP4]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] +; VF2IC1: [[PRED_STORE_IF]]: +; VF2IC1-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0 +; VF2IC1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP5]] +; VF2IC1-NEXT: store i8 1, ptr [[TMP6]], align 1 +; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE]] +; VF2IC1: [[PRED_STORE_CONTINUE]]: +; VF2IC1-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1 +; VF2IC1-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3]] +; VF2IC1: [[PRED_STORE_IF2]]: +; VF2IC1-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 +; VF2IC1-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP8]] +; VF2IC1-NEXT: store i8 1, ptr [[TMP9]], align 1 +; VF2IC1-NEXT: br label %[[PRED_STORE_CONTINUE3]] +; VF2IC1: [[PRED_STORE_CONTINUE3]]: +; VF2IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; VF2IC1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; VF2IC1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] +; VF2IC1: [[MIDDLE_BLOCK]]: +; VF2IC1-NEXT: br label %[[EXIT:.*]] +; VF2IC1: [[EXIT]]: +; VF2IC1-NEXT: ret void +; +; VF2IC2-LABEL: define void @load_store_interleave_group_block_var_cond( +; VF2IC2-SAME: ptr noalias [[DATA:%.*]], ptr [[MASKS:%.*]], ptr noalias [[DST:%.*]]) { +; VF2IC2-NEXT: [[ENTRY:.*:]] +; VF2IC2-NEXT: br label %[[VECTOR_PH:.*]] +; VF2IC2: [[VECTOR_PH]]: +; VF2IC2-NEXT: br label %[[VECTOR_BODY:.*]] +; VF2IC2: [[VECTOR_BODY]]: +; VF2IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE12:.*]] ] +; VF2IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 2 +; VF2IC2-NEXT: [[TMP1:%.*]] = shl nsw i64 [[INDEX]], 1 +; VF2IC2-NEXT: [[TMP2:%.*]] = shl nsw i64 [[TMP0]], 1 +; VF2IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP1]] +; VF2IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP2]] +; VF2IC2-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 +; VF2IC2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> +; VF2IC2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> +; VF2IC2-NEXT: [[WIDE_VEC2:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 +; VF2IC2-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> +; VF2IC2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> +; VF2IC2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; VF2IC2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8 +; VF2IC2-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC3]], <2 x i64> [[STRIDED_VEC4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; VF2IC2-NEXT: [[INTERLEAVED_VEC5:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; VF2IC2-NEXT: store <4 x i64> [[INTERLEAVED_VEC5]], ptr [[TMP4]], align 8 +; VF2IC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[INDEX]] +; VF2IC2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i32 2 +; VF2IC2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1 +; VF2IC2-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i8>, ptr [[TMP8]], align 1 +; VF2IC2-NEXT: [[TMP9:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD]], zeroinitializer +; VF2IC2-NEXT: [[TMP10:%.*]] = icmp eq <2 x i8> [[WIDE_LOAD6]], zeroinitializer +; VF2IC2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP9]], i32 0 +; VF2IC2-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] +; VF2IC2: [[PRED_STORE_IF]]: +; VF2IC2-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 0 +; VF2IC2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP12]] +; VF2IC2-NEXT: store i8 1, ptr [[TMP13]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE]] +; VF2IC2: [[PRED_STORE_CONTINUE]]: +; VF2IC2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP9]], i32 1 +; VF2IC2-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]] +; VF2IC2: [[PRED_STORE_IF7]]: +; VF2IC2-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 1 +; VF2IC2-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP15]] +; VF2IC2-NEXT: store i8 1, ptr [[TMP16]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE8]] +; VF2IC2: [[PRED_STORE_CONTINUE8]]: +; VF2IC2-NEXT: [[TMP17:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0 +; VF2IC2-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]] +; VF2IC2: [[PRED_STORE_IF9]]: +; VF2IC2-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 2 +; VF2IC2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP18]] +; VF2IC2-NEXT: store i8 1, ptr [[TMP19]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE10]] +; VF2IC2: [[PRED_STORE_CONTINUE10]]: +; VF2IC2-NEXT: [[TMP20:%.*]] = extractelement <2 x i1> [[TMP10]], i32 1 +; VF2IC2-NEXT: br i1 [[TMP20]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12]] +; VF2IC2: [[PRED_STORE_IF11]]: +; VF2IC2-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 3 +; VF2IC2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[MASKS]], i64 [[TMP21]] +; VF2IC2-NEXT: store i8 1, ptr [[TMP22]], align 1 +; VF2IC2-NEXT: br label %[[PRED_STORE_CONTINUE12]] +; VF2IC2: [[PRED_STORE_CONTINUE12]]: +; VF2IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; VF2IC2-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; VF2IC2-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] +; VF2IC2: [[MIDDLE_BLOCK]]: +; VF2IC2-NEXT: br label %[[EXIT:.*]] +; VF2IC2: [[EXIT]]: +; VF2IC2-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] + %mul.2 = shl nsw i64 %iv, 1 + %data.0 = getelementptr inbounds i64, ptr %data, i64 %mul.2 + %l.0 = load i64, ptr %data.0, align 8 + store i64 %l.0, ptr %data.0, align 8 + %add.1 = or disjoint i64 %mul.2, 1 + %data.1 = getelementptr inbounds i64, ptr %data, i64 %add.1 + %l.1 = load i64, ptr %data.1, align 8 + store i64 %l.1, ptr %data.1, align 8 + %gep.mask = getelementptr inbounds i8, ptr %masks, i64 %iv + %l.mask = load i8, ptr %gep.mask + %c = icmp eq i8 %l.mask, 0 + br i1 %c, label %then, label %loop.latch + +then: + store i8 1, ptr %gep.mask + br label %loop.latch + +loop.latch: + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv.next, 100 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} |