diff options
Diffstat (limited to 'llvm/test')
126 files changed, 23209 insertions, 5473 deletions
diff --git a/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll b/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll index e8e7cb1..b6b44ad 100644 --- a/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll +++ b/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5 ; RUN: opt < %s -disable-output "-passes=print<da>" -aa-pipeline=basic-aa 2>&1 \ ; RUN: | FileCheck %s -; RUN: opt < %s -disable-output "-passes=print<da>" -da-run-siv-routines-only 2>&1 \ -; RUN: | FileCheck %s --check-prefix=CHECK-SIV-ONLY target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.6.0" @@ -27,20 +25,6 @@ define void @exact0(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact0' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [<=|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -85,20 +69,6 @@ define void @exact1(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact1' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -144,20 +114,6 @@ define void @exact2(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact2' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -201,20 +157,6 @@ define void @exact3(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact3' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [>]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -258,20 +200,6 @@ define void @exact4(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact4' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [>]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -315,20 +243,6 @@ define void @exact5(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact5' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [=>|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -372,20 +286,6 @@ define void @exact6(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact6' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [=>|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -429,20 +329,6 @@ define void @exact7(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact7' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [*|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -486,20 +372,6 @@ define void @exact8(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact8' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -543,20 +415,6 @@ define void @exact9(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact9' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [>]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -600,20 +458,6 @@ define void @exact10(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact10' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [>]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -657,20 +501,6 @@ define void @exact11(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact11' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [=>|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -714,20 +544,6 @@ define void @exact12(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact12' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [=>|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -771,20 +587,6 @@ define void @exact13(ptr %A, ptr %B) nounwind uwtable ssp { ; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 ; CHECK-NEXT: da analyze - none! ; -; CHECK-SIV-ONLY-LABEL: 'exact13' -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - flow [*|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - confused! -; CHECK-SIV-ONLY-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; entry: br label %for.body @@ -807,123 +609,3 @@ for.body: ; preds = %entry, %for.body for.end: ; preds = %for.body ret void } - -;; max_i = INT64_MAX/6 // 1537228672809129301 -;; for (long long i = 0; i <= max_i; i++) { -;; A[-6*i + INT64_MAX] = 0; -;; if (i) -;; A[3*i - 2] = 1; -;; } -;; -;; FIXME: DependencyAnalsysis currently detects no dependency between -;; `A[-6*i + INT64_MAX]` and `A[3*i - 2]`, but it does exist. For example, -;; -;; | memory location | -6*i + INT64_MAX | 3*i - 2 -;; |------------------------|------------------------|----------- -;; | A[1] | i = max_i | i = 1 -;; | A[4611686018427387901] | i = 768614336404564651 | i = max_i -;; -;; Actually, -;; * 1 = -6*max_i + INT64_MAX = 3*1 - 2 -;; * 4611686018427387901 = -6*768614336404564651 + INT64_MAX = 3*max_i - 2 -;; - -define void @exact14(ptr %A) { -; CHECK-LABEL: 'exact14' -; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 -; CHECK-NEXT: da analyze - none! -; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-NEXT: da analyze - none! -; CHECK-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-NEXT: da analyze - none! -; -; CHECK-SIV-ONLY-LABEL: 'exact14' -; CHECK-SIV-ONLY-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-SIV-ONLY-NEXT: da analyze - output [*|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; -entry: - br label %loop.header - -loop.header: - %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.latch ] - %subscript.0 = phi i64 [ 9223372036854775807, %entry ], [ %subscript.0.next, %loop.latch ] - %subscript.1 = phi i64 [ -2, %entry ], [ %subscript.1.next, %loop.latch ] - %idx.0 = getelementptr inbounds i8, ptr %A, i64 %subscript.0 - store i8 0, ptr %idx.0 - %cond.store = icmp ne i64 %i, 0 - br i1 %cond.store, label %if.store, label %loop.latch - -if.store: - %idx.1 = getelementptr inbounds i8, ptr %A, i64 %subscript.1 - store i8 1, ptr %idx.1 - br label %loop.latch - -loop.latch: - %i.inc = add nuw nsw i64 %i, 1 - %subscript.0.next = add nsw i64 %subscript.0, -6 - %subscript.1.next = add nsw i64 %subscript.1, 3 - %exitcond = icmp sgt i64 %i.inc, 1537228672809129301 - br i1 %exitcond, label %exit, label %loop.header - -exit: - ret void -} - -;; A generalized version of @exact14. -;; -;; for (long long i = 0; i <= n / 6; i++) { -;; A[-6*i + n] = 0; -;; if (i) -;; A[3*i - 2] = 1; -;; } - -define void @exact15(ptr %A, i64 %n) { -; CHECK-LABEL: 'exact15' -; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 -; CHECK-NEXT: da analyze - none! -; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-NEXT: da analyze - output [*|<]! -; CHECK-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-NEXT: da analyze - none! -; -; CHECK-SIV-ONLY-LABEL: 'exact15' -; CHECK-SIV-ONLY-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; CHECK-SIV-ONLY-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-SIV-ONLY-NEXT: da analyze - output [*|<]! -; CHECK-SIV-ONLY-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 -; CHECK-SIV-ONLY-NEXT: da analyze - none! -; -entry: - %bound = sdiv i64 %n, 6 - %guard = icmp sgt i64 %n, 0 - br i1 %guard, label %loop.header, label %exit - -loop.header: - %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.latch ] - %subscript.0 = phi i64 [ %n, %entry ], [ %subscript.0.next, %loop.latch ] - %subscript.1 = phi i64 [ -2, %entry ], [ %subscript.1.next, %loop.latch ] - %idx.0 = getelementptr inbounds i8, ptr %A, i64 %subscript.0 - store i8 0, ptr %idx.0 - %cond.store = icmp ne i64 %i, 0 - br i1 %cond.store, label %if.store, label %loop.latch - -if.store: - %idx.1 = getelementptr inbounds i8, ptr %A, i64 %subscript.1 - store i8 1, ptr %idx.1 - br label %loop.latch - -loop.latch: - %i.inc = add nuw nsw i64 %i, 1 - %subscript.0.next = add nsw i64 %subscript.0, -6 - %subscript.1.next = add nsw i64 %subscript.1, 3 - %exitcond = icmp sgt i64 %i.inc, %bound - br i1 %exitcond, label %exit, label %loop.header - -exit: - ret void -} diff --git a/llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll b/llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll new file mode 100644 index 0000000..59e2ed3 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll @@ -0,0 +1,124 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output "-passes=print<da>" 2>&1 | FileCheck %s +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=exact-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-EXACT-SIV + +;; max_i = INT64_MAX/6 // 1537228672809129301 +;; for (long long i = 0; i <= max_i; i++) { +;; A[-6*i + INT64_MAX] = 0; +;; if (i) +;; A[3*i - 2] = 1; +;; } +;; +;; FIXME: DependencyAnalsysis currently detects no dependency between +;; `A[-6*i + INT64_MAX]` and `A[3*i - 2]`, but it does exist. For example, +;; +;; | memory location | -6*i + INT64_MAX | 3*i - 2 +;; |------------------------|------------------------|----------- +;; | A[1] | i = max_i | i = 1 +;; | A[4611686018427387901] | i = 768614336404564651 | i = max_i +;; +;; Actually, +;; * 1 = -6*max_i + INT64_MAX = 3*1 - 2 +;; * 4611686018427387901 = -6*768614336404564651 + INT64_MAX = 3*max_i - 2 +;; + +define void @exactsiv_const_ovfl(ptr %A) { +; CHECK-LABEL: 'exactsiv_const_ovfl' +; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 +; CHECK-NEXT: da analyze - none! +; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-NEXT: da analyze - none! +; CHECK-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-NEXT: da analyze - none! +; +; CHECK-EXACT-SIV-LABEL: 'exactsiv_const_ovfl' +; CHECK-EXACT-SIV-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [*|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop.header + +loop.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.latch ] + %subscript.0 = phi i64 [ 9223372036854775807, %entry ], [ %subscript.0.next, %loop.latch ] + %subscript.1 = phi i64 [ -2, %entry ], [ %subscript.1.next, %loop.latch ] + %idx.0 = getelementptr inbounds i8, ptr %A, i64 %subscript.0 + store i8 0, ptr %idx.0 + %cond.store = icmp ne i64 %i, 0 + br i1 %cond.store, label %if.store, label %loop.latch + +if.store: + %idx.1 = getelementptr inbounds i8, ptr %A, i64 %subscript.1 + store i8 1, ptr %idx.1 + br label %loop.latch + +loop.latch: + %i.inc = add nuw nsw i64 %i, 1 + %subscript.0.next = add nsw i64 %subscript.0, -6 + %subscript.1.next = add nsw i64 %subscript.1, 3 + %exitcond = icmp sgt i64 %i.inc, 1537228672809129301 + br i1 %exitcond, label %exit, label %loop.header + +exit: + ret void +} + +;; A generalized version of the above case. +;; +;; for (long long i = 0; i <= n / 6; i++) { +;; A[-6*i + n] = 0; +;; if (i) +;; A[3*i - 2] = 1; +;; } + +define void @exactsiv_param_ovfl(ptr %A, i64 %n) { +; CHECK-LABEL: 'exactsiv_param_ovfl' +; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 +; CHECK-NEXT: da analyze - none! +; CHECK-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-NEXT: da analyze - output [*|<]! +; CHECK-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-NEXT: da analyze - none! +; +; CHECK-EXACT-SIV-LABEL: 'exactsiv_param_ovfl' +; CHECK-EXACT-SIV-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [*|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +entry: + %bound = sdiv i64 %n, 6 + %guard = icmp sgt i64 %n, 0 + br i1 %guard, label %loop.header, label %exit + +loop.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.latch ] + %subscript.0 = phi i64 [ %n, %entry ], [ %subscript.0.next, %loop.latch ] + %subscript.1 = phi i64 [ -2, %entry ], [ %subscript.1.next, %loop.latch ] + %idx.0 = getelementptr inbounds i8, ptr %A, i64 %subscript.0 + store i8 0, ptr %idx.0 + %cond.store = icmp ne i64 %i, 0 + br i1 %cond.store, label %if.store, label %loop.latch + +if.store: + %idx.1 = getelementptr inbounds i8, ptr %A, i64 %subscript.1 + store i8 1, ptr %idx.1 + br label %loop.latch + +loop.latch: + %i.inc = add nuw nsw i64 %i, 1 + %subscript.0.next = add nsw i64 %subscript.0, -6 + %subscript.1.next = add nsw i64 %subscript.1, 3 + %exitcond = icmp sgt i64 %i.inc, %bound + br i1 %exitcond, label %exit, label %loop.header + +exit: + ret void +} diff --git a/llvm/test/Analysis/DependenceAnalysis/monotonicity-cast.ll b/llvm/test/Analysis/DependenceAnalysis/monotonicity-cast.ll new file mode 100644 index 0000000..e43d00d --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/monotonicity-cast.ll @@ -0,0 +1,207 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output -passes="print<da>" -da-dump-monotonicity-report \ +; RUN: -da-enable-monotonicity-check 2>&1 | FileCheck %s + +; int8_t offset = start; +; for (int i = 0; i < 100; i++, offset += step) +; a[sext(offset)] = 0; +; +define void @sext_nsw(ptr %a, i8 %start, i8 %step) { +; CHECK-LABEL: 'sext_nsw' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {(sext i8 %start to i64),+,(sext i8 %step to i64)}<nsw><%loop> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - none! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %offset = phi i8 [ %start, %entry ], [ %offset.next, %loop ] + %offset.sext = sext i8 %offset to i64 + %idx = getelementptr i8, ptr %a, i64 %offset.sext + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %offset.next = add nsw i8 %offset, %step + %exitcond = icmp eq i64 %i.inc, 100 + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; The addition for `%offset.next` can wrap, so we cannot prove monotonicity. +; +; int8_t offset = start; +; for (int i = 0; i < 100; i++, offset += step) +; a[sext(offset)] = 0; +; +define void @sext_may_wrap(ptr %a, i8 %start, i8 %step) { +; CHECK-LABEL: 'sext_may_wrap' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: (sext i8 {%start,+,%step}<%loop> to i64) +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: (sext i8 {%start,+,%step}<%loop> to i64) +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %offset = phi i8 [ %start, %entry ], [ %offset.next, %loop ] + %offset.sext = sext i8 %offset to i64 + %idx = getelementptr i8, ptr %a, i64 %offset.sext + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %offset.next = add i8 %offset, %step + %exitcond = icmp eq i64 %i.inc, 100 + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; for (int8_t i = 0; i < 100; i++) +; a[zext(offset)] = 0; +; +define void @zext_pos(ptr %a) { +; CHECK-LABEL: 'zext_pos' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {0,+,1}<nuw><nsw><%loop> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - none! +; +entry: + br label %loop + +loop: + %i = phi i8 [ 0, %entry ], [ %i.inc, %loop ] + %offset.zext = zext nneg i8 %i to i64 + %idx = getelementptr i8, ptr %a, i64 %offset.zext + store i8 0, ptr %idx + %i.inc = add nsw i8 %i, 1 + %exitcond = icmp eq i8 %i.inc, 100 + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; The zero-extened value of `offset` is no longer monotonic. In fact, the +; values of `offset` in each iteration are: +; +; iteration | 0 | 1 | 2 | ... +; -------------|-----|---|---|--------- +; offset | -1 | 0 | 1 | ... +; zext(offset) | 255 | 0 | 1 | ... +; +; +; for (int8_t i = -1; i < 100; i++) +; a[zext(offset)] = 0; +; +define void @zext_cross_zero(ptr %a) { +; CHECK-LABEL: 'zext_cross_zero' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: (zext i8 {-1,+,1}<nsw><%loop> to i64) +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: (zext i8 {-1,+,1}<nsw><%loop> to i64) +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop + +loop: + %i = phi i8 [ -1, %entry ], [ %i.inc, %loop ] + %offset.zext = zext nneg i8 %i to i64 + %idx = getelementptr i8, ptr %a, i64 %offset.zext + store i8 0, ptr %idx + %i.inc = add nsw i8 %i, 1 + %exitcond = icmp eq i8 %i.inc, 100 + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; In principle, we can prove that `zext(offset)` is monotonic since we know +; that `offset` is non-negative. +; +; int8_t offset = 0; +; for (int i = 0; i < 100; i++, offset += step) +; a[zext(offset)] = 0; +; +define void @zext_nneg_nsw(ptr %a, i8 %step) { +; CHECK-LABEL: 'zext_nneg_nsw' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: (zext i8 {0,+,%step}<nsw><%loop> to i64) +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: (zext i8 {0,+,%step}<nsw><%loop> to i64) +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %offset = phi i8 [ 0, %entry ], [ %offset.next, %loop ] + %offset.zext = zext nneg i8 %offset to i64 + %idx = getelementptr i8, ptr %a, i64 %offset.zext + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %offset.next = add nsw i8 %offset, %step + %exitcond = icmp eq i64 %i.inc, 100 + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; SCEV handles `i & 1` as an i1 addrec. Ensure that the monotonicity analysis +; properly analyzes it. +; +; for (i = 0; i < 100; i++) +; a[i & 1] = 0; +; +define void @offset_truncated_to_i1(ptr %a) { +; CHECK-LABEL: 'offset_truncated_to_i1' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: (zext i1 {false,+,true}<%loop> to i64) +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: (zext i1 {false,+,true}<%loop> to i64) +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %and = and i64 %i, 1 + %idx = getelementptr inbounds i8, ptr %a, i64 %and + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.inc, 100 + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/Analysis/DependenceAnalysis/monotonicity-delinearize.ll b/llvm/test/Analysis/DependenceAnalysis/monotonicity-delinearize.ll new file mode 100644 index 0000000..71ea4e9 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/monotonicity-delinearize.ll @@ -0,0 +1,59 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output -passes="print<da>" -da-dump-monotonicity-report \ +; RUN: -da-enable-monotonicity-check 2>&1 | FileCheck %s + +; The offset SCEV will be delinearized into a 2D array access, like as follows: +; +; - Outer subscript: {0,+,1}<nuw><nsw><%loop.i.header> +; - Inner subscript: {0,+,1}<nuw><nsw><%loop.j.header> +; +; These subscripts are both monotonic, but we also need to check the +; monotonicity of the original addrec. +; +; char A[...][32]; +; for (i = 0; i < 1ll << 62; i++) +; for (j = 0; j < 32; j++) +; if (i < (1ll << 57)) +; A[i][j] = 0; +; +define void @linearized_offset_wrap(ptr %a) { +; CHECK-LABEL: 'linearized_offset_wrap' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %gep, align 1 +; CHECK-NEXT: Expr: {{\{\{}}0,+,32}<%loop.i.header>,+,1}<nw><%loop.j.header> +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: {{\{\{}}0,+,32}<%loop.i.header>,+,1}<nw><%loop.j.header> +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop.i.header + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.header + +loop.j.header: + %j = phi i64 [ 0, %loop.i.header ], [ %j.inc, %loop.j.latch ] + %cond = icmp slt i64 %i, 144115188075855872 ; 2^57 + br i1 %cond, label %if.then, label %loop.j.latch + +if.then: + %gep = getelementptr inbounds [32 x i8], ptr %a, i64 %i, i64 %j + store i8 0, ptr %gep + br label %loop.j.latch + +loop.j.latch: + %j.inc = add nuw nsw i64 %j, 1 + %ec.j = icmp eq i64 %j.inc, 32 + br i1 %ec.j, label %loop.i.latch, label %loop.j.header + +loop.i.latch: + %i.inc = add nuw nsw i64 %i, 1 + %ec.i = icmp eq i64 %i.inc, 4611686018427387904 ; 2^62 + br i1 %ec.i, label %exit, label %loop.i.header + +exit: + ret void +} diff --git a/llvm/test/Analysis/DependenceAnalysis/monotonicity-invariant.ll b/llvm/test/Analysis/DependenceAnalysis/monotonicity-invariant.ll new file mode 100644 index 0000000..e5b6ddb --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/monotonicity-invariant.ll @@ -0,0 +1,150 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output -passes="print<da>" -da-dump-monotonicity-report \ +; RUN: -da-enable-monotonicity-check 2>&1 | FileCheck %s + +; for (int i = 0; i < n; i++) +; a[x] = 0; +define void @single_loop_invariant(ptr %a, i64 %x, i64 %n) { +; CHECK-LABEL: 'single_loop_invariant' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: %x +; CHECK-NEXT: Monotonicity: Invariant +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - consistent output [S]! +; +entry: + %guard = icmp sgt i64 %n, 0 + br i1 %guard, label %loop, label %exit + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %idx = getelementptr inbounds i8, ptr %a, i64 %x + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.inc, %n + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; for (int i = 0; i < n; i++) +; a[(i % 2 == 0 ? x : y)] = 0; +define void @single_loop_variant(ptr %a, i64 %x, i64 %y, i64 %n) { +; CHECK-LABEL: 'single_loop_variant' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: %offset +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: %offset +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + %guard = icmp sgt i64 %n, 0 + br i1 %guard, label %loop, label %exit + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %offset = phi i64 [ %x, %entry ], [ %offset.next, %loop ] + %offset.next = phi i64 [ %y, %entry ], [ %offset, %loop ] + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.inc, %n + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; for (int i = 0; i < n; i++) +; for (int j = 0; j < m; j++) +; a[x + i] = 0; +define void @invariant_plus_monotonic0(ptr %a, i64 %x, i64 %n, i64 %m) { +; CHECK-LABEL: 'invariant_plus_monotonic0' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {%x,+,1}<nsw><%loop.i.header> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - consistent output [0 S]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + %offset = phi i64 [ %x, %entry ], [ %offset.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j ] + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nuw nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %offset.inc = add nsw i64 %offset, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; for (int i = 0; i < n; i++) +; for (int j = 0; j < m; j++) +; a[x + j] = 0; +define void @invariant_plus_monotonic1(ptr %a, i64 %x, i64 %n, i64 %m) { +; CHECK-LABEL: 'invariant_plus_monotonic1' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {%x,+,1}<nsw><%loop.j> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - consistent output [S 0]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j ] + %offset = phi i64 [ %x, %loop.j.preheader ], [ %offset.inc, %loop.j ] + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nuw nsw i64 %j, 1 + %offset.inc = add nsw i64 %offset, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} diff --git a/llvm/test/Analysis/DependenceAnalysis/monotonicity-no-wrap-flags.ll b/llvm/test/Analysis/DependenceAnalysis/monotonicity-no-wrap-flags.ll new file mode 100644 index 0000000..7411dc9 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/monotonicity-no-wrap-flags.ll @@ -0,0 +1,519 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output -passes="print<da>" -da-dump-monotonicity-report \ +; RUN: -da-enable-monotonicity-check 2>&1 | FileCheck %s + +; for (int i = 0; i < n; i++) +; a[i] = 0; +; +define void @single_loop_nsw(ptr %a, i64 %n) { +; CHECK-LABEL: 'single_loop_nsw' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {0,+,1}<nuw><nsw><%loop> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - none! +; +entry: + %guard = icmp sgt i64 %n, 0 + br i1 %guard, label %loop, label %exit + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %idx = getelementptr inbounds i8, ptr %a, i64 %i + store i8 0, ptr %idx + %i.inc = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.inc, %n + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; The purpose of the variable `begin` is to avoid violating the size limitation +; of the allocated object in LLVM IR, which would cause UB. +; +; for (unsigned long long i = begin; i < end; i++) +; a[i] = 0; +; +define void @single_loop_nuw(ptr %a, i64 %begin, i64 %end) { +; CHECK-LABEL: 'single_loop_nuw' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {%begin,+,1}<nuw><%loop> +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: {%begin,+,1}<nuw><%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + %guard = icmp ult i64 %begin, %end + br i1 %guard, label %loop, label %exit + +loop: + %i = phi i64 [ %begin, %entry ], [ %i.inc, %loop ] + %idx = getelementptr i8, ptr %a, i64 %i + store i8 0, ptr %idx + %i.inc = add nuw i64 %i, 1 + %exitcond = icmp eq i64 %i.inc, %end + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +; for (int i = 0; i < n; i++) +; for (int j = 0; j < m; j++) +; a[i + j] = 0; +; +define void @nested_loop_nsw0(ptr %a, i64 %n, i64 %m) { +; CHECK-LABEL: 'nested_loop_nsw0' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}0,+,1}<nuw><nsw><%loop.i.header>,+,1}<nuw><nsw><%loop.j> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - output [* *]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j ] + %offset = add nsw i64 %i, %j + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; for (int i = n - 1; i >= 0; i--) +; for (int j = 0; j < m; j++) +; a[i + j] = 0; +; +define void @nested_loop_nsw1(ptr %a, i64 %n, i64 %m) { +; CHECK-LABEL: 'nested_loop_nsw1' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}(-1 + %n),+,-1}<nsw><%loop.i.header>,+,1}<nsw><%loop.j> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - output [* *]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ %n, %entry ], [ %i.dec, %loop.i.latch ] + %i.dec = add nsw i64 %i, -1 + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j ] + %offset = add nsw i64 %i.dec, %j + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %exitcond.i = icmp eq i64 %i.dec, 0 + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; for (int i = 0; i < n; i--) +; for (int j = 0; j < m; j++) +; a[i - j] = 0; +; +define void @nested_loop_nsw2(ptr %a, i64 %n, i64 %m) { +; CHECK-LABEL: 'nested_loop_nsw2' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}0,+,1}<nuw><nsw><%loop.i.header>,+,-1}<nsw><%loop.j> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - output [* *]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j ] + %offset = sub nsw i64 %i, %j + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; for (int i = begin0; i < end0; i++) +; for (int j = begin1; j < end1; j++) { +; unsigned long long offset = (unsigned long long)i + (unsigned long long)j; +; a[offset] = 0; +; } +; +define void @nested_loop_nuw(ptr %a, i64 %begin0, i64 %end0, i64 %begin1, i64 %end1) { +; CHECK-LABEL: 'nested_loop_nuw' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}(%begin0 + %begin1),+,1}<nw><%loop.i.header>,+,1}<nw><%loop.j> +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: {{\{\{}}(%begin0 + %begin1),+,1}<nw><%loop.i.header>,+,1}<nw><%loop.j> +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + %guard.i.0 = icmp slt i64 0, %begin0 + %guard.i.1 = icmp slt i64 %begin0, %end0 + %guard.i.2 = icmp slt i64 0, %end0 + %and.i.0 = and i1 %guard.i.0, %guard.i.1 + %and.i.1 = and i1 %and.i.0, %guard.i.2 + br i1 %and.i.1, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ %begin0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %guard.j.0 = icmp slt i64 0, %begin1 + %guard.j.1 = icmp slt i64 %begin1, %end1 + %guard.j.2 = icmp slt i64 0, %end1 + %and.j.0 = and i1 %guard.j.0, %guard.j.1 + %and.j.1 = and i1 %and.j.0, %guard.j.2 + br i1 %and.j.1, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ %begin1, %loop.j.preheader ], [ %j.inc, %loop.j ] + %offset = add nuw i64 %i, %j + %idx = getelementptr i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, %end1 + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %end0 + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; for (int i = 0; i < n; i++) +; for (int j = 0; j < m; j++) +; a[i + step*j] = 0; +; +define void @nested_loop_step(ptr %a, i64 %n, i64 %m, i64 %step) { +; CHECK-LABEL: 'nested_loop_step' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}0,+,1}<nuw><nsw><%loop.i.header>,+,%step}<nsw><%loop.j> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - output [* *]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j, label %loop.i.latch + +loop.j: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j ] + %offset.j = phi i64 [ 0, %loop.j.preheader ], [ %offset.j.next, %loop.j ] + %offset = add nsw i64 %i, %offset.j + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nsw i64 %j, 1 + %offset.j.next = add nsw i64 %offset.j, %step + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; The value of step reccurence is not invariant with respect to the outer most +; loop (the i-loop). +; +; offset_i = 0; +; for (int i = 0; i < 100; i++) { +; for (int j = 0; j < 100; j++) +; a[offset_i + j] = 0; +; offset_i += (i % 2 == 0) ? 0 : 3; +; } +; +define void @step_is_variant(ptr %a) { +; CHECK-LABEL: 'step_is_variant' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {%offset.i,+,1}<nuw><nsw><%loop.j> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop.i.header + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + %offset.i = phi i64 [ 0, %entry ], [ %offset.i.next, %loop.i.latch ] + %step.i.0 = phi i64 [ 0, %entry ], [ %step.i.1, %loop.i.latch ] + %step.i.1 = phi i64 [ 3, %entry ], [ %step.i.0, %loop.i.latch ] + br label %loop.j + +loop.j: + %j = phi i64 [ 0, %loop.i.header ], [ %j.inc, %loop.j ] + %offset = add nsw i64 %offset.i, %j + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + %j.inc = add nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, 100 + br i1 %exitcond.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %offset.i.next = add nsw i64 %offset.i, %step.i.0 + %exitcond.i = icmp eq i64 %i.inc, 100 + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; The AddRec doesn't have nsw flag for the j-loop, since the store may not be +; executed. +; +; for (int i = 0; i < n; i++) +; for (int j = 0; j < m; j++) +; if (cond) +; a[i + j] = 0; +; +define void @conditional_store0(ptr %a, i64 %n, i64 %m) { +; CHECK-LABEL: 'conditional_store0' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}0,+,1}<nuw><nsw><%loop.i.header>,+,1}<nw><%loop.j.header> +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: {{\{\{}}0,+,1}<nuw><nsw><%loop.i.header>,+,1}<nw><%loop.j.header> +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j.header, label %loop.i.latch + +loop.j.header: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j.latch ] + %offset = add nsw i64 %i, %j + %cond = freeze i1 poison + br i1 %cond, label %if.then, label %loop.j.latch + +if.then: + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + br label %loop.j.latch + +loop.j.latch: + %j.inc = add nsw i64 %j, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j.header + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; Similar to the @conditional_store0, but the definition of the `%offset` is +; different from it and we can infer `nsw` in this case. +; +; for (int i = 0; i < n; i++) +; for (int j = 0; j < m; j++) +; if (cond) +; a[i + j] = 0; +; +define void @conditional_store1(ptr %a, i64 %n, i64 %m) { +; CHECK-LABEL: 'conditional_store1' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: Expr: {{\{\{}}0,+,1}<nuw><nsw><%loop.i.header>,+,1}<nuw><nsw><%loop.j.header> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %idx, align 1 --> Dst: store i8 0, ptr %idx, align 1 +; CHECK-NEXT: da analyze - output [* *]! +; +entry: + %guard.i = icmp sgt i64 %n, 0 + br i1 %guard.i, label %loop.i.header, label %exit + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j.preheader + +loop.j.preheader: + %gurard.j = icmp sgt i64 %m, 0 + br i1 %gurard.j, label %loop.j.header, label %loop.i.latch + +loop.j.header: + %j = phi i64 [ 0, %loop.j.preheader ], [ %j.inc, %loop.j.latch ] + %offset = phi i64 [ %i, %loop.j.preheader ], [ %offset.next, %loop.j.latch ] + %cond = freeze i1 poison + br i1 %cond, label %if.then, label %loop.j.latch + +if.then: + %idx = getelementptr inbounds i8, ptr %a, i64 %offset + store i8 0, ptr %idx + br label %loop.j.latch + +loop.j.latch: + %j.inc = add nsw i64 %j, 1 + %offset.next = add nsw i64 %offset, 1 + %exitcond.j = icmp eq i64 %j.inc, %m + br i1 %exitcond.j, label %loop.i.latch, label %loop.j.header + +loop.i.latch: + %i.inc = add nsw i64 %i, 1 + %exitcond.i = icmp eq i64 %i.inc, %n + br i1 %exitcond.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; In the following case, the computation `offset = offset_i + j` will not wrap, +; but `offset_i += 1024` will wrap both in a signed sense and an unsigned +; sense. We cannot prove the monotonicity in this case. +; +; offset_i = (1ULL << 63) - 256; +; for (i = 0; i < (1ULL << 62); i++, offset_i += 1024) +; for (j = 0; j < 32; j++) { +; offset = offset_i + j; +; +; // The value of `offset` is positive in a signed sense. +; if (offset < (1ULL << 63)) +; a[offset] = 0; +; } +; +define void @outer_loop_may_wrap(ptr %a) { +; CHECK-LABEL: 'outer_loop_may_wrap' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 0, ptr %gep, align 1 +; CHECK-NEXT: Expr: {{\{\{}}9223372036854775552,+,1024}<%loop.i.header>,+,1}<nuw><nsw><%loop.j.header> +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: {9223372036854775552,+,1024}<%loop.i.header> +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-NEXT: da analyze - confused! +; +entry: + br label %loop.i.header + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + %subscript.i = phi i64 [ 9223372036854775552, %entry ], [ %subscript.i.next, %loop.i.latch ] ; The initial value is 2^63 - 256 + br label %loop.j.header + +loop.j.header: + %j = phi i64 [ 0, %loop.i.header ], [ %j.inc, %loop.j.latch ] + %subscript = phi i64 [ %subscript.i, %loop.i.header ], [ %subscript.next, %loop.j.latch ] + %cond = icmp sge i64 %subscript, 0 + br i1 %cond, label %if.then, label %loop.j.latch + +if.then: + %gep = getelementptr inbounds i8, ptr %a, i64 %subscript + store i8 0, ptr %gep + br label %loop.j.latch + +loop.j.latch: + %j.inc = add nuw nsw i64 %j, 1 + %subscript.next = add nuw nsw i64 %subscript, 1 + %ec.j = icmp eq i64 %j.inc, 32 + br i1 %ec.j, label %loop.i.latch, label %loop.j.header + +loop.i.latch: + %i.inc = add nuw nsw i64 %i, 1 + %subscript.i.next = add i64 %subscript.i, 1024 + %ec.i = icmp eq i64 %i.inc, 4611686018427387904 ; 2^62 + br i1 %ec.i, label %exit, label %loop.i.header + +exit: + ret void +} diff --git a/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll b/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll new file mode 100644 index 0000000..6247336 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll @@ -0,0 +1,77 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output -passes="print<da>" -da-dump-monotonicity-report \ +; RUN: -da-enable-monotonicity-check 2>&1 | FileCheck %s +; RUN: opt < %s -disable-output -passes="print<da>" 2>&1 | FileCheck %s -check-prefix=DISABLE-CHECK + +; +; for (i = 0; i < (1ULL << 60); i++) { +; A[i] = 1; +; +; unsigned long long offset = i * 32 + (1ULL << 62); +; // offset is positive when interpreted as a signed value. +; // To prevent violating the size limitation for an allocated object. +; if (offset < (1ULL << 63)) +; A[offset] = 2; +; } +; +; ----------------------------------------------------------------------------- +; +; There is a dependency between the two stores. To detect it, we need to check +; the monotonicity and bail out the analysis since `offset` is not monotonic. +; +; memory location | first store (A[i]) | second store (A[offset]) +; ------------------|--------------------|---------------------------- +; A[0] | i = 0 | i = 2^59 - 2^57 +; A[2^60 - 32] | i = 2^60 - 32 | i = 2^59 - 2^57 + 2^55 - 1 +; +define void @f(ptr %A) { +; CHECK-LABEL: 'f' +; CHECK-NEXT: Monotonicity check: +; CHECK-NEXT: Inst: store i8 1, ptr %idx.0, align 1 +; CHECK-NEXT: Expr: {0,+,1}<nuw><nsw><%loop.header> +; CHECK-NEXT: Monotonicity: MultivariateSignedMonotonic +; CHECK-NEXT: Inst: store i8 2, ptr %idx.1, align 1 +; CHECK-NEXT: Expr: {4611686018427387904,+,32}<%loop.header> +; CHECK-NEXT: Monotonicity: Unknown +; CHECK-NEXT: Reason: {4611686018427387904,+,32}<%loop.header> +; CHECK-EMPTY: +; CHECK-NEXT: Src: store i8 1, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.0, align 1 +; CHECK-NEXT: da analyze - none! +; CHECK-NEXT: Src: store i8 1, ptr %idx.0, align 1 --> Dst: store i8 2, ptr %idx.1, align 1 +; CHECK-NEXT: da analyze - confused! +; CHECK-NEXT: Src: store i8 2, ptr %idx.1, align 1 --> Dst: store i8 2, ptr %idx.1, align 1 +; CHECK-NEXT: da analyze - confused! +; +; DISABLE-CHECK-LABEL: 'f' +; DISABLE-CHECK-NEXT: Src: store i8 1, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.0, align 1 +; DISABLE-CHECK-NEXT: da analyze - none! +; DISABLE-CHECK-NEXT: Src: store i8 1, ptr %idx.0, align 1 --> Dst: store i8 2, ptr %idx.1, align 1 +; DISABLE-CHECK-NEXT: da analyze - none! +; DISABLE-CHECK-NEXT: Src: store i8 2, ptr %idx.1, align 1 --> Dst: store i8 2, ptr %idx.1, align 1 +; DISABLE-CHECK-NEXT: da analyze - none! +; +entry: + br label %loop.header + +loop.header: + %i = phi i64 [ 0, %entry ], [ %i.next, %loop.latch ] + %idx.0 = getelementptr inbounds i8, ptr %A, i64 %i + store i8 1, ptr %idx.0 + %offset.tmp = mul i64 %i, 32 + %offset = add i64 %offset.tmp, 4611686018427387904 ; 1ULL << 62 + %if.cond = icmp sge i64 %offset, 0 + br i1 %if.cond, label %if.then, label %loop.latch + +if.then: + %idx.1 = getelementptr inbounds i8, ptr %A, i64 %offset + store i8 2, ptr %idx.1 + br label %loop.latch + +loop.latch: + %i.next = add nuw nsw i64 %i, 1 + %exit.cond = icmp eq i64 %i.next, 1152921504606846976 ; 1ULL << 60 + br i1 %exit.cond, label %exit, label %loop.header + +exit: + ret void +} diff --git a/llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll b/llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll new file mode 100644 index 0000000..8bfbf93 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll @@ -0,0 +1,783 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=all 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-ALL +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=strong-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-STRONG-SIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=weak-crossing-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-WEAK-CROSSING-SIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=exact-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-EXACT-SIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=weak-zero-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-WEAK-ZERO-SIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=exact-rdiv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-EXACT-RDIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=symbolic-rdiv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-SYMBOLIC-RDIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=gcd-miv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-GCD-MIV +; RUN: opt < %s -disable-output "-passes=print<da>" -da-enable-dependence-test=banerjee-miv 2>&1 \ +; RUN: | FileCheck %s --check-prefix=CHECK-BANERJEE-MIV + +; for (i = 0; i < 10; i++) +; a[i] = 0; +define void @strong_siv(ptr %a) { +; CHECK-ALL-LABEL: 'strong_siv' +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-STRONG-SIV-LABEL: 'strong_siv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'strong_siv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-SIV-LABEL: 'strong_siv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'strong_siv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-RDIV-LABEL: 'strong_siv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'strong_siv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-GCD-MIV-LABEL: 'strong_siv' +; CHECK-GCD-MIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-BANERJEE-MIV-LABEL: 'strong_siv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %gep = getelementptr i8, ptr %a, i64 %i + store i8 0, ptr %gep + %i.inc = add i64 %i, 1 + %ec = icmp eq i64 %i.inc, 10 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +; for (i = 0; i < 10; i++) { +; a[i] = 1; +; a[10 - i] = 2; +; } +define void @weak_crossing_siv(ptr %a) { +; CHECK-ALL-LABEL: 'weak_crossing_siv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - output [*|<] splitable! +; CHECK-ALL-NEXT: da analyze - split level = 1, iteration = 5! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-STRONG-SIV-LABEL: 'weak_crossing_siv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'weak_crossing_siv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [*|<] splitable! +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - split level = 1, iteration = 5! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-SIV-LABEL: 'weak_crossing_siv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'weak_crossing_siv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-RDIV-LABEL: 'weak_crossing_siv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'weak_crossing_siv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-GCD-MIV-LABEL: 'weak_crossing_siv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-BANERJEE-MIV-LABEL: 'weak_crossing_siv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %i.sub10 = sub i64 10, %i + %gep.0 = getelementptr i8, ptr %a, i64 %i + %gep.1 = getelementptr i8, ptr %a, i64 %i.sub10 + store i8 1, ptr %gep.0 + store i8 2, ptr %gep.1 + %i.inc = add i64 %i, 1 + %ec = icmp eq i64 %i.inc, 10 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +; for (i = 0; i < 10; i++) { +; a[2 * i + 0] = 1; +; a[2 * i + 1] = 2; +; } +define void @exact_siv(ptr %a) { +; CHECK-ALL-LABEL: 'exact_siv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-STRONG-SIV-LABEL: 'exact_siv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'exact_siv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-SIV-LABEL: 'exact_siv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'exact_siv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-RDIV-LABEL: 'exact_siv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'exact_siv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-GCD-MIV-LABEL: 'exact_siv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - none! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-BANERJEE-MIV-LABEL: 'exact_siv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %offset.0 = mul i64 2, %i + %offset.1 = add i64 %offset.0, 1 + %gep.0 = getelementptr i8, ptr %a, i64 %offset.0 + %gep.1 = getelementptr i8, ptr %a, i64 %offset.1 + store i8 1, ptr %gep.0 + store i8 2, ptr %gep.1 + %i.inc = add i64 %i, 1 + %ec = icmp eq i64 %i.inc, 10 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +; for (i = 0; i < 10; i++) { +; a[10] = 1; +; a[i] = 2; +; } +define void @weak_zero_siv(ptr %a) { +; CHECK-ALL-LABEL: 'weak_zero_siv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - consistent output [S]! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-STRONG-SIV-LABEL: 'weak_zero_siv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [S]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'weak_zero_siv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [S]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-SIV-LABEL: 'weak_zero_siv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [S]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'weak_zero_siv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [S]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - none! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-RDIV-LABEL: 'weak_zero_siv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [S]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'weak_zero_siv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [S]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-GCD-MIV-LABEL: 'weak_zero_siv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [S]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-BANERJEE-MIV-LABEL: 'weak_zero_siv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [S]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*|<]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop ] + %gep.0 = getelementptr i8, ptr %a, i64 10 + %gep.1 = getelementptr i8, ptr %a, i64 %i + store i8 1, ptr %gep.0 + store i8 2, ptr %gep.1 + %i.inc = add i64 %i, 1 + %ec = icmp eq i64 %i.inc, 10 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +; for (i = 0; i < 10; i++) +; a[2 * i + 0] = 1; +; for (i = 0; i < 20; i++) +; a[2 * i + 1] = 2; +define void @exact_rdiv(ptr %a) { +; CHECK-ALL-LABEL: 'exact_rdiv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-STRONG-SIV-LABEL: 'exact_rdiv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'exact_rdiv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-SIV-LABEL: 'exact_rdiv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'exact_rdiv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-RDIV-LABEL: 'exact_rdiv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - none! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'exact_rdiv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [|<]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-GCD-MIV-LABEL: 'exact_rdiv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - none! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-BANERJEE-MIV-LABEL: 'exact_rdiv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [|<]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop.0 + +loop.0: + %i.0 = phi i64 [ 0, %entry ], [ %i.0.inc, %loop.0 ] + %offset.0 = phi i64 [ 0, %entry ], [ %offset.0.next, %loop.0 ] + %gep.0 = getelementptr i8, ptr %a, i64 %offset.0 + store i8 1, ptr %gep.0 + %i.0.inc = add i64 %i.0, 1 + %offset.0.next = add i64 %offset.0, 2 + %ec.0 = icmp eq i64 %i.0.inc, 10 + br i1 %ec.0, label %loop.1, label %loop.0 + +loop.1: + %i.1 = phi i64 [ 0, %loop.0 ], [ %i.1.inc, %loop.1 ] + %offset.1 = phi i64 [ 1, %loop.0 ], [ %offset.1.next, %loop.1 ] + %gep.1 = getelementptr i8, ptr %a, i64 %offset.1 + store i8 2, ptr %gep.1 + %i.1.inc = add i64 %i.1, 1 + %offset.1.next = add i64 %offset.1, 2 + %ec.1 = icmp eq i64 %i.1.inc, 20 + br i1 %ec.1, label %exit, label %loop.1 + +exit: + ret void +} + +; for (i = 0; i < 10; i++) +; a[i + 1] = 1; +; for (i = 0; i < 20; i++) +; a[-i] = 2; +define void @symbolic_rdiv(ptr %a) { +; CHECK-ALL-LABEL: 'symbolic_rdiv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-STRONG-SIV-LABEL: 'symbolic_rdiv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'symbolic_rdiv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-SIV-LABEL: 'symbolic_rdiv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'symbolic_rdiv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [|<]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-EXACT-RDIV-LABEL: 'symbolic_rdiv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - none! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'symbolic_rdiv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - none! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-GCD-MIV-LABEL: 'symbolic_rdiv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [|<]! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-BANERJEE-MIV-LABEL: 'symbolic_rdiv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [|<]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop.0 + +loop.0: + %i.0 = phi i64 [ 0, %entry ], [ %i.0.inc, %loop.0 ] + %i.0.inc = add i64 %i.0, 1 + %gep.0 = getelementptr i8, ptr %a, i64 %i.0.inc + store i8 1, ptr %gep.0 + %ec.0 = icmp eq i64 %i.0.inc, 10 + br i1 %ec.0, label %loop.1, label %loop.0 + +loop.1: + %i.1 = phi i64 [ 0, %loop.0 ], [ %i.1.inc, %loop.1 ] + %i.1.neg = sub i64 0, %i.1 + %gep.1 = getelementptr i8, ptr %a, i64 %i.1.neg + store i8 2, ptr %gep.1 + %i.1.inc = add i64 %i.1, 1 + %ec.1 = icmp eq i64 %i.1.inc, 20 + br i1 %ec.1, label %exit, label %loop.1 + +exit: + ret void +} + +; for (i = 0; i < 10; i++) +; for (j = 0; j < 10; j++) { +; a[2*i + 2*j + 0] = 1; +; a[2*i + 2*j + 1] = 2; +; } +define void @gcd_miv(ptr %a) { +; CHECK-ALL-LABEL: 'gcd_miv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - output [* *]! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - output [* *]! +; +; CHECK-STRONG-SIV-LABEL: 'gcd_miv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - output [* *]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'gcd_miv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [* *]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-EXACT-SIV-LABEL: 'gcd_miv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [* *]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'gcd_miv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - output [* *]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-EXACT-RDIV-LABEL: 'gcd_miv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - output [* *]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - output [* *|<]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - output [* *]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'gcd_miv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - output [* *]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - output [* *|<]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - output [* *]! +; +; CHECK-GCD-MIV-LABEL: 'gcd_miv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - output [* *]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - none! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - output [* *]! +; +; CHECK-BANERJEE-MIV-LABEL: 'gcd_miv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - output [* *]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - output [<> <>]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - output [* *]! +; +entry: + br label %loop.i.header + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + %offset.0.i = phi i64 [ 0, %entry ], [ %offset.0.i.next, %loop.i.latch ] + %offset.1.i = phi i64 [ 1, %entry ], [ %offset.1.i.next, %loop.i.latch ] + br label %loop.j + +loop.j: + %j = phi i64 [ 0, %loop.i.header ], [ %j.inc, %loop.j ] + %offset.0 = phi i64 [ %offset.0.i, %loop.i.header ], [ %offset.0.next, %loop.j ] + %offset.1 = phi i64 [ %offset.1.i, %loop.i.header ], [ %offset.1.next, %loop.j ] + %gep.0 = getelementptr i8, ptr %a, i64 %offset.0 + %gep.1 = getelementptr i8, ptr %a, i64 %offset.1 + store i8 1, ptr %gep.0 + store i8 2, ptr %gep.1 + %j.inc = add i64 %j, 1 + %offset.0.next = add i64 %offset.0, 2 + %offset.1.next = add i64 %offset.1, 2 + %ec.j = icmp eq i64 %j.inc, 10 + br i1 %ec.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add i64 %i, 1 + %offset.0.i.next = add i64 %offset.0.i, 2 + %offset.1.i.next = add i64 %offset.1.i, 2 + %ec.i = icmp eq i64 %i.inc, 10 + br i1 %ec.i, label %exit, label %loop.i.header + +exit: + ret void +} + +; for (i = 0; i < 10; i++) +; for (j = 0; j < 10; j++) { +; a[i + j] = 1; +; a[i + j + 100] = 2; +; } +define void @banerjee_miv(ptr %a) { +; CHECK-ALL-LABEL: 'banerjee_miv' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - output [* *]! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - output [* *]! +; +; CHECK-STRONG-SIV-LABEL: 'banerjee_miv' +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - output [* *]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-STRONG-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-STRONG-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'banerjee_miv' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [* *]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-EXACT-SIV-LABEL: 'banerjee_miv' +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [* *]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-EXACT-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-WEAK-ZERO-SIV-LABEL: 'banerjee_miv' +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - output [* *]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - output [* *|<]! +; CHECK-WEAK-ZERO-SIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-WEAK-ZERO-SIV-NEXT: da analyze - output [* *]! +; +; CHECK-EXACT-RDIV-LABEL: 'banerjee_miv' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - output [* *]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - output [* *|<]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - output [* *]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'banerjee_miv' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - output [* *]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - output [* *|<]! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - output [* *]! +; +; CHECK-GCD-MIV-LABEL: 'banerjee_miv' +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - output [* *]! +; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - output [* *|<]! +; CHECK-GCD-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-GCD-MIV-NEXT: da analyze - output [* *]! +; +; CHECK-BANERJEE-MIV-LABEL: 'banerjee_miv' +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 1, ptr %gep.0, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - output [* *]! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 1, ptr %gep.0, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - none! +; CHECK-BANERJEE-MIV-NEXT: Src: store i8 2, ptr %gep.1, align 1 --> Dst: store i8 2, ptr %gep.1, align 1 +; CHECK-BANERJEE-MIV-NEXT: da analyze - output [* *]! +; +entry: + br label %loop.i.header + +loop.i.header: + %i = phi i64 [ 0, %entry ], [ %i.inc, %loop.i.latch ] + br label %loop.j + +loop.j: + %j = phi i64 [ 0, %loop.i.header ], [ %j.inc, %loop.j ] + %offset.0 = add i64 %i, %j + %offset.1 = add i64 %offset.0, 100 + %gep.0 = getelementptr i8, ptr %a, i64 %offset.0 + %gep.1 = getelementptr i8, ptr %a, i64 %offset.1 + store i8 1, ptr %gep.0 + store i8 2, ptr %gep.1 + %j.inc = add i64 %j, 1 + %ec.j = icmp eq i64 %j.inc, 10 + br i1 %ec.j, label %loop.i.latch, label %loop.j + +loop.i.latch: + %i.inc = add i64 %i, 1 + %ec.i = icmp eq i64 %i.inc, 10 + br i1 %ec.i, label %exit, label %loop.i.header + +exit: + ret void +} diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll index b215c51..0933e67 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll @@ -1371,11 +1371,10 @@ define noundef <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %sc ; CHECK-SD-NEXT: lsr x9, x0, #16 ; CHECK-SD-NEXT: adrp x8, .LCPI14_0 ; CHECK-SD-NEXT: dup v4.8h, w0 -; CHECK-SD-NEXT: dup v1.8h, w9 -; CHECK-SD-NEXT: fmov s3, w9 -; CHECK-SD-NEXT: sqneg v2.8h, v1.8h -; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] -; CHECK-SD-NEXT: tbl v1.16b, { v2.16b, v3.16b }, v1.16b +; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI14_0] +; CHECK-SD-NEXT: dup v2.8h, w9 +; CHECK-SD-NEXT: sqneg v1.8h, v2.8h +; CHECK-SD-NEXT: tbl v1.16b, { v1.16b, v2.16b }, v3.16b ; CHECK-SD-NEXT: rev32 v2.8h, v0.8h ; CHECK-SD-NEXT: sqdmull v3.4s, v0.4h, v4.4h ; CHECK-SD-NEXT: sqdmull2 v0.4s, v0.8h, v4.8h diff --git a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll index c4de177..d7a2a83 100644 --- a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll +++ b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll @@ -5,32 +5,30 @@ define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 ; CHECK-LABEL: lower_trunc_16xi8: ; CHECK: // %bb.0: ; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ldr h1, [sp] +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: mov v0.b[1], w1 +; CHECK-NEXT: mov v0.b[2], w2 +; CHECK-NEXT: mov v0.b[3], w3 +; CHECK-NEXT: mov v0.b[4], w4 +; CHECK-NEXT: mov v0.b[5], w5 +; CHECK-NEXT: mov v0.b[6], w6 +; CHECK-NEXT: mov v0.b[7], w7 +; CHECK-NEXT: ld1 { v0.b }[8], [x8] ; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: ld1 { v1.h }[1], [x8] +; CHECK-NEXT: ld1 { v0.b }[9], [x8] ; CHECK-NEXT: add x8, sp, #16 -; CHECK-NEXT: mov v0.h[1], w1 -; CHECK-NEXT: ld1 { v1.h }[2], [x8] +; CHECK-NEXT: ld1 { v0.b }[10], [x8] ; CHECK-NEXT: add x8, sp, #24 -; CHECK-NEXT: mov v0.h[2], w2 -; CHECK-NEXT: ld1 { v1.h }[3], [x8] +; CHECK-NEXT: ld1 { v0.b }[11], [x8] ; CHECK-NEXT: add x8, sp, #32 -; CHECK-NEXT: mov v0.h[3], w3 -; CHECK-NEXT: ld1 { v1.h }[4], [x8] +; CHECK-NEXT: ld1 { v0.b }[12], [x8] ; CHECK-NEXT: add x8, sp, #40 -; CHECK-NEXT: ld1 { v1.h }[5], [x8] +; CHECK-NEXT: ld1 { v0.b }[13], [x8] ; CHECK-NEXT: add x8, sp, #48 -; CHECK-NEXT: mov v0.h[4], w4 -; CHECK-NEXT: ld1 { v1.h }[6], [x8] +; CHECK-NEXT: ld1 { v0.b }[14], [x8] ; CHECK-NEXT: add x8, sp, #56 -; CHECK-NEXT: mov v0.h[5], w5 -; CHECK-NEXT: ld1 { v1.h }[7], [x8] -; CHECK-NEXT: mov v0.h[6], w6 -; CHECK-NEXT: add v2.8h, v1.8h, v1.8h -; CHECK-NEXT: mov v0.h[7], w7 -; CHECK-NEXT: add v3.8h, v0.8h, v0.8h -; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; CHECK-NEXT: uzp1 v1.16b, v3.16b, v2.16b +; CHECK-NEXT: ld1 { v0.b }[15], [x8] +; CHECK-NEXT: add v1.16b, v0.16b, v0.16b ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %a1 = insertelement <16 x i16> poison, i16 %a, i16 0 @@ -59,18 +57,15 @@ define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 define <8 x i16> @lower_trunc_8xi16(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) { ; CHECK-LABEL: lower_trunc_8xi16: ; CHECK: // %bb.0: -; CHECK-NEXT: fmov s0, w4 -; CHECK-NEXT: fmov s1, w0 -; CHECK-NEXT: mov v0.s[1], w5 -; CHECK-NEXT: mov v1.s[1], w1 -; CHECK-NEXT: mov v0.s[2], w6 -; CHECK-NEXT: mov v1.s[2], w2 -; CHECK-NEXT: mov v0.s[3], w7 -; CHECK-NEXT: mov v1.s[3], w3 -; CHECK-NEXT: add v2.4s, v0.4s, v0.4s -; CHECK-NEXT: add v3.4s, v1.4s, v1.4s -; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; CHECK-NEXT: uzp1 v1.8h, v3.8h, v2.8h +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: mov v0.h[1], w1 +; CHECK-NEXT: mov v0.h[2], w2 +; CHECK-NEXT: mov v0.h[3], w3 +; CHECK-NEXT: mov v0.h[4], w4 +; CHECK-NEXT: mov v0.h[5], w5 +; CHECK-NEXT: mov v0.h[6], w6 +; CHECK-NEXT: mov v0.h[7], w7 +; CHECK-NEXT: add v1.8h, v0.8h, v0.8h ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %a1 = insertelement <8 x i32> poison, i32 %a, i32 0 @@ -91,14 +86,11 @@ define <8 x i16> @lower_trunc_8xi16(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 define <4 x i32> @lower_trunc_4xi32(i64 %a, i64 %b, i64 %c, i64 %d) { ; CHECK-LABEL: lower_trunc_4xi32: ; CHECK: // %bb.0: -; CHECK-NEXT: fmov d0, x2 -; CHECK-NEXT: fmov d1, x0 -; CHECK-NEXT: mov v0.d[1], x3 -; CHECK-NEXT: mov v1.d[1], x1 -; CHECK-NEXT: add v2.2d, v0.2d, v0.2d -; CHECK-NEXT: add v3.2d, v1.2d, v1.2d -; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; CHECK-NEXT: uzp1 v1.4s, v3.4s, v2.4s +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: mov v0.s[1], w1 +; CHECK-NEXT: mov v0.s[2], w2 +; CHECK-NEXT: mov v0.s[3], w3 +; CHECK-NEXT: add v1.4s, v0.4s, v0.4s ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %a1 = insertelement <4 x i64> poison, i64 %a, i64 0 @@ -115,24 +107,20 @@ define <4 x i32> @lower_trunc_4xi32(i64 %a, i64 %b, i64 %c, i64 %d) { define <8 x i32> @lower_trunc_8xi32(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) { ; CHECK-LABEL: lower_trunc_8xi32: ; CHECK: // %bb.0: -; CHECK-NEXT: fmov d0, x2 -; CHECK-NEXT: fmov d1, x0 -; CHECK-NEXT: fmov d2, x6 -; CHECK-NEXT: fmov d3, x4 -; CHECK-NEXT: mov v0.d[1], x3 -; CHECK-NEXT: mov v1.d[1], x1 -; CHECK-NEXT: mov v2.d[1], x7 -; CHECK-NEXT: mov v3.d[1], x5 -; CHECK-NEXT: add v4.2d, v0.2d, v0.2d -; CHECK-NEXT: add v5.2d, v1.2d, v1.2d -; CHECK-NEXT: add v6.2d, v2.2d, v2.2d -; CHECK-NEXT: add v7.2d, v3.2d, v3.2d +; CHECK-NEXT: fmov d0, x6 +; CHECK-NEXT: fmov d1, x4 +; CHECK-NEXT: fmov d2, x2 +; CHECK-NEXT: fmov d3, x0 +; CHECK-NEXT: mov v0.d[1], x7 +; CHECK-NEXT: mov v1.d[1], x5 +; CHECK-NEXT: mov v2.d[1], x3 +; CHECK-NEXT: mov v3.d[1], x1 +; CHECK-NEXT: uzp1 v1.4s, v1.4s, v0.4s ; CHECK-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; CHECK-NEXT: uzp1 v3.4s, v5.4s, v4.4s -; CHECK-NEXT: uzp1 v1.4s, v7.4s, v6.4s -; CHECK-NEXT: eor v0.16b, v0.16b, v3.16b -; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b +; CHECK-NEXT: add v3.4s, v1.4s, v1.4s +; CHECK-NEXT: add v0.4s, v2.4s, v2.4s +; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b +; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b ; CHECK-NEXT: ret %a1 = insertelement <8 x i64> poison, i64 %a, i64 0 %b1 = insertelement <8 x i64> %a1, i64 %b, i64 1 diff --git a/llvm/test/CodeGen/AArch64/zext-shuffle.ll b/llvm/test/CodeGen/AArch64/zext-shuffle.ll index 20d2071..a0d4e18 100644 --- a/llvm/test/CodeGen/AArch64/zext-shuffle.ll +++ b/llvm/test/CodeGen/AArch64/zext-shuffle.ll @@ -674,10 +674,8 @@ define <4 x i32> @isUndefDeInterleave_t1_bad(<8 x i16> %a) { define i16 @undeftop(<8 x i16> %0) { ; CHECK-LABEL: undeftop: ; CHECK: // %bb.0: -; CHECK-NEXT: dup v0.8h, v0.h[4] -; CHECK-NEXT: uaddl v0.4s, v0.4h, v0.4h -; CHECK-NEXT: xtn v0.4h, v0.4s -; CHECK-NEXT: umov w0, v0.h[0] +; CHECK-NEXT: add v0.8h, v0.8h, v0.8h +; CHECK-NEXT: umov w0, v0.h[4] ; CHECK-NEXT: ret %2 = shufflevector <8 x i16> %0, <8 x i16> zeroinitializer, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 9, i32 7, i32 5, i32 3> %3 = zext <8 x i16> %2 to <8 x i64> diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll index 002c03aa..e86f747 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll @@ -551,7 +551,9 @@ define amdgpu_kernel void @workgroup_one_as_release() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_lds_direct + ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_one_as_release @@ -562,6 +564,8 @@ define amdgpu_kernel void @workgroup_one_as_release() #0 { ; ; GFX11CU-LABEL: name: workgroup_one_as_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: S_WAITCNT_soft 1015 + ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup-one-as") release @@ -587,7 +591,9 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_lds_direct + ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_one_as_acq_rel @@ -599,6 +605,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel() #0 { ; ; GFX11CU-LABEL: name: workgroup_one_as_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: S_WAITCNT_soft 1015 + ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup-one-as") acq_rel @@ -624,7 +632,9 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_lds_direct + ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_one_as_seq_cst @@ -636,6 +646,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst() #0 { ; ; GFX11CU-LABEL: name: workgroup_one_as_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: S_WAITCNT_soft 1015 + ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup-one-as") seq_cst @@ -1305,8 +1317,9 @@ define amdgpu_kernel void @workgroup_release() #0 { ; ; GFX10CU-LABEL: name: workgroup_release ; GFX10CU: bb.0.entry: - ; GFX10CU-NEXT: S_WAITCNT_soft 49279 + ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_lds_direct + ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_release @@ -1317,7 +1330,8 @@ define amdgpu_kernel void @workgroup_release() #0 { ; ; GFX11CU-LABEL: name: workgroup_release ; GFX11CU: bb.0.entry: - ; GFX11CU-NEXT: S_WAITCNT_soft 64519 + ; GFX11CU-NEXT: S_WAITCNT_soft 7 + ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup") release @@ -1345,8 +1359,9 @@ define amdgpu_kernel void @workgroup_acq_rel() #0 { ; ; GFX10CU-LABEL: name: workgroup_acq_rel ; GFX10CU: bb.0.entry: - ; GFX10CU-NEXT: S_WAITCNT_soft 49279 + ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_lds_direct + ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_acq_rel @@ -1358,7 +1373,8 @@ define amdgpu_kernel void @workgroup_acq_rel() #0 { ; ; GFX11CU-LABEL: name: workgroup_acq_rel ; GFX11CU: bb.0.entry: - ; GFX11CU-NEXT: S_WAITCNT_soft 64519 + ; GFX11CU-NEXT: S_WAITCNT_soft 7 + ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup") acq_rel @@ -1386,8 +1402,9 @@ define amdgpu_kernel void @workgroup_seq_cst() #0 { ; ; GFX10CU-LABEL: name: workgroup_seq_cst ; GFX10CU: bb.0.entry: - ; GFX10CU-NEXT: S_WAITCNT_soft 49279 + ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_lds_direct + ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_seq_cst @@ -1399,7 +1416,8 @@ define amdgpu_kernel void @workgroup_seq_cst() #0 { ; ; GFX11CU-LABEL: name: workgroup_seq_cst ; GFX11CU: bb.0.entry: - ; GFX11CU-NEXT: S_WAITCNT_soft 64519 + ; GFX11CU-NEXT: S_WAITCNT_soft 7 + ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup") seq_cst diff --git a/llvm/test/CodeGen/AMDGPU/add-max.ll b/llvm/test/CodeGen/AMDGPU/add-max.ll index 00c6656..b3a7057 100644 --- a/llvm/test/CodeGen/AMDGPU/add-max.ll +++ b/llvm/test/CodeGen/AMDGPU/add-max.ll @@ -5,7 +5,7 @@ define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN-LABEL: add_max_u32_vvv: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_max_u32_e64 v0, v0, v1, v2 +; GCN-NEXT: v_add_max_u32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) @@ -16,7 +16,7 @@ define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) { define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) { ; GCN-LABEL: add_max_u32_svv: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_max_u32_e64 v0, s0, v0, v1 +; GCN-NEXT: v_add_max_u32 v0, s0, v0, v1 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.umax.i32(i32 %add, i32 %c) @@ -27,7 +27,7 @@ define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) { define amdgpu_ps float @add_max_u32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) { ; SDAG-LABEL: add_max_u32_ssv: ; SDAG: ; %bb.0: -; SDAG-NEXT: v_add_max_u32_e64 v0, s0, s1, v0 +; SDAG-NEXT: v_add_max_u32 v0, s0, s1, v0 ; SDAG-NEXT: ; return to shader part epilog ; ; GISEL-LABEL: add_max_u32_ssv: @@ -59,7 +59,7 @@ define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) { ; GCN-LABEL: add_max_u32_vsi: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_max_u32_e64 v0, v0, s0, 4 +; GCN-NEXT: v_add_max_u32 v0, v0, s0, 4 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.umax.i32(i32 %add, i32 4) @@ -70,7 +70,7 @@ define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) { define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) { ; GCN-LABEL: add_max_u32_svl: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_max_u32_e64 v0, s0, v0, 0x64 +; GCN-NEXT: v_add_max_u32 v0, s0, v0, 0x64 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.umax.i32(i32 %add, i32 100) @@ -81,7 +81,7 @@ define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) { define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b) { ; SDAG-LABEL: add_max_u32_slv: ; SDAG: ; %bb.0: -; SDAG-NEXT: v_add_max_u32_e64 v0, 0x64, s0, v0 +; SDAG-NEXT: v_add_max_u32 v0, 0x64, s0, v0 ; SDAG-NEXT: ; return to shader part epilog ; ; GISEL-LABEL: add_max_u32_slv: @@ -99,7 +99,7 @@ define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b) { define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN-LABEL: add_max_i32_vvv: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_max_i32_e64 v0, v0, v1, v2 +; GCN-NEXT: v_add_max_i32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.smax.i32(i32 %add, i32 %c) @@ -110,7 +110,7 @@ define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) { define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN-LABEL: add_min_u32_vvv: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_min_u32_e64 v0, v0, v1, v2 +; GCN-NEXT: v_add_min_u32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.umin.i32(i32 %add, i32 %c) @@ -121,7 +121,7 @@ define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) { define amdgpu_ps float @add_min_i32_vvv(i32 %a, i32 %b, i32 %c) { ; GCN-LABEL: add_min_i32_vvv: ; GCN: ; %bb.0: -; GCN-NEXT: v_add_min_i32_e64 v0, v0, v1, v2 +; GCN-NEXT: v_add_min_i32 v0, v0, v1, v2 ; GCN-NEXT: ; return to shader part epilog %add = add i32 %a, %b %max = call i32 @llvm.smin.i32(i32 %add, i32 %c) diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index 7ee0015f..711d57b 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -39137,7 +39137,7 @@ define bfloat @v_sitofp_i64_to_bf16(i64 %x) { ; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v2 ; GFX1250-NEXT: v_add_nc_u32_e32 v2, 32, v2 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_min_u32_e64 v2, v3, -1, v2 +; GFX1250-NEXT: v_add_min_u32 v2, v3, -1, v2 ; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v2, v[0:1] ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_min_u32_e32 v0, 1, v0 @@ -39487,8 +39487,8 @@ define <2 x bfloat> @v_sitofp_v2i64_to_v2bf16(<2 x i64> %x) { ; GFX1250-NEXT: v_dual_ashrrev_i32 v5, 31, v5 :: v_dual_ashrrev_i32 v4, 31, v4 ; GFX1250-NEXT: v_dual_add_nc_u32 v5, 32, v5 :: v_dual_add_nc_u32 v4, 32, v4 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_min_u32_e64 v5, v7, -1, v5 -; GFX1250-NEXT: v_add_min_u32_e64 v4, v6, -1, v4 +; GFX1250-NEXT: v_add_min_u32 v5, v7, -1, v5 +; GFX1250-NEXT: v_add_min_u32 v4, v6, -1, v4 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v5, v[0:1] ; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v4, v[2:3] @@ -39979,9 +39979,9 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX1250TRUE16-NEXT: v_dual_add_nc_u32 v7, 32, v7 :: v_dual_add_nc_u32 v6, 32, v6 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8 -; GFX1250TRUE16-NEXT: v_add_min_u32_e64 v7, v10, -1, v7 +; GFX1250TRUE16-NEXT: v_add_min_u32 v7, v10, -1, v7 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_add_min_u32_e64 v6, v9, -1, v6 +; GFX1250TRUE16-NEXT: v_add_min_u32 v6, v9, -1, v6 ; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[2:3], v7, v[2:3] ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[4:5], v6, v[4:5] @@ -39991,7 +39991,7 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX1250TRUE16-NEXT: v_min_u32_e32 v4, 1, v4 ; GFX1250TRUE16-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250TRUE16-NEXT: v_add_min_u32_e64 v8, v11, -1, v8 +; GFX1250TRUE16-NEXT: v_add_min_u32 v8, v11, -1, v8 ; GFX1250TRUE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v4, v5, v4 bitop3:0x54 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2 @@ -40027,8 +40027,8 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX1250FAKE16-NEXT: v_dual_ashrrev_i32 v6, 31, v6 :: v_dual_ashrrev_i32 v7, 31, v7 ; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v6, 32, v6 :: v_dual_add_nc_u32 v7, 32, v7 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_add_min_u32_e64 v6, v10, -1, v6 -; GFX1250FAKE16-NEXT: v_add_min_u32_e64 v7, v11, -1, v7 +; GFX1250FAKE16-NEXT: v_add_min_u32 v6, v10, -1, v6 +; GFX1250FAKE16-NEXT: v_add_min_u32 v7, v11, -1, v7 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[2:3], v6, v[2:3] ; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[0:1], v7, v[0:1] @@ -40038,7 +40038,7 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX1250FAKE16-NEXT: v_min_u32_e32 v0, 1, v0 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1250FAKE16-NEXT: v_or_b32_e32 v2, v3, v2 -; GFX1250FAKE16-NEXT: v_add_min_u32_e64 v8, v9, -1, v8 +; GFX1250FAKE16-NEXT: v_add_min_u32 v8, v9, -1, v8 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 ; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2 @@ -40656,18 +40656,18 @@ define <4 x bfloat> @v_sitofp_v4i64_to_v4bf16(<4 x i64> %x) { ; GFX1250-NEXT: v_dual_add_nc_u32 v9, 32, v9 :: v_dual_add_nc_u32 v8, 32, v8 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-NEXT: v_dual_ashrrev_i32 v10, 31, v10 :: v_dual_bitop2_b32 v11, v0, v1 bitop3:0x14 -; GFX1250-NEXT: v_add_min_u32_e64 v9, v13, -1, v9 +; GFX1250-NEXT: v_add_min_u32 v9, v13, -1, v9 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_add_min_u32_e64 v8, v12, -1, v8 +; GFX1250-NEXT: v_add_min_u32 v8, v12, -1, v8 ; GFX1250-NEXT: v_dual_ashrrev_i32 v11, 31, v11 :: v_dual_add_nc_u32 v10, 32, v10 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1250-NEXT: v_lshlrev_b64_e32 v[4:5], v9, v[4:5] ; GFX1250-NEXT: v_lshlrev_b64_e32 v[6:7], v8, v[6:7] ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-NEXT: v_add_nc_u32_e32 v11, 32, v11 -; GFX1250-NEXT: v_add_min_u32_e64 v10, v14, -1, v10 +; GFX1250-NEXT: v_add_min_u32 v10, v14, -1, v10 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_min_u32_e64 v11, v15, -1, v11 +; GFX1250-NEXT: v_add_min_u32 v11, v15, -1, v11 ; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v10, v[2:3] ; GFX1250-NEXT: v_min_u32_e32 v6, 1, v6 ; GFX1250-NEXT: v_min_u32_e32 v4, 1, v4 diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll index b91963f..d23509b 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll @@ -150,7 +150,6 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX10CU-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds ; GFX10CU-NEXT: v_mov_b32_e32 v0, s13 ; GFX10CU-NEXT: s_waitcnt vmcnt(0) -; GFX10CU-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10CU-NEXT: s_barrier ; GFX10CU-NEXT: ds_read_b32 v0, v0 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll index e8b8d05..e8eccb0 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll @@ -147,14 +147,13 @@ define weak_odr amdgpu_kernel void @dpp_test1(ptr %arg) local_unnamed_addr { ; GFX8-OPT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 ; GFX8-OPT-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-OPT-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-OPT-NEXT: s_barrier -; GFX8-OPT-NEXT: v_add_u32_e32 v1, vcc, v1, v1 -; GFX8-OPT-NEXT: s_nop 1 -; GFX8-OPT-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf -; GFX8-OPT-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; GFX8-OPT-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-OPT-NEXT: v_add_u32_e32 v4, vcc, v1, v1 +; GFX8-OPT-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-OPT-NEXT: v_add_u32_e32 v0, vcc, s0, v0 -; GFX8-OPT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-OPT-NEXT: v_mov_b32_dpp v2, v4 quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf +; GFX8-OPT-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-OPT-NEXT: v_add_u32_e32 v2, vcc, v2, v4 +; GFX8-OPT-NEXT: s_barrier ; GFX8-OPT-NEXT: flat_store_dword v[0:1], v2 ; GFX8-OPT-NEXT: s_endpgm ; @@ -194,14 +193,14 @@ define weak_odr amdgpu_kernel void @dpp_test1(ptr %arg) local_unnamed_addr { ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: ds_read_b32 v1, v0 -; GFX10-NEXT: s_barrier -; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_add_co_u32 v0, s0, s0, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v1 -; GFX10-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v3, v1, v1 ; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 +; GFX10-NEXT: v_mov_b32_dpp v2, v3 quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf +; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v3 +; GFX10-NEXT: s_barrier +; GFX10-NEXT: buffer_gl0_inv ; GFX10-NEXT: flat_store_dword v[0:1], v2 ; GFX10-NEXT: s_endpgm ; @@ -213,15 +212,15 @@ define weak_odr amdgpu_kernel void @dpp_test1(ptr %arg) local_unnamed_addr { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_and_b32_e32 v0, 0xffc, v0 ; GFX11-NEXT: ds_load_b32 v1, v0 -; GFX11-NEXT: s_barrier -; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: v_add_co_u32 v0, s0, s0, v0 -; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf -; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-NEXT: v_add_nc_u32_e32 v3, v1, v1 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_dpp v2, v3 quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf +; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v3 +; GFX11-NEXT: s_barrier +; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-NEXT: s_endpgm bb: diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll index 516c3946..282a7ae 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll @@ -15,7 +15,6 @@ define amdgpu_kernel void @test_s_barrier() { ; ; GFX10-CU-LABEL: test_s_barrier: ; GFX10-CU: ; %bb.0: ; %entry -; GFX10-CU-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-CU-NEXT: s_barrier ; GFX10-CU-NEXT: s_endpgm ; @@ -26,7 +25,6 @@ define amdgpu_kernel void @test_s_barrier() { ; ; GFX11-CU-LABEL: test_s_barrier: ; GFX11-CU: ; %bb.0: ; %entry -; GFX11-CU-NEXT: s_waitcnt_depctr 0xffe3 ; GFX11-CU-NEXT: s_barrier ; GFX11-CU-NEXT: s_endpgm ; @@ -38,7 +36,6 @@ define amdgpu_kernel void @test_s_barrier() { ; ; GFX12-CU-LABEL: test_s_barrier: ; GFX12-CU: ; %bb.0: ; %entry -; GFX12-CU-NEXT: s_wait_alu 0xffe3 ; GFX12-CU-NEXT: s_barrier_signal -1 ; GFX12-CU-NEXT: s_barrier_wait -1 ; GFX12-CU-NEXT: s_endpgm @@ -63,8 +60,8 @@ define amdgpu_kernel void @test_s_barrier_workgroup_fence() { ; ; GFX10-CU-LABEL: test_s_barrier_workgroup_fence: ; GFX10-CU: ; %bb.0: ; %entry -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-CU-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_barrier ; GFX10-CU-NEXT: s_endpgm ; @@ -77,8 +74,8 @@ define amdgpu_kernel void @test_s_barrier_workgroup_fence() { ; ; GFX11-CU-LABEL: test_s_barrier_workgroup_fence: ; GFX11-CU: ; %bb.0: ; %entry -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-CU-NEXT: s_waitcnt_depctr 0xffe3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_barrier ; GFX11-CU-NEXT: s_endpgm ; @@ -94,8 +91,10 @@ define amdgpu_kernel void @test_s_barrier_workgroup_fence() { ; ; GFX12-CU-LABEL: test_s_barrier_workgroup_fence: ; GFX12-CU: ; %bb.0: ; %entry -; GFX12-CU-NEXT: s_wait_dscnt 0x0 -; GFX12-CU-NEXT: s_wait_alu 0xffe3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: s_barrier_signal -1 ; GFX12-CU-NEXT: s_barrier_wait -1 ; GFX12-CU-NEXT: s_endpgm @@ -125,7 +124,6 @@ define amdgpu_kernel void @test_s_barrier_agent_fence() { ; GFX10-CU: ; %bb.0: ; %entry ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-CU-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-CU-NEXT: s_barrier ; GFX10-CU-NEXT: s_endpgm ; @@ -140,7 +138,6 @@ define amdgpu_kernel void @test_s_barrier_agent_fence() { ; GFX11-CU: ; %bb.0: ; %entry ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-CU-NEXT: s_waitcnt_depctr 0xffe3 ; GFX11-CU-NEXT: s_barrier ; GFX11-CU-NEXT: s_endpgm ; @@ -160,7 +157,6 @@ define amdgpu_kernel void @test_s_barrier_agent_fence() { ; GFX12-CU-NEXT: s_wait_samplecnt 0x0 ; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX12-CU-NEXT: s_wait_alu 0xffe3 ; GFX12-CU-NEXT: s_barrier_signal -1 ; GFX12-CU-NEXT: s_barrier_wait -1 ; GFX12-CU-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll index 6a76f43..7efbff9 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll @@ -107,6 +107,8 @@ define amdgpu_kernel void @workgroup_release_fence() { ; ; GFX10-CU-LABEL: workgroup_release_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_release_fence: @@ -139,6 +141,8 @@ define amdgpu_kernel void @workgroup_release_fence() { ; ; GFX11-CU-LABEL: workgroup_release_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_release_fence: @@ -151,6 +155,10 @@ define amdgpu_kernel void @workgroup_release_fence() { ; ; GFX12-CU-LABEL: workgroup_release_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_release_fence: @@ -181,6 +189,8 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() { ; ; GFX10-CU-LABEL: workgroup_acq_rel_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_acq_rel_fence: @@ -216,6 +226,8 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() { ; ; GFX11-CU-LABEL: workgroup_acq_rel_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_acq_rel_fence: @@ -229,6 +241,10 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() { ; ; GFX12-CU-LABEL: workgroup_acq_rel_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_acq_rel_fence: @@ -259,6 +275,8 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() { ; ; GFX10-CU-LABEL: workgroup_seq_cst_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_seq_cst_fence: @@ -294,6 +312,8 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() { ; ; GFX11-CU-LABEL: workgroup_seq_cst_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_seq_cst_fence: @@ -307,6 +327,10 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() { ; ; GFX12-CU-LABEL: workgroup_seq_cst_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_seq_cst_fence: @@ -412,6 +436,8 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() { ; ; GFX10-CU-LABEL: workgroup_one_as_release_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_one_as_release_fence: @@ -444,6 +470,8 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() { ; ; GFX11-CU-LABEL: workgroup_one_as_release_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_one_as_release_fence: @@ -456,6 +484,10 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() { ; ; GFX12-CU-LABEL: workgroup_one_as_release_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_one_as_release_fence: @@ -486,6 +518,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() { ; ; GFX10-CU-LABEL: workgroup_one_as_acq_rel_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_one_as_acq_rel_fence: @@ -521,6 +555,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() { ; ; GFX11-CU-LABEL: workgroup_one_as_acq_rel_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_one_as_acq_rel_fence: @@ -534,6 +570,10 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() { ; ; GFX12-CU-LABEL: workgroup_one_as_acq_rel_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_one_as_acq_rel_fence: @@ -564,6 +604,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() { ; ; GFX10-CU-LABEL: workgroup_one_as_seq_cst_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_one_as_seq_cst_fence: @@ -599,6 +641,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() { ; ; GFX11-CU-LABEL: workgroup_one_as_seq_cst_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_one_as_seq_cst_fence: @@ -612,6 +656,10 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() { ; ; GFX12-CU-LABEL: workgroup_one_as_seq_cst_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_one_as_seq_cst_fence: diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll index d288bfc..1cca64a 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll @@ -1093,7 +1093,8 @@ define amdgpu_kernel void @workgroup_release_fence() { ; ; GFX10-CU-LABEL: workgroup_release_fence: ; GFX10-CU: ; %bb.0: ; %entry -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_release_fence: @@ -1129,7 +1130,8 @@ define amdgpu_kernel void @workgroup_release_fence() { ; ; GFX11-CU-LABEL: workgroup_release_fence: ; GFX11-CU: ; %bb.0: ; %entry -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_release_fence: @@ -1142,7 +1144,10 @@ define amdgpu_kernel void @workgroup_release_fence() { ; ; GFX12-CU-LABEL: workgroup_release_fence: ; GFX12-CU: ; %bb.0: ; %entry -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_release_fence: @@ -1175,7 +1180,8 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() { ; ; GFX10-CU-LABEL: workgroup_acq_rel_fence: ; GFX10-CU: ; %bb.0: ; %entry -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_acq_rel_fence: @@ -1214,7 +1220,8 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() { ; ; GFX11-CU-LABEL: workgroup_acq_rel_fence: ; GFX11-CU: ; %bb.0: ; %entry -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_acq_rel_fence: @@ -1228,7 +1235,10 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() { ; ; GFX12-CU-LABEL: workgroup_acq_rel_fence: ; GFX12-CU: ; %bb.0: ; %entry -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_acq_rel_fence: @@ -1261,7 +1271,8 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() { ; ; GFX10-CU-LABEL: workgroup_seq_cst_fence: ; GFX10-CU: ; %bb.0: ; %entry -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_seq_cst_fence: @@ -1300,7 +1311,8 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() { ; ; GFX11-CU-LABEL: workgroup_seq_cst_fence: ; GFX11-CU: ; %bb.0: ; %entry -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_seq_cst_fence: @@ -1314,7 +1326,10 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() { ; ; GFX12-CU-LABEL: workgroup_seq_cst_fence: ; GFX12-CU: ; %bb.0: ; %entry -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_seq_cst_fence: @@ -1420,6 +1435,8 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() { ; ; GFX10-CU-LABEL: workgroup_one_as_release_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_one_as_release_fence: @@ -1452,6 +1469,8 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() { ; ; GFX11-CU-LABEL: workgroup_one_as_release_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_one_as_release_fence: @@ -1464,6 +1483,10 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() { ; ; GFX12-CU-LABEL: workgroup_one_as_release_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_one_as_release_fence: @@ -1494,6 +1517,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() { ; ; GFX10-CU-LABEL: workgroup_one_as_acq_rel_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_one_as_acq_rel_fence: @@ -1529,6 +1554,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() { ; ; GFX11-CU-LABEL: workgroup_one_as_acq_rel_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_one_as_acq_rel_fence: @@ -1542,6 +1569,10 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() { ; ; GFX12-CU-LABEL: workgroup_one_as_acq_rel_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_one_as_acq_rel_fence: @@ -1572,6 +1603,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() { ; ; GFX10-CU-LABEL: workgroup_one_as_seq_cst_fence: ; GFX10-CU: ; %bb.0: ; %entry +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: workgroup_one_as_seq_cst_fence: @@ -1607,6 +1640,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() { ; ; GFX11-CU-LABEL: workgroup_one_as_seq_cst_fence: ; GFX11-CU: ; %bb.0: ; %entry +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: workgroup_one_as_seq_cst_fence: @@ -1620,6 +1655,10 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() { ; ; GFX12-CU-LABEL: workgroup_one_as_seq_cst_fence: ; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: workgroup_one_as_seq_cst_fence: diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll index d277441..2afa577 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll @@ -1072,7 +1072,8 @@ define amdgpu_kernel void @flat_volatile_workgroup_release_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -1109,7 +1110,8 @@ define amdgpu_kernel void @flat_volatile_workgroup_release_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -1136,7 +1138,10 @@ define amdgpu_kernel void @flat_volatile_workgroup_release_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll index 3826953..d384aec 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll @@ -656,12 +656,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_load( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -765,12 +765,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_load( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_load_b32 v2, v[0:1] -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -800,12 +800,14 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_load( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_load_b32 v2, v[0:1] -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -1193,7 +1195,8 @@ define amdgpu_kernel void @flat_workgroup_release_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -1278,7 +1281,8 @@ define amdgpu_kernel void @flat_workgroup_release_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -1305,7 +1309,10 @@ define amdgpu_kernel void @flat_workgroup_release_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -1372,7 +1379,8 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -1457,7 +1465,8 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -1484,7 +1493,10 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -1891,7 +1903,8 @@ define amdgpu_kernel void @flat_workgroup_release_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -1976,7 +1989,8 @@ define amdgpu_kernel void @flat_workgroup_release_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -2003,7 +2017,10 @@ define amdgpu_kernel void @flat_workgroup_release_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -2074,9 +2091,11 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v[0:1], v2 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_acq_rel_atomicrmw: @@ -2170,9 +2189,11 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_acq_rel_atomicrmw: @@ -2200,9 +2221,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_acq_rel_atomicrmw: @@ -2273,9 +2297,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v[0:1], v2 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_seq_cst_atomicrmw: @@ -2369,9 +2395,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_seq_cst_atomicrmw: @@ -2399,9 +2427,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_seq_cst_atomicrmw: @@ -2697,12 +2728,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v2, v[0:1], v2 glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -2813,12 +2844,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -2850,12 +2881,14 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -2935,12 +2968,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v2, v[0:1], v2 glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -3051,12 +3084,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -3088,12 +3121,14 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -3731,7 +3766,8 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_endpgm ; @@ -3854,7 +3890,8 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -3889,7 +3926,10 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -4007,9 +4047,11 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_acq_rel_monotonic_cmpxchg: @@ -4141,9 +4183,11 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_acq_rel_monotonic_cmpxchg: @@ -4179,9 +4223,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_acq_rel_monotonic_cmpxchg: @@ -4299,9 +4346,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_seq_cst_monotonic_cmpxchg: @@ -4433,9 +4482,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_seq_cst_monotonic_cmpxchg: @@ -4471,9 +4522,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_seq_cst_monotonic_cmpxchg: @@ -5137,9 +5191,11 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_release_acquire_cmpxchg: @@ -5271,9 +5327,11 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_release_acquire_cmpxchg: @@ -5309,9 +5367,12 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_release_acquire_cmpxchg: @@ -5429,9 +5490,11 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_acq_rel_acquire_cmpxchg: @@ -5563,9 +5626,11 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_acq_rel_acquire_cmpxchg: @@ -5601,9 +5666,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_acq_rel_acquire_cmpxchg: @@ -5721,9 +5789,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_seq_cst_acquire_cmpxchg: @@ -5855,9 +5925,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_seq_cst_acquire_cmpxchg: @@ -5893,9 +5965,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_seq_cst_acquire_cmpxchg: @@ -6013,9 +6088,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_seq_cst_seq_cst_cmpxchg: @@ -6147,9 +6224,11 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_seq_cst_seq_cst_cmpxchg: @@ -6185,9 +6264,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_seq_cst_seq_cst_cmpxchg: @@ -6923,7 +7005,8 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 @@ -7070,7 +7153,8 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -7113,7 +7197,10 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -7245,12 +7332,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -7399,12 +7486,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -7444,12 +7531,14 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -7577,12 +7666,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -7731,12 +7820,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -7776,12 +7865,14 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -8535,12 +8626,12 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -8689,12 +8780,12 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -8734,12 +8825,14 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -8867,12 +8960,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -9021,12 +9114,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -9066,12 +9159,14 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -9199,12 +9294,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -9353,12 +9448,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -9398,12 +9493,14 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -9531,7 +9628,8 @@ define amdgpu_kernel void @flat_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9685,7 +9783,8 @@ define amdgpu_kernel void @flat_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9730,7 +9829,10 @@ define amdgpu_kernel void @flat_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9863,7 +9965,8 @@ define amdgpu_kernel void @flat_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -10017,7 +10120,8 @@ define amdgpu_kernel void @flat_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -10062,7 +10166,10 @@ define amdgpu_kernel void @flat_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -10195,12 +10302,12 @@ define amdgpu_kernel void @flat_workgroup_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -10349,12 +10456,12 @@ define amdgpu_kernel void @flat_workgroup_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -10394,12 +10501,14 @@ define amdgpu_kernel void @flat_workgroup_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -10527,12 +10636,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -10681,12 +10790,12 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -10726,12 +10835,14 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -10859,12 +10970,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -11013,12 +11124,12 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -11058,12 +11169,14 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -11732,10 +11845,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_load( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -11834,10 +11950,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_load( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_load_b32 v2, v[0:1] +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -11868,10 +11987,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_load( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_load_b32 v2, v[0:1] +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -12258,6 +12382,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -12339,6 +12465,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -12365,6 +12493,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -12430,6 +12562,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -12511,6 +12645,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -12537,6 +12673,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -12933,6 +13073,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -13014,6 +13156,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -13040,6 +13184,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -13107,7 +13255,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v[0:1], v2 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_acq_rel_atomicrmw: @@ -13194,7 +13345,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_acq_rel_atomicrmw: @@ -13222,7 +13376,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_acq_rel_atomicrmw: @@ -13290,7 +13449,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v[0:1], v2 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_seq_cst_atomicrmw: @@ -13377,7 +13539,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_seq_cst_atomicrmw: @@ -13405,7 +13570,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s3 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v[0:1], v2 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_seq_cst_atomicrmw: @@ -13696,10 +13866,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v2, v[0:1], v2 glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -13805,10 +13978,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -13841,10 +14017,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -13923,10 +14104,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_swap v2, v[0:1], v2 glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -14032,10 +14216,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -14068,10 +14255,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_swap_b32 v2, v[0:1], v2 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -14699,6 +14891,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_endpgm ; @@ -14818,6 +15012,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -14852,6 +15048,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -14966,7 +15166,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_acq_rel_monotonic_cmpxchg: @@ -15091,7 +15294,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_acq_rel_monotonic_cmpxchg: @@ -15127,7 +15333,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_acq_rel_monotonic_cmpxchg: @@ -15242,7 +15453,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_seq_cst_monotonic_cmpxchg: @@ -15367,7 +15581,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_seq_cst_monotonic_cmpxchg: @@ -15403,7 +15620,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_seq_cst_monotonic_cmpxchg: @@ -16046,7 +16268,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_release_acquire_cmpxchg: @@ -16171,7 +16396,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_release_acquire_cmpxchg: @@ -16207,7 +16435,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_release_acquire_cmpxchg: @@ -16322,7 +16555,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_acq_rel_acquire_cmpxchg: @@ -16447,7 +16683,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_acq_rel_acquire_cmpxchg: @@ -16483,7 +16722,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_acq_rel_acquire_cmpxchg: @@ -16598,7 +16842,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_seq_cst_acquire_cmpxchg: @@ -16723,7 +16970,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_seq_cst_acquire_cmpxchg: @@ -16759,7 +17009,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_seq_cst_acquire_cmpxchg: @@ -16874,6 +17129,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_endpgm ; @@ -16999,6 +17256,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -17035,6 +17294,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -17150,6 +17413,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] ; GFX10-CU-NEXT: s_endpgm ; @@ -17275,6 +17540,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -17311,6 +17578,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -17426,7 +17697,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_release_seq_cst_cmpxchg: @@ -17551,7 +17825,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_release_seq_cst_cmpxchg: @@ -17587,7 +17864,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_release_seq_cst_cmpxchg: @@ -17702,7 +17984,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_acq_rel_seq_cst_cmpxchg: @@ -17827,7 +18112,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_acq_rel_seq_cst_cmpxchg: @@ -17863,7 +18151,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_acq_rel_seq_cst_cmpxchg: @@ -17978,7 +18271,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: flat_workgroup_one_as_seq_cst_seq_cst_cmpxchg: @@ -18103,7 +18399,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: flat_workgroup_one_as_seq_cst_seq_cst_cmpxchg: @@ -18139,7 +18438,12 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: flat_workgroup_one_as_seq_cst_seq_cst_cmpxchg: @@ -18870,6 +19174,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 @@ -19013,6 +19319,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -19055,6 +19363,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -19185,10 +19497,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -19332,10 +19647,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -19376,10 +19694,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -19506,10 +19829,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -19653,10 +19979,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -19697,10 +20026,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -20445,10 +20779,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -20592,10 +20929,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -20636,10 +20976,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -20766,10 +21111,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -20913,10 +21261,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -20957,10 +21308,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -21087,10 +21443,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -21234,10 +21593,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -21278,10 +21640,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -21408,6 +21775,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 @@ -21555,6 +21924,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -21599,6 +21970,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -21729,6 +22104,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 @@ -21876,6 +22253,8 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -21920,6 +22299,10 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 @@ -22050,10 +22433,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -22197,10 +22583,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -22241,10 +22630,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -22371,10 +22765,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -22518,10 +22915,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -22562,10 +22962,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; @@ -22692,10 +23097,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: flat_store_dword v[0:1], v2 ; GFX10-CU-NEXT: s_endpgm ; @@ -22839,10 +23247,13 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 glc +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX11-CU-NEXT: s_endpgm ; @@ -22883,10 +23294,15 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:16 th:TH_ATOMIC_RETURN +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: flat_store_b32 v[0:1], v2 ; GFX12-CU-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll index 3bf5ed8..c326edf 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll @@ -959,7 +959,8 @@ define amdgpu_kernel void @global_volatile_workgroup_release_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -1001,7 +1002,8 @@ define amdgpu_kernel void @global_volatile_workgroup_release_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -1026,7 +1028,10 @@ define amdgpu_kernel void @global_volatile_workgroup_release_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll index b755c5d..868b438 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll @@ -667,7 +667,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_load( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0 ; GFX10-CU-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x8 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_load_dword v1, v0, s[6:7] ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -763,7 +764,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_load( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_load_b64 s[2:3], s[4:5], 0x0 ; GFX11-CU-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_load_b32 v1, v0, s[2:3] ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -790,7 +792,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_load( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_load_b64 s[2:3], s[4:5], 0x0 ; GFX12-CU-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: global_load_b32 v1, v0, s[2:3] ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 @@ -1204,7 +1209,8 @@ define amdgpu_kernel void @global_workgroup_release_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -1290,7 +1296,8 @@ define amdgpu_kernel void @global_workgroup_release_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -1315,7 +1322,10 @@ define amdgpu_kernel void @global_workgroup_release_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; @@ -1391,7 +1401,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -1477,7 +1488,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -1502,7 +1514,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; @@ -1918,7 +1933,8 @@ define amdgpu_kernel void @global_workgroup_release_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -2003,7 +2019,8 @@ define amdgpu_kernel void @global_workgroup_release_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -2028,7 +2045,10 @@ define amdgpu_kernel void @global_workgroup_release_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; @@ -2105,8 +2125,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v0, v1, s[4:5] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_acq_rel_atomicrmw: @@ -2196,8 +2218,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_acq_rel_atomicrmw: @@ -2223,8 +2247,12 @@ define amdgpu_kernel void @global_workgroup_acq_rel_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_acq_rel_atomicrmw: @@ -2301,8 +2329,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v0, v1, s[4:5] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_seq_cst_atomicrmw: @@ -2392,8 +2422,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_seq_cst_atomicrmw: @@ -2419,8 +2451,12 @@ define amdgpu_kernel void @global_workgroup_seq_cst_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_seq_cst_atomicrmw: @@ -2705,7 +2741,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v1, v0, v1, s[4:5] glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -2807,7 +2844,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -2837,7 +2875,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -2926,7 +2967,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v1, v0, v1, s[4:5] glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -3028,7 +3070,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -3058,7 +3101,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -3644,7 +3690,8 @@ define amdgpu_kernel void @global_workgroup_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -3758,7 +3805,8 @@ define amdgpu_kernel void @global_workgroup_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -3791,7 +3839,10 @@ define amdgpu_kernel void @global_workgroup_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -3900,8 +3951,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_acq_rel_monotonic_cmpxchg: @@ -4020,8 +4073,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_acq_rel_monotonic_cmpxchg: @@ -4055,8 +4110,12 @@ define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_acq_rel_monotonic_cmpxchg: @@ -4165,8 +4224,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_seq_cst_monotonic_cmpxchg: @@ -4285,8 +4346,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_seq_cst_monotonic_cmpxchg: @@ -4320,8 +4383,12 @@ define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_seq_cst_monotonic_cmpxchg: @@ -4920,8 +4987,10 @@ define amdgpu_kernel void @global_workgroup_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_release_acquire_cmpxchg: @@ -5040,8 +5109,10 @@ define amdgpu_kernel void @global_workgroup_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_release_acquire_cmpxchg: @@ -5075,8 +5146,12 @@ define amdgpu_kernel void @global_workgroup_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_release_acquire_cmpxchg: @@ -5185,8 +5260,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_acq_rel_acquire_cmpxchg: @@ -5305,8 +5382,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_acq_rel_acquire_cmpxchg: @@ -5340,8 +5419,12 @@ define amdgpu_kernel void @global_workgroup_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_acq_rel_acquire_cmpxchg: @@ -5450,8 +5533,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_seq_cst_acquire_cmpxchg: @@ -5570,8 +5655,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_seq_cst_acquire_cmpxchg: @@ -5605,8 +5692,12 @@ define amdgpu_kernel void @global_workgroup_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_seq_cst_acquire_cmpxchg: @@ -5715,7 +5806,8 @@ define amdgpu_kernel void @global_workgroup_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -5835,7 +5927,8 @@ define amdgpu_kernel void @global_workgroup_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -5870,7 +5963,10 @@ define amdgpu_kernel void @global_workgroup_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -5980,7 +6076,8 @@ define amdgpu_kernel void @global_workgroup_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -6100,7 +6197,8 @@ define amdgpu_kernel void @global_workgroup_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -6135,7 +6233,10 @@ define amdgpu_kernel void @global_workgroup_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -6245,8 +6346,10 @@ define amdgpu_kernel void @global_workgroup_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_release_seq_cst_cmpxchg: @@ -6365,8 +6468,10 @@ define amdgpu_kernel void @global_workgroup_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_release_seq_cst_cmpxchg: @@ -6400,8 +6505,12 @@ define amdgpu_kernel void @global_workgroup_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_release_seq_cst_cmpxchg: @@ -6510,8 +6619,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_acq_rel_seq_cst_cmpxchg: @@ -6630,8 +6741,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_acq_rel_seq_cst_cmpxchg: @@ -6665,8 +6778,12 @@ define amdgpu_kernel void @global_workgroup_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_acq_rel_seq_cst_cmpxchg: @@ -6775,8 +6892,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_seq_cst_seq_cst_cmpxchg: @@ -6895,8 +7014,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_seq_cst_seq_cst_cmpxchg: @@ -6930,8 +7051,12 @@ define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_seq_cst_seq_cst_cmpxchg: @@ -7588,7 +7713,8 @@ define amdgpu_kernel void @global_workgroup_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -7717,7 +7843,8 @@ define amdgpu_kernel void @global_workgroup_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -7754,7 +7881,10 @@ define amdgpu_kernel void @global_workgroup_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -7877,7 +8007,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -8009,7 +8140,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -8047,7 +8179,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -8170,7 +8305,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -8302,7 +8438,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -8340,7 +8477,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9009,7 +9149,8 @@ define amdgpu_kernel void @global_workgroup_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -9141,7 +9282,8 @@ define amdgpu_kernel void @global_workgroup_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9179,7 +9321,10 @@ define amdgpu_kernel void @global_workgroup_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9302,7 +9447,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -9434,7 +9580,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9472,7 +9619,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9595,7 +9745,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -9727,7 +9878,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9765,7 +9917,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -9888,7 +10043,8 @@ define amdgpu_kernel void @global_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -10020,7 +10176,8 @@ define amdgpu_kernel void @global_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10058,7 +10215,10 @@ define amdgpu_kernel void @global_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10181,7 +10341,8 @@ define amdgpu_kernel void @global_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -10313,7 +10474,8 @@ define amdgpu_kernel void @global_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10351,7 +10513,10 @@ define amdgpu_kernel void @global_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10474,7 +10639,8 @@ define amdgpu_kernel void @global_workgroup_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -10606,7 +10772,8 @@ define amdgpu_kernel void @global_workgroup_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10644,7 +10811,10 @@ define amdgpu_kernel void @global_workgroup_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10767,7 +10937,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -10899,7 +11070,8 @@ define amdgpu_kernel void @global_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -10937,7 +11109,10 @@ define amdgpu_kernel void @global_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -11060,7 +11235,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -11192,7 +11368,8 @@ define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -11230,7 +11407,10 @@ define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -11914,7 +12094,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_load( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0 ; GFX10-CU-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x8 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_load_dword v1, v0, s[6:7] ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -12009,7 +12190,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_load( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_load_b64 s[2:3], s[4:5], 0x0 ; GFX11-CU-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_load_b32 v1, v0, s[2:3] ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -12036,6 +12218,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_load( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_load_b64 s[2:3], s[4:5], 0x0 ; GFX12-CU-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: global_load_b32 v1, v0, s[2:3] ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 @@ -12447,6 +12633,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -12529,6 +12717,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -12553,6 +12743,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; @@ -12626,6 +12820,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_store( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -12708,6 +12904,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_store( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -12732,6 +12930,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_store( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; @@ -13145,6 +13347,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v0, v1, s[4:5] ; GFX10-CU-NEXT: s_endpgm ; @@ -13226,6 +13430,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] ; GFX11-CU-NEXT: s_endpgm ; @@ -13250,6 +13456,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] ; GFX12-CU-NEXT: s_endpgm ; @@ -13324,7 +13534,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v0, v1, s[4:5] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_acq_rel_atomicrmw: @@ -13411,7 +13624,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_acq_rel_atomicrmw: @@ -13437,7 +13653,12 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_acq_rel_atomicrmw: @@ -13512,7 +13733,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v0, v1, s[4:5] +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_seq_cst_atomicrmw: @@ -13599,7 +13823,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_seq_cst_atomicrmw: @@ -13625,7 +13852,12 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_seq_cst_atomicrmw: @@ -13908,6 +14140,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v1, v0, v1, s[4:5] glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -14006,6 +14240,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -14035,6 +14271,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -14121,6 +14361,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: s_load_dword s6, s[8:9], 0x8 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_swap v1, v0, v1, s[4:5] glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -14219,6 +14461,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -14248,6 +14492,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: s_load_b32 s2, s[4:5], 0x8 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -14831,6 +15079,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -14941,6 +15191,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -14973,6 +15225,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -15079,7 +15335,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_acq_rel_monotonic_cmpxchg: @@ -15195,7 +15454,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_acq_rel_monotonic_cmpxchg: @@ -15229,7 +15491,12 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_acq_rel_monotonic_cmpxchg: @@ -15336,7 +15603,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_seq_cst_monotonic_cmpxchg: @@ -15452,7 +15722,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_seq_cst_monotonic_cmpxchg: @@ -15486,7 +15759,12 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_seq_cst_monotonic_cmpxchg: @@ -16083,7 +16361,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_release_acquire_cmpxchg: @@ -16199,7 +16480,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_release_acquire_cmpxchg: @@ -16233,7 +16517,12 @@ define amdgpu_kernel void @global_workgroup_one_as_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_release_acquire_cmpxchg: @@ -16340,7 +16629,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_acq_rel_acquire_cmpxchg: @@ -16456,7 +16748,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_acq_rel_acquire_cmpxchg: @@ -16490,7 +16785,12 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_acq_rel_acquire_cmpxchg: @@ -16597,7 +16897,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_seq_cst_acquire_cmpxchg: @@ -16713,7 +17016,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_seq_cst_acquire_cmpxchg: @@ -16747,7 +17053,12 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_seq_cst_acquire_cmpxchg: @@ -16854,6 +17165,8 @@ define amdgpu_kernel void @global_workgroup_one_as_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -16970,6 +17283,8 @@ define amdgpu_kernel void @global_workgroup_one_as_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -17004,6 +17319,10 @@ define amdgpu_kernel void @global_workgroup_one_as_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -17111,6 +17430,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -17227,6 +17548,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -17261,6 +17584,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -17368,7 +17695,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_release_seq_cst_cmpxchg: @@ -17484,7 +17814,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_release_seq_cst_cmpxchg: @@ -17518,7 +17851,12 @@ define amdgpu_kernel void @global_workgroup_one_as_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_release_seq_cst_cmpxchg: @@ -17625,7 +17963,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_acq_rel_seq_cst_cmpxchg: @@ -17741,7 +18082,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_acq_rel_seq_cst_cmpxchg: @@ -17775,7 +18119,12 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_acq_rel_seq_cst_cmpxchg: @@ -17882,7 +18231,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v0, v[1:2], s[4:5] offset:16 +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: s_endpgm ; ; SKIP-CACHE-INV-LABEL: global_workgroup_one_as_seq_cst_seq_cst_cmpxchg: @@ -17998,7 +18350,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: s_endpgm ; ; GFX12-WGP-LABEL: global_workgroup_one_as_seq_cst_seq_cst_cmpxchg: @@ -18032,7 +18387,12 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v0, v[1:2], s[0:1] offset:16 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: s_endpgm ; ; GFX1250-LABEL: global_workgroup_one_as_seq_cst_seq_cst_cmpxchg: @@ -18687,6 +19047,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_ret_cmpxchg ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -18812,6 +19174,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_ret_cmpxchg ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -18848,6 +19212,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_ret_cmpxchg ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -18968,6 +19336,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -19096,6 +19466,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -19133,6 +19505,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -19253,6 +19629,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -19381,6 +19759,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -19418,6 +19798,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20084,6 +20468,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -20212,6 +20598,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20249,6 +20637,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20369,6 +20761,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -20497,6 +20891,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20534,6 +20930,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20654,6 +21054,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -20782,6 +21184,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20819,6 +21223,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -20939,6 +21347,8 @@ define amdgpu_kernel void @global_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -21067,6 +21477,8 @@ define amdgpu_kernel void @global_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21104,6 +21516,10 @@ define amdgpu_kernel void @global_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21224,6 +21640,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -21352,6 +21770,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21389,6 +21809,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21509,6 +21933,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -21637,6 +22063,8 @@ define amdgpu_kernel void @global_workgroup_one_as_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21674,6 +22102,10 @@ define amdgpu_kernel void @global_workgroup_one_as_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21794,6 +22226,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -21922,6 +22356,8 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -21959,6 +22395,10 @@ define amdgpu_kernel void @global_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -22079,6 +22519,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v3, s6 ; GFX10-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX10-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: global_atomic_cmpswap v1, v0, v[1:2], s[4:5] offset:16 glc ; GFX10-CU-NEXT: s_waitcnt vmcnt(0) ; GFX10-CU-NEXT: global_store_dword v0, v1, s[4:5] @@ -22207,6 +22649,8 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX11-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX11-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 glc ; GFX11-CU-NEXT: s_waitcnt vmcnt(0) ; GFX11-CU-NEXT: global_store_b32 v0, v1, s[0:1] @@ -22244,6 +22688,10 @@ define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v3, s2 ; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec ; GFX12-CU-NEXT: v_mov_b32_e32 v2, v3 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 ; GFX12-CU-NEXT: global_atomic_cmpswap_b32 v1, v0, v[1:2], s[0:1] offset:16 th:TH_ATOMIC_RETURN ; GFX12-CU-NEXT: s_wait_loadcnt 0x0 ; GFX12-CU-NEXT: global_store_b32 v0, v1, s[0:1] diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll index 986b48b..712109d 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll @@ -622,7 +622,8 @@ define amdgpu_kernel void @local_agent_seq_cst_load( ; GFX10-CU-NEXT: s_load_dword s4, s[8:9], 0x4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_read_b32 v1, v0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -719,7 +720,8 @@ define amdgpu_kernel void @local_agent_seq_cst_load( ; GFX11-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_load_b32 v1, v0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -749,7 +751,10 @@ define amdgpu_kernel void @local_agent_seq_cst_load( ; GFX12-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_load_b32 v1, v0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -1121,7 +1126,8 @@ define amdgpu_kernel void @local_agent_release_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1200,7 +1206,8 @@ define amdgpu_kernel void @local_agent_release_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1225,7 +1232,10 @@ define amdgpu_kernel void @local_agent_release_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1291,7 +1301,8 @@ define amdgpu_kernel void @local_agent_seq_cst_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1370,7 +1381,8 @@ define amdgpu_kernel void @local_agent_seq_cst_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1395,7 +1407,10 @@ define amdgpu_kernel void @local_agent_seq_cst_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1778,7 +1793,8 @@ define amdgpu_kernel void @local_agent_release_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1857,7 +1873,8 @@ define amdgpu_kernel void @local_agent_release_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1882,7 +1899,10 @@ define amdgpu_kernel void @local_agent_release_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1952,7 +1972,8 @@ define amdgpu_kernel void @local_agent_acq_rel_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2039,7 +2060,8 @@ define amdgpu_kernel void @local_agent_acq_rel_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2067,7 +2089,10 @@ define amdgpu_kernel void @local_agent_acq_rel_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2139,7 +2164,8 @@ define amdgpu_kernel void @local_agent_seq_cst_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2226,7 +2252,8 @@ define amdgpu_kernel void @local_agent_seq_cst_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2254,7 +2281,10 @@ define amdgpu_kernel void @local_agent_seq_cst_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2535,7 +2565,8 @@ define amdgpu_kernel void @local_agent_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2639,7 +2670,8 @@ define amdgpu_kernel void @local_agent_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2671,7 +2703,10 @@ define amdgpu_kernel void @local_agent_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2756,7 +2791,8 @@ define amdgpu_kernel void @local_agent_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2860,7 +2896,8 @@ define amdgpu_kernel void @local_agent_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2892,7 +2929,10 @@ define amdgpu_kernel void @local_agent_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -3348,7 +3388,8 @@ define amdgpu_kernel void @local_agent_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -3441,7 +3482,8 @@ define amdgpu_kernel void @local_agent_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -3470,7 +3512,10 @@ define amdgpu_kernel void @local_agent_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -3551,7 +3596,8 @@ define amdgpu_kernel void @local_agent_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3652,7 +3698,8 @@ define amdgpu_kernel void @local_agent_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3684,7 +3731,10 @@ define amdgpu_kernel void @local_agent_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -3767,7 +3817,8 @@ define amdgpu_kernel void @local_agent_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3868,7 +3919,8 @@ define amdgpu_kernel void @local_agent_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3900,7 +3952,10 @@ define amdgpu_kernel void @local_agent_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4375,7 +4430,8 @@ define amdgpu_kernel void @local_agent_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4476,7 +4532,8 @@ define amdgpu_kernel void @local_agent_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4508,7 +4565,10 @@ define amdgpu_kernel void @local_agent_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4591,7 +4651,8 @@ define amdgpu_kernel void @local_agent_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4692,7 +4753,8 @@ define amdgpu_kernel void @local_agent_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4724,7 +4786,10 @@ define amdgpu_kernel void @local_agent_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4807,7 +4872,8 @@ define amdgpu_kernel void @local_agent_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4908,7 +4974,8 @@ define amdgpu_kernel void @local_agent_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4940,7 +5007,10 @@ define amdgpu_kernel void @local_agent_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5023,7 +5093,8 @@ define amdgpu_kernel void @local_agent_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5124,7 +5195,8 @@ define amdgpu_kernel void @local_agent_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5156,7 +5228,10 @@ define amdgpu_kernel void @local_agent_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5239,7 +5314,8 @@ define amdgpu_kernel void @local_agent_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5340,7 +5416,8 @@ define amdgpu_kernel void @local_agent_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5372,7 +5449,10 @@ define amdgpu_kernel void @local_agent_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5455,7 +5535,8 @@ define amdgpu_kernel void @local_agent_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5556,7 +5637,8 @@ define amdgpu_kernel void @local_agent_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5588,7 +5670,10 @@ define amdgpu_kernel void @local_agent_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5671,7 +5756,8 @@ define amdgpu_kernel void @local_agent_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5772,7 +5858,8 @@ define amdgpu_kernel void @local_agent_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5804,7 +5891,10 @@ define amdgpu_kernel void @local_agent_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5887,7 +5977,8 @@ define amdgpu_kernel void @local_agent_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5988,7 +6079,8 @@ define amdgpu_kernel void @local_agent_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -6020,7 +6112,10 @@ define amdgpu_kernel void @local_agent_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -6567,7 +6662,8 @@ define amdgpu_kernel void @local_agent_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6682,7 +6778,8 @@ define amdgpu_kernel void @local_agent_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6717,7 +6814,10 @@ define amdgpu_kernel void @local_agent_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 @@ -6814,7 +6914,8 @@ define amdgpu_kernel void @local_agent_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -6932,7 +7033,8 @@ define amdgpu_kernel void @local_agent_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -6968,7 +7070,10 @@ define amdgpu_kernel void @local_agent_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7065,7 +7170,8 @@ define amdgpu_kernel void @local_agent_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7183,7 +7289,8 @@ define amdgpu_kernel void @local_agent_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7219,7 +7326,10 @@ define amdgpu_kernel void @local_agent_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7778,7 +7888,8 @@ define amdgpu_kernel void @local_agent_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7896,7 +8007,8 @@ define amdgpu_kernel void @local_agent_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7932,7 +8044,10 @@ define amdgpu_kernel void @local_agent_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8029,7 +8144,8 @@ define amdgpu_kernel void @local_agent_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8147,7 +8263,8 @@ define amdgpu_kernel void @local_agent_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8183,7 +8300,10 @@ define amdgpu_kernel void @local_agent_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8280,7 +8400,8 @@ define amdgpu_kernel void @local_agent_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8398,7 +8519,8 @@ define amdgpu_kernel void @local_agent_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8434,7 +8556,10 @@ define amdgpu_kernel void @local_agent_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8531,7 +8656,8 @@ define amdgpu_kernel void @local_agent_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8649,7 +8775,8 @@ define amdgpu_kernel void @local_agent_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8685,7 +8812,10 @@ define amdgpu_kernel void @local_agent_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8782,7 +8912,8 @@ define amdgpu_kernel void @local_agent_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8900,7 +9031,8 @@ define amdgpu_kernel void @local_agent_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8936,7 +9068,10 @@ define amdgpu_kernel void @local_agent_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9033,7 +9168,8 @@ define amdgpu_kernel void @local_agent_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9151,7 +9287,8 @@ define amdgpu_kernel void @local_agent_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9187,7 +9324,10 @@ define amdgpu_kernel void @local_agent_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9284,7 +9424,8 @@ define amdgpu_kernel void @local_agent_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9402,7 +9543,8 @@ define amdgpu_kernel void @local_agent_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9438,7 +9580,10 @@ define amdgpu_kernel void @local_agent_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9535,7 +9680,8 @@ define amdgpu_kernel void @local_agent_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9653,7 +9799,8 @@ define amdgpu_kernel void @local_agent_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9689,7 +9836,10 @@ define amdgpu_kernel void @local_agent_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll index 8926893..6d1e4e6 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll @@ -622,7 +622,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_load( ; GFX10-CU-NEXT: s_load_dword s4, s[8:9], 0x4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_read_b32 v1, v0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -719,7 +720,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_load( ; GFX11-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_load_b32 v1, v0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -749,7 +751,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_load( ; GFX12-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_load_b32 v1, v0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -1121,7 +1126,8 @@ define amdgpu_kernel void @local_cluster_release_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1200,7 +1206,8 @@ define amdgpu_kernel void @local_cluster_release_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1225,7 +1232,10 @@ define amdgpu_kernel void @local_cluster_release_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1291,7 +1301,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1370,7 +1381,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1395,7 +1407,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1778,7 +1793,8 @@ define amdgpu_kernel void @local_cluster_release_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1857,7 +1873,8 @@ define amdgpu_kernel void @local_cluster_release_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1882,7 +1899,10 @@ define amdgpu_kernel void @local_cluster_release_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1952,7 +1972,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2039,7 +2060,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2067,7 +2089,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2139,7 +2164,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2226,7 +2252,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2254,7 +2281,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2535,7 +2565,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2639,7 +2670,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2671,7 +2703,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2756,7 +2791,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2860,7 +2896,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2892,7 +2929,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -3348,7 +3388,8 @@ define amdgpu_kernel void @local_cluster_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -3441,7 +3482,8 @@ define amdgpu_kernel void @local_cluster_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -3470,7 +3512,10 @@ define amdgpu_kernel void @local_cluster_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -3551,7 +3596,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3652,7 +3698,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3684,7 +3731,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -3767,7 +3817,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3868,7 +3919,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3900,7 +3952,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4375,7 +4430,8 @@ define amdgpu_kernel void @local_cluster_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4476,7 +4532,8 @@ define amdgpu_kernel void @local_cluster_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4508,7 +4565,10 @@ define amdgpu_kernel void @local_cluster_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4591,7 +4651,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4692,7 +4753,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4724,7 +4786,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4807,7 +4872,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4908,7 +4974,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4940,7 +5007,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5023,7 +5093,8 @@ define amdgpu_kernel void @local_cluster_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5124,7 +5195,8 @@ define amdgpu_kernel void @local_cluster_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5156,7 +5228,10 @@ define amdgpu_kernel void @local_cluster_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5239,7 +5314,8 @@ define amdgpu_kernel void @local_cluster_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5340,7 +5416,8 @@ define amdgpu_kernel void @local_cluster_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5372,7 +5449,10 @@ define amdgpu_kernel void @local_cluster_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5455,7 +5535,8 @@ define amdgpu_kernel void @local_cluster_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5556,7 +5637,8 @@ define amdgpu_kernel void @local_cluster_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5588,7 +5670,10 @@ define amdgpu_kernel void @local_cluster_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5671,7 +5756,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5772,7 +5858,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5804,7 +5891,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5887,7 +5977,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5988,7 +6079,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -6020,7 +6112,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -6567,7 +6662,8 @@ define amdgpu_kernel void @local_cluster_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6682,7 +6778,8 @@ define amdgpu_kernel void @local_cluster_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6717,7 +6814,10 @@ define amdgpu_kernel void @local_cluster_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 @@ -6814,7 +6914,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -6932,7 +7033,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -6968,7 +7070,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7065,7 +7170,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7183,7 +7289,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7219,7 +7326,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7778,7 +7888,8 @@ define amdgpu_kernel void @local_cluster_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7896,7 +8007,8 @@ define amdgpu_kernel void @local_cluster_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7932,7 +8044,10 @@ define amdgpu_kernel void @local_cluster_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8029,7 +8144,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8147,7 +8263,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8183,7 +8300,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8280,7 +8400,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8398,7 +8519,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8434,7 +8556,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8531,7 +8656,8 @@ define amdgpu_kernel void @local_cluster_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8649,7 +8775,8 @@ define amdgpu_kernel void @local_cluster_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8685,7 +8812,10 @@ define amdgpu_kernel void @local_cluster_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8782,7 +8912,8 @@ define amdgpu_kernel void @local_cluster_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8900,7 +9031,8 @@ define amdgpu_kernel void @local_cluster_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8936,7 +9068,10 @@ define amdgpu_kernel void @local_cluster_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9033,7 +9168,8 @@ define amdgpu_kernel void @local_cluster_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9151,7 +9287,8 @@ define amdgpu_kernel void @local_cluster_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9187,7 +9324,10 @@ define amdgpu_kernel void @local_cluster_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9284,7 +9424,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9402,7 +9543,8 @@ define amdgpu_kernel void @local_cluster_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9438,7 +9580,10 @@ define amdgpu_kernel void @local_cluster_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9535,7 +9680,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9653,7 +9799,8 @@ define amdgpu_kernel void @local_cluster_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9689,7 +9836,10 @@ define amdgpu_kernel void @local_cluster_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll index 81bbe0a..577d2ca 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll @@ -622,7 +622,8 @@ define amdgpu_kernel void @local_system_seq_cst_load( ; GFX10-CU-NEXT: s_load_dword s4, s[8:9], 0x4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_read_b32 v1, v0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -719,7 +720,8 @@ define amdgpu_kernel void @local_system_seq_cst_load( ; GFX11-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_load_b32 v1, v0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -749,7 +751,10 @@ define amdgpu_kernel void @local_system_seq_cst_load( ; GFX12-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_load_b32 v1, v0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -1121,7 +1126,8 @@ define amdgpu_kernel void @local_system_release_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1200,7 +1206,8 @@ define amdgpu_kernel void @local_system_release_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1225,7 +1232,10 @@ define amdgpu_kernel void @local_system_release_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1291,7 +1301,8 @@ define amdgpu_kernel void @local_system_seq_cst_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1370,7 +1381,8 @@ define amdgpu_kernel void @local_system_seq_cst_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1395,7 +1407,10 @@ define amdgpu_kernel void @local_system_seq_cst_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1778,7 +1793,8 @@ define amdgpu_kernel void @local_system_release_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1857,7 +1873,8 @@ define amdgpu_kernel void @local_system_release_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1882,7 +1899,10 @@ define amdgpu_kernel void @local_system_release_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1952,7 +1972,8 @@ define amdgpu_kernel void @local_system_acq_rel_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2039,7 +2060,8 @@ define amdgpu_kernel void @local_system_acq_rel_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2067,7 +2089,10 @@ define amdgpu_kernel void @local_system_acq_rel_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2139,7 +2164,8 @@ define amdgpu_kernel void @local_system_seq_cst_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2226,7 +2252,8 @@ define amdgpu_kernel void @local_system_seq_cst_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2254,7 +2281,10 @@ define amdgpu_kernel void @local_system_seq_cst_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2535,7 +2565,8 @@ define amdgpu_kernel void @local_system_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2639,7 +2670,8 @@ define amdgpu_kernel void @local_system_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2671,7 +2703,10 @@ define amdgpu_kernel void @local_system_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2756,7 +2791,8 @@ define amdgpu_kernel void @local_system_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2860,7 +2896,8 @@ define amdgpu_kernel void @local_system_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2892,7 +2929,10 @@ define amdgpu_kernel void @local_system_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -3348,7 +3388,8 @@ define amdgpu_kernel void @local_system_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -3441,7 +3482,8 @@ define amdgpu_kernel void @local_system_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -3470,7 +3512,10 @@ define amdgpu_kernel void @local_system_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -3551,7 +3596,8 @@ define amdgpu_kernel void @local_system_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3652,7 +3698,8 @@ define amdgpu_kernel void @local_system_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3684,7 +3731,10 @@ define amdgpu_kernel void @local_system_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -3767,7 +3817,8 @@ define amdgpu_kernel void @local_system_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3868,7 +3919,8 @@ define amdgpu_kernel void @local_system_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3900,7 +3952,10 @@ define amdgpu_kernel void @local_system_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4375,7 +4430,8 @@ define amdgpu_kernel void @local_system_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4476,7 +4532,8 @@ define amdgpu_kernel void @local_system_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4508,7 +4565,10 @@ define amdgpu_kernel void @local_system_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4591,7 +4651,8 @@ define amdgpu_kernel void @local_system_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4692,7 +4753,8 @@ define amdgpu_kernel void @local_system_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4724,7 +4786,10 @@ define amdgpu_kernel void @local_system_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4807,7 +4872,8 @@ define amdgpu_kernel void @local_system_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4908,7 +4974,8 @@ define amdgpu_kernel void @local_system_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4940,7 +5007,10 @@ define amdgpu_kernel void @local_system_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5023,7 +5093,8 @@ define amdgpu_kernel void @local_system_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5124,7 +5195,8 @@ define amdgpu_kernel void @local_system_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5156,7 +5228,10 @@ define amdgpu_kernel void @local_system_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5239,7 +5314,8 @@ define amdgpu_kernel void @local_system_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5340,7 +5416,8 @@ define amdgpu_kernel void @local_system_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5372,7 +5449,10 @@ define amdgpu_kernel void @local_system_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5455,7 +5535,8 @@ define amdgpu_kernel void @local_system_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5556,7 +5637,8 @@ define amdgpu_kernel void @local_system_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5588,7 +5670,10 @@ define amdgpu_kernel void @local_system_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5671,7 +5756,8 @@ define amdgpu_kernel void @local_system_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5772,7 +5858,8 @@ define amdgpu_kernel void @local_system_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5804,7 +5891,10 @@ define amdgpu_kernel void @local_system_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5887,7 +5977,8 @@ define amdgpu_kernel void @local_system_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5988,7 +6079,8 @@ define amdgpu_kernel void @local_system_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -6020,7 +6112,10 @@ define amdgpu_kernel void @local_system_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -6567,7 +6662,8 @@ define amdgpu_kernel void @local_system_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6682,7 +6778,8 @@ define amdgpu_kernel void @local_system_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6717,7 +6814,10 @@ define amdgpu_kernel void @local_system_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 @@ -6814,7 +6914,8 @@ define amdgpu_kernel void @local_system_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -6932,7 +7033,8 @@ define amdgpu_kernel void @local_system_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -6968,7 +7070,10 @@ define amdgpu_kernel void @local_system_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7065,7 +7170,8 @@ define amdgpu_kernel void @local_system_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7183,7 +7289,8 @@ define amdgpu_kernel void @local_system_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7219,7 +7326,10 @@ define amdgpu_kernel void @local_system_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7778,7 +7888,8 @@ define amdgpu_kernel void @local_system_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7896,7 +8007,8 @@ define amdgpu_kernel void @local_system_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7932,7 +8044,10 @@ define amdgpu_kernel void @local_system_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8029,7 +8144,8 @@ define amdgpu_kernel void @local_system_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8147,7 +8263,8 @@ define amdgpu_kernel void @local_system_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8183,7 +8300,10 @@ define amdgpu_kernel void @local_system_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8280,7 +8400,8 @@ define amdgpu_kernel void @local_system_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8398,7 +8519,8 @@ define amdgpu_kernel void @local_system_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8434,7 +8556,10 @@ define amdgpu_kernel void @local_system_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8531,7 +8656,8 @@ define amdgpu_kernel void @local_system_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8649,7 +8775,8 @@ define amdgpu_kernel void @local_system_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8685,7 +8812,10 @@ define amdgpu_kernel void @local_system_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8782,7 +8912,8 @@ define amdgpu_kernel void @local_system_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8900,7 +9031,8 @@ define amdgpu_kernel void @local_system_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8936,7 +9068,10 @@ define amdgpu_kernel void @local_system_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9033,7 +9168,8 @@ define amdgpu_kernel void @local_system_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9151,7 +9287,8 @@ define amdgpu_kernel void @local_system_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9187,7 +9324,10 @@ define amdgpu_kernel void @local_system_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9284,7 +9424,8 @@ define amdgpu_kernel void @local_system_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9402,7 +9543,8 @@ define amdgpu_kernel void @local_system_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9438,7 +9580,10 @@ define amdgpu_kernel void @local_system_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9535,7 +9680,8 @@ define amdgpu_kernel void @local_system_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9653,7 +9799,8 @@ define amdgpu_kernel void @local_system_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9689,7 +9836,10 @@ define amdgpu_kernel void @local_system_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll index 980141a..d686e7a 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll @@ -819,7 +819,8 @@ define amdgpu_kernel void @local_volatile_workgroup_release_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -854,7 +855,8 @@ define amdgpu_kernel void @local_volatile_workgroup_release_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -879,7 +881,10 @@ define amdgpu_kernel void @local_volatile_workgroup_release_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll index 6a233a2..ab4d783 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll @@ -622,7 +622,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_load( ; GFX10-CU-NEXT: s_load_dword s4, s[8:9], 0x4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_read_b32 v1, v0 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -719,7 +720,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_load( ; GFX11-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_load_b32 v1, v0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -749,7 +751,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_load( ; GFX12-CU-NEXT: s_load_b32 s0, s[4:5], 0x4 ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_load_b32 v1, v0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -1121,7 +1126,8 @@ define amdgpu_kernel void @local_workgroup_release_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1200,7 +1206,8 @@ define amdgpu_kernel void @local_workgroup_release_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1225,7 +1232,10 @@ define amdgpu_kernel void @local_workgroup_release_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1291,7 +1301,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_store( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_write_b32 v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1370,7 +1381,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_store( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_store_b32 v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1395,7 +1407,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_store( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_store_b32 v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1778,7 +1793,8 @@ define amdgpu_kernel void @local_workgroup_release_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_endpgm ; @@ -1857,7 +1873,8 @@ define amdgpu_kernel void @local_workgroup_release_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_endpgm ; @@ -1882,7 +1899,10 @@ define amdgpu_kernel void @local_workgroup_release_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_endpgm ; @@ -1952,7 +1972,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2039,7 +2060,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2067,7 +2089,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2139,7 +2164,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v0, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -2226,7 +2252,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -2254,7 +2281,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v0, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -2535,7 +2565,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2639,7 +2670,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2671,7 +2703,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2756,7 +2791,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_ret_atomicrmw( ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_wrxchg_rtn_b32 v1, v0, v1 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -2860,7 +2896,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_ret_atomicrmw( ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -2892,7 +2929,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_ret_atomicrmw( ; GFX12-CU-NEXT: s_wait_kmcnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_storexchg_rtn_b32 v1, v0, v1 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -3348,7 +3388,8 @@ define amdgpu_kernel void @local_workgroup_release_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_endpgm ; @@ -3441,7 +3482,8 @@ define amdgpu_kernel void @local_workgroup_release_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_endpgm ; @@ -3470,7 +3512,10 @@ define amdgpu_kernel void @local_workgroup_release_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_endpgm ; @@ -3551,7 +3596,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3652,7 +3698,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3684,7 +3731,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -3767,7 +3817,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -3868,7 +3919,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -3900,7 +3952,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4375,7 +4430,8 @@ define amdgpu_kernel void @local_workgroup_release_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4476,7 +4532,8 @@ define amdgpu_kernel void @local_workgroup_release_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4508,7 +4565,10 @@ define amdgpu_kernel void @local_workgroup_release_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4591,7 +4651,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4692,7 +4753,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4724,7 +4786,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -4807,7 +4872,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_acquire_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -4908,7 +4974,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_acquire_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -4940,7 +5007,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_acquire_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5023,7 +5093,8 @@ define amdgpu_kernel void @local_workgroup_monotonic_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5124,7 +5195,8 @@ define amdgpu_kernel void @local_workgroup_monotonic_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5156,7 +5228,10 @@ define amdgpu_kernel void @local_workgroup_monotonic_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5239,7 +5314,8 @@ define amdgpu_kernel void @local_workgroup_acquire_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5340,7 +5416,8 @@ define amdgpu_kernel void @local_workgroup_acquire_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5372,7 +5449,10 @@ define amdgpu_kernel void @local_workgroup_acquire_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5455,7 +5535,8 @@ define amdgpu_kernel void @local_workgroup_release_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5556,7 +5637,8 @@ define amdgpu_kernel void @local_workgroup_release_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5588,7 +5670,10 @@ define amdgpu_kernel void @local_workgroup_release_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5671,7 +5756,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5772,7 +5858,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -5804,7 +5891,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -5887,7 +5977,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_b32 v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: s_endpgm @@ -5988,7 +6079,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: s_endpgm @@ -6020,7 +6112,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s1 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s0 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_b32 v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: s_endpgm @@ -6567,7 +6662,8 @@ define amdgpu_kernel void @local_workgroup_release_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6682,7 +6778,8 @@ define amdgpu_kernel void @local_workgroup_release_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) @@ -6717,7 +6814,10 @@ define amdgpu_kernel void @local_workgroup_release_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 @@ -6814,7 +6914,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -6932,7 +7033,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -6968,7 +7070,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7065,7 +7170,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7183,7 +7289,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7219,7 +7326,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7778,7 +7888,8 @@ define amdgpu_kernel void @local_workgroup_release_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -7896,7 +8007,8 @@ define amdgpu_kernel void @local_workgroup_release_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -7932,7 +8044,10 @@ define amdgpu_kernel void @local_workgroup_release_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8029,7 +8144,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8147,7 +8263,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8183,7 +8300,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8280,7 +8400,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8398,7 +8519,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8434,7 +8556,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_acquire_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8531,7 +8656,8 @@ define amdgpu_kernel void @local_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8649,7 +8775,8 @@ define amdgpu_kernel void @local_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8685,7 +8812,10 @@ define amdgpu_kernel void @local_workgroup_monotonic_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8782,7 +8912,8 @@ define amdgpu_kernel void @local_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -8900,7 +9031,8 @@ define amdgpu_kernel void @local_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -8936,7 +9068,10 @@ define amdgpu_kernel void @local_workgroup_acquire_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9033,7 +9168,8 @@ define amdgpu_kernel void @local_workgroup_release_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9151,7 +9287,8 @@ define amdgpu_kernel void @local_workgroup_release_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9187,7 +9324,10 @@ define amdgpu_kernel void @local_workgroup_release_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9284,7 +9424,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9402,7 +9543,8 @@ define amdgpu_kernel void @local_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9438,7 +9580,10 @@ define amdgpu_kernel void @local_workgroup_acq_rel_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9535,7 +9680,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-CU-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-CU-NEXT: v_mov_b32_e32 v2, s5 -; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-CU-NEXT: ds_cmpst_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-CU-NEXT: v_mov_b32_e32 v0, s4 @@ -9653,7 +9799,8 @@ define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX11-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-CU-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-CU-NEXT: v_mov_b32_e32 v0, s0 @@ -9689,7 +9836,10 @@ define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_ret_cmpxchg( ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2 ; GFX12-CU-NEXT: v_mov_b32_e32 v2, s1 -; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_storecnt 0x0 +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-CU-NEXT: ds_cmpstore_rtn_b32 v1, v0, v1, v2 offset:16 ; GFX12-CU-NEXT: s_wait_dscnt 0x0 ; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir new file mode 100644 index 0000000..93f7bcc --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir @@ -0,0 +1,83 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=postmisched -o - %s | FileCheck %s + +# Ensure WMMA operations stay before the final atomic fence and barrier group. +# This allows the latency of the WMMA operations to be hidden by barrier wait. +--- +name: test +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0, $sgpr12, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr40, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8, $vgpr9_vgpr10_vgpr11_vgpr12, $vgpr13_vgpr14_vgpr15_vgpr16, $vgpr17_vgpr18_vgpr19_vgpr20, $vgpr21_vgpr22_vgpr23_vgpr24, $vgpr25_vgpr26_vgpr27_vgpr28, $vgpr29_vgpr30_vgpr31_vgpr32 + + ; CHECK-LABEL: name: test + ; CHECK: liveins: $sgpr0, $sgpr12, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr40, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8, $vgpr9_vgpr10_vgpr11_vgpr12, $vgpr13_vgpr14_vgpr15_vgpr16, $vgpr17_vgpr18_vgpr19_vgpr20, $vgpr21_vgpr22_vgpr23_vgpr24, $vgpr25_vgpr26_vgpr27_vgpr28, $vgpr29_vgpr30_vgpr31_vgpr32 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: ATOMIC_FENCE 5, 2 + ; CHECK-NEXT: S_BARRIER + ; CHECK-NEXT: ATOMIC_FENCE 4, 2 + ; CHECK-NEXT: BUNDLE implicit-def $vgpr41_vgpr42_vgpr43_vgpr44, implicit-def $vgpr41, implicit-def $vgpr41_lo16, implicit-def $vgpr41_hi16, implicit-def $vgpr42, implicit-def $vgpr42_lo16, implicit-def $vgpr42_hi16, implicit-def $vgpr43, implicit-def $vgpr43_lo16, implicit-def $vgpr43_hi16, implicit-def $vgpr44, implicit-def $vgpr44_lo16, implicit-def $vgpr44_hi16, implicit-def $vgpr41_vgpr42, implicit-def $vgpr41_vgpr42_vgpr43, implicit-def $vgpr42_vgpr43, implicit-def $vgpr42_vgpr43_vgpr44, implicit-def $vgpr43_vgpr44, implicit-def $vgpr45_vgpr46_vgpr47_vgpr48, implicit-def $vgpr45, implicit-def $vgpr45_lo16, implicit-def $vgpr45_hi16, implicit-def $vgpr46, implicit-def $vgpr46_lo16, implicit-def $vgpr46_hi16, implicit-def $vgpr47, implicit-def $vgpr47_lo16, implicit-def $vgpr47_hi16, implicit-def $vgpr48, implicit-def $vgpr48_lo16, implicit-def $vgpr48_hi16, implicit-def $vgpr45_vgpr46, implicit-def $vgpr45_vgpr46_vgpr47, implicit-def $vgpr46_vgpr47, implicit-def $vgpr46_vgpr47_vgpr48, implicit-def $vgpr47_vgpr48, implicit-def $vgpr49_vgpr50_vgpr51_vgpr52, implicit-def $vgpr49, implicit-def $vgpr49_lo16, implicit-def $vgpr49_hi16, implicit-def $vgpr50, implicit-def $vgpr50_lo16, implicit-def $vgpr50_hi16, implicit-def $vgpr51, implicit-def $vgpr51_lo16, implicit-def $vgpr51_hi16, implicit-def $vgpr52, implicit-def $vgpr52_lo16, implicit-def $vgpr52_hi16, implicit-def $vgpr49_vgpr50, implicit-def $vgpr49_vgpr50_vgpr51, implicit-def $vgpr50_vgpr51, implicit-def $vgpr50_vgpr51_vgpr52, implicit-def $vgpr51_vgpr52, implicit-def $vgpr53_vgpr54_vgpr55_vgpr56, implicit-def $vgpr53, implicit-def $vgpr53_lo16, implicit-def $vgpr53_hi16, implicit-def $vgpr54, implicit-def $vgpr54_lo16, implicit-def $vgpr54_hi16, implicit-def $vgpr55, implicit-def $vgpr55_lo16, implicit-def $vgpr55_hi16, implicit-def $vgpr56, implicit-def $vgpr56_lo16, implicit-def $vgpr56_hi16, implicit-def $vgpr53_vgpr54, implicit-def $vgpr53_vgpr54_vgpr55, implicit-def $vgpr54_vgpr55, implicit-def $vgpr54_vgpr55_vgpr56, implicit-def $vgpr55_vgpr56, implicit-def $vgpr57_vgpr58_vgpr59_vgpr60, implicit-def $vgpr57, implicit-def $vgpr57_lo16, implicit-def $vgpr57_hi16, implicit-def $vgpr58, implicit-def $vgpr58_lo16, implicit-def $vgpr58_hi16, implicit-def $vgpr59, implicit-def $vgpr59_lo16, implicit-def $vgpr59_hi16, implicit-def $vgpr60, implicit-def $vgpr60_lo16, implicit-def $vgpr60_hi16, implicit-def $vgpr57_vgpr58, implicit-def $vgpr57_vgpr58_vgpr59, implicit-def $vgpr58_vgpr59, implicit-def $vgpr58_vgpr59_vgpr60, implicit-def $vgpr59_vgpr60, implicit-def $vgpr61_vgpr62_vgpr63_vgpr64, implicit-def $vgpr61, implicit-def $vgpr61_lo16, implicit-def $vgpr61_hi16, implicit-def $vgpr62, implicit-def $vgpr62_lo16, implicit-def $vgpr62_hi16, implicit-def $vgpr63, implicit-def $vgpr63_lo16, implicit-def $vgpr63_hi16, implicit-def $vgpr64, implicit-def $vgpr64_lo16, implicit-def $vgpr64_hi16, implicit-def $vgpr61_vgpr62, implicit-def $vgpr61_vgpr62_vgpr63, implicit-def $vgpr62_vgpr63, implicit-def $vgpr62_vgpr63_vgpr64, implicit-def $vgpr63_vgpr64, implicit-def $vgpr65_vgpr66_vgpr67_vgpr68, implicit-def $vgpr65, implicit-def $vgpr65_lo16, implicit-def $vgpr65_hi16, implicit-def $vgpr66, implicit-def $vgpr66_lo16, implicit-def $vgpr66_hi16, implicit-def $vgpr67, implicit-def $vgpr67_lo16, implicit-def $vgpr67_hi16, implicit-def $vgpr68, implicit-def $vgpr68_lo16, implicit-def $vgpr68_hi16, implicit-def $vgpr65_vgpr66, implicit-def $vgpr65_vgpr66_vgpr67, implicit-def $vgpr66_vgpr67, implicit-def $vgpr66_vgpr67_vgpr68, implicit-def $vgpr67_vgpr68, implicit-def $vgpr69_vgpr70_vgpr71_vgpr72, implicit-def $vgpr69, implicit-def $vgpr69_lo16, implicit-def $vgpr69_hi16, implicit-def $vgpr70, implicit-def $vgpr70_lo16, implicit-def $vgpr70_hi16, implicit-def $vgpr71, implicit-def $vgpr71_lo16, implicit-def $vgpr71_hi16, implicit-def $vgpr72, implicit-def $vgpr72_lo16, implicit-def $vgpr72_hi16, implicit-def $vgpr69_vgpr70, implicit-def $vgpr69_vgpr70_vgpr71, implicit-def $vgpr70_vgpr71, implicit-def $vgpr70_vgpr71_vgpr72, implicit-def $vgpr71_vgpr72, implicit-def $vgpr73_vgpr74_vgpr75_vgpr76, implicit-def $vgpr73, implicit-def $vgpr73_lo16, implicit-def $vgpr73_hi16, implicit-def $vgpr74, implicit-def $vgpr74_lo16, implicit-def $vgpr74_hi16, implicit-def $vgpr75, implicit-def $vgpr75_lo16, implicit-def $vgpr75_hi16, implicit-def $vgpr76, implicit-def $vgpr76_lo16, implicit-def $vgpr76_hi16, implicit-def $vgpr73_vgpr74, implicit-def $vgpr73_vgpr74_vgpr75, implicit-def $vgpr74_vgpr75, implicit-def $vgpr74_vgpr75_vgpr76, implicit-def $vgpr75_vgpr76, implicit-def $vgpr77_vgpr78_vgpr79_vgpr80, implicit-def $vgpr77, implicit-def $vgpr77_lo16, implicit-def $vgpr77_hi16, implicit-def $vgpr78, implicit-def $vgpr78_lo16, implicit-def $vgpr78_hi16, implicit-def $vgpr79, implicit-def $vgpr79_lo16, implicit-def $vgpr79_hi16, implicit-def $vgpr80, implicit-def $vgpr80_lo16, implicit-def $vgpr80_hi16, implicit-def $vgpr77_vgpr78, implicit-def $vgpr77_vgpr78_vgpr79, implicit-def $vgpr78_vgpr79, implicit-def $vgpr78_vgpr79_vgpr80, implicit-def $vgpr79_vgpr80, implicit-def $vgpr81_vgpr82_vgpr83_vgpr84, implicit-def $vgpr81, implicit-def $vgpr81_lo16, implicit-def $vgpr81_hi16, implicit-def $vgpr82, implicit-def $vgpr82_lo16, implicit-def $vgpr82_hi16, implicit-def $vgpr83, implicit-def $vgpr83_lo16, implicit-def $vgpr83_hi16, implicit-def $vgpr84, implicit-def $vgpr84_lo16, implicit-def $vgpr84_hi16, implicit-def $vgpr81_vgpr82, implicit-def $vgpr81_vgpr82_vgpr83, implicit-def $vgpr82_vgpr83, implicit-def $vgpr82_vgpr83_vgpr84, implicit-def $vgpr83_vgpr84, implicit-def $vgpr85_vgpr86_vgpr87_vgpr88, implicit-def $vgpr85, implicit-def $vgpr85_lo16, implicit-def $vgpr85_hi16, implicit-def $vgpr86, implicit-def $vgpr86_lo16, implicit-def $vgpr86_hi16, implicit-def $vgpr87, implicit-def $vgpr87_lo16, implicit-def $vgpr87_hi16, implicit-def $vgpr88, implicit-def $vgpr88_lo16, implicit-def $vgpr88_hi16, implicit-def $vgpr85_vgpr86, implicit-def $vgpr85_vgpr86_vgpr87, implicit-def $vgpr86_vgpr87, implicit-def $vgpr86_vgpr87_vgpr88, implicit-def $vgpr87_vgpr88, implicit killed $vgpr36, implicit $exec, implicit killed $vgpr37, implicit killed $vgpr38 { + ; CHECK-NEXT: $vgpr41_vgpr42_vgpr43_vgpr44 = DS_READ_B128_gfx9 $vgpr36, 0, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr45_vgpr46_vgpr47_vgpr48 = DS_READ2_B64_gfx9 $vgpr36, 2, 3, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr49_vgpr50_vgpr51_vgpr52 = DS_READ_B128_gfx9 $vgpr37, 0, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr53_vgpr54_vgpr55_vgpr56 = DS_READ2_B64_gfx9 $vgpr37, 2, 3, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr57_vgpr58_vgpr59_vgpr60 = DS_READ_B128_gfx9 $vgpr37, 768, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr61_vgpr62_vgpr63_vgpr64 = DS_READ2_B64_gfx9 killed $vgpr37, 98, 99, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr65_vgpr66_vgpr67_vgpr68 = DS_READ_B128_gfx9 $vgpr36, 768, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr69_vgpr70_vgpr71_vgpr72 = DS_READ2_B64_gfx9 $vgpr36, 98, 99, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr73_vgpr74_vgpr75_vgpr76 = DS_READ_B128_gfx9 $vgpr36, 1536, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr77_vgpr78_vgpr79_vgpr80 = DS_READ2_B64_gfx9 $vgpr36, 194, 195, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr81_vgpr82_vgpr83_vgpr84 = DS_READ_B128_gfx9 killed $vgpr36, 2304, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: $vgpr85_vgpr86_vgpr87_vgpr88 = DS_READ2_B64_gfx9 killed $vgpr38, 0, 1, 0, implicit $exec :: (load (s128), addrspace 3) + ; CHECK-NEXT: } + ; CHECK-NEXT: $sgpr1 = S_ADD_I32 $sgpr0, 16, implicit-def dead $scc + ; CHECK-NEXT: $vgpr39 = V_ADD_U32_e32 32, killed $vgpr39, implicit $exec + ; CHECK-NEXT: $vgpr40 = V_ADD_U32_e32 32, killed $vgpr40, implicit $exec + ; CHECK-NEXT: S_CMP_LT_U32 killed $sgpr0, killed $sgpr12, implicit-def $scc + ; CHECK-NEXT: $sgpr0 = S_MOV_B32 killed $sgpr1 + ; CHECK-NEXT: early-clobber $vgpr29_vgpr30_vgpr31_vgpr32 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48, 8, $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr29_vgpr30_vgpr31_vgpr32, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr25_vgpr26_vgpr27_vgpr28 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48, 8, $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr25_vgpr26_vgpr27_vgpr28, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr21_vgpr22_vgpr23_vgpr24 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72, 8, $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr21_vgpr22_vgpr23_vgpr24, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr17_vgpr18_vgpr19_vgpr20 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72, 8, $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr17_vgpr18_vgpr19_vgpr20, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr13_vgpr14_vgpr15_vgpr16 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80, 8, $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr13_vgpr14_vgpr15_vgpr16, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr9_vgpr10_vgpr11_vgpr12 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80, 8, $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr9_vgpr10_vgpr11_vgpr12, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr5_vgpr6_vgpr7_vgpr8 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88, 8, killed $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr5_vgpr6_vgpr7_vgpr8, 0, 0, implicit $exec + ; CHECK-NEXT: early-clobber $vgpr1_vgpr2_vgpr3_vgpr4 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88, 8, killed $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr1_vgpr2_vgpr3_vgpr4, 0, 0, implicit $exec + ; CHECK-NEXT: ATOMIC_FENCE 5, 2 + ; CHECK-NEXT: S_BARRIER + ; CHECK-NEXT: ATOMIC_FENCE 4, 2 + ATOMIC_FENCE 5, 2 + S_BARRIER + ATOMIC_FENCE 4, 2 + BUNDLE implicit-def $vgpr41_vgpr42_vgpr43_vgpr44, implicit-def $vgpr41, implicit-def $vgpr41_lo16, implicit-def $vgpr41_hi16, implicit-def $vgpr42, implicit-def $vgpr42_lo16, implicit-def $vgpr42_hi16, implicit-def $vgpr43, implicit-def $vgpr43_lo16, implicit-def $vgpr43_hi16, implicit-def $vgpr44, implicit-def $vgpr44_lo16, implicit-def $vgpr44_hi16, implicit-def $vgpr41_vgpr42, implicit-def $vgpr41_vgpr42_vgpr43, implicit-def $vgpr42_vgpr43, implicit-def $vgpr42_vgpr43_vgpr44, implicit-def $vgpr43_vgpr44, implicit-def $vgpr45_vgpr46_vgpr47_vgpr48, implicit-def $vgpr45, implicit-def $vgpr45_lo16, implicit-def $vgpr45_hi16, implicit-def $vgpr46, implicit-def $vgpr46_lo16, implicit-def $vgpr46_hi16, implicit-def $vgpr47, implicit-def $vgpr47_lo16, implicit-def $vgpr47_hi16, implicit-def $vgpr48, implicit-def $vgpr48_lo16, implicit-def $vgpr48_hi16, implicit-def $vgpr45_vgpr46, implicit-def $vgpr45_vgpr46_vgpr47, implicit-def $vgpr46_vgpr47, implicit-def $vgpr46_vgpr47_vgpr48, implicit-def $vgpr47_vgpr48, implicit-def $vgpr49_vgpr50_vgpr51_vgpr52, implicit-def $vgpr49, implicit-def $vgpr49_lo16, implicit-def $vgpr49_hi16, implicit-def $vgpr50, implicit-def $vgpr50_lo16, implicit-def $vgpr50_hi16, implicit-def $vgpr51, implicit-def $vgpr51_lo16, implicit-def $vgpr51_hi16, implicit-def $vgpr52, implicit-def $vgpr52_lo16, implicit-def $vgpr52_hi16, implicit-def $vgpr49_vgpr50, implicit-def $vgpr49_vgpr50_vgpr51, implicit-def $vgpr50_vgpr51, implicit-def $vgpr50_vgpr51_vgpr52, implicit-def $vgpr51_vgpr52, implicit-def $vgpr53_vgpr54_vgpr55_vgpr56, implicit-def $vgpr53, implicit-def $vgpr53_lo16, implicit-def $vgpr53_hi16, implicit-def $vgpr54, implicit-def $vgpr54_lo16, implicit-def $vgpr54_hi16, implicit-def $vgpr55, implicit-def $vgpr55_lo16, implicit-def $vgpr55_hi16, implicit-def $vgpr56, implicit-def $vgpr56_lo16, implicit-def $vgpr56_hi16, implicit-def $vgpr53_vgpr54, implicit-def $vgpr53_vgpr54_vgpr55, implicit-def $vgpr54_vgpr55, implicit-def $vgpr54_vgpr55_vgpr56, implicit-def $vgpr55_vgpr56, implicit-def $vgpr57_vgpr58_vgpr59_vgpr60, implicit-def $vgpr57, implicit-def $vgpr57_lo16, implicit-def $vgpr57_hi16, implicit-def $vgpr58, implicit-def $vgpr58_lo16, implicit-def $vgpr58_hi16, implicit-def $vgpr59, implicit-def $vgpr59_lo16, implicit-def $vgpr59_hi16, implicit-def $vgpr60, implicit-def $vgpr60_lo16, implicit-def $vgpr60_hi16, implicit-def $vgpr57_vgpr58, implicit-def $vgpr57_vgpr58_vgpr59, implicit-def $vgpr58_vgpr59, implicit-def $vgpr58_vgpr59_vgpr60, implicit-def $vgpr59_vgpr60, implicit-def $vgpr61_vgpr62_vgpr63_vgpr64, implicit-def $vgpr61, implicit-def $vgpr61_lo16, implicit-def $vgpr61_hi16, implicit-def $vgpr62, implicit-def $vgpr62_lo16, implicit-def $vgpr62_hi16, implicit-def $vgpr63, implicit-def $vgpr63_lo16, implicit-def $vgpr63_hi16, implicit-def $vgpr64, implicit-def $vgpr64_lo16, implicit-def $vgpr64_hi16, implicit-def $vgpr61_vgpr62, implicit-def $vgpr61_vgpr62_vgpr63, implicit-def $vgpr62_vgpr63, implicit-def $vgpr62_vgpr63_vgpr64, implicit-def $vgpr63_vgpr64, implicit-def $vgpr65_vgpr66_vgpr67_vgpr68, implicit-def $vgpr65, implicit-def $vgpr65_lo16, implicit-def $vgpr65_hi16, implicit-def $vgpr66, implicit-def $vgpr66_lo16, implicit-def $vgpr66_hi16, implicit-def $vgpr67, implicit-def $vgpr67_lo16, implicit-def $vgpr67_hi16, implicit-def $vgpr68, implicit-def $vgpr68_lo16, implicit-def $vgpr68_hi16, implicit-def $vgpr65_vgpr66, implicit-def $vgpr65_vgpr66_vgpr67, implicit-def $vgpr66_vgpr67, implicit-def $vgpr66_vgpr67_vgpr68, implicit-def $vgpr67_vgpr68, implicit-def $vgpr69_vgpr70_vgpr71_vgpr72, implicit-def $vgpr69, implicit-def $vgpr69_lo16, implicit-def $vgpr69_hi16, implicit-def $vgpr70, implicit-def $vgpr70_lo16, implicit-def $vgpr70_hi16, implicit-def $vgpr71, implicit-def $vgpr71_lo16, implicit-def $vgpr71_hi16, implicit-def $vgpr72, implicit-def $vgpr72_lo16, implicit-def $vgpr72_hi16, implicit-def $vgpr69_vgpr70, implicit-def $vgpr69_vgpr70_vgpr71, implicit-def $vgpr70_vgpr71, implicit-def $vgpr70_vgpr71_vgpr72, implicit-def $vgpr71_vgpr72, implicit-def $vgpr73_vgpr74_vgpr75_vgpr76, implicit-def $vgpr73, implicit-def $vgpr73_lo16, implicit-def $vgpr73_hi16, implicit-def $vgpr74, implicit-def $vgpr74_lo16, implicit-def $vgpr74_hi16, implicit-def $vgpr75, implicit-def $vgpr75_lo16, implicit-def $vgpr75_hi16, implicit-def $vgpr76, implicit-def $vgpr76_lo16, implicit-def $vgpr76_hi16, implicit-def $vgpr73_vgpr74, implicit-def $vgpr73_vgpr74_vgpr75, implicit-def $vgpr74_vgpr75, implicit-def $vgpr74_vgpr75_vgpr76, implicit-def $vgpr75_vgpr76, implicit-def $vgpr77_vgpr78_vgpr79_vgpr80, implicit-def $vgpr77, implicit-def $vgpr77_lo16, implicit-def $vgpr77_hi16, implicit-def $vgpr78, implicit-def $vgpr78_lo16, implicit-def $vgpr78_hi16, implicit-def $vgpr79, implicit-def $vgpr79_lo16, implicit-def $vgpr79_hi16, implicit-def $vgpr80, implicit-def $vgpr80_lo16, implicit-def $vgpr80_hi16, implicit-def $vgpr77_vgpr78, implicit-def $vgpr77_vgpr78_vgpr79, implicit-def $vgpr78_vgpr79, implicit-def $vgpr78_vgpr79_vgpr80, implicit-def $vgpr79_vgpr80, implicit-def $vgpr81_vgpr82_vgpr83_vgpr84, implicit-def $vgpr81, implicit-def $vgpr81_lo16, implicit-def $vgpr81_hi16, implicit-def $vgpr82, implicit-def $vgpr82_lo16, implicit-def $vgpr82_hi16, implicit-def $vgpr83, implicit-def $vgpr83_lo16, implicit-def $vgpr83_hi16, implicit-def $vgpr84, implicit-def $vgpr84_lo16, implicit-def $vgpr84_hi16, implicit-def $vgpr81_vgpr82, implicit-def $vgpr81_vgpr82_vgpr83, implicit-def $vgpr82_vgpr83, implicit-def $vgpr82_vgpr83_vgpr84, implicit-def $vgpr83_vgpr84, implicit-def $vgpr85_vgpr86_vgpr87_vgpr88, implicit-def $vgpr85, implicit-def $vgpr85_lo16, implicit-def $vgpr85_hi16, implicit-def $vgpr86, implicit-def $vgpr86_lo16, implicit-def $vgpr86_hi16, implicit-def $vgpr87, implicit-def $vgpr87_lo16, implicit-def $vgpr87_hi16, implicit-def $vgpr88, implicit-def $vgpr88_lo16, implicit-def $vgpr88_hi16, implicit-def $vgpr85_vgpr86, implicit-def $vgpr85_vgpr86_vgpr87, implicit-def $vgpr86_vgpr87, implicit-def $vgpr86_vgpr87_vgpr88, implicit-def $vgpr87_vgpr88, implicit $vgpr36, implicit $exec, implicit $vgpr37, implicit $vgpr38 { + $vgpr41_vgpr42_vgpr43_vgpr44 = DS_READ_B128_gfx9 $vgpr36, 0, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr45_vgpr46_vgpr47_vgpr48 = DS_READ2_B64_gfx9 $vgpr36, 2, 3, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr49_vgpr50_vgpr51_vgpr52 = DS_READ_B128_gfx9 $vgpr37, 0, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr53_vgpr54_vgpr55_vgpr56 = DS_READ2_B64_gfx9 $vgpr37, 2, 3, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr57_vgpr58_vgpr59_vgpr60 = DS_READ_B128_gfx9 $vgpr37, 768, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr61_vgpr62_vgpr63_vgpr64 = DS_READ2_B64_gfx9 $vgpr37, 98, 99, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr65_vgpr66_vgpr67_vgpr68 = DS_READ_B128_gfx9 $vgpr36, 768, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr69_vgpr70_vgpr71_vgpr72 = DS_READ2_B64_gfx9 $vgpr36, 98, 99, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr73_vgpr74_vgpr75_vgpr76 = DS_READ_B128_gfx9 $vgpr36, 1536, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr77_vgpr78_vgpr79_vgpr80 = DS_READ2_B64_gfx9 $vgpr36, 194, 195, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr81_vgpr82_vgpr83_vgpr84 = DS_READ_B128_gfx9 $vgpr36, 2304, 0, implicit $exec :: (load (s128), addrspace 3) + $vgpr85_vgpr86_vgpr87_vgpr88 = DS_READ2_B64_gfx9 $vgpr38, 0, 1, 0, implicit $exec :: (load (s128), addrspace 3) + } + $sgpr1 = S_ADD_I32 $sgpr0, 16, implicit-def dead $scc + $vgpr39 = V_ADD_U32_e32 32, killed $vgpr39, implicit $exec + $vgpr40 = V_ADD_U32_e32 32, killed $vgpr40, implicit $exec + S_CMP_LT_U32 killed $sgpr0, $sgpr12, implicit-def $scc + early-clobber $vgpr29_vgpr30_vgpr31_vgpr32 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48, 8, $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr29_vgpr30_vgpr31_vgpr32, 0, 0, implicit $exec + early-clobber $vgpr25_vgpr26_vgpr27_vgpr28 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48, 8, $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr25_vgpr26_vgpr27_vgpr28, 0, 0, implicit $exec + early-clobber $vgpr21_vgpr22_vgpr23_vgpr24 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72, 8, $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr21_vgpr22_vgpr23_vgpr24, 0, 0, implicit $exec + early-clobber $vgpr17_vgpr18_vgpr19_vgpr20 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72, 8, $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr17_vgpr18_vgpr19_vgpr20, 0, 0, implicit $exec + early-clobber $vgpr13_vgpr14_vgpr15_vgpr16 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80, 8, $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr13_vgpr14_vgpr15_vgpr16, 0, 0, implicit $exec + early-clobber $vgpr9_vgpr10_vgpr11_vgpr12 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80, 8, $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr9_vgpr10_vgpr11_vgpr12, 0, 0, implicit $exec + early-clobber $vgpr5_vgpr6_vgpr7_vgpr8 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88, 8, killed $vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56, 8, killed $vgpr5_vgpr6_vgpr7_vgpr8, 0, 0, implicit $exec + early-clobber $vgpr1_vgpr2_vgpr3_vgpr4 = V_WMMA_F32_16X16X16_F16_twoaddr_w64 8, killed $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88, 8, killed $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64, 8, killed $vgpr1_vgpr2_vgpr3_vgpr4, 0, 0, implicit $exec + $sgpr0 = S_MOV_B32 killed $sgpr1 + ATOMIC_FENCE 5, 2 + S_BARRIER + ATOMIC_FENCE 4, 2 + +... diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll b/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll index f3cb5a7..30f5277 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll @@ -26,17 +26,17 @@ define amdgpu_kernel void @barrier_vmcnt_global(ptr addrspace(1) %arg) { ; GFX9-LABEL: barrier_vmcnt_global: ; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 +; GFX9-NEXT: v_add_u32_e32 v2, 1, v0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_dword v2, v1, s[0:1] -; GFX9-NEXT: v_add_u32_e32 v1, 1, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: global_load_dword v3, v1, s[0:1] +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2] +; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_barrier -; GFX9-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NEXT: global_store_dword v[0:1], v3, off ; GFX9-NEXT: s_endpgm bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() @@ -369,10 +369,9 @@ define amdgpu_kernel void @barrier_vmcnt_vscnt_flat_workgroup(ptr %arg) { ; GFX8-NEXT: flat_load_dword v3, v[2:3] ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0 ; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2] -; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc -; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_barrier ; GFX8-NEXT: flat_store_dword v[0:1], v3 ; GFX8-NEXT: s_endpgm @@ -393,10 +392,9 @@ define amdgpu_kernel void @barrier_vmcnt_vscnt_flat_workgroup(ptr %arg) { ; GFX9-NEXT: flat_load_dword v3, v[2:3] ; GFX9-NEXT: v_add_u32_e32 v2, 1, v0 ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2] -; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc -; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_barrier ; GFX9-NEXT: flat_store_dword v[0:1], v3 ; GFX9-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/ARM/llround-conv.ll b/llvm/test/CodeGen/ARM/llround-conv.ll index f734db8..20fe272 100644 --- a/llvm/test/CodeGen/ARM/llround-conv.ll +++ b/llvm/test/CodeGen/ARM/llround-conv.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT ; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8 ; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 define i64 @testmsxh_builtin(half %x) { @@ -22,6 +23,14 @@ define i64 @testmsxh_builtin(half %x) { ; CHECK-NOFP16-NEXT: bl llroundf ; CHECK-NOFP16-NEXT: pop {r11, pc} ; +; CHECK-FPv8-LABEL: testmsxh_builtin: +; CHECK-FPv8: @ %bb.0: @ %entry +; CHECK-FPv8-NEXT: .save {r11, lr} +; CHECK-FPv8-NEXT: push {r11, lr} +; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0 +; CHECK-FPv8-NEXT: bl llroundf +; CHECK-FPv8-NEXT: pop {r11, pc} +; ; CHECK-FP16-LABEL: testmsxh_builtin: ; CHECK-FP16: @ %bb.0: @ %entry ; CHECK-FP16-NEXT: .save {r11, lr} diff --git a/llvm/test/CodeGen/ARM/lround-conv.ll b/llvm/test/CodeGen/ARM/lround-conv.ll index 03f7a0d..7466bcb 100644 --- a/llvm/test/CodeGen/ARM/lround-conv.ll +++ b/llvm/test/CodeGen/ARM/lround-conv.ll @@ -4,11 +4,39 @@ ; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8 ; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 -;define i32 @testmswh_builtin(half %x) { -;entry: -; %0 = tail call i32 @llvm.lround.i32.f16(half %x) -; ret i32 %0 -;} +define i32 @testmswh_builtin(half %x) { +; CHECK-SOFT-LABEL: testmswh_builtin: +; CHECK-SOFT: @ %bb.0: @ %entry +; CHECK-SOFT-NEXT: .save {r11, lr} +; CHECK-SOFT-NEXT: push {r11, lr} +; CHECK-SOFT-NEXT: bl __aeabi_h2f +; CHECK-SOFT-NEXT: pop {r11, lr} +; CHECK-SOFT-NEXT: b lroundf +; +; CHECK-NOFP16-LABEL: testmswh_builtin: +; CHECK-NOFP16: @ %bb.0: @ %entry +; CHECK-NOFP16-NEXT: .save {r11, lr} +; CHECK-NOFP16-NEXT: push {r11, lr} +; CHECK-NOFP16-NEXT: vmov r0, s0 +; CHECK-NOFP16-NEXT: bl __aeabi_h2f +; CHECK-NOFP16-NEXT: vmov s0, r0 +; CHECK-NOFP16-NEXT: pop {r11, lr} +; CHECK-NOFP16-NEXT: b lroundf +; +; CHECK-FPv8-LABEL: testmswh_builtin: +; CHECK-FPv8: @ %bb.0: @ %entry +; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0 +; CHECK-FPv8-NEXT: b lroundf +; +; CHECK-FP16-LABEL: testmswh_builtin: +; CHECK-FP16: @ %bb.0: @ %entry +; CHECK-FP16-NEXT: vcvta.s32.f16 s0, s0 +; CHECK-FP16-NEXT: vmov r0, s0 +; CHECK-FP16-NEXT: bx lr +entry: + %0 = tail call i32 @llvm.lround.i32.f16(half %x) + ret i32 %0 +} define i32 @testmsws_builtin(float %x) { ; CHECK-LABEL: testmsws_builtin: @@ -40,8 +68,3 @@ entry: ret i32 %0 } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK-FP16: {{.*}} -; CHECK-FPv8: {{.*}} -; CHECK-NOFP16: {{.*}} -; CHECK-SOFT: {{.*}} diff --git a/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll b/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll new file mode 100644 index 0000000..9190d03 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll @@ -0,0 +1,19 @@ +; RUN: opt -S -dxil-prepare < %s | FileCheck %s + +; Ensures that dxil-prepare will remove the llvm.errno.tbaa metadata + +target triple = "dxil-unknown-shadermodel6.0-compute" + +define void @main() { +entry: + ret void +} + +; CHECK-NOT: !llvm.errno.tbaa +; CHECK-NOT: {{^!}} + +!llvm.errno.tbaa = !{!0} + +!0 = !{!1, !1, i64 0} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/Hexagon/bitcast-i64-to-v64i1.ll b/llvm/test/CodeGen/Hexagon/bitcast-i64-to-v64i1.ll new file mode 100644 index 0000000..f7e5cdb --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/bitcast-i64-to-v64i1.ll @@ -0,0 +1,33 @@ +; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s +; CHECK-DAG: r[[REGH:([0-9]+)]]:[[REGL:([0-9]+)]] = combine(##.LCPI0_0,#-1) +; CHECK-DAG: [[VREG1:v([0-9]+)]] = vmem(r[[REGH]]+#0) +; CHECK-DAG: [[REG1:(r[0-9]+)]] = memw(r{{[0-9]+}}+#4) +; CHECK-DAG: [[VREG2:v([0-9]+)]] = vsplat([[REG1]]) +; CHECK-DAG: [[REG2:(r[0-9]+)]] = memw(r{{[0-9]+}}+#0) +; CHECK-DAG: [[VREG3:v([0-9]+)]] = vsplat([[REG2]]) +; CHECK-DAG: [[VREG4:v([0-9]+)]] = vand([[VREG2]],[[VREG1]]) +; CHECK-DAG: [[VREG5:v([0-9]+)]] = vand([[VREG3]],[[VREG1]]) +; CHECK-DAG: [[QREG:q[0-9]+]] = vand([[VREG4]],r{{[0-9]+}}) +; CHECK-DAG: [[VREG6:v([0-9]+)]] = vand([[QREG]],r{{[0-9]+}}) +; CHECK-DAG: [[QREG1:q[0-9]+]] = vand([[VREG5]],r{{[0-9]+}}) +; CHECK-DAG: [[VREG7:v([0-9]+)]] = vand([[QREG1]],r{{[0-9]+}}) +; CHECK-DAG: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h) +; CHECK-DAG: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h) +; CHECK-DAG: [[VREG8:v([0-9]+)]] = vror(v{{[0-9]+}},r{{[0-9]+}}) +; CHECK-DAG: [[VREG9:v([0-9]+)]] = vor([[VREG8]],v{{[0-9]+}}) +; CHECK-DAG: q{{[0-9]+}} = vand([[VREG9]],r{{[0-9]+}}) +define void @bitcast_i64_to_v64i1_full(ptr %in, ptr %out) { +entry: + %load = load i64, ptr %in, align 4 + %bitcast = bitcast i64 %load to <64 x i1> + %e0 = extractelement <64 x i1> %bitcast, i32 0 + %e1 = extractelement <64 x i1> %bitcast, i32 1 + %z0 = zext i1 %e0 to i8 + %z1 = zext i1 %e1 to i8 + %ptr0 = getelementptr i8, ptr %out, i32 0 + %ptr1 = getelementptr i8, ptr %out, i32 1 + store i8 %z0, ptr %ptr0, align 1 + store i8 %z1, ptr %ptr1, align 1 + ret void +} + diff --git a/llvm/test/CodeGen/Hexagon/insert-big.ll b/llvm/test/CodeGen/Hexagon/insert-big.ll new file mode 100644 index 0000000..8735a66 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/insert-big.ll @@ -0,0 +1,47 @@ +; Check that llc does not abort, which happened due to incorrect MIR. +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=1 < %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=2 < %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=3 < %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=4 < %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=5 < %s + +; Look for this symptom, in case llc does not check invalid IR. +; CHECK-NOT: insert(%14,%5,#5,#5) + +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=1 -debug-only=hexinsert -stop-after hexinsert < %s 2>&1 | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=2 -debug-only=hexinsert -stop-after hexinsert < %s 2>&1 | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=3 -debug-only=hexinsert -stop-after hexinsert < %s 2>&1 | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=4 -debug-only=hexinsert -stop-after hexinsert < %s 2>&1 | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -insert-max-ifmap=5 -debug-only=hexinsert -stop-after hexinsert < %s 2>&1 | FileCheck %s + +; REQUIRES: asserts + +define i32 @f(i32 %0, i32 %1, i32 %2) { +entry: + switch i32 %0, label %common.ret1 [ + i32 8907, label %3 + i32 4115, label %6 + ] + +common.ret1: + %common.ret1.op = phi i32 [ %5, %3 ], [ %526, %6 ], [ 0, %entry ] + ret i32 %common.ret1.op + +3: + %4 = shl i32 %2, 5 + %5 = and i32 %4, 992 + br label %common.ret1 + +6: + %7 = shl i32 %0, 10 + %8 = and i32 %7, 7168 + %9 = shl i32 %0, 5 + %10 = and i32 %9, 992 + %11 = or i32 %10, %8 + %12 = and i32 %0, 1 + %13 = or i32 %11, %12 + %14 = shl i32 %1, 1 + %15 = and i32 %14, 2031616 + %526 = or i32 %13, %15 + br label %common.ret1 +} diff --git a/llvm/test/CodeGen/Hexagon/qfp-conv.ll b/llvm/test/CodeGen/Hexagon/qfp-conv.ll new file mode 100644 index 0000000..d2d393e --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/qfp-conv.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=hexagon -mattr=+hvxv68,+hvx,+hvx-length128b < %s | FileCheck %s + +; Test that the Qfloat optimization pass doesn't crash due to an invalid +; instructions. + +; CHECK: v{{[0-9]+}}.hf = v{{[0-9]:[0-9]}}.qf32 + +define void @test( + <32 x i32>* %optr, + <64 x i32> %in64, + <32 x i32> %va, + <32 x i32> %vb +) local_unnamed_addr #0 { +entry: + br label %for.body + +for.body: + %optr.068 = phi <32 x i32>* [ %optr, %entry ], [ %incdec.ptr6, %for.body ] + %0 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %in64) #2 + %1 = tail call <32 x i32> @llvm.hexagon.V6.vdealh.128B(<32 x i32> %0) #2 + %2 = tail call <128 x i1> @llvm.hexagon.V6.vgth.128B(<32 x i32> %va, <32 x i32> %1) #2 + %3 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %2, <32 x i32> %va, <32 x i32> %vb) #2 + %4 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %3, <32 x i32> %vb) #2 + %5 = tail call <32 x i32> @llvm.hexagon.V6.vpackhub.sat.128B(<32 x i32> %va, <32 x i32> %4) #2 + store <32 x i32> %5, <32 x i32>* %optr.068, align 1 + %incdec.ptr6 = getelementptr inbounds <32 x i32>, <32 x i32>* %optr.068, i32 1 + br label %for.body +} + +declare <32 x i32> @llvm.hexagon.V6.vdealh.128B(<32 x i32>) #1 +declare <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32>) #1 +declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 +declare <32 x i32> @llvm.hexagon.V6.vpackhub.sat.128B(<32 x i32>, <32 x i32>) #1 +declare <128 x i1> @llvm.hexagon.V6.vgth.128B(<32 x i32>, <32 x i32>) #1 +declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1>, <32 x i32>, <32 x i32>) #1 diff --git a/llvm/test/CodeGen/Hexagon/qfp-enabled.ll b/llvm/test/CodeGen/Hexagon/qfp-enabled.ll new file mode 100644 index 0000000..a5cc5fa --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/qfp-enabled.ll @@ -0,0 +1,19 @@ +; Tests if the flag to disable qfp optimizer pass works or not. + +; RUN: llc -march=hexagon -mcpu=hexagonv69 -mattr=+hvxv69,+hvx-length128b \ +; RUN: < %s -o -| FileCheck %s --check-prefix=ENABLED +; RUN: llc -march=hexagon -mcpu=hexagonv69 -mattr=+hvxv69,+hvx-length128b \ +; RUN: -disable-qfp-opt < %s -o -| FileCheck %s --check-prefix=DISABLED + +define dso_local <32 x i32> @conv1_qf32(<32 x i32> noundef %input1, <32 x i32> noundef %input2) local_unnamed_addr { +entry: +; DISABLED: [[V2:v[0-9]+]].qf32 = vadd(v0.sf,v1.sf) +; DISABLED: [[V3:v[0-9]+]].sf = [[V2]].qf32 +; DISABLED: qf32 = vadd(v0.sf,[[V3]].sf) +; ENABLED: [[V4:v[0-9]+]].qf32 = vadd(v0.sf,v1.sf) +; ENABLED: qf32 = vadd([[V4]].qf32,v0.sf) + %0 = tail call <32 x i32> @llvm.hexagon.V6.vadd.sf.128B(<32 x i32> %input1, <32 x i32> %input2) + %1 = tail call <32 x i32> @llvm.hexagon.V6.vconv.sf.qf32.128B(<32 x i32> %0) + %2 = tail call <32 x i32> @llvm.hexagon.V6.vadd.sf.128B(<32 x i32> %input1, <32 x i32> %1) + ret <32 x i32> %2 +} diff --git a/llvm/test/CodeGen/Hexagon/qfp-remove-kill.mir b/llvm/test/CodeGen/Hexagon/qfp-remove-kill.mir new file mode 100644 index 0000000..d8dde7d --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/qfp-remove-kill.mir @@ -0,0 +1,95 @@ +# RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b \ +# RUN: -run-pass hexagon-qfp-optimizer -run-pass machineverifier %s -o - | FileCheck %s + +# Test that the killed RegState from DefMI operands are removed +# killed RegState should be set for MI operands +# CHECK-LABEL: name: qfpAdd +# CHECK: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG1:([0-9]+)]] +# CHECK-NEXT: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG2:([0-9]+)]] +# CHECK-NEXT: V6_vadd_qf32 killed %[[REG1]], killed %[[REG2]] +# CHECK-NEXT: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG3:([0-9]+)]] +# CHECK-NEXT: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG4:([0-9]+)]] +# CHECK-NEXT: V6_vadd_qf32 killed %[[REG3]], killed %[[REG4]] + +--- +name: qfpAdd +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1, $r2, $r3 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %2:intregs = COPY $r2 + %3:intregs = COPY $r3 + %4:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %5:hvxvr = V6_vL32Ub_ai %1:intregs, 0 + %6:hvxvr = V6_vL32Ub_ai %2:intregs, 0 + %7:hvxvr = V6_vL32Ub_ai %3:intregs, 0 + %8:hvxvr = V6_vconv_sf_qf32 killed %4:hvxvr + %9:hvxvr = V6_vconv_sf_qf32 killed %5:hvxvr + %10:hvxvr = V6_vadd_sf %8:hvxvr, %9:hvxvr + %11:hvxvr = V6_vconv_sf_qf32 killed %6:hvxvr + %12:hvxvr = V6_vconv_sf_qf32 killed %7:hvxvr + %13:hvxvr = V6_vadd_sf killed %11:hvxvr, killed %12:hvxvr +... + + +# Test that the killed RegState from DefMI operands are removed +# CHECK-LABEL: name: qfpAddMix +# CHECK: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG1:([0-9]+)]] +# CHECK-NEXT: V6_vadd_qf32_mix killed %[[REG1]], %{{[0-9]+}} +# CHECK: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG2:([0-9]+)]] +# CHECK-NEXT: V6_vadd_qf32_mix killed %[[REG2]], %{{[0-9]+}} + +--- +name: qfpAddMix +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1, $r2 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %2:intregs = COPY $r2 + %3:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %4:hvxvr = V6_vL32Ub_ai %1:intregs, 0 + %5:hvxvr = V6_vL32Ub_ai %2:intregs, 0 + %6:hvxvr = V6_vmpy_qf32_sf %4, %5 + %7:hvxvr = V6_vconv_sf_qf32 killed %6:hvxvr + %8:hvxvr = V6_vadd_sf %3:hvxvr, %7:hvxvr + %9:hvxvr = V6_vmpy_qf32_sf %4, %5 + %10:hvxvr = V6_vconv_sf_qf32 killed %9:hvxvr + %11:hvxvr = V6_vadd_sf %3:hvxvr, killed %10:hvxvr +... + + +# Test that we do generate V6_vsub_qf32_mix for the below test. +# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf32 +# is passed as first operand. So, V6_vsub_qf32_mix must be generated. +# CHECK-LABEL: name: qfpAddSwapMix +# CHECK: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG1:([0-9]+)]] +# CHECK-NEXT: V6_vadd_qf32_mix killed %[[REG1]], %{{[0-9]+}} +# CHECK: %{{[0-9]+}}:hvxvr = V6_vconv_sf_qf32 %[[REG2:([0-9]+)]] +# CHECK-NEXT: V6_vadd_qf32_mix killed %[[REG2]], %{{[0-9]+}} + +--- +name: qfpAddSwapMix +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1, $r2 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %2:intregs = COPY $r2 + %3:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %4:hvxvr = V6_vL32Ub_ai %1:intregs, 0 + %5:hvxvr = V6_vL32Ub_ai %2:intregs, 0 + %6:hvxvr = V6_vmpy_qf32_sf %4, %5 + %7:hvxvr = V6_vconv_sf_qf32 killed %6:hvxvr + %8:hvxvr = V6_vadd_sf %7:hvxvr, %3:hvxvr + %9:hvxvr = V6_vmpy_qf32_sf %4, %5 + %10:hvxvr = V6_vconv_sf_qf32 killed %9:hvxvr + %11:hvxvr = V6_vadd_sf killed %10:hvxvr, %3:hvxvr +... diff --git a/llvm/test/CodeGen/Hexagon/qfp-subreg-bug.mir b/llvm/test/CodeGen/Hexagon/qfp-subreg-bug.mir new file mode 100644 index 0000000..1d78203 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/qfp-subreg-bug.mir @@ -0,0 +1,33 @@ +# RUN: llc -march=hexagon -mcpu=hexagonv69 -mattr=+hvxv69,+hvx-length128b -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s + +# CHECK: V6_vshuffvdd +# CHECK: V6_vadd_sf +# CHECK: V6_vadd_qf32_mix{{.*}}vsub_lo +# CHECK: V6_vadd_qf32_mix{{.*}}vsub_hi + +--- +name: qfp_subreg_fix +alignment: 16 +tracksRegLiveness: true + +body: | + bb.0: + %10:intregs = IMPLICIT_DEF + %9:hvxvr = V6_vL32Ub_ai %10, 0 :: (load (s1024) from `ptr undef`, align 4) + %11:intregs = A2_tfrsi 15360 + %12:hvxvr = V6_lvsplath %11 + %13:hvxwr = V6_vmpy_qf32_hf %9, %12 + %15:hvxvr = V6_vconv_sf_qf32 %13.vsub_lo + %17:hvxvr = V6_vconv_sf_qf32 %13.vsub_hi + %18:intregslow8 = A2_tfrsi -4 + %19:hvxwr = V6_vshuffvdd %17, %15, %18 + %21:hvxvr = V6_vadd_sf %19.vsub_hi, %19.vsub_hi + %22:hvxvr = V6_vconv_sf_qf32 %21 + %24:hvxvr = V6_vadd_sf %19.vsub_lo, %19.vsub_lo + %25:hvxvr = V6_vconv_sf_qf32 %24 + %26:hvxvr = V6_vadd_sf %25, %19.vsub_lo + %27:hvxvr = V6_vconv_sf_qf32 %26 + %28:hvxvr = V6_vadd_sf %22, %19.vsub_hi + %29:hvxvr = V6_vconv_sf_qf32 %28 + +... diff --git a/llvm/test/CodeGen/Hexagon/qfpopt-rem-conv-add.ll b/llvm/test/CodeGen/Hexagon/qfpopt-rem-conv-add.ll new file mode 100644 index 0000000..c16370c --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/qfpopt-rem-conv-add.ll @@ -0,0 +1,21 @@ +; Tests if generated vadd instruction takes in qf32 +; type as first parameter instead of a sf type without +; any conversion instruction of type sf = qf32 + +; RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s + +; CHECK: [[V2:v[0-9]+]] = vxor([[V2]],[[V2]]) +; CHECK: [[V0:v[0-9]+]].qf32 = vmpy([[V0]].sf,[[V2]].sf) +; CHECK: [[V1:v[0-9]+]].qf32 = vmpy([[V1]].sf,[[V2]].sf) +; CHECK: [[V4:v[0-9]+]].qf32 = vadd([[V0]].qf32,[[V2]].sf) +; CHECK: [[V5:v[0-9]+]].qf32 = vadd([[V1]].qf32,[[V2]].sf) + +define void @_Z19compute_ripple_geluIDF16_EviPT_PKS0_(ptr %out_ptr, <64 x float> %conv14.ripple.vectorized) #0 { +entry: + %mul16.ripple.vectorized = fmul <64 x float> %conv14.ripple.vectorized, zeroinitializer + %conv17.ripple.vectorized = fptrunc <64 x float> %mul16.ripple.vectorized to <64 x half> + store <64 x half> %conv17.ripple.vectorized, ptr %out_ptr, align 2 + ret void +} + +attributes #0 = { "target-features"="+hvx-length128b,+hvxv75,+v75,-long-calls,-small-data" } diff --git a/llvm/test/CodeGen/Hexagon/vect/qfp-mix.mir b/llvm/test/CodeGen/Hexagon/vect/qfp-mix.mir new file mode 100644 index 0000000..9a9e938 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/vect/qfp-mix.mir @@ -0,0 +1,79 @@ +# RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b \ +# RUN: -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s + + +# Test that the operands are swapped for Add if the second operand +# is a qf32 to sf conversion. V6_vadd_qf32_mix supports first operand +# as qf32. +# CHECK-LABEL: name: qfpAddMix +# CHECK: %[[REG:([0-9]+)]]:hvxvr = V6_vmpy_qf32_sf +# CHECK: V6_vadd_qf32_mix %[[REG]] + +--- +name: qfpAddMix +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1, $r2, $r3 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %2:intregs = COPY $r2 + %3:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %4:hvxvr = V6_vL32Ub_ai %1:intregs, 0 + %5:hvxvr = V6_vL32Ub_ai %2:intregs, 0 + %6:hvxvr = V6_vmpy_qf32_sf %4, %5 + %7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr + %8:hvxvr = V6_vadd_sf %3:hvxvr, %7:hvxvr +... + + +# Test that we do not generate V6_vsub_qf32_mix for the below test. +# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf32 +# is passed as second operand. As sub is not commutative, we should not +# generate the mix instruction. +# CHECK-LABEL: name: qfpSubNoMix +# CHECK-NOT: V6_vsub_qf32_mix + +--- +name: qfpSubNoMix +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1, $r2, $r3 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %2:intregs = COPY $r2 + %3:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %4:hvxvr = V6_vL32Ub_ai %1:intregs, 0 + %5:hvxvr = V6_vL32Ub_ai %2:intregs, 0 + %6:hvxvr = V6_vmpy_qf32_sf %4, %5 + %7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr + %8:hvxvr = V6_vsub_sf %3:hvxvr, %7:hvxvr +... + + +# Test that we do generate V6_vsub_qf32_mix for the below test. +# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf32 +# is passed as first operand. So, V6_vsub_qf32_mix must be generated. +# CHECK-LABEL: name: qfpSubMix +# CHECK: V6_vsub_qf32_mix + +--- +name: qfpSubMix +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1, $r2, $r3 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %2:intregs = COPY $r2 + %3:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %4:hvxvr = V6_vL32Ub_ai %1:intregs, 0 + %5:hvxvr = V6_vL32Ub_ai %2:intregs, 0 + %6:hvxvr = V6_vmpy_qf32_sf %4, %5 + %7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr + %8:hvxvr = V6_vsub_sf %7:hvxvr, %3:hvxvr +... diff --git a/llvm/test/CodeGen/Hexagon/vect/qfp-zeroinit.mir b/llvm/test/CodeGen/Hexagon/vect/qfp-zeroinit.mir new file mode 100644 index 0000000..f0b1d3c --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/vect/qfp-zeroinit.mir @@ -0,0 +1,23 @@ +# RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s + +# CHECK-LABEL: name: qfpAdd32 +# CHECK: V6_vd0 +# CHECK-NEXT: V6_vL32Ub_ai +# CHECK-NEXT: V6_vadd_sf +# CHECK-NEXT: V6_vconv_sf_qf32 +# CHECK-NEXT: V6_vS32Ub_ai +--- +name: qfpAdd32 +tracksRegLiveness: true + +body: | + bb.0: + liveins: $r0, $r1 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %3:hvxvr = V6_vd0 + %4:hvxvr = V6_vL32Ub_ai %0:intregs, 0 + %5:hvxvr = V6_vadd_sf %3:hvxvr, %4:hvxvr + %6:hvxvr = V6_vconv_sf_qf32 %5:hvxvr + V6_vS32Ub_ai %1:intregs, 0, %6:hvxvr +... diff --git a/llvm/test/CodeGen/Hexagon/vect/unique-vreg-def.ll b/llvm/test/CodeGen/Hexagon/vect/unique-vreg-def.ll new file mode 100644 index 0000000..2d46da7 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/vect/unique-vreg-def.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; REQUIRES: hexagon + +; This test was asserting because getVRegDef() was called on a register with +; multiple defs. +; Checks that the test does not assert and vsub is generated. +; CHECK: vsub + +target triple = "hexagon" + +@v = common dso_local local_unnamed_addr global <32 x i32> zeroinitializer, align 128 + +; Function Attrs: nounwind +define dso_local void @hvx_twoSum(<32 x i32>* nocapture noundef writeonly %s2lo) local_unnamed_addr #0 { +entry: + %0 = load <32 x i32>, <32 x i32>* @v, align 128 + %call = tail call inreg <32 x i32> @MY_Vsf_equals_Vqf32(<32 x i32> noundef %0) #3 + %1 = tail call <32 x i32> @llvm.hexagon.V6.vsub.sf.128B(<32 x i32> %call, <32 x i32> %call) + store <32 x i32> %1, <32 x i32>* @v, align 128 + store <32 x i32> %1, <32 x i32>* %s2lo, align 128 + ret void +} + +declare dso_local inreg <32 x i32> @MY_Vsf_equals_Vqf32(<32 x i32> noundef) local_unnamed_addr #1 + +; Function Attrs: nofree nosync nounwind readnone +declare <32 x i32> @llvm.hexagon.V6.vsub.sf.128B(<32 x i32>, <32 x i32>) #2 + +attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv73" "target-features"="+hvx-length128b,+hvxv73,+v73,-long-calls" } +attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv73" "target-features"="+hvx-length128b,+hvxv73,+v73,-long-calls" } +attributes #2 = { nofree nosync nounwind readnone } +attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_3D_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_3D_vocab.json new file mode 100644 index 0000000..5de715b --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_3D_vocab.json @@ -0,0 +1,22 @@ +{ + "entities": { + "KILL": [0.1, 0.2, 0.3], + "MOV": [0.4, 0.5, 0.6], + "LEA": [0.7, 0.8, 0.9], + "RET": [1.0, 1.1, 1.2], + "ADD": [1.3, 1.4, 1.5], + "SUB": [1.6, 1.7, 1.8], + "IMUL": [1.9, 2.0, 2.1], + "AND": [2.2, 2.3, 2.4], + "OR": [2.5, 2.6, 2.7], + "XOR": [2.8, 2.9, 3.0], + "CMP": [3.1, 3.2, 3.3], + "TEST": [3.4, 3.5, 3.6], + "JMP": [3.7, 3.8, 3.9], + "CALL": [4.0, 4.1, 4.2], + "PUSH": [4.3, 4.4, 4.5], + "POP": [4.6, 4.7, 4.8], + "NOP": [4.9, 5.0, 5.1], + "COPY": [5.2, 5.3, 5.4] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/if-else.mir b/llvm/test/CodeGen/MIR2Vec/if-else.mir new file mode 100644 index 0000000..5734a23 --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/if-else.mir @@ -0,0 +1,144 @@ +# REQUIRES: x86-registered-target +# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=none -print-mir2vec -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_3D_vocab.json %s -o /dev/null 2>&1 | FileCheck %s + +--- | + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + + define dso_local i32 @abc(i32 noundef %a, i32 noundef %b) { + entry: + %retval = alloca i32, align 4 + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + store i32 %a, ptr %a.addr, align 4 + store i32 %b, ptr %b.addr, align 4 + %0 = load i32, ptr %a.addr, align 4 + %1 = load i32, ptr %b.addr, align 4 + %cmp = icmp sgt i32 %0, %1 + br i1 %cmp, label %if.then, label %if.else + + if.then: ; preds = %entry + %2 = load i32, ptr %b.addr, align 4 + store i32 %2, ptr %retval, align 4 + br label %return + + if.else: ; preds = %entry + %3 = load i32, ptr %a.addr, align 4 + store i32 %3, ptr %retval, align 4 + br label %return + + return: ; preds = %if.else, %if.then + %4 = load i32, ptr %retval, align 4 + ret i32 %4 + } +... +--- +name: abc +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: false +isSSA: true +noVRegs: false +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: true +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr32, preferred-register: '', flags: [ ] } + - { id: 1, class: gr32, preferred-register: '', flags: [ ] } + - { id: 2, class: gr32, preferred-register: '', flags: [ ] } + - { id: 3, class: gr32, preferred-register: '', flags: [ ] } + - { id: 4, class: gr32, preferred-register: '', flags: [ ] } + - { id: 5, class: gr32, preferred-register: '', flags: [ ] } +liveins: + - { reg: '$edi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: false + localFrameSize: 0 +fixedStack: [] +stack: + - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: a.addr, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: b.addr, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + amxProgModel: None +body: | + bb.0.entry: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $edi, $esi + + %1:gr32 = COPY $esi + %0:gr32 = COPY $edi + MOV32mr %stack.1.a.addr, 1, $noreg, 0, $noreg, %0 :: (store (s32) into %ir.a.addr) + MOV32mr %stack.2.b.addr, 1, $noreg, 0, $noreg, %1 :: (store (s32) into %ir.b.addr) + %2:gr32 = SUB32rr %0, %1, implicit-def $eflags + JCC_1 %bb.2, 14, implicit $eflags + JMP_1 %bb.1 + + bb.1.if.then: + successors: %bb.3(0x80000000) + + %4:gr32 = MOV32rm %stack.2.b.addr, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.b.addr) + MOV32mr %stack.0.retval, 1, $noreg, 0, $noreg, killed %4 :: (store (s32) into %ir.retval) + JMP_1 %bb.3 + + bb.2.if.else: + successors: %bb.3(0x80000000) + + %3:gr32 = MOV32rm %stack.1.a.addr, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.a.addr) + MOV32mr %stack.0.retval, 1, $noreg, 0, $noreg, killed %3 :: (store (s32) into %ir.retval) + + bb.3.return: + %5:gr32 = MOV32rm %stack.0.retval, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.retval) + $eax = COPY %5 + RET 0, $eax +... + +# CHECK: Machine basic block vectors: +# CHECK-NEXT: Machine basic block: abc:entry: +# CHECK-NEXT: [ 16.50 17.10 17.70 ] +# CHECK-NEXT: Machine basic block: abc:if.then: +# CHECK-NEXT: [ 4.50 4.80 5.10 ] +# CHECK-NEXT: Machine basic block: abc:if.else: +# CHECK-NEXT: [ 0.80 1.00 1.20 ] +# CHECK-NEXT: Machine basic block: abc:return: +# CHECK-NEXT: [ 6.60 6.90 7.20 ]
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/mir2vec-basic-symbolic.mir b/llvm/test/CodeGen/MIR2Vec/mir2vec-basic-symbolic.mir new file mode 100644 index 0000000..338cb63 --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/mir2vec-basic-symbolic.mir @@ -0,0 +1,76 @@ +# REQUIRES: x86-registered-target +# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=none -print-mir2vec -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_3D_vocab.json %s -o /dev/null 2>&1 | FileCheck %s + +--- | + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + + define dso_local noundef i32 @add_function(i32 noundef %a, i32 noundef %b) { + entry: + %sum = add nsw i32 %a, %b + %result = mul nsw i32 %sum, 2 + ret i32 %result + } + + define dso_local void @simple_function() { + entry: + ret void + } +... +--- +name: add_function +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32 } + - { id: 2, class: gr32 } + - { id: 3, class: gr32 } +liveins: + - { reg: '$edi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $edi, $esi + + %1:gr32 = COPY $esi + %0:gr32 = COPY $edi + %2:gr32 = nsw ADD32rr %0, %1, implicit-def dead $eflags + %3:gr32 = ADD32rr %2, %2, implicit-def dead $eflags + $eax = COPY %3 + RET 0, $eax + +--- +name: simple_function +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: + RET 0 + +# CHECK: MIR2Vec embeddings for machine function add_function: +# CHECK: Function vector: [ 19.20 19.80 20.40 ] +# CHECK-NEXT: Machine basic block vectors: +# CHECK-NEXT: Machine basic block: add_function:entry: +# CHECK-NEXT: [ 19.20 19.80 20.40 ] +# CHECK-NEXT: Machine instruction vectors: +# CHECK-NEXT: Machine instruction: %1:gr32 = COPY $esi +# CHECK-NEXT: [ 5.20 5.30 5.40 ] +# CHECK-NEXT: Machine instruction: %0:gr32 = COPY $edi +# CHECK-NEXT: [ 5.20 5.30 5.40 ] +# CHECK-NEXT: Machine instruction: %2:gr32 = nsw ADD32rr %0:gr32(tied-def 0), %1:gr32, implicit-def dead $eflags +# CHECK-NEXT: [ 1.30 1.40 1.50 ] +# CHECK-NEXT: Machine instruction: %3:gr32 = ADD32rr %2:gr32(tied-def 0), %2:gr32, implicit-def dead $eflags +# CHECK-NEXT: [ 1.30 1.40 1.50 ] +# CHECK-NEXT: Machine instruction: $eax = COPY %3:gr32 +# CHECK-NEXT: [ 5.20 5.30 5.40 ] +# CHECK-NEXT: Machine instruction: RET 0, $eax +# CHECK-NEXT: [ 1.00 1.10 1.20 ] + +# CHECK: MIR2Vec embeddings for machine function simple_function: +# CHECK-NEXT:Function vector: [ 1.00 1.10 1.20 ] +# CHECK-NEXT: Machine basic block vectors: +# CHECK-NEXT: Machine basic block: simple_function:entry: +# CHECK-NEXT: [ 1.00 1.10 1.20 ] +# CHECK-NEXT: Machine instruction vectors: +# CHECK-NEXT: Machine instruction: RET 0 +# CHECK-NEXT: [ 1.00 1.10 1.20 ]
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll b/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll index 80b4048..c6554bc 100644 --- a/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll +++ b/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll @@ -1,8 +1,8 @@ -; REQUIRES: x86_64-linux -; RUN: llc -o /dev/null -print-mir2vec-vocab %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID -; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_zero_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-ZERO-DIM -; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_invalid_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ENTITIES -; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_inconsistent_dims.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-INCONSISTENT-DIMS +; REQUIRES: x86-registered-target +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o /dev/null -print-mir2vec-vocab %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_zero_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-ZERO-DIM +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_invalid_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ENTITIES +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_inconsistent_dims.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-INCONSISTENT-DIMS define dso_local void @test() { entry: diff --git a/llvm/test/CodeGen/PowerPC/all-atomics.ll b/llvm/test/CodeGen/PowerPC/all-atomics.ll index 7e892fc..93968b71 100644 --- a/llvm/test/CodeGen/PowerPC/all-atomics.ll +++ b/llvm/test/CodeGen/PowerPC/all-atomics.ll @@ -33,7 +33,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 5, 0, 4 ; CHECK-NEXT: addi 5, 5, 1 ; CHECK-NEXT: stbcx. 5, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_1 +; CHECK-NEXT: bne- 0, .LBB0_1 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: addis 5, 2, uc@toc@ha ; CHECK-NEXT: lwsync @@ -44,7 +44,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 6, 0, 5 ; CHECK-NEXT: addi 6, 6, 1 ; CHECK-NEXT: stbcx. 6, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_3 +; CHECK-NEXT: bne- 0, .LBB0_3 ; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: addis 6, 2, ss@toc@ha ; CHECK-NEXT: lwsync @@ -55,7 +55,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 7, 0, 6 ; CHECK-NEXT: addi 7, 7, 1 ; CHECK-NEXT: sthcx. 7, 0, 6 -; CHECK-NEXT: bne 0, .LBB0_5 +; CHECK-NEXT: bne- 0, .LBB0_5 ; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: addis 7, 2, us@toc@ha ; CHECK-NEXT: lwsync @@ -66,7 +66,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 7, 0, 8 ; CHECK-NEXT: addi 7, 7, 1 ; CHECK-NEXT: sthcx. 7, 0, 8 -; CHECK-NEXT: bne 0, .LBB0_7 +; CHECK-NEXT: bne- 0, .LBB0_7 ; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: addis 7, 2, si@toc@ha ; CHECK-NEXT: lwsync @@ -77,7 +77,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 7, 0, 9 ; CHECK-NEXT: addi 7, 7, 1 ; CHECK-NEXT: stwcx. 7, 0, 9 -; CHECK-NEXT: bne 0, .LBB0_9 +; CHECK-NEXT: bne- 0, .LBB0_9 ; CHECK-NEXT: # %bb.10: # %entry ; CHECK-NEXT: addis 7, 2, ui@toc@ha ; CHECK-NEXT: lwsync @@ -88,7 +88,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 7, 0, 10 ; CHECK-NEXT: addi 7, 7, 1 ; CHECK-NEXT: stwcx. 7, 0, 10 -; CHECK-NEXT: bne 0, .LBB0_11 +; CHECK-NEXT: bne- 0, .LBB0_11 ; CHECK-NEXT: # %bb.12: # %entry ; CHECK-NEXT: addis 7, 2, sll@toc@ha ; CHECK-NEXT: lwsync @@ -100,7 +100,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 12, 0, 11 ; CHECK-NEXT: addi 12, 12, 1 ; CHECK-NEXT: stdcx. 12, 0, 11 -; CHECK-NEXT: bne 0, .LBB0_13 +; CHECK-NEXT: bne- 0, .LBB0_13 ; CHECK-NEXT: # %bb.14: # %entry ; CHECK-NEXT: addis 12, 2, ull@toc@ha ; CHECK-NEXT: lwsync @@ -111,7 +111,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 30, 0, 12 ; CHECK-NEXT: addi 0, 30, 1 ; CHECK-NEXT: stdcx. 0, 0, 12 -; CHECK-NEXT: bne 0, .LBB0_15 +; CHECK-NEXT: bne- 0, .LBB0_15 ; CHECK-NEXT: # %bb.16: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -120,7 +120,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 4 ; CHECK-NEXT: sub 0, 0, 3 ; CHECK-NEXT: stbcx. 0, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_17 +; CHECK-NEXT: bne- 0, .LBB0_17 ; CHECK-NEXT: # %bb.18: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -129,7 +129,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 5 ; CHECK-NEXT: sub 0, 0, 3 ; CHECK-NEXT: stbcx. 0, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_19 +; CHECK-NEXT: bne- 0, .LBB0_19 ; CHECK-NEXT: # %bb.20: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -138,7 +138,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 6 ; CHECK-NEXT: sub 0, 0, 3 ; CHECK-NEXT: sthcx. 0, 0, 6 -; CHECK-NEXT: bne 0, .LBB0_21 +; CHECK-NEXT: bne- 0, .LBB0_21 ; CHECK-NEXT: # %bb.22: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -147,7 +147,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 8 ; CHECK-NEXT: sub 0, 0, 3 ; CHECK-NEXT: sthcx. 0, 0, 8 -; CHECK-NEXT: bne 0, .LBB0_23 +; CHECK-NEXT: bne- 0, .LBB0_23 ; CHECK-NEXT: # %bb.24: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -156,7 +156,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 9 ; CHECK-NEXT: sub 0, 0, 3 ; CHECK-NEXT: stwcx. 0, 0, 9 -; CHECK-NEXT: bne 0, .LBB0_25 +; CHECK-NEXT: bne- 0, .LBB0_25 ; CHECK-NEXT: # %bb.26: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -165,7 +165,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 10 ; CHECK-NEXT: sub 0, 0, 3 ; CHECK-NEXT: stwcx. 0, 0, 10 -; CHECK-NEXT: bne 0, .LBB0_27 +; CHECK-NEXT: bne- 0, .LBB0_27 ; CHECK-NEXT: # %bb.28: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -174,7 +174,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 11 ; CHECK-NEXT: sub 0, 0, 7 ; CHECK-NEXT: stdcx. 0, 0, 11 -; CHECK-NEXT: bne 0, .LBB0_29 +; CHECK-NEXT: bne- 0, .LBB0_29 ; CHECK-NEXT: # %bb.30: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -183,7 +183,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 12 ; CHECK-NEXT: sub 0, 0, 7 ; CHECK-NEXT: stdcx. 0, 0, 12 -; CHECK-NEXT: bne 0, .LBB0_31 +; CHECK-NEXT: bne- 0, .LBB0_31 ; CHECK-NEXT: # %bb.32: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -192,7 +192,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 4 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: stbcx. 0, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_33 +; CHECK-NEXT: bne- 0, .LBB0_33 ; CHECK-NEXT: # %bb.34: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -201,7 +201,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 5 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: stbcx. 0, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_35 +; CHECK-NEXT: bne- 0, .LBB0_35 ; CHECK-NEXT: # %bb.36: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -210,7 +210,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 6 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: sthcx. 0, 0, 6 -; CHECK-NEXT: bne 0, .LBB0_37 +; CHECK-NEXT: bne- 0, .LBB0_37 ; CHECK-NEXT: # %bb.38: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -219,7 +219,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 8 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: sthcx. 0, 0, 8 -; CHECK-NEXT: bne 0, .LBB0_39 +; CHECK-NEXT: bne- 0, .LBB0_39 ; CHECK-NEXT: # %bb.40: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -228,7 +228,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 9 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: stwcx. 0, 0, 9 -; CHECK-NEXT: bne 0, .LBB0_41 +; CHECK-NEXT: bne- 0, .LBB0_41 ; CHECK-NEXT: # %bb.42: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -237,7 +237,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 10 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: stwcx. 0, 0, 10 -; CHECK-NEXT: bne 0, .LBB0_43 +; CHECK-NEXT: bne- 0, .LBB0_43 ; CHECK-NEXT: # %bb.44: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -246,7 +246,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 11 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: stdcx. 0, 0, 11 -; CHECK-NEXT: bne 0, .LBB0_45 +; CHECK-NEXT: bne- 0, .LBB0_45 ; CHECK-NEXT: # %bb.46: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -255,7 +255,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 12 ; CHECK-NEXT: ori 0, 0, 1 ; CHECK-NEXT: stdcx. 0, 0, 12 -; CHECK-NEXT: bne 0, .LBB0_47 +; CHECK-NEXT: bne- 0, .LBB0_47 ; CHECK-NEXT: # %bb.48: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -264,7 +264,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 4 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: stbcx. 0, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_49 +; CHECK-NEXT: bne- 0, .LBB0_49 ; CHECK-NEXT: # %bb.50: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -273,7 +273,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 5 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: stbcx. 0, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_51 +; CHECK-NEXT: bne- 0, .LBB0_51 ; CHECK-NEXT: # %bb.52: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -282,7 +282,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 6 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: sthcx. 0, 0, 6 -; CHECK-NEXT: bne 0, .LBB0_53 +; CHECK-NEXT: bne- 0, .LBB0_53 ; CHECK-NEXT: # %bb.54: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -291,7 +291,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 8 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: sthcx. 0, 0, 8 -; CHECK-NEXT: bne 0, .LBB0_55 +; CHECK-NEXT: bne- 0, .LBB0_55 ; CHECK-NEXT: # %bb.56: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -300,7 +300,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 9 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: stwcx. 0, 0, 9 -; CHECK-NEXT: bne 0, .LBB0_57 +; CHECK-NEXT: bne- 0, .LBB0_57 ; CHECK-NEXT: # %bb.58: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -309,7 +309,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 10 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: stwcx. 0, 0, 10 -; CHECK-NEXT: bne 0, .LBB0_59 +; CHECK-NEXT: bne- 0, .LBB0_59 ; CHECK-NEXT: # %bb.60: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -318,7 +318,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 11 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: stdcx. 0, 0, 11 -; CHECK-NEXT: bne 0, .LBB0_61 +; CHECK-NEXT: bne- 0, .LBB0_61 ; CHECK-NEXT: # %bb.62: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -327,7 +327,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 12 ; CHECK-NEXT: xori 0, 0, 1 ; CHECK-NEXT: stdcx. 0, 0, 12 -; CHECK-NEXT: bne 0, .LBB0_63 +; CHECK-NEXT: bne- 0, .LBB0_63 ; CHECK-NEXT: # %bb.64: # %entry ; CHECK-NEXT: addis 30, 2, u128@toc@ha ; CHECK-NEXT: lwsync @@ -361,7 +361,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 4 ; CHECK-NEXT: nand 0, 3, 0 ; CHECK-NEXT: stbcx. 0, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_69 +; CHECK-NEXT: bne- 0, .LBB0_69 ; CHECK-NEXT: # %bb.70: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -370,7 +370,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 5 ; CHECK-NEXT: nand 0, 3, 0 ; CHECK-NEXT: stbcx. 0, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_71 +; CHECK-NEXT: bne- 0, .LBB0_71 ; CHECK-NEXT: # %bb.72: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -379,7 +379,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 6 ; CHECK-NEXT: nand 0, 3, 0 ; CHECK-NEXT: sthcx. 0, 0, 6 -; CHECK-NEXT: bne 0, .LBB0_73 +; CHECK-NEXT: bne- 0, .LBB0_73 ; CHECK-NEXT: # %bb.74: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -388,7 +388,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 0, 0, 8 ; CHECK-NEXT: nand 0, 3, 0 ; CHECK-NEXT: sthcx. 0, 0, 8 -; CHECK-NEXT: bne 0, .LBB0_75 +; CHECK-NEXT: bne- 0, .LBB0_75 ; CHECK-NEXT: # %bb.76: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -397,7 +397,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 9 ; CHECK-NEXT: nand 0, 3, 0 ; CHECK-NEXT: stwcx. 0, 0, 9 -; CHECK-NEXT: bne 0, .LBB0_77 +; CHECK-NEXT: bne- 0, .LBB0_77 ; CHECK-NEXT: # %bb.78: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -406,7 +406,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 0, 0, 10 ; CHECK-NEXT: nand 0, 3, 0 ; CHECK-NEXT: stwcx. 0, 0, 10 -; CHECK-NEXT: bne 0, .LBB0_79 +; CHECK-NEXT: bne- 0, .LBB0_79 ; CHECK-NEXT: # %bb.80: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -415,7 +415,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 11 ; CHECK-NEXT: nand 0, 7, 0 ; CHECK-NEXT: stdcx. 0, 0, 11 -; CHECK-NEXT: bne 0, .LBB0_81 +; CHECK-NEXT: bne- 0, .LBB0_81 ; CHECK-NEXT: # %bb.82: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -424,7 +424,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 0, 0, 12 ; CHECK-NEXT: nand 0, 7, 0 ; CHECK-NEXT: stdcx. 0, 0, 12 -; CHECK-NEXT: bne 0, .LBB0_83 +; CHECK-NEXT: bne- 0, .LBB0_83 ; CHECK-NEXT: # %bb.84: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -433,7 +433,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 0, 0, 4 ; CHECK-NEXT: and 0, 3, 0 ; CHECK-NEXT: stbcx. 0, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_85 +; CHECK-NEXT: bne- 0, .LBB0_85 ; CHECK-NEXT: # %bb.86: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -442,7 +442,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 4, 0, 5 ; CHECK-NEXT: and 4, 3, 4 ; CHECK-NEXT: stbcx. 4, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_87 +; CHECK-NEXT: bne- 0, .LBB0_87 ; CHECK-NEXT: # %bb.88: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -451,7 +451,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 4, 0, 6 ; CHECK-NEXT: and 4, 3, 4 ; CHECK-NEXT: sthcx. 4, 0, 6 -; CHECK-NEXT: bne 0, .LBB0_89 +; CHECK-NEXT: bne- 0, .LBB0_89 ; CHECK-NEXT: # %bb.90: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -460,7 +460,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 4, 0, 8 ; CHECK-NEXT: and 4, 3, 4 ; CHECK-NEXT: sthcx. 4, 0, 8 -; CHECK-NEXT: bne 0, .LBB0_91 +; CHECK-NEXT: bne- 0, .LBB0_91 ; CHECK-NEXT: # %bb.92: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -469,7 +469,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 4, 0, 9 ; CHECK-NEXT: and 4, 3, 4 ; CHECK-NEXT: stwcx. 4, 0, 9 -; CHECK-NEXT: bne 0, .LBB0_93 +; CHECK-NEXT: bne- 0, .LBB0_93 ; CHECK-NEXT: # %bb.94: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -478,7 +478,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 4, 0, 10 ; CHECK-NEXT: and 4, 3, 4 ; CHECK-NEXT: stwcx. 4, 0, 10 -; CHECK-NEXT: bne 0, .LBB0_95 +; CHECK-NEXT: bne- 0, .LBB0_95 ; CHECK-NEXT: # %bb.96: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -487,7 +487,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 3, 0, 11 ; CHECK-NEXT: and 3, 7, 3 ; CHECK-NEXT: stdcx. 3, 0, 11 -; CHECK-NEXT: bne 0, .LBB0_97 +; CHECK-NEXT: bne- 0, .LBB0_97 ; CHECK-NEXT: # %bb.98: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sync @@ -496,7 +496,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 3, 0, 12 ; CHECK-NEXT: and 3, 7, 3 ; CHECK-NEXT: stdcx. 3, 0, 12 -; CHECK-NEXT: bne 0, .LBB0_99 +; CHECK-NEXT: bne- 0, .LBB0_99 ; CHECK-NEXT: # %bb.100: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload @@ -545,7 +545,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB0_1 +; AIX32-NEXT: bne- 0, L..BB0_1 ; AIX32-NEXT: # %bb.2: # %entry ; AIX32-NEXT: lwz 3, L..C1(2) # @uc ; AIX32-NEXT: lwsync @@ -564,7 +564,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: bne 0, L..BB0_3 +; AIX32-NEXT: bne- 0, L..BB0_3 ; AIX32-NEXT: # %bb.4: # %entry ; AIX32-NEXT: lwz 3, L..C2(2) # @ss ; AIX32-NEXT: lwsync @@ -584,7 +584,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB0_5 +; AIX32-NEXT: bne- 0, L..BB0_5 ; AIX32-NEXT: # %bb.6: # %entry ; AIX32-NEXT: lwz 3, L..C3(2) # @us ; AIX32-NEXT: lwsync @@ -604,7 +604,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 23 -; AIX32-NEXT: bne 0, L..BB0_7 +; AIX32-NEXT: bne- 0, L..BB0_7 ; AIX32-NEXT: # %bb.8: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: lwz 20, L..C4(2) # @si @@ -614,7 +614,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 20 ; AIX32-NEXT: addi 3, 3, 1 ; AIX32-NEXT: stwcx. 3, 0, 20 -; AIX32-NEXT: bne 0, L..BB0_9 +; AIX32-NEXT: bne- 0, L..BB0_9 ; AIX32-NEXT: # %bb.10: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: lwz 19, L..C5(2) # @ui @@ -624,7 +624,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 19 ; AIX32-NEXT: addi 3, 3, 1 ; AIX32-NEXT: stwcx. 3, 0, 19 -; AIX32-NEXT: bne 0, L..BB0_11 +; AIX32-NEXT: bne- 0, L..BB0_11 ; AIX32-NEXT: # %bb.12: # %entry ; AIX32-NEXT: lwz 31, L..C6(2) # @sll ; AIX32-NEXT: lwsync @@ -652,7 +652,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB0_13 +; AIX32-NEXT: bne- 0, L..BB0_13 ; AIX32-NEXT: # %bb.14: # %entry ; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: lwsync @@ -666,7 +666,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: bne 0, L..BB0_15 +; AIX32-NEXT: bne- 0, L..BB0_15 ; AIX32-NEXT: # %bb.16: # %entry ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -681,7 +681,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB0_17 +; AIX32-NEXT: bne- 0, L..BB0_17 ; AIX32-NEXT: # %bb.18: # %entry ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -696,7 +696,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 23 -; AIX32-NEXT: bne 0, L..BB0_19 +; AIX32-NEXT: bne- 0, L..BB0_19 ; AIX32-NEXT: # %bb.20: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -705,7 +705,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 20 ; AIX32-NEXT: sub 3, 3, 15 ; AIX32-NEXT: stwcx. 3, 0, 20 -; AIX32-NEXT: bne 0, L..BB0_21 +; AIX32-NEXT: bne- 0, L..BB0_21 ; AIX32-NEXT: # %bb.22: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -714,7 +714,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 19 ; AIX32-NEXT: sub 3, 3, 15 ; AIX32-NEXT: stwcx. 3, 0, 19 -; AIX32-NEXT: bne 0, L..BB0_23 +; AIX32-NEXT: bne- 0, L..BB0_23 ; AIX32-NEXT: # %bb.24: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -740,7 +740,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB0_25 +; AIX32-NEXT: bne- 0, L..BB0_25 ; AIX32-NEXT: # %bb.26: # %entry ; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: lwsync @@ -754,7 +754,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: bne 0, L..BB0_27 +; AIX32-NEXT: bne- 0, L..BB0_27 ; AIX32-NEXT: # %bb.28: # %entry ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -769,7 +769,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB0_29 +; AIX32-NEXT: bne- 0, L..BB0_29 ; AIX32-NEXT: # %bb.30: # %entry ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -784,7 +784,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 23 -; AIX32-NEXT: bne 0, L..BB0_31 +; AIX32-NEXT: bne- 0, L..BB0_31 ; AIX32-NEXT: # %bb.32: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -793,7 +793,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 20 ; AIX32-NEXT: ori 3, 3, 1 ; AIX32-NEXT: stwcx. 3, 0, 20 -; AIX32-NEXT: bne 0, L..BB0_33 +; AIX32-NEXT: bne- 0, L..BB0_33 ; AIX32-NEXT: # %bb.34: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -802,7 +802,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 19 ; AIX32-NEXT: ori 3, 3, 1 ; AIX32-NEXT: stwcx. 3, 0, 19 -; AIX32-NEXT: bne 0, L..BB0_35 +; AIX32-NEXT: bne- 0, L..BB0_35 ; AIX32-NEXT: # %bb.36: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -828,7 +828,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB0_37 +; AIX32-NEXT: bne- 0, L..BB0_37 ; AIX32-NEXT: # %bb.38: # %entry ; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: lwsync @@ -842,7 +842,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: bne 0, L..BB0_39 +; AIX32-NEXT: bne- 0, L..BB0_39 ; AIX32-NEXT: # %bb.40: # %entry ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -857,7 +857,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB0_41 +; AIX32-NEXT: bne- 0, L..BB0_41 ; AIX32-NEXT: # %bb.42: # %entry ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -872,7 +872,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 23 -; AIX32-NEXT: bne 0, L..BB0_43 +; AIX32-NEXT: bne- 0, L..BB0_43 ; AIX32-NEXT: # %bb.44: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -881,7 +881,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 20 ; AIX32-NEXT: xori 3, 3, 1 ; AIX32-NEXT: stwcx. 3, 0, 20 -; AIX32-NEXT: bne 0, L..BB0_45 +; AIX32-NEXT: bne- 0, L..BB0_45 ; AIX32-NEXT: # %bb.46: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -890,7 +890,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 19 ; AIX32-NEXT: xori 3, 3, 1 ; AIX32-NEXT: stwcx. 3, 0, 19 -; AIX32-NEXT: bne 0, L..BB0_47 +; AIX32-NEXT: bne- 0, L..BB0_47 ; AIX32-NEXT: # %bb.48: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -986,7 +986,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB0_53 +; AIX32-NEXT: bne- 0, L..BB0_53 ; AIX32-NEXT: # %bb.54: # %atomicrmw.end ; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: lwsync @@ -1001,7 +1001,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: bne 0, L..BB0_55 +; AIX32-NEXT: bne- 0, L..BB0_55 ; AIX32-NEXT: # %bb.56: # %atomicrmw.end ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -1017,7 +1017,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB0_57 +; AIX32-NEXT: bne- 0, L..BB0_57 ; AIX32-NEXT: # %bb.58: # %atomicrmw.end ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -1033,7 +1033,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 23 -; AIX32-NEXT: bne 0, L..BB0_59 +; AIX32-NEXT: bne- 0, L..BB0_59 ; AIX32-NEXT: # %bb.60: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -1042,7 +1042,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 20 ; AIX32-NEXT: nand 3, 29, 3 ; AIX32-NEXT: stwcx. 3, 0, 20 -; AIX32-NEXT: bne 0, L..BB0_61 +; AIX32-NEXT: bne- 0, L..BB0_61 ; AIX32-NEXT: # %bb.62: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -1051,7 +1051,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 19 ; AIX32-NEXT: nand 3, 29, 3 ; AIX32-NEXT: stwcx. 3, 0, 19 -; AIX32-NEXT: bne 0, L..BB0_63 +; AIX32-NEXT: bne- 0, L..BB0_63 ; AIX32-NEXT: # %bb.64: # %atomicrmw.end ; AIX32-NEXT: lwz 31, L..C6(2) # @sll ; AIX32-NEXT: lwsync @@ -1079,7 +1079,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB0_65 +; AIX32-NEXT: bne- 0, L..BB0_65 ; AIX32-NEXT: # %bb.66: # %atomicrmw.end ; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: lwsync @@ -1093,7 +1093,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: bne 0, L..BB0_67 +; AIX32-NEXT: bne- 0, L..BB0_67 ; AIX32-NEXT: # %bb.68: # %atomicrmw.end ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -1108,7 +1108,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB0_69 +; AIX32-NEXT: bne- 0, L..BB0_69 ; AIX32-NEXT: # %bb.70: # %atomicrmw.end ; AIX32-NEXT: li 3, 0 ; AIX32-NEXT: lwsync @@ -1123,7 +1123,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 4, 5, 4 ; AIX32-NEXT: stwcx. 4, 0, 23 -; AIX32-NEXT: bne 0, L..BB0_71 +; AIX32-NEXT: bne- 0, L..BB0_71 ; AIX32-NEXT: # %bb.72: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -1132,7 +1132,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 20 ; AIX32-NEXT: and 3, 29, 3 ; AIX32-NEXT: stwcx. 3, 0, 20 -; AIX32-NEXT: bne 0, L..BB0_73 +; AIX32-NEXT: bne- 0, L..BB0_73 ; AIX32-NEXT: # %bb.74: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: sync @@ -1141,7 +1141,7 @@ define dso_local void @test_op_ignore() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 19 ; AIX32-NEXT: and 3, 29, 3 ; AIX32-NEXT: stwcx. 3, 0, 19 -; AIX32-NEXT: bne 0, L..BB0_75 +; AIX32-NEXT: bne- 0, L..BB0_75 ; AIX32-NEXT: # %bb.76: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -1252,7 +1252,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 5, 0, 6 ; CHECK-NEXT: addi 7, 5, 11 ; CHECK-NEXT: stbcx. 7, 0, 6 -; CHECK-NEXT: bne 0, .LBB1_1 +; CHECK-NEXT: bne- 0, .LBB1_1 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 5, sc@toc@l(4) @@ -1264,7 +1264,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 7, 0, 8 ; CHECK-NEXT: addi 9, 7, 11 ; CHECK-NEXT: stbcx. 9, 0, 8 -; CHECK-NEXT: bne 0, .LBB1_3 +; CHECK-NEXT: bne- 0, .LBB1_3 ; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 7, uc@toc@l(5) @@ -1276,7 +1276,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 9, 0, 10 ; CHECK-NEXT: addi 11, 9, 11 ; CHECK-NEXT: sthcx. 11, 0, 10 -; CHECK-NEXT: bne 0, .LBB1_5 +; CHECK-NEXT: bne- 0, .LBB1_5 ; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 9, ss@toc@l(7) @@ -1288,7 +1288,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 11, 0, 0 ; CHECK-NEXT: addi 12, 11, 11 ; CHECK-NEXT: sthcx. 12, 0, 0 -; CHECK-NEXT: bne 0, .LBB1_7 +; CHECK-NEXT: bne- 0, .LBB1_7 ; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: addis 12, 2, si@toc@ha ; CHECK-NEXT: lwsync @@ -1300,7 +1300,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 11, 0, 29 ; CHECK-NEXT: addi 30, 11, 11 ; CHECK-NEXT: stwcx. 30, 0, 29 -; CHECK-NEXT: bne 0, .LBB1_9 +; CHECK-NEXT: bne- 0, .LBB1_9 ; CHECK-NEXT: # %bb.10: # %entry ; CHECK-NEXT: addis 30, 2, ui@toc@ha ; CHECK-NEXT: lwsync @@ -1312,7 +1312,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 11, 0, 27 ; CHECK-NEXT: addi 28, 11, 11 ; CHECK-NEXT: stwcx. 28, 0, 27 -; CHECK-NEXT: bne 0, .LBB1_11 +; CHECK-NEXT: bne- 0, .LBB1_11 ; CHECK-NEXT: # %bb.12: # %entry ; CHECK-NEXT: addis 28, 2, sll@toc@ha ; CHECK-NEXT: lwsync @@ -1325,7 +1325,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 26, 0, 25 ; CHECK-NEXT: addi 24, 26, 11 ; CHECK-NEXT: stdcx. 24, 0, 25 -; CHECK-NEXT: bne 0, .LBB1_13 +; CHECK-NEXT: bne- 0, .LBB1_13 ; CHECK-NEXT: # %bb.14: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 26, sll@toc@l(28) @@ -1337,7 +1337,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 24 ; CHECK-NEXT: addi 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 24 -; CHECK-NEXT: bne 0, .LBB1_15 +; CHECK-NEXT: bne- 0, .LBB1_15 ; CHECK-NEXT: # %bb.16: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, ull@toc@l(26) @@ -1347,7 +1347,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 6 ; CHECK-NEXT: sub 22, 23, 3 ; CHECK-NEXT: stbcx. 22, 0, 6 -; CHECK-NEXT: bne 0, .LBB1_17 +; CHECK-NEXT: bne- 0, .LBB1_17 ; CHECK-NEXT: # %bb.18: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, sc@toc@l(4) @@ -1357,7 +1357,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 8 ; CHECK-NEXT: sub 22, 23, 3 ; CHECK-NEXT: stbcx. 22, 0, 8 -; CHECK-NEXT: bne 0, .LBB1_19 +; CHECK-NEXT: bne- 0, .LBB1_19 ; CHECK-NEXT: # %bb.20: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, uc@toc@l(5) @@ -1367,7 +1367,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 10 ; CHECK-NEXT: sub 22, 23, 3 ; CHECK-NEXT: sthcx. 22, 0, 10 -; CHECK-NEXT: bne 0, .LBB1_21 +; CHECK-NEXT: bne- 0, .LBB1_21 ; CHECK-NEXT: # %bb.22: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, ss@toc@l(7) @@ -1377,7 +1377,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 0 ; CHECK-NEXT: sub 22, 23, 3 ; CHECK-NEXT: sthcx. 22, 0, 0 -; CHECK-NEXT: bne 0, .LBB1_23 +; CHECK-NEXT: bne- 0, .LBB1_23 ; CHECK-NEXT: # %bb.24: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, us@toc@l(9) @@ -1387,7 +1387,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 29 ; CHECK-NEXT: sub 22, 23, 3 ; CHECK-NEXT: stwcx. 22, 0, 29 -; CHECK-NEXT: bne 0, .LBB1_25 +; CHECK-NEXT: bne- 0, .LBB1_25 ; CHECK-NEXT: # %bb.26: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, si@toc@l(12) @@ -1397,7 +1397,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 27 ; CHECK-NEXT: sub 22, 23, 3 ; CHECK-NEXT: stwcx. 22, 0, 27 -; CHECK-NEXT: bne 0, .LBB1_27 +; CHECK-NEXT: bne- 0, .LBB1_27 ; CHECK-NEXT: # %bb.28: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, ui@toc@l(30) @@ -1407,7 +1407,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 25 ; CHECK-NEXT: sub 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 25 -; CHECK-NEXT: bne 0, .LBB1_29 +; CHECK-NEXT: bne- 0, .LBB1_29 ; CHECK-NEXT: # %bb.30: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, sll@toc@l(28) @@ -1417,7 +1417,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 24 ; CHECK-NEXT: sub 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 24 -; CHECK-NEXT: bne 0, .LBB1_31 +; CHECK-NEXT: bne- 0, .LBB1_31 ; CHECK-NEXT: # %bb.32: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, ull@toc@l(26) @@ -1427,7 +1427,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 6 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: stbcx. 22, 0, 6 -; CHECK-NEXT: bne 0, .LBB1_33 +; CHECK-NEXT: bne- 0, .LBB1_33 ; CHECK-NEXT: # %bb.34: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, sc@toc@l(4) @@ -1437,7 +1437,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 8 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: stbcx. 22, 0, 8 -; CHECK-NEXT: bne 0, .LBB1_35 +; CHECK-NEXT: bne- 0, .LBB1_35 ; CHECK-NEXT: # %bb.36: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, uc@toc@l(5) @@ -1447,7 +1447,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 10 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: sthcx. 22, 0, 10 -; CHECK-NEXT: bne 0, .LBB1_37 +; CHECK-NEXT: bne- 0, .LBB1_37 ; CHECK-NEXT: # %bb.38: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, ss@toc@l(7) @@ -1457,7 +1457,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 0 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: sthcx. 22, 0, 0 -; CHECK-NEXT: bne 0, .LBB1_39 +; CHECK-NEXT: bne- 0, .LBB1_39 ; CHECK-NEXT: # %bb.40: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, us@toc@l(9) @@ -1467,7 +1467,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 29 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: stwcx. 22, 0, 29 -; CHECK-NEXT: bne 0, .LBB1_41 +; CHECK-NEXT: bne- 0, .LBB1_41 ; CHECK-NEXT: # %bb.42: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, si@toc@l(12) @@ -1477,7 +1477,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 27 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: stwcx. 22, 0, 27 -; CHECK-NEXT: bne 0, .LBB1_43 +; CHECK-NEXT: bne- 0, .LBB1_43 ; CHECK-NEXT: # %bb.44: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, ui@toc@l(30) @@ -1487,7 +1487,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 25 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 25 -; CHECK-NEXT: bne 0, .LBB1_45 +; CHECK-NEXT: bne- 0, .LBB1_45 ; CHECK-NEXT: # %bb.46: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, sll@toc@l(28) @@ -1497,7 +1497,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 24 ; CHECK-NEXT: ori 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 24 -; CHECK-NEXT: bne 0, .LBB1_47 +; CHECK-NEXT: bne- 0, .LBB1_47 ; CHECK-NEXT: # %bb.48: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, ull@toc@l(26) @@ -1507,7 +1507,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 6 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: stbcx. 22, 0, 6 -; CHECK-NEXT: bne 0, .LBB1_49 +; CHECK-NEXT: bne- 0, .LBB1_49 ; CHECK-NEXT: # %bb.50: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, sc@toc@l(4) @@ -1517,7 +1517,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 8 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: stbcx. 22, 0, 8 -; CHECK-NEXT: bne 0, .LBB1_51 +; CHECK-NEXT: bne- 0, .LBB1_51 ; CHECK-NEXT: # %bb.52: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, uc@toc@l(5) @@ -1527,7 +1527,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 10 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: sthcx. 22, 0, 10 -; CHECK-NEXT: bne 0, .LBB1_53 +; CHECK-NEXT: bne- 0, .LBB1_53 ; CHECK-NEXT: # %bb.54: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, ss@toc@l(7) @@ -1537,7 +1537,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 0 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: sthcx. 22, 0, 0 -; CHECK-NEXT: bne 0, .LBB1_55 +; CHECK-NEXT: bne- 0, .LBB1_55 ; CHECK-NEXT: # %bb.56: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, us@toc@l(9) @@ -1547,7 +1547,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 29 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: stwcx. 22, 0, 29 -; CHECK-NEXT: bne 0, .LBB1_57 +; CHECK-NEXT: bne- 0, .LBB1_57 ; CHECK-NEXT: # %bb.58: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, si@toc@l(12) @@ -1557,7 +1557,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 27 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: stwcx. 22, 0, 27 -; CHECK-NEXT: bne 0, .LBB1_59 +; CHECK-NEXT: bne- 0, .LBB1_59 ; CHECK-NEXT: # %bb.60: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, ui@toc@l(30) @@ -1567,7 +1567,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 25 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 25 -; CHECK-NEXT: bne 0, .LBB1_61 +; CHECK-NEXT: bne- 0, .LBB1_61 ; CHECK-NEXT: # %bb.62: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, sll@toc@l(28) @@ -1577,7 +1577,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 24 ; CHECK-NEXT: xori 22, 23, 11 ; CHECK-NEXT: stdcx. 22, 0, 24 -; CHECK-NEXT: bne 0, .LBB1_63 +; CHECK-NEXT: bne- 0, .LBB1_63 ; CHECK-NEXT: # %bb.64: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, ull@toc@l(26) @@ -1587,7 +1587,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 6 ; CHECK-NEXT: nand 22, 3, 23 ; CHECK-NEXT: stbcx. 22, 0, 6 -; CHECK-NEXT: bne 0, .LBB1_65 +; CHECK-NEXT: bne- 0, .LBB1_65 ; CHECK-NEXT: # %bb.66: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, sc@toc@l(4) @@ -1597,7 +1597,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 8 ; CHECK-NEXT: nand 22, 3, 23 ; CHECK-NEXT: stbcx. 22, 0, 8 -; CHECK-NEXT: bne 0, .LBB1_67 +; CHECK-NEXT: bne- 0, .LBB1_67 ; CHECK-NEXT: # %bb.68: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, uc@toc@l(5) @@ -1607,7 +1607,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 10 ; CHECK-NEXT: nand 22, 3, 23 ; CHECK-NEXT: sthcx. 22, 0, 10 -; CHECK-NEXT: bne 0, .LBB1_69 +; CHECK-NEXT: bne- 0, .LBB1_69 ; CHECK-NEXT: # %bb.70: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, ss@toc@l(7) @@ -1617,7 +1617,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 23, 0, 0 ; CHECK-NEXT: nand 22, 3, 23 ; CHECK-NEXT: sthcx. 22, 0, 0 -; CHECK-NEXT: bne 0, .LBB1_71 +; CHECK-NEXT: bne- 0, .LBB1_71 ; CHECK-NEXT: # %bb.72: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 23, us@toc@l(9) @@ -1627,7 +1627,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 29 ; CHECK-NEXT: nand 22, 3, 23 ; CHECK-NEXT: stwcx. 22, 0, 29 -; CHECK-NEXT: bne 0, .LBB1_73 +; CHECK-NEXT: bne- 0, .LBB1_73 ; CHECK-NEXT: # %bb.74: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, si@toc@l(12) @@ -1637,7 +1637,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 23, 0, 27 ; CHECK-NEXT: nand 22, 3, 23 ; CHECK-NEXT: stwcx. 22, 0, 27 -; CHECK-NEXT: bne 0, .LBB1_75 +; CHECK-NEXT: bne- 0, .LBB1_75 ; CHECK-NEXT: # %bb.76: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 23, ui@toc@l(30) @@ -1647,7 +1647,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 25 ; CHECK-NEXT: nand 22, 11, 23 ; CHECK-NEXT: stdcx. 22, 0, 25 -; CHECK-NEXT: bne 0, .LBB1_77 +; CHECK-NEXT: bne- 0, .LBB1_77 ; CHECK-NEXT: # %bb.78: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, sll@toc@l(28) @@ -1657,7 +1657,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 23, 0, 24 ; CHECK-NEXT: nand 22, 11, 23 ; CHECK-NEXT: stdcx. 22, 0, 24 -; CHECK-NEXT: bne 0, .LBB1_79 +; CHECK-NEXT: bne- 0, .LBB1_79 ; CHECK-NEXT: # %bb.80: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 23, ull@toc@l(26) @@ -1667,7 +1667,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 23, 0, 6 ; CHECK-NEXT: and 22, 3, 23 ; CHECK-NEXT: stbcx. 22, 0, 6 -; CHECK-NEXT: bne 0, .LBB1_81 +; CHECK-NEXT: bne- 0, .LBB1_81 ; CHECK-NEXT: # %bb.82: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 23, sc@toc@l(4) @@ -1677,7 +1677,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 4, 0, 8 ; CHECK-NEXT: and 6, 3, 4 ; CHECK-NEXT: stbcx. 6, 0, 8 -; CHECK-NEXT: bne 0, .LBB1_83 +; CHECK-NEXT: bne- 0, .LBB1_83 ; CHECK-NEXT: # %bb.84: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 4, uc@toc@l(5) @@ -1687,7 +1687,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 4, 0, 10 ; CHECK-NEXT: and 5, 3, 4 ; CHECK-NEXT: sthcx. 5, 0, 10 -; CHECK-NEXT: bne 0, .LBB1_85 +; CHECK-NEXT: bne- 0, .LBB1_85 ; CHECK-NEXT: # %bb.86: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 4, ss@toc@l(7) @@ -1697,7 +1697,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 4, 0, 0 ; CHECK-NEXT: and 5, 3, 4 ; CHECK-NEXT: sthcx. 5, 0, 0 -; CHECK-NEXT: bne 0, .LBB1_87 +; CHECK-NEXT: bne- 0, .LBB1_87 ; CHECK-NEXT: # %bb.88: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 4, us@toc@l(9) @@ -1707,7 +1707,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 4, 0, 29 ; CHECK-NEXT: and 5, 3, 4 ; CHECK-NEXT: stwcx. 5, 0, 29 -; CHECK-NEXT: bne 0, .LBB1_89 +; CHECK-NEXT: bne- 0, .LBB1_89 ; CHECK-NEXT: # %bb.90: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 4, si@toc@l(12) @@ -1717,7 +1717,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 4, 0, 27 ; CHECK-NEXT: and 5, 3, 4 ; CHECK-NEXT: stwcx. 5, 0, 27 -; CHECK-NEXT: bne 0, .LBB1_91 +; CHECK-NEXT: bne- 0, .LBB1_91 ; CHECK-NEXT: # %bb.92: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 4, ui@toc@l(30) @@ -1727,7 +1727,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 3, 0, 25 ; CHECK-NEXT: and 4, 11, 3 ; CHECK-NEXT: stdcx. 4, 0, 25 -; CHECK-NEXT: bne 0, .LBB1_93 +; CHECK-NEXT: bne- 0, .LBB1_93 ; CHECK-NEXT: # %bb.94: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 3, sll@toc@l(28) @@ -1737,7 +1737,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 3, 0, 24 ; CHECK-NEXT: and 4, 11, 3 ; CHECK-NEXT: stdcx. 4, 0, 24 -; CHECK-NEXT: bne 0, .LBB1_95 +; CHECK-NEXT: bne- 0, .LBB1_95 ; CHECK-NEXT: # %bb.96: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 3, ull@toc@l(26) @@ -1794,7 +1794,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 25 -; AIX32-NEXT: bne 0, L..BB1_1 +; AIX32-NEXT: bne- 0, L..BB1_1 ; AIX32-NEXT: # %bb.2: # %entry ; AIX32-NEXT: srw 3, 4, 26 ; AIX32-NEXT: lwsync @@ -1817,7 +1817,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 21 -; AIX32-NEXT: bne 0, L..BB1_3 +; AIX32-NEXT: bne- 0, L..BB1_3 ; AIX32-NEXT: # %bb.4: # %entry ; AIX32-NEXT: srw 3, 4, 22 ; AIX32-NEXT: lwz 23, L..C2(2) # @ss @@ -1840,7 +1840,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 17 -; AIX32-NEXT: bne 0, L..BB1_5 +; AIX32-NEXT: bne- 0, L..BB1_5 ; AIX32-NEXT: # %bb.6: # %entry ; AIX32-NEXT: srw 3, 4, 18 ; AIX32-NEXT: lwz 19, L..C3(2) # @us @@ -1863,7 +1863,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 14 -; AIX32-NEXT: bne 0, L..BB1_7 +; AIX32-NEXT: bne- 0, L..BB1_7 ; AIX32-NEXT: # %bb.8: # %entry ; AIX32-NEXT: srw 3, 4, 15 ; AIX32-NEXT: lwsync @@ -1876,7 +1876,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 29 ; AIX32-NEXT: addi 4, 3, 11 ; AIX32-NEXT: stwcx. 4, 0, 29 -; AIX32-NEXT: bne 0, L..BB1_9 +; AIX32-NEXT: bne- 0, L..BB1_9 ; AIX32-NEXT: # %bb.10: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(29) @@ -1887,7 +1887,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: addi 4, 3, 11 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB1_11 +; AIX32-NEXT: bne- 0, L..BB1_11 ; AIX32-NEXT: # %bb.12: # %entry ; AIX32-NEXT: lwz 31, L..C6(2) # @sll ; AIX32-NEXT: lwsync @@ -1920,7 +1920,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 25 -; AIX32-NEXT: bne 0, L..BB1_13 +; AIX32-NEXT: bne- 0, L..BB1_13 ; AIX32-NEXT: # %bb.14: # %entry ; AIX32-NEXT: srw 3, 4, 26 ; AIX32-NEXT: lwsync @@ -1938,7 +1938,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 21 -; AIX32-NEXT: bne 0, L..BB1_15 +; AIX32-NEXT: bne- 0, L..BB1_15 ; AIX32-NEXT: # %bb.16: # %entry ; AIX32-NEXT: srw 3, 4, 22 ; AIX32-NEXT: lwsync @@ -1957,7 +1957,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 17 -; AIX32-NEXT: bne 0, L..BB1_17 +; AIX32-NEXT: bne- 0, L..BB1_17 ; AIX32-NEXT: # %bb.18: # %entry ; AIX32-NEXT: srw 3, 4, 18 ; AIX32-NEXT: lwsync @@ -1975,7 +1975,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 14 -; AIX32-NEXT: bne 0, L..BB1_19 +; AIX32-NEXT: bne- 0, L..BB1_19 ; AIX32-NEXT: # %bb.20: # %entry ; AIX32-NEXT: srw 3, 4, 15 ; AIX32-NEXT: lwsync @@ -1987,7 +1987,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 29 ; AIX32-NEXT: sub 4, 3, 7 ; AIX32-NEXT: stwcx. 4, 0, 29 -; AIX32-NEXT: bne 0, L..BB1_21 +; AIX32-NEXT: bne- 0, L..BB1_21 ; AIX32-NEXT: # %bb.22: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(29) @@ -1997,7 +1997,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: sub 4, 3, 7 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB1_23 +; AIX32-NEXT: bne- 0, L..BB1_23 ; AIX32-NEXT: # %bb.24: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -2028,7 +2028,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 25 -; AIX32-NEXT: bne 0, L..BB1_25 +; AIX32-NEXT: bne- 0, L..BB1_25 ; AIX32-NEXT: # %bb.26: # %entry ; AIX32-NEXT: srw 3, 4, 26 ; AIX32-NEXT: lwsync @@ -2046,7 +2046,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 21 -; AIX32-NEXT: bne 0, L..BB1_27 +; AIX32-NEXT: bne- 0, L..BB1_27 ; AIX32-NEXT: # %bb.28: # %entry ; AIX32-NEXT: srw 3, 4, 22 ; AIX32-NEXT: lwsync @@ -2064,7 +2064,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 17 -; AIX32-NEXT: bne 0, L..BB1_29 +; AIX32-NEXT: bne- 0, L..BB1_29 ; AIX32-NEXT: # %bb.30: # %entry ; AIX32-NEXT: srw 3, 4, 18 ; AIX32-NEXT: lwsync @@ -2082,7 +2082,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 14 -; AIX32-NEXT: bne 0, L..BB1_31 +; AIX32-NEXT: bne- 0, L..BB1_31 ; AIX32-NEXT: # %bb.32: # %entry ; AIX32-NEXT: srw 3, 4, 15 ; AIX32-NEXT: lwsync @@ -2094,7 +2094,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 29 ; AIX32-NEXT: ori 4, 3, 11 ; AIX32-NEXT: stwcx. 4, 0, 29 -; AIX32-NEXT: bne 0, L..BB1_33 +; AIX32-NEXT: bne- 0, L..BB1_33 ; AIX32-NEXT: # %bb.34: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(29) @@ -2104,7 +2104,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: ori 4, 3, 11 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB1_35 +; AIX32-NEXT: bne- 0, L..BB1_35 ; AIX32-NEXT: # %bb.36: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -2135,7 +2135,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 25 -; AIX32-NEXT: bne 0, L..BB1_37 +; AIX32-NEXT: bne- 0, L..BB1_37 ; AIX32-NEXT: # %bb.38: # %entry ; AIX32-NEXT: srw 3, 4, 26 ; AIX32-NEXT: lwsync @@ -2153,7 +2153,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 21 -; AIX32-NEXT: bne 0, L..BB1_39 +; AIX32-NEXT: bne- 0, L..BB1_39 ; AIX32-NEXT: # %bb.40: # %entry ; AIX32-NEXT: srw 3, 4, 22 ; AIX32-NEXT: lwsync @@ -2171,7 +2171,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 17 -; AIX32-NEXT: bne 0, L..BB1_41 +; AIX32-NEXT: bne- 0, L..BB1_41 ; AIX32-NEXT: # %bb.42: # %entry ; AIX32-NEXT: srw 3, 4, 18 ; AIX32-NEXT: lwsync @@ -2189,7 +2189,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 14 -; AIX32-NEXT: bne 0, L..BB1_43 +; AIX32-NEXT: bne- 0, L..BB1_43 ; AIX32-NEXT: # %bb.44: # %entry ; AIX32-NEXT: srw 3, 4, 15 ; AIX32-NEXT: lwsync @@ -2201,7 +2201,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 29 ; AIX32-NEXT: xori 4, 3, 11 ; AIX32-NEXT: stwcx. 4, 0, 29 -; AIX32-NEXT: bne 0, L..BB1_45 +; AIX32-NEXT: bne- 0, L..BB1_45 ; AIX32-NEXT: # %bb.46: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(29) @@ -2211,7 +2211,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: xori 4, 3, 11 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB1_47 +; AIX32-NEXT: bne- 0, L..BB1_47 ; AIX32-NEXT: # %bb.48: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -2242,7 +2242,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 25 -; AIX32-NEXT: bne 0, L..BB1_49 +; AIX32-NEXT: bne- 0, L..BB1_49 ; AIX32-NEXT: # %bb.50: # %entry ; AIX32-NEXT: srw 3, 4, 26 ; AIX32-NEXT: lwsync @@ -2261,7 +2261,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 21 -; AIX32-NEXT: bne 0, L..BB1_51 +; AIX32-NEXT: bne- 0, L..BB1_51 ; AIX32-NEXT: # %bb.52: # %entry ; AIX32-NEXT: srw 3, 4, 22 ; AIX32-NEXT: lwsync @@ -2279,7 +2279,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 17 -; AIX32-NEXT: bne 0, L..BB1_53 +; AIX32-NEXT: bne- 0, L..BB1_53 ; AIX32-NEXT: # %bb.54: # %entry ; AIX32-NEXT: srw 3, 4, 18 ; AIX32-NEXT: lwsync @@ -2297,7 +2297,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 14 -; AIX32-NEXT: bne 0, L..BB1_55 +; AIX32-NEXT: bne- 0, L..BB1_55 ; AIX32-NEXT: # %bb.56: # %entry ; AIX32-NEXT: srw 3, 4, 15 ; AIX32-NEXT: lwsync @@ -2309,7 +2309,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 29 ; AIX32-NEXT: nand 4, 7, 3 ; AIX32-NEXT: stwcx. 4, 0, 29 -; AIX32-NEXT: bne 0, L..BB1_57 +; AIX32-NEXT: bne- 0, L..BB1_57 ; AIX32-NEXT: # %bb.58: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(29) @@ -2319,7 +2319,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: nand 4, 7, 3 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB1_59 +; AIX32-NEXT: bne- 0, L..BB1_59 ; AIX32-NEXT: # %bb.60: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -2350,7 +2350,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 25 -; AIX32-NEXT: bne 0, L..BB1_61 +; AIX32-NEXT: bne- 0, L..BB1_61 ; AIX32-NEXT: # %bb.62: # %entry ; AIX32-NEXT: srw 3, 4, 26 ; AIX32-NEXT: lwsync @@ -2368,7 +2368,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 21 -; AIX32-NEXT: bne 0, L..BB1_63 +; AIX32-NEXT: bne- 0, L..BB1_63 ; AIX32-NEXT: # %bb.64: # %entry ; AIX32-NEXT: srw 3, 4, 22 ; AIX32-NEXT: lwsync @@ -2387,7 +2387,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 17 -; AIX32-NEXT: bne 0, L..BB1_65 +; AIX32-NEXT: bne- 0, L..BB1_65 ; AIX32-NEXT: # %bb.66: # %entry ; AIX32-NEXT: srw 3, 4, 18 ; AIX32-NEXT: lwsync @@ -2405,7 +2405,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: stwcx. 5, 0, 14 -; AIX32-NEXT: bne 0, L..BB1_67 +; AIX32-NEXT: bne- 0, L..BB1_67 ; AIX32-NEXT: # %bb.68: # %entry ; AIX32-NEXT: srw 3, 4, 15 ; AIX32-NEXT: lwsync @@ -2417,7 +2417,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 29 ; AIX32-NEXT: and 4, 7, 3 ; AIX32-NEXT: stwcx. 4, 0, 29 -; AIX32-NEXT: bne 0, L..BB1_69 +; AIX32-NEXT: bne- 0, L..BB1_69 ; AIX32-NEXT: # %bb.70: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(29) @@ -2427,7 +2427,7 @@ define dso_local void @test_fetch_and_op() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: and 4, 7, 3 ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: bne 0, L..BB1_71 +; AIX32-NEXT: bne- 0, L..BB1_71 ; AIX32-NEXT: # %bb.72: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: li 4, 0 @@ -2599,7 +2599,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 8, 0, 7 ; CHECK-NEXT: add 8, 6, 8 ; CHECK-NEXT: stbcx. 8, 0, 7 -; CHECK-NEXT: bne 0, .LBB2_1 +; CHECK-NEXT: bne- 0, .LBB2_1 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 8, sc@toc@l(5) @@ -2610,7 +2610,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 8, 0, 4 ; CHECK-NEXT: add 8, 6, 8 ; CHECK-NEXT: stbcx. 8, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_3 +; CHECK-NEXT: bne- 0, .LBB2_3 ; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: addis 6, 2, ss@toc@ha ; CHECK-NEXT: lwsync @@ -2623,7 +2623,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 10, 0, 9 ; CHECK-NEXT: add 10, 8, 10 ; CHECK-NEXT: sthcx. 10, 0, 9 -; CHECK-NEXT: bne 0, .LBB2_5 +; CHECK-NEXT: bne- 0, .LBB2_5 ; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: addis 8, 2, us@toc@ha @@ -2636,7 +2636,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 12, 0, 11 ; CHECK-NEXT: add 12, 10, 12 ; CHECK-NEXT: sthcx. 12, 0, 11 -; CHECK-NEXT: bne 0, .LBB2_7 +; CHECK-NEXT: bne- 0, .LBB2_7 ; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: addis 10, 2, si@toc@ha @@ -2649,7 +2649,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 30, 0, 0 ; CHECK-NEXT: add 30, 12, 30 ; CHECK-NEXT: stwcx. 30, 0, 0 -; CHECK-NEXT: bne 0, .LBB2_9 +; CHECK-NEXT: bne- 0, .LBB2_9 ; CHECK-NEXT: # %bb.10: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: addis 12, 2, ui@toc@ha @@ -2662,7 +2662,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 28, 0, 29 ; CHECK-NEXT: add 28, 30, 28 ; CHECK-NEXT: stwcx. 28, 0, 29 -; CHECK-NEXT: bne 0, .LBB2_11 +; CHECK-NEXT: bne- 0, .LBB2_11 ; CHECK-NEXT: # %bb.12: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: addis 30, 2, sll@toc@ha @@ -2675,7 +2675,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 26, 0, 27 ; CHECK-NEXT: add 26, 28, 26 ; CHECK-NEXT: stdcx. 26, 0, 27 -; CHECK-NEXT: bne 0, .LBB2_13 +; CHECK-NEXT: bne- 0, .LBB2_13 ; CHECK-NEXT: # %bb.14: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: addis 28, 2, ull@toc@ha @@ -2688,7 +2688,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 26 ; CHECK-NEXT: add 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 26 -; CHECK-NEXT: bne 0, .LBB2_15 +; CHECK-NEXT: bne- 0, .LBB2_15 ; CHECK-NEXT: # %bb.16: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, ull@toc@l(28) @@ -2699,7 +2699,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 7 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: stbcx. 24, 0, 7 -; CHECK-NEXT: bne 0, .LBB2_17 +; CHECK-NEXT: bne- 0, .LBB2_17 ; CHECK-NEXT: # %bb.18: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, sc@toc@l(5) @@ -2710,7 +2710,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 4 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: stbcx. 24, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_19 +; CHECK-NEXT: bne- 0, .LBB2_19 ; CHECK-NEXT: # %bb.20: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, uc@toc@l(3) @@ -2721,7 +2721,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 9 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: sthcx. 24, 0, 9 -; CHECK-NEXT: bne 0, .LBB2_21 +; CHECK-NEXT: bne- 0, .LBB2_21 ; CHECK-NEXT: # %bb.22: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, ss@toc@l(6) @@ -2732,7 +2732,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 11 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: sthcx. 24, 0, 11 -; CHECK-NEXT: bne 0, .LBB2_23 +; CHECK-NEXT: bne- 0, .LBB2_23 ; CHECK-NEXT: # %bb.24: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, us@toc@l(8) @@ -2743,7 +2743,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 0 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: stwcx. 24, 0, 0 -; CHECK-NEXT: bne 0, .LBB2_25 +; CHECK-NEXT: bne- 0, .LBB2_25 ; CHECK-NEXT: # %bb.26: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, si@toc@l(10) @@ -2754,7 +2754,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 29 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: stwcx. 24, 0, 29 -; CHECK-NEXT: bne 0, .LBB2_27 +; CHECK-NEXT: bne- 0, .LBB2_27 ; CHECK-NEXT: # %bb.28: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, ui@toc@l(12) @@ -2765,7 +2765,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 27 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: stdcx. 24, 0, 27 -; CHECK-NEXT: bne 0, .LBB2_29 +; CHECK-NEXT: bne- 0, .LBB2_29 ; CHECK-NEXT: # %bb.30: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, sll@toc@l(30) @@ -2776,7 +2776,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 26 ; CHECK-NEXT: sub 24, 24, 25 ; CHECK-NEXT: stdcx. 24, 0, 26 -; CHECK-NEXT: bne 0, .LBB2_31 +; CHECK-NEXT: bne- 0, .LBB2_31 ; CHECK-NEXT: # %bb.32: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, ull@toc@l(28) @@ -2787,7 +2787,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 7 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 7 -; CHECK-NEXT: bne 0, .LBB2_33 +; CHECK-NEXT: bne- 0, .LBB2_33 ; CHECK-NEXT: # %bb.34: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, sc@toc@l(5) @@ -2798,7 +2798,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 4 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_35 +; CHECK-NEXT: bne- 0, .LBB2_35 ; CHECK-NEXT: # %bb.36: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, uc@toc@l(3) @@ -2809,7 +2809,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 9 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: sthcx. 24, 0, 9 -; CHECK-NEXT: bne 0, .LBB2_37 +; CHECK-NEXT: bne- 0, .LBB2_37 ; CHECK-NEXT: # %bb.38: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, ss@toc@l(6) @@ -2820,7 +2820,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 11 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: sthcx. 24, 0, 11 -; CHECK-NEXT: bne 0, .LBB2_39 +; CHECK-NEXT: bne- 0, .LBB2_39 ; CHECK-NEXT: # %bb.40: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, us@toc@l(8) @@ -2831,7 +2831,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 0 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: stwcx. 24, 0, 0 -; CHECK-NEXT: bne 0, .LBB2_41 +; CHECK-NEXT: bne- 0, .LBB2_41 ; CHECK-NEXT: # %bb.42: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, si@toc@l(10) @@ -2842,7 +2842,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 29 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: stwcx. 24, 0, 29 -; CHECK-NEXT: bne 0, .LBB2_43 +; CHECK-NEXT: bne- 0, .LBB2_43 ; CHECK-NEXT: # %bb.44: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, ui@toc@l(12) @@ -2853,7 +2853,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 27 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 27 -; CHECK-NEXT: bne 0, .LBB2_45 +; CHECK-NEXT: bne- 0, .LBB2_45 ; CHECK-NEXT: # %bb.46: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, sll@toc@l(30) @@ -2864,7 +2864,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 26 ; CHECK-NEXT: or 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 26 -; CHECK-NEXT: bne 0, .LBB2_47 +; CHECK-NEXT: bne- 0, .LBB2_47 ; CHECK-NEXT: # %bb.48: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, ull@toc@l(28) @@ -2875,7 +2875,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 7 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 7 -; CHECK-NEXT: bne 0, .LBB2_49 +; CHECK-NEXT: bne- 0, .LBB2_49 ; CHECK-NEXT: # %bb.50: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, sc@toc@l(5) @@ -2886,7 +2886,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 4 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_51 +; CHECK-NEXT: bne- 0, .LBB2_51 ; CHECK-NEXT: # %bb.52: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, uc@toc@l(3) @@ -2897,7 +2897,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 9 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: sthcx. 24, 0, 9 -; CHECK-NEXT: bne 0, .LBB2_53 +; CHECK-NEXT: bne- 0, .LBB2_53 ; CHECK-NEXT: # %bb.54: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, ss@toc@l(6) @@ -2908,7 +2908,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 11 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: sthcx. 24, 0, 11 -; CHECK-NEXT: bne 0, .LBB2_55 +; CHECK-NEXT: bne- 0, .LBB2_55 ; CHECK-NEXT: # %bb.56: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, us@toc@l(8) @@ -2919,7 +2919,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 0 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: stwcx. 24, 0, 0 -; CHECK-NEXT: bne 0, .LBB2_57 +; CHECK-NEXT: bne- 0, .LBB2_57 ; CHECK-NEXT: # %bb.58: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, si@toc@l(10) @@ -2930,7 +2930,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 29 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: stwcx. 24, 0, 29 -; CHECK-NEXT: bne 0, .LBB2_59 +; CHECK-NEXT: bne- 0, .LBB2_59 ; CHECK-NEXT: # %bb.60: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, ui@toc@l(12) @@ -2941,7 +2941,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 27 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 27 -; CHECK-NEXT: bne 0, .LBB2_61 +; CHECK-NEXT: bne- 0, .LBB2_61 ; CHECK-NEXT: # %bb.62: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, sll@toc@l(30) @@ -2952,7 +2952,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 26 ; CHECK-NEXT: xor 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 26 -; CHECK-NEXT: bne 0, .LBB2_63 +; CHECK-NEXT: bne- 0, .LBB2_63 ; CHECK-NEXT: # %bb.64: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, ull@toc@l(28) @@ -2963,7 +2963,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 7 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 7 -; CHECK-NEXT: bne 0, .LBB2_65 +; CHECK-NEXT: bne- 0, .LBB2_65 ; CHECK-NEXT: # %bb.66: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, sc@toc@l(5) @@ -2974,7 +2974,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 4 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_67 +; CHECK-NEXT: bne- 0, .LBB2_67 ; CHECK-NEXT: # %bb.68: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, uc@toc@l(3) @@ -2985,7 +2985,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 9 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: sthcx. 24, 0, 9 -; CHECK-NEXT: bne 0, .LBB2_69 +; CHECK-NEXT: bne- 0, .LBB2_69 ; CHECK-NEXT: # %bb.70: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, ss@toc@l(6) @@ -2996,7 +2996,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 24, 0, 11 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: sthcx. 24, 0, 11 -; CHECK-NEXT: bne 0, .LBB2_71 +; CHECK-NEXT: bne- 0, .LBB2_71 ; CHECK-NEXT: # %bb.72: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 24, us@toc@l(8) @@ -3007,7 +3007,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 0 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: stwcx. 24, 0, 0 -; CHECK-NEXT: bne 0, .LBB2_73 +; CHECK-NEXT: bne- 0, .LBB2_73 ; CHECK-NEXT: # %bb.74: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, si@toc@l(10) @@ -3018,7 +3018,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 24, 0, 29 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: stwcx. 24, 0, 29 -; CHECK-NEXT: bne 0, .LBB2_75 +; CHECK-NEXT: bne- 0, .LBB2_75 ; CHECK-NEXT: # %bb.76: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 24, ui@toc@l(12) @@ -3029,7 +3029,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 27 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 27 -; CHECK-NEXT: bne 0, .LBB2_77 +; CHECK-NEXT: bne- 0, .LBB2_77 ; CHECK-NEXT: # %bb.78: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, sll@toc@l(30) @@ -3040,7 +3040,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 24, 0, 26 ; CHECK-NEXT: nand 24, 25, 24 ; CHECK-NEXT: stdcx. 24, 0, 26 -; CHECK-NEXT: bne 0, .LBB2_79 +; CHECK-NEXT: bne- 0, .LBB2_79 ; CHECK-NEXT: # %bb.80: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 24, ull@toc@l(28) @@ -3085,7 +3085,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 24, 0, 7 ; CHECK-NEXT: and 24, 25, 24 ; CHECK-NEXT: stbcx. 24, 0, 7 -; CHECK-NEXT: bne 0, .LBB2_85 +; CHECK-NEXT: bne- 0, .LBB2_85 ; CHECK-NEXT: # %bb.86: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 24, sc@toc@l(5) @@ -3096,7 +3096,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lbarx 5, 0, 4 ; CHECK-NEXT: and 5, 7, 5 ; CHECK-NEXT: stbcx. 5, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_87 +; CHECK-NEXT: bne- 0, .LBB2_87 ; CHECK-NEXT: # %bb.88: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 5, uc@toc@l(3) @@ -3106,7 +3106,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 4, 0, 9 ; CHECK-NEXT: and 4, 5, 4 ; CHECK-NEXT: sthcx. 4, 0, 9 -; CHECK-NEXT: bne 0, .LBB2_89 +; CHECK-NEXT: bne- 0, .LBB2_89 ; CHECK-NEXT: # %bb.90: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 4, ss@toc@l(6) @@ -3117,7 +3117,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lharx 5, 0, 11 ; CHECK-NEXT: and 5, 4, 5 ; CHECK-NEXT: sthcx. 5, 0, 11 -; CHECK-NEXT: bne 0, .LBB2_91 +; CHECK-NEXT: bne- 0, .LBB2_91 ; CHECK-NEXT: # %bb.92: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 5, us@toc@l(8) @@ -3128,7 +3128,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 5, 0, 0 ; CHECK-NEXT: and 5, 4, 5 ; CHECK-NEXT: stwcx. 5, 0, 0 -; CHECK-NEXT: bne 0, .LBB2_93 +; CHECK-NEXT: bne- 0, .LBB2_93 ; CHECK-NEXT: # %bb.94: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 5, si@toc@l(10) @@ -3139,7 +3139,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: lwarx 5, 0, 29 ; CHECK-NEXT: and 5, 4, 5 ; CHECK-NEXT: stwcx. 5, 0, 29 -; CHECK-NEXT: bne 0, .LBB2_95 +; CHECK-NEXT: bne- 0, .LBB2_95 ; CHECK-NEXT: # %bb.96: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 5, ui@toc@l(12) @@ -3150,7 +3150,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 5, 0, 27 ; CHECK-NEXT: and 5, 4, 5 ; CHECK-NEXT: stdcx. 5, 0, 27 -; CHECK-NEXT: bne 0, .LBB2_97 +; CHECK-NEXT: bne- 0, .LBB2_97 ; CHECK-NEXT: # %bb.98: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 5, sll@toc@l(30) @@ -3161,7 +3161,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; CHECK-NEXT: ldarx 4, 0, 26 ; CHECK-NEXT: and 4, 3, 4 ; CHECK-NEXT: stdcx. 4, 0, 26 -; CHECK-NEXT: bne 0, .LBB2_99 +; CHECK-NEXT: bne- 0, .LBB2_99 ; CHECK-NEXT: # %bb.100: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 4, ull@toc@l(28) @@ -3225,7 +3225,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 22 -; AIX32-NEXT: bne 0, L..BB2_1 +; AIX32-NEXT: bne- 0, L..BB2_1 ; AIX32-NEXT: # %bb.2: # %entry ; AIX32-NEXT: srw 4, 6, 24 ; AIX32-NEXT: lwsync @@ -3248,7 +3248,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 19 -; AIX32-NEXT: bne 0, L..BB2_3 +; AIX32-NEXT: bne- 0, L..BB2_3 ; AIX32-NEXT: # %bb.4: # %entry ; AIX32-NEXT: srw 4, 6, 21 ; AIX32-NEXT: lwz 23, L..C2(2) # @ss @@ -3273,7 +3273,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 16 -; AIX32-NEXT: bne 0, L..BB2_5 +; AIX32-NEXT: bne- 0, L..BB2_5 ; AIX32-NEXT: # %bb.6: # %entry ; AIX32-NEXT: srw 4, 6, 18 ; AIX32-NEXT: lwz 20, L..C3(2) # @us @@ -3298,7 +3298,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 14 -; AIX32-NEXT: bne 0, L..BB2_7 +; AIX32-NEXT: bne- 0, L..BB2_7 ; AIX32-NEXT: # %bb.8: # %entry ; AIX32-NEXT: srw 4, 6, 15 ; AIX32-NEXT: lwsync @@ -3313,7 +3313,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 13 ; AIX32-NEXT: add 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 13 -; AIX32-NEXT: bne 0, L..BB2_9 +; AIX32-NEXT: bne- 0, L..BB2_9 ; AIX32-NEXT: # %bb.10: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(13) @@ -3325,7 +3325,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: add 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB2_11 +; AIX32-NEXT: bne- 0, L..BB2_11 ; AIX32-NEXT: # %bb.12: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: lwz 31, L..C6(2) # @sll @@ -3367,7 +3367,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 22 -; AIX32-NEXT: bne 0, L..BB2_13 +; AIX32-NEXT: bne- 0, L..BB2_13 ; AIX32-NEXT: # %bb.14: # %entry ; AIX32-NEXT: srw 4, 6, 24 ; AIX32-NEXT: lwsync @@ -3387,7 +3387,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 19 -; AIX32-NEXT: bne 0, L..BB2_15 +; AIX32-NEXT: bne- 0, L..BB2_15 ; AIX32-NEXT: # %bb.16: # %entry ; AIX32-NEXT: srw 4, 6, 21 ; AIX32-NEXT: li 5, 0 @@ -3408,7 +3408,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 16 -; AIX32-NEXT: bne 0, L..BB2_17 +; AIX32-NEXT: bne- 0, L..BB2_17 ; AIX32-NEXT: # %bb.18: # %entry ; AIX32-NEXT: srw 4, 6, 18 ; AIX32-NEXT: lwsync @@ -3429,7 +3429,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 14 -; AIX32-NEXT: bne 0, L..BB2_19 +; AIX32-NEXT: bne- 0, L..BB2_19 ; AIX32-NEXT: # %bb.20: # %entry ; AIX32-NEXT: srw 4, 6, 15 ; AIX32-NEXT: lwsync @@ -3443,7 +3443,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 13 ; AIX32-NEXT: sub 4, 4, 3 ; AIX32-NEXT: stwcx. 4, 0, 13 -; AIX32-NEXT: bne 0, L..BB2_21 +; AIX32-NEXT: bne- 0, L..BB2_21 ; AIX32-NEXT: # %bb.22: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(13) @@ -3454,7 +3454,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: sub 4, 4, 3 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB2_23 +; AIX32-NEXT: bne- 0, L..BB2_23 ; AIX32-NEXT: # %bb.24: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(25) @@ -3493,7 +3493,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 22 -; AIX32-NEXT: bne 0, L..BB2_25 +; AIX32-NEXT: bne- 0, L..BB2_25 ; AIX32-NEXT: # %bb.26: # %entry ; AIX32-NEXT: srw 4, 6, 24 ; AIX32-NEXT: lwsync @@ -3513,7 +3513,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 19 -; AIX32-NEXT: bne 0, L..BB2_27 +; AIX32-NEXT: bne- 0, L..BB2_27 ; AIX32-NEXT: # %bb.28: # %entry ; AIX32-NEXT: srw 4, 6, 21 ; AIX32-NEXT: li 5, 0 @@ -3534,7 +3534,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 16 -; AIX32-NEXT: bne 0, L..BB2_29 +; AIX32-NEXT: bne- 0, L..BB2_29 ; AIX32-NEXT: # %bb.30: # %entry ; AIX32-NEXT: srw 4, 6, 18 ; AIX32-NEXT: lwsync @@ -3555,7 +3555,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 14 -; AIX32-NEXT: bne 0, L..BB2_31 +; AIX32-NEXT: bne- 0, L..BB2_31 ; AIX32-NEXT: # %bb.32: # %entry ; AIX32-NEXT: srw 4, 6, 15 ; AIX32-NEXT: lwsync @@ -3569,7 +3569,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 13 ; AIX32-NEXT: or 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 13 -; AIX32-NEXT: bne 0, L..BB2_33 +; AIX32-NEXT: bne- 0, L..BB2_33 ; AIX32-NEXT: # %bb.34: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(13) @@ -3580,7 +3580,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: or 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB2_35 +; AIX32-NEXT: bne- 0, L..BB2_35 ; AIX32-NEXT: # %bb.36: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(25) @@ -3617,7 +3617,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 22 -; AIX32-NEXT: bne 0, L..BB2_37 +; AIX32-NEXT: bne- 0, L..BB2_37 ; AIX32-NEXT: # %bb.38: # %entry ; AIX32-NEXT: srw 4, 6, 24 ; AIX32-NEXT: lwsync @@ -3637,7 +3637,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 19 -; AIX32-NEXT: bne 0, L..BB2_39 +; AIX32-NEXT: bne- 0, L..BB2_39 ; AIX32-NEXT: # %bb.40: # %entry ; AIX32-NEXT: srw 4, 6, 21 ; AIX32-NEXT: li 5, 0 @@ -3658,7 +3658,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 16 -; AIX32-NEXT: bne 0, L..BB2_41 +; AIX32-NEXT: bne- 0, L..BB2_41 ; AIX32-NEXT: # %bb.42: # %entry ; AIX32-NEXT: srw 4, 6, 18 ; AIX32-NEXT: lwsync @@ -3679,7 +3679,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 14 -; AIX32-NEXT: bne 0, L..BB2_43 +; AIX32-NEXT: bne- 0, L..BB2_43 ; AIX32-NEXT: # %bb.44: # %entry ; AIX32-NEXT: srw 4, 6, 15 ; AIX32-NEXT: lwsync @@ -3693,7 +3693,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 13 ; AIX32-NEXT: xor 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 13 -; AIX32-NEXT: bne 0, L..BB2_45 +; AIX32-NEXT: bne- 0, L..BB2_45 ; AIX32-NEXT: # %bb.46: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(13) @@ -3704,7 +3704,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: xor 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB2_47 +; AIX32-NEXT: bne- 0, L..BB2_47 ; AIX32-NEXT: # %bb.48: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(25) @@ -3741,7 +3741,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 22 -; AIX32-NEXT: bne 0, L..BB2_49 +; AIX32-NEXT: bne- 0, L..BB2_49 ; AIX32-NEXT: # %bb.50: # %entry ; AIX32-NEXT: srw 4, 6, 24 ; AIX32-NEXT: lwsync @@ -3761,7 +3761,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 19 -; AIX32-NEXT: bne 0, L..BB2_51 +; AIX32-NEXT: bne- 0, L..BB2_51 ; AIX32-NEXT: # %bb.52: # %entry ; AIX32-NEXT: srw 4, 6, 21 ; AIX32-NEXT: li 5, 0 @@ -3782,7 +3782,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 16 -; AIX32-NEXT: bne 0, L..BB2_53 +; AIX32-NEXT: bne- 0, L..BB2_53 ; AIX32-NEXT: # %bb.54: # %entry ; AIX32-NEXT: srw 4, 6, 18 ; AIX32-NEXT: lwsync @@ -3803,7 +3803,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 14 -; AIX32-NEXT: bne 0, L..BB2_55 +; AIX32-NEXT: bne- 0, L..BB2_55 ; AIX32-NEXT: # %bb.56: # %entry ; AIX32-NEXT: srw 4, 6, 15 ; AIX32-NEXT: lwsync @@ -3817,7 +3817,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 13 ; AIX32-NEXT: nand 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 13 -; AIX32-NEXT: bne 0, L..BB2_57 +; AIX32-NEXT: bne- 0, L..BB2_57 ; AIX32-NEXT: # %bb.58: # %entry ; AIX32-NEXT: stw 23, 56(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 27, 60(1) # 4-byte Folded Spill @@ -3830,7 +3830,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: nand 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB2_59 +; AIX32-NEXT: bne- 0, L..BB2_59 ; AIX32-NEXT: # %bb.60: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(25) @@ -3951,7 +3951,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 22 -; AIX32-NEXT: bne 0, L..BB2_65 +; AIX32-NEXT: bne- 0, L..BB2_65 ; AIX32-NEXT: # %bb.66: # %atomicrmw.end ; AIX32-NEXT: srw 4, 6, 24 ; AIX32-NEXT: lwsync @@ -3973,7 +3973,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 19 -; AIX32-NEXT: bne 0, L..BB2_67 +; AIX32-NEXT: bne- 0, L..BB2_67 ; AIX32-NEXT: # %bb.68: # %atomicrmw.end ; AIX32-NEXT: srw 4, 6, 21 ; AIX32-NEXT: li 5, 0 @@ -3993,7 +3993,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 16 -; AIX32-NEXT: bne 0, L..BB2_69 +; AIX32-NEXT: bne- 0, L..BB2_69 ; AIX32-NEXT: # %bb.70: # %atomicrmw.end ; AIX32-NEXT: srw 4, 6, 18 ; AIX32-NEXT: lwsync @@ -4014,7 +4014,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: and 7, 7, 5 ; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: stwcx. 7, 0, 14 -; AIX32-NEXT: bne 0, L..BB2_71 +; AIX32-NEXT: bne- 0, L..BB2_71 ; AIX32-NEXT: # %bb.72: # %atomicrmw.end ; AIX32-NEXT: srw 4, 6, 15 ; AIX32-NEXT: lwsync @@ -4028,7 +4028,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 13 ; AIX32-NEXT: and 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 13 -; AIX32-NEXT: bne 0, L..BB2_73 +; AIX32-NEXT: bne- 0, L..BB2_73 ; AIX32-NEXT: # %bb.74: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(13) @@ -4039,7 +4039,7 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 { ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: and 4, 3, 4 ; AIX32-NEXT: stwcx. 4, 0, 25 -; AIX32-NEXT: bne 0, L..BB2_75 +; AIX32-NEXT: bne- 0, L..BB2_75 ; AIX32-NEXT: # %bb.76: # %atomicrmw.end ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(25) @@ -5371,7 +5371,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: lbarx 5, 0, 4 ; CHECK-NEXT: stbcx. 7, 0, 4 -; CHECK-NEXT: bne 0, .LBB4_1 +; CHECK-NEXT: bne- 0, .LBB4_1 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: addis 4, 2, uc@toc@ha ; CHECK-NEXT: lwsync @@ -5382,7 +5382,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: lbarx 5, 0, 6 ; CHECK-NEXT: stbcx. 7, 0, 6 -; CHECK-NEXT: bne 0, .LBB4_3 +; CHECK-NEXT: bne- 0, .LBB4_3 ; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stb 5, uc@toc@l(4) @@ -5393,7 +5393,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: lharx 6, 0, 8 ; CHECK-NEXT: sthcx. 7, 0, 8 -; CHECK-NEXT: bne 0, .LBB4_5 +; CHECK-NEXT: bne- 0, .LBB4_5 ; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 6, ss@toc@l(5) @@ -5404,7 +5404,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: lharx 8, 0, 9 ; CHECK-NEXT: sthcx. 7, 0, 9 -; CHECK-NEXT: bne 0, .LBB4_7 +; CHECK-NEXT: bne- 0, .LBB4_7 ; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 8, us@toc@l(6) @@ -5415,7 +5415,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: lwarx 9, 0, 10 ; CHECK-NEXT: stwcx. 7, 0, 10 -; CHECK-NEXT: bne 0, .LBB4_9 +; CHECK-NEXT: bne- 0, .LBB4_9 ; CHECK-NEXT: # %bb.10: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 9, si@toc@l(8) @@ -5426,7 +5426,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: lwarx 10, 0, 11 ; CHECK-NEXT: stwcx. 7, 0, 11 -; CHECK-NEXT: bne 0, .LBB4_11 +; CHECK-NEXT: bne- 0, .LBB4_11 ; CHECK-NEXT: # %bb.12: # %entry ; CHECK-NEXT: addis 7, 2, sll@toc@ha ; CHECK-NEXT: lwsync @@ -5438,7 +5438,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: ldarx 12, 0, 10 ; CHECK-NEXT: stdcx. 11, 0, 10 -; CHECK-NEXT: bne 0, .LBB4_13 +; CHECK-NEXT: bne- 0, .LBB4_13 ; CHECK-NEXT: # %bb.14: # %entry ; CHECK-NEXT: addis 10, 2, ull@toc@ha ; CHECK-NEXT: lwsync @@ -5449,7 +5449,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; CHECK-NEXT: # ; CHECK-NEXT: ldarx 12, 0, 0 ; CHECK-NEXT: stdcx. 11, 0, 0 -; CHECK-NEXT: bne 0, .LBB4_15 +; CHECK-NEXT: bne- 0, .LBB4_15 ; CHECK-NEXT: # %bb.16: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 12, ull@toc@l(10) @@ -5504,7 +5504,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; AIX32-NEXT: andc 9, 8, 6 ; AIX32-NEXT: or 9, 7, 9 ; AIX32-NEXT: stwcx. 9, 0, 5 -; AIX32-NEXT: bne 0, L..BB4_1 +; AIX32-NEXT: bne- 0, L..BB4_1 ; AIX32-NEXT: # %bb.2: # %entry ; AIX32-NEXT: srw 4, 8, 4 ; AIX32-NEXT: lwz 28, L..C1(2) # @uc @@ -5525,7 +5525,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; AIX32-NEXT: andc 9, 8, 6 ; AIX32-NEXT: or 9, 7, 9 ; AIX32-NEXT: stwcx. 9, 0, 5 -; AIX32-NEXT: bne 0, L..BB4_3 +; AIX32-NEXT: bne- 0, L..BB4_3 ; AIX32-NEXT: # %bb.4: # %entry ; AIX32-NEXT: srw 4, 8, 4 ; AIX32-NEXT: lwz 27, L..C2(2) # @ss @@ -5547,7 +5547,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; AIX32-NEXT: andc 9, 8, 6 ; AIX32-NEXT: or 9, 7, 9 ; AIX32-NEXT: stwcx. 9, 0, 5 -; AIX32-NEXT: bne 0, L..BB4_5 +; AIX32-NEXT: bne- 0, L..BB4_5 ; AIX32-NEXT: # %bb.6: # %entry ; AIX32-NEXT: srw 4, 8, 4 ; AIX32-NEXT: lwz 26, L..C3(2) # @us @@ -5569,7 +5569,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; AIX32-NEXT: andc 9, 8, 6 ; AIX32-NEXT: or 9, 7, 9 ; AIX32-NEXT: stwcx. 9, 0, 5 -; AIX32-NEXT: bne 0, L..BB4_7 +; AIX32-NEXT: bne- 0, L..BB4_7 ; AIX32-NEXT: # %bb.8: # %entry ; AIX32-NEXT: srw 4, 8, 4 ; AIX32-NEXT: lwsync @@ -5581,7 +5581,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 25 ; AIX32-NEXT: stwcx. 3, 0, 25 -; AIX32-NEXT: bne 0, L..BB4_9 +; AIX32-NEXT: bne- 0, L..BB4_9 ; AIX32-NEXT: # %bb.10: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 4, 0(25) @@ -5591,7 +5591,7 @@ define dso_local void @test_lock() local_unnamed_addr #0 { ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 24 ; AIX32-NEXT: stwcx. 3, 0, 24 -; AIX32-NEXT: bne 0, L..BB4_11 +; AIX32-NEXT: bne- 0, L..BB4_11 ; AIX32-NEXT: # %bb.12: # %entry ; AIX32-NEXT: lwz 31, L..C6(2) # @sll ; AIX32-NEXT: lwsync @@ -5695,7 +5695,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 3, 0, 6 -; CHECK-NEXT: bne 0, .LBB5_1 +; CHECK-NEXT: bne- 0, .LBB5_1 ; CHECK-NEXT: .LBB5_3: # %entry ; CHECK-NEXT: stw 5, ui@toc@l(4) ; CHECK-NEXT: addis 5, 2, si@toc@ha @@ -5709,7 +5709,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 3, 0, 7 -; CHECK-NEXT: bne 0, .LBB5_4 +; CHECK-NEXT: bne- 0, .LBB5_4 ; CHECK-NEXT: .LBB5_6: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 8, si@toc@l(5) @@ -5721,7 +5721,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 3, 0, 6 -; CHECK-NEXT: bne 0, .LBB5_7 +; CHECK-NEXT: bne- 0, .LBB5_7 ; CHECK-NEXT: .LBB5_9: # %entry ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 8, ui@toc@l(4) @@ -5734,7 +5734,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 3, 0, 7 -; CHECK-NEXT: bne 0, .LBB5_10 +; CHECK-NEXT: bne- 0, .LBB5_10 ; CHECK-NEXT: .LBB5_12: # %entry ; CHECK-NEXT: stw 4, si@toc@l(5) ; CHECK-NEXT: blr @@ -5751,7 +5751,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; AIX32-NEXT: # %bb.2: # %entry ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 3, 0, 4 -; AIX32-NEXT: bne 0, L..BB5_1 +; AIX32-NEXT: bne- 0, L..BB5_1 ; AIX32-NEXT: L..BB5_3: # %entry ; AIX32-NEXT: stw 5, 0(4) ; AIX32-NEXT: lwz 5, L..C4(2) # @si @@ -5764,7 +5764,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; AIX32-NEXT: # %bb.5: # %entry ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 3, 0, 5 -; AIX32-NEXT: bne 0, L..BB5_4 +; AIX32-NEXT: bne- 0, L..BB5_4 ; AIX32-NEXT: L..BB5_6: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 6, 0(5) @@ -5776,7 +5776,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; AIX32-NEXT: # %bb.8: # %entry ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 3, 0, 4 -; AIX32-NEXT: bne 0, L..BB5_7 +; AIX32-NEXT: bne- 0, L..BB5_7 ; AIX32-NEXT: L..BB5_9: # %entry ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 6, 0(4) @@ -5789,7 +5789,7 @@ define dso_local void @test_atomic() local_unnamed_addr #0 { ; AIX32-NEXT: # %bb.11: # %entry ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 3, 0, 5 -; AIX32-NEXT: bne 0, L..BB5_10 +; AIX32-NEXT: bne- 0, L..BB5_10 ; AIX32-NEXT: L..BB5_12: # %entry ; AIX32-NEXT: stw 4, 0(5) ; AIX32-NEXT: blr @@ -5870,7 +5870,7 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB7_1 +; CHECK-NEXT: bne- 0, .LBB7_1 ; CHECK-NEXT: .LBB7_3: # %entry ; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 4, 66 @@ -5954,7 +5954,7 @@ define dso_local signext i32 @atommax4(ptr nocapture noundef %ptr, i32 noundef s ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB8_1 +; CHECK-NEXT: bne- 0, .LBB8_1 ; CHECK-NEXT: .LBB8_3: # %entry ; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 4, 66 @@ -5973,7 +5973,7 @@ define dso_local signext i32 @atommax4(ptr nocapture noundef %ptr, i32 noundef s ; AIX32-NEXT: # %bb.2: # %entry ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 4, 0, 3 -; AIX32-NEXT: bne 0, L..BB8_1 +; AIX32-NEXT: bne- 0, L..BB8_1 ; AIX32-NEXT: L..BB8_3: # %entry ; AIX32-NEXT: li 3, 55 ; AIX32-NEXT: li 4, 66 @@ -6000,7 +6000,7 @@ define dso_local signext i16 @atommax2(ptr nocapture noundef %ptr, i16 noundef s ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB9_1 +; CHECK-NEXT: bne- 0, .LBB9_1 ; CHECK-NEXT: .LBB9_3: # %entry ; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 4, 66 @@ -6033,7 +6033,7 @@ define dso_local signext i16 @atommax2(ptr nocapture noundef %ptr, i16 noundef s ; AIX32-NEXT: andc 10, 9, 7 ; AIX32-NEXT: or 10, 8, 10 ; AIX32-NEXT: stwcx. 10, 0, 3 -; AIX32-NEXT: bne 0, L..BB9_1 +; AIX32-NEXT: bne- 0, L..BB9_1 ; AIX32-NEXT: L..BB9_3: # %entry ; AIX32-NEXT: srw 3, 9, 6 ; AIX32-NEXT: lwsync @@ -6063,7 +6063,7 @@ define dso_local zeroext i8 @atommax1(ptr nocapture noundef %ptr, i8 noundef zer ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB10_1 +; CHECK-NEXT: bne- 0, .LBB10_1 ; CHECK-NEXT: .LBB10_3: # %entry ; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 4, 66 @@ -6092,7 +6092,7 @@ define dso_local zeroext i8 @atommax1(ptr nocapture noundef %ptr, i8 noundef zer ; AIX32-NEXT: andc 10, 9, 7 ; AIX32-NEXT: or 10, 8, 10 ; AIX32-NEXT: stwcx. 10, 0, 3 -; AIX32-NEXT: bne 0, L..BB10_1 +; AIX32-NEXT: bne- 0, L..BB10_1 ; AIX32-NEXT: L..BB10_3: # %entry ; AIX32-NEXT: srw 3, 9, 5 ; AIX32-NEXT: lwsync diff --git a/llvm/test/CodeGen/PowerPC/atomic-minmax.ll b/llvm/test/CodeGen/PowerPC/atomic-minmax.ll index 747d9e5..44a4f16 100644 --- a/llvm/test/CodeGen/PowerPC/atomic-minmax.ll +++ b/llvm/test/CodeGen/PowerPC/atomic-minmax.ll @@ -14,7 +14,7 @@ define void @a32min(ptr nocapture dereferenceable(4) %minimum, i32 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB0_1 +; CHECK-NEXT: bne- 0, .LBB0_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -34,7 +34,7 @@ define void @a32max(ptr nocapture dereferenceable(4) %minimum, i32 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB1_1 +; CHECK-NEXT: bne- 0, .LBB1_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -54,7 +54,7 @@ define void @a32umin(ptr nocapture dereferenceable(4) %minimum, i32 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB2_1 +; CHECK-NEXT: bne- 0, .LBB2_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -74,7 +74,7 @@ define void @a32umax(ptr nocapture dereferenceable(4) %minimum, i32 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB3_1 +; CHECK-NEXT: bne- 0, .LBB3_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -96,7 +96,7 @@ define void @a16min(ptr nocapture dereferenceable(4) %minimum, i16 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB4_1 +; CHECK-NEXT: bne- 0, .LBB4_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -118,7 +118,7 @@ define void @a16max(ptr nocapture dereferenceable(4) %minimum, i16 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB5_1 +; CHECK-NEXT: bne- 0, .LBB5_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -138,7 +138,7 @@ define void @a16umin(ptr nocapture dereferenceable(4) %minimum, i16 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB6_1 +; CHECK-NEXT: bne- 0, .LBB6_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -158,7 +158,7 @@ define void @a16umax(ptr nocapture dereferenceable(4) %minimum, i16 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB7_1 +; CHECK-NEXT: bne- 0, .LBB7_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -180,7 +180,7 @@ define void @a8min(ptr nocapture dereferenceable(4) %minimum, i8 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB8_1 +; CHECK-NEXT: bne- 0, .LBB8_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -202,7 +202,7 @@ define void @a8max(ptr nocapture dereferenceable(4) %minimum, i8 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB9_1 +; CHECK-NEXT: bne- 0, .LBB9_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -222,7 +222,7 @@ define void @a8umin(ptr nocapture dereferenceable(4) %minimum, i8 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB10_1 +; CHECK-NEXT: bne- 0, .LBB10_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -242,7 +242,7 @@ define void @a8umax(ptr nocapture dereferenceable(4) %minimum, i8 %val) #1 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB11_1 +; CHECK-NEXT: bne- 0, .LBB11_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -262,7 +262,7 @@ define void @a64min(ptr nocapture dereferenceable(4) %minimum, i64 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB12_1 +; CHECK-NEXT: bne- 0, .LBB12_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -282,7 +282,7 @@ define void @a64max(ptr nocapture dereferenceable(4) %minimum, i64 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB13_1 +; CHECK-NEXT: bne- 0, .LBB13_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -302,7 +302,7 @@ define void @a64umin(ptr nocapture dereferenceable(4) %minimum, i64 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB14_1 +; CHECK-NEXT: bne- 0, .LBB14_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -322,7 +322,7 @@ define void @a64umax(ptr nocapture dereferenceable(4) %minimum, i64 %val) #0 { ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 4, 0, 3 -; CHECK-NEXT: bne 0, .LBB15_1 +; CHECK-NEXT: bne- 0, .LBB15_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -356,7 +356,7 @@ define void @ae16min(ptr nocapture dereferenceable(4) %minimum, i16 %val) #0 { ; CHECK-NEXT: andc 8, 8, 6 ; CHECK-NEXT: or 8, 7, 8 ; CHECK-NEXT: stwcx. 8, 0, 3 -; CHECK-NEXT: bne 0, .LBB16_1 +; CHECK-NEXT: bne- 0, .LBB16_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -390,7 +390,7 @@ define void @ae16max(ptr nocapture dereferenceable(4) %minimum, i16 %val) #0 { ; CHECK-NEXT: andc 8, 8, 6 ; CHECK-NEXT: or 8, 7, 8 ; CHECK-NEXT: stwcx. 8, 0, 3 -; CHECK-NEXT: bne 0, .LBB17_1 +; CHECK-NEXT: bne- 0, .LBB17_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -421,7 +421,7 @@ define void @ae16umin(ptr nocapture dereferenceable(4) %minimum, i16 %val) #0 { ; CHECK-NEXT: andc 7, 7, 5 ; CHECK-NEXT: or 7, 6, 7 ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB18_1 +; CHECK-NEXT: bne- 0, .LBB18_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -452,7 +452,7 @@ define void @ae16umax(ptr nocapture dereferenceable(4) %minimum, i16 %val) #0 { ; CHECK-NEXT: andc 7, 7, 5 ; CHECK-NEXT: or 7, 6, 7 ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB19_1 +; CHECK-NEXT: bne- 0, .LBB19_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -485,7 +485,7 @@ define void @ae8min(ptr nocapture dereferenceable(4) %minimum, i8 %val) #0 { ; CHECK-NEXT: andc 8, 8, 6 ; CHECK-NEXT: or 8, 7, 8 ; CHECK-NEXT: stwcx. 8, 0, 3 -; CHECK-NEXT: bne 0, .LBB20_1 +; CHECK-NEXT: bne- 0, .LBB20_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -518,7 +518,7 @@ define void @ae8max(ptr nocapture dereferenceable(4) %minimum, i8 %val) #0 { ; CHECK-NEXT: andc 8, 8, 6 ; CHECK-NEXT: or 8, 7, 8 ; CHECK-NEXT: stwcx. 8, 0, 3 -; CHECK-NEXT: bne 0, .LBB21_1 +; CHECK-NEXT: bne- 0, .LBB21_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -548,7 +548,7 @@ define void @ae8umin(ptr nocapture dereferenceable(4) %minimum, i8 %val) #0 { ; CHECK-NEXT: andc 7, 7, 5 ; CHECK-NEXT: or 7, 6, 7 ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB22_1 +; CHECK-NEXT: bne- 0, .LBB22_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: @@ -578,7 +578,7 @@ define void @ae8umax(ptr nocapture dereferenceable(4) %minimum, i8 %val) #0 { ; CHECK-NEXT: andc 7, 7, 5 ; CHECK-NEXT: or 7, 6, 7 ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB23_1 +; CHECK-NEXT: bne- 0, .LBB23_1 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/atomics-regression.ll b/llvm/test/CodeGen/PowerPC/atomics-regression.ll index 90990bb..cfc3a99 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-regression.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-regression.ll @@ -2291,7 +2291,7 @@ define i8 @test120(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB120_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB120_1 +; PPC64LE-NEXT: bne- 0, .LBB120_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2306,7 +2306,7 @@ define i8 @test121(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB121_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: stbcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB121_1 +; PPC64LE-NEXT: bne- 0, .LBB121_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2321,7 +2321,7 @@ define i8 @test122(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB122_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB122_1 +; PPC64LE-NEXT: bne- 0, .LBB122_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2336,7 +2336,7 @@ define i8 @test123(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB123_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB123_1 +; PPC64LE-NEXT: bne- 0, .LBB123_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2352,7 +2352,7 @@ define i8 @test124(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB124_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB124_1 +; PPC64LE-NEXT: bne- 0, .LBB124_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2367,7 +2367,7 @@ define i16 @test125(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB125_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB125_1 +; PPC64LE-NEXT: bne- 0, .LBB125_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2382,7 +2382,7 @@ define i16 @test126(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB126_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sthcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB126_1 +; PPC64LE-NEXT: bne- 0, .LBB126_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2397,7 +2397,7 @@ define i16 @test127(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB127_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB127_1 +; PPC64LE-NEXT: bne- 0, .LBB127_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2412,7 +2412,7 @@ define i16 @test128(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB128_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB128_1 +; PPC64LE-NEXT: bne- 0, .LBB128_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2428,7 +2428,7 @@ define i16 @test129(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB129_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB129_1 +; PPC64LE-NEXT: bne- 0, .LBB129_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2443,7 +2443,7 @@ define i32 @test130(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB130_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB130_1 +; PPC64LE-NEXT: bne- 0, .LBB130_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2458,7 +2458,7 @@ define i32 @test131(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB131_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB131_1 +; PPC64LE-NEXT: bne- 0, .LBB131_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2473,7 +2473,7 @@ define i32 @test132(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB132_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB132_1 +; PPC64LE-NEXT: bne- 0, .LBB132_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2488,7 +2488,7 @@ define i32 @test133(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB133_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB133_1 +; PPC64LE-NEXT: bne- 0, .LBB133_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2504,7 +2504,7 @@ define i32 @test134(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB134_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB134_1 +; PPC64LE-NEXT: bne- 0, .LBB134_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2519,7 +2519,7 @@ define i64 @test135(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB135_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB135_1 +; PPC64LE-NEXT: bne- 0, .LBB135_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2534,7 +2534,7 @@ define i64 @test136(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB136_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB136_1 +; PPC64LE-NEXT: bne- 0, .LBB136_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2549,7 +2549,7 @@ define i64 @test137(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB137_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB137_1 +; PPC64LE-NEXT: bne- 0, .LBB137_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2564,7 +2564,7 @@ define i64 @test138(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB138_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB138_1 +; PPC64LE-NEXT: bne- 0, .LBB138_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2580,7 +2580,7 @@ define i64 @test139(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB139_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB139_1 +; PPC64LE-NEXT: bne- 0, .LBB139_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2596,7 +2596,7 @@ define i8 @test140(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB140_1 +; PPC64LE-NEXT: bne- 0, .LBB140_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2612,7 +2612,7 @@ define i8 @test141(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB141_1 +; PPC64LE-NEXT: bne- 0, .LBB141_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2628,7 +2628,7 @@ define i8 @test142(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB142_1 +; PPC64LE-NEXT: bne- 0, .LBB142_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2644,7 +2644,7 @@ define i8 @test143(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB143_1 +; PPC64LE-NEXT: bne- 0, .LBB143_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2661,7 +2661,7 @@ define i8 @test144(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB144_1 +; PPC64LE-NEXT: bne- 0, .LBB144_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2677,7 +2677,7 @@ define i16 @test145(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB145_1 +; PPC64LE-NEXT: bne- 0, .LBB145_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2693,7 +2693,7 @@ define i16 @test146(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB146_1 +; PPC64LE-NEXT: bne- 0, .LBB146_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2709,7 +2709,7 @@ define i16 @test147(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB147_1 +; PPC64LE-NEXT: bne- 0, .LBB147_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2725,7 +2725,7 @@ define i16 @test148(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB148_1 +; PPC64LE-NEXT: bne- 0, .LBB148_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2742,7 +2742,7 @@ define i16 @test149(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB149_1 +; PPC64LE-NEXT: bne- 0, .LBB149_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2758,7 +2758,7 @@ define i32 @test150(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB150_1 +; PPC64LE-NEXT: bne- 0, .LBB150_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2774,7 +2774,7 @@ define i32 @test151(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB151_1 +; PPC64LE-NEXT: bne- 0, .LBB151_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2790,7 +2790,7 @@ define i32 @test152(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB152_1 +; PPC64LE-NEXT: bne- 0, .LBB152_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2806,7 +2806,7 @@ define i32 @test153(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB153_1 +; PPC64LE-NEXT: bne- 0, .LBB153_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2823,7 +2823,7 @@ define i32 @test154(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB154_1 +; PPC64LE-NEXT: bne- 0, .LBB154_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2839,7 +2839,7 @@ define i64 @test155(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB155_1 +; PPC64LE-NEXT: bne- 0, .LBB155_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2855,7 +2855,7 @@ define i64 @test156(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB156_1 +; PPC64LE-NEXT: bne- 0, .LBB156_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2871,7 +2871,7 @@ define i64 @test157(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB157_1 +; PPC64LE-NEXT: bne- 0, .LBB157_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2887,7 +2887,7 @@ define i64 @test158(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB158_1 +; PPC64LE-NEXT: bne- 0, .LBB158_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2904,7 +2904,7 @@ define i64 @test159(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB159_1 +; PPC64LE-NEXT: bne- 0, .LBB159_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2920,7 +2920,7 @@ define i8 @test160(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB160_1 +; PPC64LE-NEXT: bne- 0, .LBB160_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2936,7 +2936,7 @@ define i8 @test161(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB161_1 +; PPC64LE-NEXT: bne- 0, .LBB161_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2952,7 +2952,7 @@ define i8 @test162(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB162_1 +; PPC64LE-NEXT: bne- 0, .LBB162_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -2968,7 +2968,7 @@ define i8 @test163(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB163_1 +; PPC64LE-NEXT: bne- 0, .LBB163_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -2985,7 +2985,7 @@ define i8 @test164(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB164_1 +; PPC64LE-NEXT: bne- 0, .LBB164_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3001,7 +3001,7 @@ define i16 @test165(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB165_1 +; PPC64LE-NEXT: bne- 0, .LBB165_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3017,7 +3017,7 @@ define i16 @test166(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB166_1 +; PPC64LE-NEXT: bne- 0, .LBB166_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3033,7 +3033,7 @@ define i16 @test167(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB167_1 +; PPC64LE-NEXT: bne- 0, .LBB167_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3049,7 +3049,7 @@ define i16 @test168(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB168_1 +; PPC64LE-NEXT: bne- 0, .LBB168_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3066,7 +3066,7 @@ define i16 @test169(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB169_1 +; PPC64LE-NEXT: bne- 0, .LBB169_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3082,7 +3082,7 @@ define i32 @test170(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB170_1 +; PPC64LE-NEXT: bne- 0, .LBB170_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3098,7 +3098,7 @@ define i32 @test171(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB171_1 +; PPC64LE-NEXT: bne- 0, .LBB171_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3114,7 +3114,7 @@ define i32 @test172(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB172_1 +; PPC64LE-NEXT: bne- 0, .LBB172_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3130,7 +3130,7 @@ define i32 @test173(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB173_1 +; PPC64LE-NEXT: bne- 0, .LBB173_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3147,7 +3147,7 @@ define i32 @test174(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB174_1 +; PPC64LE-NEXT: bne- 0, .LBB174_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3163,7 +3163,7 @@ define i64 @test175(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB175_1 +; PPC64LE-NEXT: bne- 0, .LBB175_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3179,7 +3179,7 @@ define i64 @test176(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB176_1 +; PPC64LE-NEXT: bne- 0, .LBB176_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3195,7 +3195,7 @@ define i64 @test177(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB177_1 +; PPC64LE-NEXT: bne- 0, .LBB177_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3211,7 +3211,7 @@ define i64 @test178(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB178_1 +; PPC64LE-NEXT: bne- 0, .LBB178_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3228,7 +3228,7 @@ define i64 @test179(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB179_1 +; PPC64LE-NEXT: bne- 0, .LBB179_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3244,7 +3244,7 @@ define i8 @test180(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB180_1 +; PPC64LE-NEXT: bne- 0, .LBB180_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3260,7 +3260,7 @@ define i8 @test181(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB181_1 +; PPC64LE-NEXT: bne- 0, .LBB181_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3276,7 +3276,7 @@ define i8 @test182(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB182_1 +; PPC64LE-NEXT: bne- 0, .LBB182_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3292,7 +3292,7 @@ define i8 @test183(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB183_1 +; PPC64LE-NEXT: bne- 0, .LBB183_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3309,7 +3309,7 @@ define i8 @test184(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB184_1 +; PPC64LE-NEXT: bne- 0, .LBB184_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3325,7 +3325,7 @@ define i16 @test185(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB185_1 +; PPC64LE-NEXT: bne- 0, .LBB185_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3341,7 +3341,7 @@ define i16 @test186(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB186_1 +; PPC64LE-NEXT: bne- 0, .LBB186_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3357,7 +3357,7 @@ define i16 @test187(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB187_1 +; PPC64LE-NEXT: bne- 0, .LBB187_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3373,7 +3373,7 @@ define i16 @test188(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB188_1 +; PPC64LE-NEXT: bne- 0, .LBB188_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3390,7 +3390,7 @@ define i16 @test189(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB189_1 +; PPC64LE-NEXT: bne- 0, .LBB189_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3406,7 +3406,7 @@ define i32 @test190(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB190_1 +; PPC64LE-NEXT: bne- 0, .LBB190_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3422,7 +3422,7 @@ define i32 @test191(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB191_1 +; PPC64LE-NEXT: bne- 0, .LBB191_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3438,7 +3438,7 @@ define i32 @test192(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB192_1 +; PPC64LE-NEXT: bne- 0, .LBB192_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3454,7 +3454,7 @@ define i32 @test193(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB193_1 +; PPC64LE-NEXT: bne- 0, .LBB193_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3471,7 +3471,7 @@ define i32 @test194(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB194_1 +; PPC64LE-NEXT: bne- 0, .LBB194_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3487,7 +3487,7 @@ define i64 @test195(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB195_1 +; PPC64LE-NEXT: bne- 0, .LBB195_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3503,7 +3503,7 @@ define i64 @test196(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB196_1 +; PPC64LE-NEXT: bne- 0, .LBB196_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3519,7 +3519,7 @@ define i64 @test197(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB197_1 +; PPC64LE-NEXT: bne- 0, .LBB197_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3535,7 +3535,7 @@ define i64 @test198(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB198_1 +; PPC64LE-NEXT: bne- 0, .LBB198_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3552,7 +3552,7 @@ define i64 @test199(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB199_1 +; PPC64LE-NEXT: bne- 0, .LBB199_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3568,7 +3568,7 @@ define i8 @test200(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB200_1 +; PPC64LE-NEXT: bne- 0, .LBB200_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3584,7 +3584,7 @@ define i8 @test201(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB201_1 +; PPC64LE-NEXT: bne- 0, .LBB201_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3600,7 +3600,7 @@ define i8 @test202(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB202_1 +; PPC64LE-NEXT: bne- 0, .LBB202_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3616,7 +3616,7 @@ define i8 @test203(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB203_1 +; PPC64LE-NEXT: bne- 0, .LBB203_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3633,7 +3633,7 @@ define i8 @test204(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB204_1 +; PPC64LE-NEXT: bne- 0, .LBB204_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3649,7 +3649,7 @@ define i16 @test205(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB205_1 +; PPC64LE-NEXT: bne- 0, .LBB205_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3665,7 +3665,7 @@ define i16 @test206(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB206_1 +; PPC64LE-NEXT: bne- 0, .LBB206_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3681,7 +3681,7 @@ define i16 @test207(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB207_1 +; PPC64LE-NEXT: bne- 0, .LBB207_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3697,7 +3697,7 @@ define i16 @test208(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB208_1 +; PPC64LE-NEXT: bne- 0, .LBB208_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3714,7 +3714,7 @@ define i16 @test209(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB209_1 +; PPC64LE-NEXT: bne- 0, .LBB209_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3730,7 +3730,7 @@ define i32 @test210(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB210_1 +; PPC64LE-NEXT: bne- 0, .LBB210_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3746,7 +3746,7 @@ define i32 @test211(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB211_1 +; PPC64LE-NEXT: bne- 0, .LBB211_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3762,7 +3762,7 @@ define i32 @test212(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB212_1 +; PPC64LE-NEXT: bne- 0, .LBB212_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3778,7 +3778,7 @@ define i32 @test213(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB213_1 +; PPC64LE-NEXT: bne- 0, .LBB213_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3795,7 +3795,7 @@ define i32 @test214(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB214_1 +; PPC64LE-NEXT: bne- 0, .LBB214_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3811,7 +3811,7 @@ define i64 @test215(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB215_1 +; PPC64LE-NEXT: bne- 0, .LBB215_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3827,7 +3827,7 @@ define i64 @test216(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB216_1 +; PPC64LE-NEXT: bne- 0, .LBB216_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3843,7 +3843,7 @@ define i64 @test217(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB217_1 +; PPC64LE-NEXT: bne- 0, .LBB217_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3859,7 +3859,7 @@ define i64 @test218(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB218_1 +; PPC64LE-NEXT: bne- 0, .LBB218_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3876,7 +3876,7 @@ define i64 @test219(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB219_1 +; PPC64LE-NEXT: bne- 0, .LBB219_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3892,7 +3892,7 @@ define i8 @test220(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB220_1 +; PPC64LE-NEXT: bne- 0, .LBB220_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3908,7 +3908,7 @@ define i8 @test221(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB221_1 +; PPC64LE-NEXT: bne- 0, .LBB221_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3924,7 +3924,7 @@ define i8 @test222(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB222_1 +; PPC64LE-NEXT: bne- 0, .LBB222_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3940,7 +3940,7 @@ define i8 @test223(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB223_1 +; PPC64LE-NEXT: bne- 0, .LBB223_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3957,7 +3957,7 @@ define i8 @test224(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB224_1 +; PPC64LE-NEXT: bne- 0, .LBB224_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -3973,7 +3973,7 @@ define i16 @test225(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB225_1 +; PPC64LE-NEXT: bne- 0, .LBB225_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -3989,7 +3989,7 @@ define i16 @test226(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB226_1 +; PPC64LE-NEXT: bne- 0, .LBB226_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4005,7 +4005,7 @@ define i16 @test227(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB227_1 +; PPC64LE-NEXT: bne- 0, .LBB227_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4021,7 +4021,7 @@ define i16 @test228(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB228_1 +; PPC64LE-NEXT: bne- 0, .LBB228_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4038,7 +4038,7 @@ define i16 @test229(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB229_1 +; PPC64LE-NEXT: bne- 0, .LBB229_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4054,7 +4054,7 @@ define i32 @test230(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB230_1 +; PPC64LE-NEXT: bne- 0, .LBB230_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4070,7 +4070,7 @@ define i32 @test231(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB231_1 +; PPC64LE-NEXT: bne- 0, .LBB231_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4086,7 +4086,7 @@ define i32 @test232(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB232_1 +; PPC64LE-NEXT: bne- 0, .LBB232_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4102,7 +4102,7 @@ define i32 @test233(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB233_1 +; PPC64LE-NEXT: bne- 0, .LBB233_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4119,7 +4119,7 @@ define i32 @test234(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB234_1 +; PPC64LE-NEXT: bne- 0, .LBB234_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4135,7 +4135,7 @@ define i64 @test235(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB235_1 +; PPC64LE-NEXT: bne- 0, .LBB235_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4151,7 +4151,7 @@ define i64 @test236(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB236_1 +; PPC64LE-NEXT: bne- 0, .LBB236_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4167,7 +4167,7 @@ define i64 @test237(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB237_1 +; PPC64LE-NEXT: bne- 0, .LBB237_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4183,7 +4183,7 @@ define i64 @test238(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB238_1 +; PPC64LE-NEXT: bne- 0, .LBB238_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4200,7 +4200,7 @@ define i64 @test239(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB239_1 +; PPC64LE-NEXT: bne- 0, .LBB239_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4216,7 +4216,7 @@ define i8 @test240(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB240_1 +; PPC64LE-NEXT: bne- 0, .LBB240_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4232,7 +4232,7 @@ define i8 @test241(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB241_1 +; PPC64LE-NEXT: bne- 0, .LBB241_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4248,7 +4248,7 @@ define i8 @test242(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB242_1 +; PPC64LE-NEXT: bne- 0, .LBB242_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4264,7 +4264,7 @@ define i8 @test243(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB243_1 +; PPC64LE-NEXT: bne- 0, .LBB243_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4281,7 +4281,7 @@ define i8 @test244(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB244_1 +; PPC64LE-NEXT: bne- 0, .LBB244_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4297,7 +4297,7 @@ define i16 @test245(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB245_1 +; PPC64LE-NEXT: bne- 0, .LBB245_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4313,7 +4313,7 @@ define i16 @test246(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB246_1 +; PPC64LE-NEXT: bne- 0, .LBB246_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4329,7 +4329,7 @@ define i16 @test247(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB247_1 +; PPC64LE-NEXT: bne- 0, .LBB247_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4345,7 +4345,7 @@ define i16 @test248(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB248_1 +; PPC64LE-NEXT: bne- 0, .LBB248_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4362,7 +4362,7 @@ define i16 @test249(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB249_1 +; PPC64LE-NEXT: bne- 0, .LBB249_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4378,7 +4378,7 @@ define i32 @test250(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB250_1 +; PPC64LE-NEXT: bne- 0, .LBB250_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4394,7 +4394,7 @@ define i32 @test251(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB251_1 +; PPC64LE-NEXT: bne- 0, .LBB251_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4410,7 +4410,7 @@ define i32 @test252(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB252_1 +; PPC64LE-NEXT: bne- 0, .LBB252_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4426,7 +4426,7 @@ define i32 @test253(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB253_1 +; PPC64LE-NEXT: bne- 0, .LBB253_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4443,7 +4443,7 @@ define i32 @test254(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB254_1 +; PPC64LE-NEXT: bne- 0, .LBB254_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4459,7 +4459,7 @@ define i64 @test255(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB255_1 +; PPC64LE-NEXT: bne- 0, .LBB255_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4475,7 +4475,7 @@ define i64 @test256(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB256_1 +; PPC64LE-NEXT: bne- 0, .LBB256_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4491,7 +4491,7 @@ define i64 @test257(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB257_1 +; PPC64LE-NEXT: bne- 0, .LBB257_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4507,7 +4507,7 @@ define i64 @test258(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB258_1 +; PPC64LE-NEXT: bne- 0, .LBB258_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4524,7 +4524,7 @@ define i64 @test259(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB259_1 +; PPC64LE-NEXT: bne- 0, .LBB259_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4544,7 +4544,7 @@ define i8 @test260(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB260_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB260_1 +; PPC64LE-NEXT: bne- 0, .LBB260_1 ; PPC64LE-NEXT: .LBB260_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -4563,7 +4563,7 @@ define i8 @test261(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB261_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB261_1 +; PPC64LE-NEXT: bne- 0, .LBB261_1 ; PPC64LE-NEXT: .LBB261_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4584,7 +4584,7 @@ define i8 @test262(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB262_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB262_1 +; PPC64LE-NEXT: bne- 0, .LBB262_1 ; PPC64LE-NEXT: .LBB262_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -4604,7 +4604,7 @@ define i8 @test263(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB263_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB263_1 +; PPC64LE-NEXT: bne- 0, .LBB263_1 ; PPC64LE-NEXT: .LBB263_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4625,7 +4625,7 @@ define i8 @test264(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB264_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB264_1 +; PPC64LE-NEXT: bne- 0, .LBB264_1 ; PPC64LE-NEXT: .LBB264_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4645,7 +4645,7 @@ define i16 @test265(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB265_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB265_1 +; PPC64LE-NEXT: bne- 0, .LBB265_1 ; PPC64LE-NEXT: .LBB265_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -4664,7 +4664,7 @@ define i16 @test266(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB266_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB266_1 +; PPC64LE-NEXT: bne- 0, .LBB266_1 ; PPC64LE-NEXT: .LBB266_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4685,7 +4685,7 @@ define i16 @test267(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB267_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB267_1 +; PPC64LE-NEXT: bne- 0, .LBB267_1 ; PPC64LE-NEXT: .LBB267_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -4705,7 +4705,7 @@ define i16 @test268(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB268_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB268_1 +; PPC64LE-NEXT: bne- 0, .LBB268_1 ; PPC64LE-NEXT: .LBB268_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4726,7 +4726,7 @@ define i16 @test269(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB269_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB269_1 +; PPC64LE-NEXT: bne- 0, .LBB269_1 ; PPC64LE-NEXT: .LBB269_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4744,7 +4744,7 @@ define i32 @test270(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB270_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB270_1 +; PPC64LE-NEXT: bne- 0, .LBB270_1 ; PPC64LE-NEXT: .LBB270_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4762,7 +4762,7 @@ define i32 @test271(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB271_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB271_1 +; PPC64LE-NEXT: bne- 0, .LBB271_1 ; PPC64LE-NEXT: .LBB271_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4780,7 +4780,7 @@ define i32 @test272(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB272_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB272_1 +; PPC64LE-NEXT: bne- 0, .LBB272_1 ; PPC64LE-NEXT: .LBB272_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4798,7 +4798,7 @@ define i32 @test273(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB273_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB273_1 +; PPC64LE-NEXT: bne- 0, .LBB273_1 ; PPC64LE-NEXT: .LBB273_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4817,7 +4817,7 @@ define i32 @test274(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB274_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB274_1 +; PPC64LE-NEXT: bne- 0, .LBB274_1 ; PPC64LE-NEXT: .LBB274_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4835,7 +4835,7 @@ define i64 @test275(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB275_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB275_1 +; PPC64LE-NEXT: bne- 0, .LBB275_1 ; PPC64LE-NEXT: .LBB275_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4853,7 +4853,7 @@ define i64 @test276(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB276_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB276_1 +; PPC64LE-NEXT: bne- 0, .LBB276_1 ; PPC64LE-NEXT: .LBB276_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4871,7 +4871,7 @@ define i64 @test277(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB277_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB277_1 +; PPC64LE-NEXT: bne- 0, .LBB277_1 ; PPC64LE-NEXT: .LBB277_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -4889,7 +4889,7 @@ define i64 @test278(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB278_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB278_1 +; PPC64LE-NEXT: bne- 0, .LBB278_1 ; PPC64LE-NEXT: .LBB278_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4908,7 +4908,7 @@ define i64 @test279(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB279_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB279_1 +; PPC64LE-NEXT: bne- 0, .LBB279_1 ; PPC64LE-NEXT: .LBB279_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -4928,7 +4928,7 @@ define i8 @test280(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB280_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB280_1 +; PPC64LE-NEXT: bne- 0, .LBB280_1 ; PPC64LE-NEXT: .LBB280_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -4947,7 +4947,7 @@ define i8 @test281(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB281_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB281_1 +; PPC64LE-NEXT: bne- 0, .LBB281_1 ; PPC64LE-NEXT: .LBB281_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -4968,7 +4968,7 @@ define i8 @test282(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB282_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB282_1 +; PPC64LE-NEXT: bne- 0, .LBB282_1 ; PPC64LE-NEXT: .LBB282_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -4988,7 +4988,7 @@ define i8 @test283(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB283_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB283_1 +; PPC64LE-NEXT: bne- 0, .LBB283_1 ; PPC64LE-NEXT: .LBB283_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -5009,7 +5009,7 @@ define i8 @test284(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB284_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB284_1 +; PPC64LE-NEXT: bne- 0, .LBB284_1 ; PPC64LE-NEXT: .LBB284_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -5029,7 +5029,7 @@ define i16 @test285(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB285_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB285_1 +; PPC64LE-NEXT: bne- 0, .LBB285_1 ; PPC64LE-NEXT: .LBB285_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -5048,7 +5048,7 @@ define i16 @test286(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB286_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB286_1 +; PPC64LE-NEXT: bne- 0, .LBB286_1 ; PPC64LE-NEXT: .LBB286_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -5069,7 +5069,7 @@ define i16 @test287(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB287_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB287_1 +; PPC64LE-NEXT: bne- 0, .LBB287_1 ; PPC64LE-NEXT: .LBB287_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -5089,7 +5089,7 @@ define i16 @test288(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB288_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB288_1 +; PPC64LE-NEXT: bne- 0, .LBB288_1 ; PPC64LE-NEXT: .LBB288_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -5110,7 +5110,7 @@ define i16 @test289(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB289_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB289_1 +; PPC64LE-NEXT: bne- 0, .LBB289_1 ; PPC64LE-NEXT: .LBB289_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -5128,7 +5128,7 @@ define i32 @test290(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB290_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB290_1 +; PPC64LE-NEXT: bne- 0, .LBB290_1 ; PPC64LE-NEXT: .LBB290_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5146,7 +5146,7 @@ define i32 @test291(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB291_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB291_1 +; PPC64LE-NEXT: bne- 0, .LBB291_1 ; PPC64LE-NEXT: .LBB291_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5164,7 +5164,7 @@ define i32 @test292(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB292_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB292_1 +; PPC64LE-NEXT: bne- 0, .LBB292_1 ; PPC64LE-NEXT: .LBB292_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5182,7 +5182,7 @@ define i32 @test293(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB293_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB293_1 +; PPC64LE-NEXT: bne- 0, .LBB293_1 ; PPC64LE-NEXT: .LBB293_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5201,7 +5201,7 @@ define i32 @test294(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB294_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB294_1 +; PPC64LE-NEXT: bne- 0, .LBB294_1 ; PPC64LE-NEXT: .LBB294_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5219,7 +5219,7 @@ define i64 @test295(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB295_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB295_1 +; PPC64LE-NEXT: bne- 0, .LBB295_1 ; PPC64LE-NEXT: .LBB295_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5237,7 +5237,7 @@ define i64 @test296(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB296_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB296_1 +; PPC64LE-NEXT: bne- 0, .LBB296_1 ; PPC64LE-NEXT: .LBB296_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5255,7 +5255,7 @@ define i64 @test297(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB297_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB297_1 +; PPC64LE-NEXT: bne- 0, .LBB297_1 ; PPC64LE-NEXT: .LBB297_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5273,7 +5273,7 @@ define i64 @test298(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB298_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB298_1 +; PPC64LE-NEXT: bne- 0, .LBB298_1 ; PPC64LE-NEXT: .LBB298_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5292,7 +5292,7 @@ define i64 @test299(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB299_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB299_1 +; PPC64LE-NEXT: bne- 0, .LBB299_1 ; PPC64LE-NEXT: .LBB299_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5310,7 +5310,7 @@ define i8 @test300(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB300_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB300_1 +; PPC64LE-NEXT: bne- 0, .LBB300_1 ; PPC64LE-NEXT: .LBB300_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5328,7 +5328,7 @@ define i8 @test301(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB301_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB301_1 +; PPC64LE-NEXT: bne- 0, .LBB301_1 ; PPC64LE-NEXT: .LBB301_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5346,7 +5346,7 @@ define i8 @test302(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB302_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB302_1 +; PPC64LE-NEXT: bne- 0, .LBB302_1 ; PPC64LE-NEXT: .LBB302_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5364,7 +5364,7 @@ define i8 @test303(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB303_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB303_1 +; PPC64LE-NEXT: bne- 0, .LBB303_1 ; PPC64LE-NEXT: .LBB303_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5383,7 +5383,7 @@ define i8 @test304(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB304_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB304_1 +; PPC64LE-NEXT: bne- 0, .LBB304_1 ; PPC64LE-NEXT: .LBB304_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5401,7 +5401,7 @@ define i16 @test305(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB305_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB305_1 +; PPC64LE-NEXT: bne- 0, .LBB305_1 ; PPC64LE-NEXT: .LBB305_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5419,7 +5419,7 @@ define i16 @test306(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB306_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB306_1 +; PPC64LE-NEXT: bne- 0, .LBB306_1 ; PPC64LE-NEXT: .LBB306_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5437,7 +5437,7 @@ define i16 @test307(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB307_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB307_1 +; PPC64LE-NEXT: bne- 0, .LBB307_1 ; PPC64LE-NEXT: .LBB307_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5455,7 +5455,7 @@ define i16 @test308(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB308_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB308_1 +; PPC64LE-NEXT: bne- 0, .LBB308_1 ; PPC64LE-NEXT: .LBB308_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5474,7 +5474,7 @@ define i16 @test309(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB309_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB309_1 +; PPC64LE-NEXT: bne- 0, .LBB309_1 ; PPC64LE-NEXT: .LBB309_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5492,7 +5492,7 @@ define i32 @test310(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB310_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB310_1 +; PPC64LE-NEXT: bne- 0, .LBB310_1 ; PPC64LE-NEXT: .LBB310_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5510,7 +5510,7 @@ define i32 @test311(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB311_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB311_1 +; PPC64LE-NEXT: bne- 0, .LBB311_1 ; PPC64LE-NEXT: .LBB311_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5528,7 +5528,7 @@ define i32 @test312(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB312_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB312_1 +; PPC64LE-NEXT: bne- 0, .LBB312_1 ; PPC64LE-NEXT: .LBB312_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5546,7 +5546,7 @@ define i32 @test313(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB313_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB313_1 +; PPC64LE-NEXT: bne- 0, .LBB313_1 ; PPC64LE-NEXT: .LBB313_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5565,7 +5565,7 @@ define i32 @test314(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB314_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB314_1 +; PPC64LE-NEXT: bne- 0, .LBB314_1 ; PPC64LE-NEXT: .LBB314_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5583,7 +5583,7 @@ define i64 @test315(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB315_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB315_1 +; PPC64LE-NEXT: bne- 0, .LBB315_1 ; PPC64LE-NEXT: .LBB315_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5601,7 +5601,7 @@ define i64 @test316(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB316_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB316_1 +; PPC64LE-NEXT: bne- 0, .LBB316_1 ; PPC64LE-NEXT: .LBB316_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5619,7 +5619,7 @@ define i64 @test317(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB317_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB317_1 +; PPC64LE-NEXT: bne- 0, .LBB317_1 ; PPC64LE-NEXT: .LBB317_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5637,7 +5637,7 @@ define i64 @test318(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB318_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB318_1 +; PPC64LE-NEXT: bne- 0, .LBB318_1 ; PPC64LE-NEXT: .LBB318_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5656,7 +5656,7 @@ define i64 @test319(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB319_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB319_1 +; PPC64LE-NEXT: bne- 0, .LBB319_1 ; PPC64LE-NEXT: .LBB319_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5674,7 +5674,7 @@ define i8 @test320(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB320_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB320_1 +; PPC64LE-NEXT: bne- 0, .LBB320_1 ; PPC64LE-NEXT: .LBB320_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5692,7 +5692,7 @@ define i8 @test321(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB321_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB321_1 +; PPC64LE-NEXT: bne- 0, .LBB321_1 ; PPC64LE-NEXT: .LBB321_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5710,7 +5710,7 @@ define i8 @test322(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB322_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB322_1 +; PPC64LE-NEXT: bne- 0, .LBB322_1 ; PPC64LE-NEXT: .LBB322_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5728,7 +5728,7 @@ define i8 @test323(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB323_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB323_1 +; PPC64LE-NEXT: bne- 0, .LBB323_1 ; PPC64LE-NEXT: .LBB323_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5747,7 +5747,7 @@ define i8 @test324(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB324_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB324_1 +; PPC64LE-NEXT: bne- 0, .LBB324_1 ; PPC64LE-NEXT: .LBB324_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5765,7 +5765,7 @@ define i16 @test325(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB325_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB325_1 +; PPC64LE-NEXT: bne- 0, .LBB325_1 ; PPC64LE-NEXT: .LBB325_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5783,7 +5783,7 @@ define i16 @test326(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB326_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB326_1 +; PPC64LE-NEXT: bne- 0, .LBB326_1 ; PPC64LE-NEXT: .LBB326_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5801,7 +5801,7 @@ define i16 @test327(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB327_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB327_1 +; PPC64LE-NEXT: bne- 0, .LBB327_1 ; PPC64LE-NEXT: .LBB327_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5819,7 +5819,7 @@ define i16 @test328(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB328_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB328_1 +; PPC64LE-NEXT: bne- 0, .LBB328_1 ; PPC64LE-NEXT: .LBB328_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5838,7 +5838,7 @@ define i16 @test329(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB329_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB329_1 +; PPC64LE-NEXT: bne- 0, .LBB329_1 ; PPC64LE-NEXT: .LBB329_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5856,7 +5856,7 @@ define i32 @test330(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB330_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB330_1 +; PPC64LE-NEXT: bne- 0, .LBB330_1 ; PPC64LE-NEXT: .LBB330_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5874,7 +5874,7 @@ define i32 @test331(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB331_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB331_1 +; PPC64LE-NEXT: bne- 0, .LBB331_1 ; PPC64LE-NEXT: .LBB331_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5892,7 +5892,7 @@ define i32 @test332(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB332_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB332_1 +; PPC64LE-NEXT: bne- 0, .LBB332_1 ; PPC64LE-NEXT: .LBB332_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5910,7 +5910,7 @@ define i32 @test333(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB333_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB333_1 +; PPC64LE-NEXT: bne- 0, .LBB333_1 ; PPC64LE-NEXT: .LBB333_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5929,7 +5929,7 @@ define i32 @test334(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB334_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB334_1 +; PPC64LE-NEXT: bne- 0, .LBB334_1 ; PPC64LE-NEXT: .LBB334_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -5947,7 +5947,7 @@ define i64 @test335(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB335_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB335_1 +; PPC64LE-NEXT: bne- 0, .LBB335_1 ; PPC64LE-NEXT: .LBB335_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -5965,7 +5965,7 @@ define i64 @test336(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB336_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB336_1 +; PPC64LE-NEXT: bne- 0, .LBB336_1 ; PPC64LE-NEXT: .LBB336_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5983,7 +5983,7 @@ define i64 @test337(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB337_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB337_1 +; PPC64LE-NEXT: bne- 0, .LBB337_1 ; PPC64LE-NEXT: .LBB337_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6001,7 +6001,7 @@ define i64 @test338(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB338_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB338_1 +; PPC64LE-NEXT: bne- 0, .LBB338_1 ; PPC64LE-NEXT: .LBB338_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6020,7 +6020,7 @@ define i64 @test339(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB339_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB339_1 +; PPC64LE-NEXT: bne- 0, .LBB339_1 ; PPC64LE-NEXT: .LBB339_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6035,7 +6035,7 @@ define i8 @test340(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB340_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB340_1 +; PPC64LE-NEXT: bne- 0, .LBB340_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6050,7 +6050,7 @@ define i8 @test341(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB341_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: stbcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB341_1 +; PPC64LE-NEXT: bne- 0, .LBB341_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6065,7 +6065,7 @@ define i8 @test342(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB342_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB342_1 +; PPC64LE-NEXT: bne- 0, .LBB342_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6080,7 +6080,7 @@ define i8 @test343(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB343_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB343_1 +; PPC64LE-NEXT: bne- 0, .LBB343_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6096,7 +6096,7 @@ define i8 @test344(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: .LBB344_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB344_1 +; PPC64LE-NEXT: bne- 0, .LBB344_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6111,7 +6111,7 @@ define i16 @test345(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB345_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB345_1 +; PPC64LE-NEXT: bne- 0, .LBB345_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6126,7 +6126,7 @@ define i16 @test346(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB346_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sthcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB346_1 +; PPC64LE-NEXT: bne- 0, .LBB346_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6141,7 +6141,7 @@ define i16 @test347(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB347_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB347_1 +; PPC64LE-NEXT: bne- 0, .LBB347_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6156,7 +6156,7 @@ define i16 @test348(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB348_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB348_1 +; PPC64LE-NEXT: bne- 0, .LBB348_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6172,7 +6172,7 @@ define i16 @test349(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: .LBB349_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB349_1 +; PPC64LE-NEXT: bne- 0, .LBB349_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6187,7 +6187,7 @@ define i32 @test350(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB350_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB350_1 +; PPC64LE-NEXT: bne- 0, .LBB350_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6202,7 +6202,7 @@ define i32 @test351(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB351_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB351_1 +; PPC64LE-NEXT: bne- 0, .LBB351_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6217,7 +6217,7 @@ define i32 @test352(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB352_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB352_1 +; PPC64LE-NEXT: bne- 0, .LBB352_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6232,7 +6232,7 @@ define i32 @test353(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB353_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB353_1 +; PPC64LE-NEXT: bne- 0, .LBB353_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6248,7 +6248,7 @@ define i32 @test354(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: .LBB354_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB354_1 +; PPC64LE-NEXT: bne- 0, .LBB354_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6263,7 +6263,7 @@ define i64 @test355(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB355_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB355_1 +; PPC64LE-NEXT: bne- 0, .LBB355_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6278,7 +6278,7 @@ define i64 @test356(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB356_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB356_1 +; PPC64LE-NEXT: bne- 0, .LBB356_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6293,7 +6293,7 @@ define i64 @test357(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB357_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB357_1 +; PPC64LE-NEXT: bne- 0, .LBB357_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6308,7 +6308,7 @@ define i64 @test358(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB358_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB358_1 +; PPC64LE-NEXT: bne- 0, .LBB358_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6324,7 +6324,7 @@ define i64 @test359(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: .LBB359_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB359_1 +; PPC64LE-NEXT: bne- 0, .LBB359_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6340,7 +6340,7 @@ define i8 @test360(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB360_1 +; PPC64LE-NEXT: bne- 0, .LBB360_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6356,7 +6356,7 @@ define i8 @test361(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB361_1 +; PPC64LE-NEXT: bne- 0, .LBB361_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6372,7 +6372,7 @@ define i8 @test362(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB362_1 +; PPC64LE-NEXT: bne- 0, .LBB362_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6388,7 +6388,7 @@ define i8 @test363(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB363_1 +; PPC64LE-NEXT: bne- 0, .LBB363_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6405,7 +6405,7 @@ define i8 @test364(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB364_1 +; PPC64LE-NEXT: bne- 0, .LBB364_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6421,7 +6421,7 @@ define i16 @test365(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB365_1 +; PPC64LE-NEXT: bne- 0, .LBB365_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6437,7 +6437,7 @@ define i16 @test366(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB366_1 +; PPC64LE-NEXT: bne- 0, .LBB366_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6453,7 +6453,7 @@ define i16 @test367(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB367_1 +; PPC64LE-NEXT: bne- 0, .LBB367_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6469,7 +6469,7 @@ define i16 @test368(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB368_1 +; PPC64LE-NEXT: bne- 0, .LBB368_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6486,7 +6486,7 @@ define i16 @test369(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB369_1 +; PPC64LE-NEXT: bne- 0, .LBB369_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6502,7 +6502,7 @@ define i32 @test370(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB370_1 +; PPC64LE-NEXT: bne- 0, .LBB370_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6518,7 +6518,7 @@ define i32 @test371(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB371_1 +; PPC64LE-NEXT: bne- 0, .LBB371_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6534,7 +6534,7 @@ define i32 @test372(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB372_1 +; PPC64LE-NEXT: bne- 0, .LBB372_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6550,7 +6550,7 @@ define i32 @test373(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB373_1 +; PPC64LE-NEXT: bne- 0, .LBB373_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6567,7 +6567,7 @@ define i32 @test374(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB374_1 +; PPC64LE-NEXT: bne- 0, .LBB374_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6583,7 +6583,7 @@ define i64 @test375(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB375_1 +; PPC64LE-NEXT: bne- 0, .LBB375_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6599,7 +6599,7 @@ define i64 @test376(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB376_1 +; PPC64LE-NEXT: bne- 0, .LBB376_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6615,7 +6615,7 @@ define i64 @test377(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB377_1 +; PPC64LE-NEXT: bne- 0, .LBB377_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6631,7 +6631,7 @@ define i64 @test378(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB378_1 +; PPC64LE-NEXT: bne- 0, .LBB378_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6648,7 +6648,7 @@ define i64 @test379(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB379_1 +; PPC64LE-NEXT: bne- 0, .LBB379_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6664,7 +6664,7 @@ define i8 @test380(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB380_1 +; PPC64LE-NEXT: bne- 0, .LBB380_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6680,7 +6680,7 @@ define i8 @test381(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB381_1 +; PPC64LE-NEXT: bne- 0, .LBB381_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6696,7 +6696,7 @@ define i8 @test382(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB382_1 +; PPC64LE-NEXT: bne- 0, .LBB382_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6712,7 +6712,7 @@ define i8 @test383(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB383_1 +; PPC64LE-NEXT: bne- 0, .LBB383_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6729,7 +6729,7 @@ define i8 @test384(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB384_1 +; PPC64LE-NEXT: bne- 0, .LBB384_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6745,7 +6745,7 @@ define i16 @test385(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB385_1 +; PPC64LE-NEXT: bne- 0, .LBB385_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6761,7 +6761,7 @@ define i16 @test386(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB386_1 +; PPC64LE-NEXT: bne- 0, .LBB386_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6777,7 +6777,7 @@ define i16 @test387(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB387_1 +; PPC64LE-NEXT: bne- 0, .LBB387_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6793,7 +6793,7 @@ define i16 @test388(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB388_1 +; PPC64LE-NEXT: bne- 0, .LBB388_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6810,7 +6810,7 @@ define i16 @test389(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB389_1 +; PPC64LE-NEXT: bne- 0, .LBB389_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6826,7 +6826,7 @@ define i32 @test390(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB390_1 +; PPC64LE-NEXT: bne- 0, .LBB390_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6842,7 +6842,7 @@ define i32 @test391(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB391_1 +; PPC64LE-NEXT: bne- 0, .LBB391_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6858,7 +6858,7 @@ define i32 @test392(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB392_1 +; PPC64LE-NEXT: bne- 0, .LBB392_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6874,7 +6874,7 @@ define i32 @test393(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB393_1 +; PPC64LE-NEXT: bne- 0, .LBB393_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6891,7 +6891,7 @@ define i32 @test394(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB394_1 +; PPC64LE-NEXT: bne- 0, .LBB394_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6907,7 +6907,7 @@ define i64 @test395(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB395_1 +; PPC64LE-NEXT: bne- 0, .LBB395_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6923,7 +6923,7 @@ define i64 @test396(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB396_1 +; PPC64LE-NEXT: bne- 0, .LBB396_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6939,7 +6939,7 @@ define i64 @test397(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB397_1 +; PPC64LE-NEXT: bne- 0, .LBB397_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -6955,7 +6955,7 @@ define i64 @test398(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB398_1 +; PPC64LE-NEXT: bne- 0, .LBB398_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6972,7 +6972,7 @@ define i64 @test399(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB399_1 +; PPC64LE-NEXT: bne- 0, .LBB399_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -6988,7 +6988,7 @@ define i8 @test400(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB400_1 +; PPC64LE-NEXT: bne- 0, .LBB400_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7004,7 +7004,7 @@ define i8 @test401(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB401_1 +; PPC64LE-NEXT: bne- 0, .LBB401_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7020,7 +7020,7 @@ define i8 @test402(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB402_1 +; PPC64LE-NEXT: bne- 0, .LBB402_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7036,7 +7036,7 @@ define i8 @test403(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB403_1 +; PPC64LE-NEXT: bne- 0, .LBB403_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7053,7 +7053,7 @@ define i8 @test404(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB404_1 +; PPC64LE-NEXT: bne- 0, .LBB404_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7069,7 +7069,7 @@ define i16 @test405(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB405_1 +; PPC64LE-NEXT: bne- 0, .LBB405_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7085,7 +7085,7 @@ define i16 @test406(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB406_1 +; PPC64LE-NEXT: bne- 0, .LBB406_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7101,7 +7101,7 @@ define i16 @test407(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB407_1 +; PPC64LE-NEXT: bne- 0, .LBB407_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7117,7 +7117,7 @@ define i16 @test408(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB408_1 +; PPC64LE-NEXT: bne- 0, .LBB408_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7134,7 +7134,7 @@ define i16 @test409(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB409_1 +; PPC64LE-NEXT: bne- 0, .LBB409_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7150,7 +7150,7 @@ define i32 @test410(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB410_1 +; PPC64LE-NEXT: bne- 0, .LBB410_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7166,7 +7166,7 @@ define i32 @test411(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB411_1 +; PPC64LE-NEXT: bne- 0, .LBB411_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7182,7 +7182,7 @@ define i32 @test412(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB412_1 +; PPC64LE-NEXT: bne- 0, .LBB412_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7198,7 +7198,7 @@ define i32 @test413(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB413_1 +; PPC64LE-NEXT: bne- 0, .LBB413_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7215,7 +7215,7 @@ define i32 @test414(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB414_1 +; PPC64LE-NEXT: bne- 0, .LBB414_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7231,7 +7231,7 @@ define i64 @test415(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB415_1 +; PPC64LE-NEXT: bne- 0, .LBB415_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7247,7 +7247,7 @@ define i64 @test416(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB416_1 +; PPC64LE-NEXT: bne- 0, .LBB416_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7263,7 +7263,7 @@ define i64 @test417(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB417_1 +; PPC64LE-NEXT: bne- 0, .LBB417_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7279,7 +7279,7 @@ define i64 @test418(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB418_1 +; PPC64LE-NEXT: bne- 0, .LBB418_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7296,7 +7296,7 @@ define i64 @test419(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB419_1 +; PPC64LE-NEXT: bne- 0, .LBB419_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7312,7 +7312,7 @@ define i8 @test420(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB420_1 +; PPC64LE-NEXT: bne- 0, .LBB420_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7328,7 +7328,7 @@ define i8 @test421(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB421_1 +; PPC64LE-NEXT: bne- 0, .LBB421_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7344,7 +7344,7 @@ define i8 @test422(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB422_1 +; PPC64LE-NEXT: bne- 0, .LBB422_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7360,7 +7360,7 @@ define i8 @test423(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB423_1 +; PPC64LE-NEXT: bne- 0, .LBB423_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7377,7 +7377,7 @@ define i8 @test424(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB424_1 +; PPC64LE-NEXT: bne- 0, .LBB424_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7393,7 +7393,7 @@ define i16 @test425(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB425_1 +; PPC64LE-NEXT: bne- 0, .LBB425_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7409,7 +7409,7 @@ define i16 @test426(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB426_1 +; PPC64LE-NEXT: bne- 0, .LBB426_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7425,7 +7425,7 @@ define i16 @test427(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB427_1 +; PPC64LE-NEXT: bne- 0, .LBB427_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7441,7 +7441,7 @@ define i16 @test428(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB428_1 +; PPC64LE-NEXT: bne- 0, .LBB428_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7458,7 +7458,7 @@ define i16 @test429(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB429_1 +; PPC64LE-NEXT: bne- 0, .LBB429_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7474,7 +7474,7 @@ define i32 @test430(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB430_1 +; PPC64LE-NEXT: bne- 0, .LBB430_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7490,7 +7490,7 @@ define i32 @test431(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB431_1 +; PPC64LE-NEXT: bne- 0, .LBB431_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7506,7 +7506,7 @@ define i32 @test432(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB432_1 +; PPC64LE-NEXT: bne- 0, .LBB432_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7522,7 +7522,7 @@ define i32 @test433(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB433_1 +; PPC64LE-NEXT: bne- 0, .LBB433_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7539,7 +7539,7 @@ define i32 @test434(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB434_1 +; PPC64LE-NEXT: bne- 0, .LBB434_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7555,7 +7555,7 @@ define i64 @test435(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB435_1 +; PPC64LE-NEXT: bne- 0, .LBB435_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7571,7 +7571,7 @@ define i64 @test436(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB436_1 +; PPC64LE-NEXT: bne- 0, .LBB436_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7587,7 +7587,7 @@ define i64 @test437(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB437_1 +; PPC64LE-NEXT: bne- 0, .LBB437_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7603,7 +7603,7 @@ define i64 @test438(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB438_1 +; PPC64LE-NEXT: bne- 0, .LBB438_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7620,7 +7620,7 @@ define i64 @test439(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB439_1 +; PPC64LE-NEXT: bne- 0, .LBB439_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7636,7 +7636,7 @@ define i8 @test440(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB440_1 +; PPC64LE-NEXT: bne- 0, .LBB440_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7652,7 +7652,7 @@ define i8 @test441(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB441_1 +; PPC64LE-NEXT: bne- 0, .LBB441_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7668,7 +7668,7 @@ define i8 @test442(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB442_1 +; PPC64LE-NEXT: bne- 0, .LBB442_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7684,7 +7684,7 @@ define i8 @test443(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB443_1 +; PPC64LE-NEXT: bne- 0, .LBB443_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7701,7 +7701,7 @@ define i8 @test444(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB444_1 +; PPC64LE-NEXT: bne- 0, .LBB444_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7717,7 +7717,7 @@ define i16 @test445(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB445_1 +; PPC64LE-NEXT: bne- 0, .LBB445_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7733,7 +7733,7 @@ define i16 @test446(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB446_1 +; PPC64LE-NEXT: bne- 0, .LBB446_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7749,7 +7749,7 @@ define i16 @test447(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB447_1 +; PPC64LE-NEXT: bne- 0, .LBB447_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7765,7 +7765,7 @@ define i16 @test448(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB448_1 +; PPC64LE-NEXT: bne- 0, .LBB448_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7782,7 +7782,7 @@ define i16 @test449(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB449_1 +; PPC64LE-NEXT: bne- 0, .LBB449_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7798,7 +7798,7 @@ define i32 @test450(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB450_1 +; PPC64LE-NEXT: bne- 0, .LBB450_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7814,7 +7814,7 @@ define i32 @test451(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB451_1 +; PPC64LE-NEXT: bne- 0, .LBB451_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7830,7 +7830,7 @@ define i32 @test452(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB452_1 +; PPC64LE-NEXT: bne- 0, .LBB452_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7846,7 +7846,7 @@ define i32 @test453(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB453_1 +; PPC64LE-NEXT: bne- 0, .LBB453_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7863,7 +7863,7 @@ define i32 @test454(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB454_1 +; PPC64LE-NEXT: bne- 0, .LBB454_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7879,7 +7879,7 @@ define i64 @test455(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB455_1 +; PPC64LE-NEXT: bne- 0, .LBB455_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7895,7 +7895,7 @@ define i64 @test456(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB456_1 +; PPC64LE-NEXT: bne- 0, .LBB456_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7911,7 +7911,7 @@ define i64 @test457(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB457_1 +; PPC64LE-NEXT: bne- 0, .LBB457_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7927,7 +7927,7 @@ define i64 @test458(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB458_1 +; PPC64LE-NEXT: bne- 0, .LBB458_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7944,7 +7944,7 @@ define i64 @test459(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB459_1 +; PPC64LE-NEXT: bne- 0, .LBB459_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -7960,7 +7960,7 @@ define i8 @test460(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB460_1 +; PPC64LE-NEXT: bne- 0, .LBB460_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -7976,7 +7976,7 @@ define i8 @test461(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB461_1 +; PPC64LE-NEXT: bne- 0, .LBB461_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7992,7 +7992,7 @@ define i8 @test462(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB462_1 +; PPC64LE-NEXT: bne- 0, .LBB462_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8008,7 +8008,7 @@ define i8 @test463(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB463_1 +; PPC64LE-NEXT: bne- 0, .LBB463_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8025,7 +8025,7 @@ define i8 @test464(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB464_1 +; PPC64LE-NEXT: bne- 0, .LBB464_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8041,7 +8041,7 @@ define i16 @test465(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB465_1 +; PPC64LE-NEXT: bne- 0, .LBB465_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8057,7 +8057,7 @@ define i16 @test466(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB466_1 +; PPC64LE-NEXT: bne- 0, .LBB466_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8073,7 +8073,7 @@ define i16 @test467(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB467_1 +; PPC64LE-NEXT: bne- 0, .LBB467_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8089,7 +8089,7 @@ define i16 @test468(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB468_1 +; PPC64LE-NEXT: bne- 0, .LBB468_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8106,7 +8106,7 @@ define i16 @test469(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB469_1 +; PPC64LE-NEXT: bne- 0, .LBB469_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8122,7 +8122,7 @@ define i32 @test470(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB470_1 +; PPC64LE-NEXT: bne- 0, .LBB470_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8138,7 +8138,7 @@ define i32 @test471(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB471_1 +; PPC64LE-NEXT: bne- 0, .LBB471_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8154,7 +8154,7 @@ define i32 @test472(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB472_1 +; PPC64LE-NEXT: bne- 0, .LBB472_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8170,7 +8170,7 @@ define i32 @test473(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB473_1 +; PPC64LE-NEXT: bne- 0, .LBB473_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8187,7 +8187,7 @@ define i32 @test474(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB474_1 +; PPC64LE-NEXT: bne- 0, .LBB474_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8203,7 +8203,7 @@ define i64 @test475(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB475_1 +; PPC64LE-NEXT: bne- 0, .LBB475_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8219,7 +8219,7 @@ define i64 @test476(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB476_1 +; PPC64LE-NEXT: bne- 0, .LBB476_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8235,7 +8235,7 @@ define i64 @test477(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB477_1 +; PPC64LE-NEXT: bne- 0, .LBB477_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8251,7 +8251,7 @@ define i64 @test478(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB478_1 +; PPC64LE-NEXT: bne- 0, .LBB478_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8268,7 +8268,7 @@ define i64 @test479(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB479_1 +; PPC64LE-NEXT: bne- 0, .LBB479_1 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8288,7 +8288,7 @@ define i8 @test480(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB480_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB480_1 +; PPC64LE-NEXT: bne- 0, .LBB480_1 ; PPC64LE-NEXT: .LBB480_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8307,7 +8307,7 @@ define i8 @test481(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB481_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB481_1 +; PPC64LE-NEXT: bne- 0, .LBB481_1 ; PPC64LE-NEXT: .LBB481_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8328,7 +8328,7 @@ define i8 @test482(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB482_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB482_1 +; PPC64LE-NEXT: bne- 0, .LBB482_1 ; PPC64LE-NEXT: .LBB482_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8348,7 +8348,7 @@ define i8 @test483(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB483_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB483_1 +; PPC64LE-NEXT: bne- 0, .LBB483_1 ; PPC64LE-NEXT: .LBB483_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8369,7 +8369,7 @@ define i8 @test484(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB484_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB484_1 +; PPC64LE-NEXT: bne- 0, .LBB484_1 ; PPC64LE-NEXT: .LBB484_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8389,7 +8389,7 @@ define i16 @test485(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB485_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB485_1 +; PPC64LE-NEXT: bne- 0, .LBB485_1 ; PPC64LE-NEXT: .LBB485_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8408,7 +8408,7 @@ define i16 @test486(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB486_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB486_1 +; PPC64LE-NEXT: bne- 0, .LBB486_1 ; PPC64LE-NEXT: .LBB486_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8429,7 +8429,7 @@ define i16 @test487(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB487_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB487_1 +; PPC64LE-NEXT: bne- 0, .LBB487_1 ; PPC64LE-NEXT: .LBB487_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8449,7 +8449,7 @@ define i16 @test488(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB488_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB488_1 +; PPC64LE-NEXT: bne- 0, .LBB488_1 ; PPC64LE-NEXT: .LBB488_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8470,7 +8470,7 @@ define i16 @test489(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB489_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB489_1 +; PPC64LE-NEXT: bne- 0, .LBB489_1 ; PPC64LE-NEXT: .LBB489_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8488,7 +8488,7 @@ define i32 @test490(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB490_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB490_1 +; PPC64LE-NEXT: bne- 0, .LBB490_1 ; PPC64LE-NEXT: .LBB490_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8506,7 +8506,7 @@ define i32 @test491(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB491_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB491_1 +; PPC64LE-NEXT: bne- 0, .LBB491_1 ; PPC64LE-NEXT: .LBB491_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8524,7 +8524,7 @@ define i32 @test492(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB492_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB492_1 +; PPC64LE-NEXT: bne- 0, .LBB492_1 ; PPC64LE-NEXT: .LBB492_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8542,7 +8542,7 @@ define i32 @test493(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB493_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB493_1 +; PPC64LE-NEXT: bne- 0, .LBB493_1 ; PPC64LE-NEXT: .LBB493_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8561,7 +8561,7 @@ define i32 @test494(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB494_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB494_1 +; PPC64LE-NEXT: bne- 0, .LBB494_1 ; PPC64LE-NEXT: .LBB494_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8579,7 +8579,7 @@ define i64 @test495(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB495_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB495_1 +; PPC64LE-NEXT: bne- 0, .LBB495_1 ; PPC64LE-NEXT: .LBB495_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8597,7 +8597,7 @@ define i64 @test496(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB496_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB496_1 +; PPC64LE-NEXT: bne- 0, .LBB496_1 ; PPC64LE-NEXT: .LBB496_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8615,7 +8615,7 @@ define i64 @test497(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB497_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB497_1 +; PPC64LE-NEXT: bne- 0, .LBB497_1 ; PPC64LE-NEXT: .LBB497_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8633,7 +8633,7 @@ define i64 @test498(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB498_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB498_1 +; PPC64LE-NEXT: bne- 0, .LBB498_1 ; PPC64LE-NEXT: .LBB498_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8652,7 +8652,7 @@ define i64 @test499(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB499_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB499_1 +; PPC64LE-NEXT: bne- 0, .LBB499_1 ; PPC64LE-NEXT: .LBB499_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8672,7 +8672,7 @@ define i8 @test500(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB500_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB500_1 +; PPC64LE-NEXT: bne- 0, .LBB500_1 ; PPC64LE-NEXT: .LBB500_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8691,7 +8691,7 @@ define i8 @test501(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB501_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB501_1 +; PPC64LE-NEXT: bne- 0, .LBB501_1 ; PPC64LE-NEXT: .LBB501_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8712,7 +8712,7 @@ define i8 @test502(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB502_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB502_1 +; PPC64LE-NEXT: bne- 0, .LBB502_1 ; PPC64LE-NEXT: .LBB502_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8732,7 +8732,7 @@ define i8 @test503(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB503_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB503_1 +; PPC64LE-NEXT: bne- 0, .LBB503_1 ; PPC64LE-NEXT: .LBB503_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8753,7 +8753,7 @@ define i8 @test504(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB504_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB504_1 +; PPC64LE-NEXT: bne- 0, .LBB504_1 ; PPC64LE-NEXT: .LBB504_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8773,7 +8773,7 @@ define i16 @test505(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB505_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB505_1 +; PPC64LE-NEXT: bne- 0, .LBB505_1 ; PPC64LE-NEXT: .LBB505_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8792,7 +8792,7 @@ define i16 @test506(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB506_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB506_1 +; PPC64LE-NEXT: bne- 0, .LBB506_1 ; PPC64LE-NEXT: .LBB506_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8813,7 +8813,7 @@ define i16 @test507(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB507_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB507_1 +; PPC64LE-NEXT: bne- 0, .LBB507_1 ; PPC64LE-NEXT: .LBB507_3: ; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: blr @@ -8833,7 +8833,7 @@ define i16 @test508(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB508_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB508_1 +; PPC64LE-NEXT: bne- 0, .LBB508_1 ; PPC64LE-NEXT: .LBB508_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8854,7 +8854,7 @@ define i16 @test509(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB509_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB509_1 +; PPC64LE-NEXT: bne- 0, .LBB509_1 ; PPC64LE-NEXT: .LBB509_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 4 @@ -8872,7 +8872,7 @@ define i32 @test510(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB510_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB510_1 +; PPC64LE-NEXT: bne- 0, .LBB510_1 ; PPC64LE-NEXT: .LBB510_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8890,7 +8890,7 @@ define i32 @test511(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB511_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB511_1 +; PPC64LE-NEXT: bne- 0, .LBB511_1 ; PPC64LE-NEXT: .LBB511_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8908,7 +8908,7 @@ define i32 @test512(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB512_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB512_1 +; PPC64LE-NEXT: bne- 0, .LBB512_1 ; PPC64LE-NEXT: .LBB512_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8926,7 +8926,7 @@ define i32 @test513(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB513_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB513_1 +; PPC64LE-NEXT: bne- 0, .LBB513_1 ; PPC64LE-NEXT: .LBB513_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8945,7 +8945,7 @@ define i32 @test514(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB514_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB514_1 +; PPC64LE-NEXT: bne- 0, .LBB514_1 ; PPC64LE-NEXT: .LBB514_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -8963,7 +8963,7 @@ define i64 @test515(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB515_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB515_1 +; PPC64LE-NEXT: bne- 0, .LBB515_1 ; PPC64LE-NEXT: .LBB515_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -8981,7 +8981,7 @@ define i64 @test516(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB516_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB516_1 +; PPC64LE-NEXT: bne- 0, .LBB516_1 ; PPC64LE-NEXT: .LBB516_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8999,7 +8999,7 @@ define i64 @test517(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB517_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB517_1 +; PPC64LE-NEXT: bne- 0, .LBB517_1 ; PPC64LE-NEXT: .LBB517_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9017,7 +9017,7 @@ define i64 @test518(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB518_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB518_1 +; PPC64LE-NEXT: bne- 0, .LBB518_1 ; PPC64LE-NEXT: .LBB518_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9036,7 +9036,7 @@ define i64 @test519(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB519_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB519_1 +; PPC64LE-NEXT: bne- 0, .LBB519_1 ; PPC64LE-NEXT: .LBB519_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9054,7 +9054,7 @@ define i8 @test520(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB520_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB520_1 +; PPC64LE-NEXT: bne- 0, .LBB520_1 ; PPC64LE-NEXT: .LBB520_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9072,7 +9072,7 @@ define i8 @test521(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB521_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB521_1 +; PPC64LE-NEXT: bne- 0, .LBB521_1 ; PPC64LE-NEXT: .LBB521_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9090,7 +9090,7 @@ define i8 @test522(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB522_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB522_1 +; PPC64LE-NEXT: bne- 0, .LBB522_1 ; PPC64LE-NEXT: .LBB522_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9108,7 +9108,7 @@ define i8 @test523(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB523_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB523_1 +; PPC64LE-NEXT: bne- 0, .LBB523_1 ; PPC64LE-NEXT: .LBB523_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9127,7 +9127,7 @@ define i8 @test524(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: bgt 0, .LBB524_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB524_1 +; PPC64LE-NEXT: bne- 0, .LBB524_1 ; PPC64LE-NEXT: .LBB524_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9145,7 +9145,7 @@ define i16 @test525(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB525_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB525_1 +; PPC64LE-NEXT: bne- 0, .LBB525_1 ; PPC64LE-NEXT: .LBB525_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9163,7 +9163,7 @@ define i16 @test526(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB526_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB526_1 +; PPC64LE-NEXT: bne- 0, .LBB526_1 ; PPC64LE-NEXT: .LBB526_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9181,7 +9181,7 @@ define i16 @test527(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB527_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB527_1 +; PPC64LE-NEXT: bne- 0, .LBB527_1 ; PPC64LE-NEXT: .LBB527_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9199,7 +9199,7 @@ define i16 @test528(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB528_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB528_1 +; PPC64LE-NEXT: bne- 0, .LBB528_1 ; PPC64LE-NEXT: .LBB528_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9218,7 +9218,7 @@ define i16 @test529(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: bgt 0, .LBB529_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB529_1 +; PPC64LE-NEXT: bne- 0, .LBB529_1 ; PPC64LE-NEXT: .LBB529_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9236,7 +9236,7 @@ define i32 @test530(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB530_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB530_1 +; PPC64LE-NEXT: bne- 0, .LBB530_1 ; PPC64LE-NEXT: .LBB530_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9254,7 +9254,7 @@ define i32 @test531(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB531_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB531_1 +; PPC64LE-NEXT: bne- 0, .LBB531_1 ; PPC64LE-NEXT: .LBB531_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9272,7 +9272,7 @@ define i32 @test532(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB532_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB532_1 +; PPC64LE-NEXT: bne- 0, .LBB532_1 ; PPC64LE-NEXT: .LBB532_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9290,7 +9290,7 @@ define i32 @test533(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB533_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB533_1 +; PPC64LE-NEXT: bne- 0, .LBB533_1 ; PPC64LE-NEXT: .LBB533_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9309,7 +9309,7 @@ define i32 @test534(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: bgt 0, .LBB534_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB534_1 +; PPC64LE-NEXT: bne- 0, .LBB534_1 ; PPC64LE-NEXT: .LBB534_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9327,7 +9327,7 @@ define i64 @test535(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB535_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB535_1 +; PPC64LE-NEXT: bne- 0, .LBB535_1 ; PPC64LE-NEXT: .LBB535_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9345,7 +9345,7 @@ define i64 @test536(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB536_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB536_1 +; PPC64LE-NEXT: bne- 0, .LBB536_1 ; PPC64LE-NEXT: .LBB536_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9363,7 +9363,7 @@ define i64 @test537(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB537_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB537_1 +; PPC64LE-NEXT: bne- 0, .LBB537_1 ; PPC64LE-NEXT: .LBB537_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9381,7 +9381,7 @@ define i64 @test538(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB538_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB538_1 +; PPC64LE-NEXT: bne- 0, .LBB538_1 ; PPC64LE-NEXT: .LBB538_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9400,7 +9400,7 @@ define i64 @test539(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: bgt 0, .LBB539_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB539_1 +; PPC64LE-NEXT: bne- 0, .LBB539_1 ; PPC64LE-NEXT: .LBB539_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9418,7 +9418,7 @@ define i8 @test540(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB540_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB540_1 +; PPC64LE-NEXT: bne- 0, .LBB540_1 ; PPC64LE-NEXT: .LBB540_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9436,7 +9436,7 @@ define i8 @test541(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB541_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB541_1 +; PPC64LE-NEXT: bne- 0, .LBB541_1 ; PPC64LE-NEXT: .LBB541_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9454,7 +9454,7 @@ define i8 @test542(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB542_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB542_1 +; PPC64LE-NEXT: bne- 0, .LBB542_1 ; PPC64LE-NEXT: .LBB542_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9472,7 +9472,7 @@ define i8 @test543(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB543_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB543_1 +; PPC64LE-NEXT: bne- 0, .LBB543_1 ; PPC64LE-NEXT: .LBB543_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9491,7 +9491,7 @@ define i8 @test544(ptr %ptr, i8 %val) { ; PPC64LE-NEXT: blt 0, .LBB544_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB544_1 +; PPC64LE-NEXT: bne- 0, .LBB544_1 ; PPC64LE-NEXT: .LBB544_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9509,7 +9509,7 @@ define i16 @test545(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB545_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB545_1 +; PPC64LE-NEXT: bne- 0, .LBB545_1 ; PPC64LE-NEXT: .LBB545_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9527,7 +9527,7 @@ define i16 @test546(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB546_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB546_1 +; PPC64LE-NEXT: bne- 0, .LBB546_1 ; PPC64LE-NEXT: .LBB546_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9545,7 +9545,7 @@ define i16 @test547(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB547_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB547_1 +; PPC64LE-NEXT: bne- 0, .LBB547_1 ; PPC64LE-NEXT: .LBB547_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9563,7 +9563,7 @@ define i16 @test548(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB548_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB548_1 +; PPC64LE-NEXT: bne- 0, .LBB548_1 ; PPC64LE-NEXT: .LBB548_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9582,7 +9582,7 @@ define i16 @test549(ptr %ptr, i16 %val) { ; PPC64LE-NEXT: blt 0, .LBB549_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB549_1 +; PPC64LE-NEXT: bne- 0, .LBB549_1 ; PPC64LE-NEXT: .LBB549_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9600,7 +9600,7 @@ define i32 @test550(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB550_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB550_1 +; PPC64LE-NEXT: bne- 0, .LBB550_1 ; PPC64LE-NEXT: .LBB550_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9618,7 +9618,7 @@ define i32 @test551(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB551_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB551_1 +; PPC64LE-NEXT: bne- 0, .LBB551_1 ; PPC64LE-NEXT: .LBB551_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9636,7 +9636,7 @@ define i32 @test552(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB552_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB552_1 +; PPC64LE-NEXT: bne- 0, .LBB552_1 ; PPC64LE-NEXT: .LBB552_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9654,7 +9654,7 @@ define i32 @test553(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB553_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB553_1 +; PPC64LE-NEXT: bne- 0, .LBB553_1 ; PPC64LE-NEXT: .LBB553_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9673,7 +9673,7 @@ define i32 @test554(ptr %ptr, i32 %val) { ; PPC64LE-NEXT: blt 0, .LBB554_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB554_1 +; PPC64LE-NEXT: bne- 0, .LBB554_1 ; PPC64LE-NEXT: .LBB554_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9691,7 +9691,7 @@ define i64 @test555(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB555_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB555_1 +; PPC64LE-NEXT: bne- 0, .LBB555_1 ; PPC64LE-NEXT: .LBB555_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9709,7 +9709,7 @@ define i64 @test556(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB556_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 -; PPC64LE-NEXT: bne 0, .LBB556_1 +; PPC64LE-NEXT: bne- 0, .LBB556_1 ; PPC64LE-NEXT: .LBB556_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -9727,7 +9727,7 @@ define i64 @test557(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB557_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB557_1 +; PPC64LE-NEXT: bne- 0, .LBB557_1 ; PPC64LE-NEXT: .LBB557_3: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr @@ -9745,7 +9745,7 @@ define i64 @test558(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB558_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB558_1 +; PPC64LE-NEXT: bne- 0, .LBB558_1 ; PPC64LE-NEXT: .LBB558_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 @@ -9764,7 +9764,7 @@ define i64 @test559(ptr %ptr, i64 %val) { ; PPC64LE-NEXT: blt 0, .LBB559_3 ; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB559_1 +; PPC64LE-NEXT: bne- 0, .LBB559_1 ; PPC64LE-NEXT: .LBB559_3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: mr 3, 5 diff --git a/llvm/test/CodeGen/PowerPC/atomics.ll b/llvm/test/CodeGen/PowerPC/atomics.ll index 183c8e1..ff1a722 100644 --- a/llvm/test/CodeGen/PowerPC/atomics.ll +++ b/llvm/test/CodeGen/PowerPC/atomics.ll @@ -341,7 +341,7 @@ define i8 @add_i8_monotonic(ptr %mem, i8 %operand) { ; PPC32-NEXT: and r8, r8, r6 ; PPC32-NEXT: or r8, r8, r9 ; PPC32-NEXT: stwcx. r8, 0, r5 -; PPC32-NEXT: bne cr0, .LBB12_1 +; PPC32-NEXT: bne- cr0, .LBB12_1 ; PPC32-NEXT: # %bb.2: ; PPC32-NEXT: srw r3, r7, r3 ; PPC32-NEXT: clrlwi r3, r3, 24 @@ -362,7 +362,7 @@ define i8 @add_i8_monotonic(ptr %mem, i8 %operand) { ; PPC64-NEXT: and r8, r8, r6 ; PPC64-NEXT: or r8, r8, r9 ; PPC64-NEXT: stwcx. r8, 0, r5 -; PPC64-NEXT: bne cr0, .LBB12_1 +; PPC64-NEXT: bne- cr0, .LBB12_1 ; PPC64-NEXT: # %bb.2: ; PPC64-NEXT: srw r3, r7, r3 ; PPC64-NEXT: clrlwi r3, r3, 24 @@ -388,7 +388,7 @@ define i16 @xor_i16_seq_cst(ptr %mem, i16 %operand) { ; PPC32-NEXT: and r8, r8, r6 ; PPC32-NEXT: or r8, r8, r9 ; PPC32-NEXT: stwcx. r8, 0, r3 -; PPC32-NEXT: bne cr0, .LBB13_1 +; PPC32-NEXT: bne- cr0, .LBB13_1 ; PPC32-NEXT: # %bb.2: ; PPC32-NEXT: srw r3, r7, r5 ; PPC32-NEXT: clrlwi r3, r3, 16 @@ -412,7 +412,7 @@ define i16 @xor_i16_seq_cst(ptr %mem, i16 %operand) { ; PPC64-NEXT: and r8, r8, r6 ; PPC64-NEXT: or r8, r8, r9 ; PPC64-NEXT: stwcx. r8, 0, r3 -; PPC64-NEXT: bne cr0, .LBB13_1 +; PPC64-NEXT: bne- cr0, .LBB13_1 ; PPC64-NEXT: # %bb.2: ; PPC64-NEXT: srw r3, r7, r5 ; PPC64-NEXT: clrlwi r3, r3, 16 @@ -428,7 +428,7 @@ define i32 @xchg_i32_acq_rel(ptr %mem, i32 %operand) { ; CHECK-NEXT: .LBB14_1: ; CHECK-NEXT: lwarx r5, 0, r3 ; CHECK-NEXT: stwcx. r4, 0, r3 -; CHECK-NEXT: bne cr0, .LBB14_1 +; CHECK-NEXT: bne- cr0, .LBB14_1 ; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: mr r3, r5 ; CHECK-NEXT: lwsync @@ -458,7 +458,7 @@ define i64 @and_i64_release(ptr %mem, i64 %operand) { ; PPC64-NEXT: ldarx r5, 0, r3 ; PPC64-NEXT: and r6, r4, r5 ; PPC64-NEXT: stdcx. r6, 0, r3 -; PPC64-NEXT: bne cr0, .LBB15_1 +; PPC64-NEXT: bne- cr0, .LBB15_1 ; PPC64-NEXT: # %bb.2: ; PPC64-NEXT: mr r3, r5 ; PPC64-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll index f7df003..b1fb907 100644 --- a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll +++ b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll @@ -4,10 +4,9 @@ ; for minor code generation differences. ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -mattr=-isel < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL -; Also check that with -enable-unsafe-fp-math we do not get that extra +; Also check that with fpexcept.ignore we do not get that extra ; code sequence. Simply verify that there is no "isel" present. -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE -; CHECK-UNSAFE-NOT: isel + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -15,9 +14,8 @@ define float @test(i64 %x) nounwind readnone { ; Verify that we get the code sequence needed to avoid double-rounding. ; Note that only parts of the sequence are checked for here, to allow ; for minor code generation differences. -; Also check that with -enable-unsafe-fp-math we do not get that extra +; Also check that with fpexcept.ignore we do not get that extra ; code sequence. Simply verify that there is no "isel" present. -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: clrldi 4, 3, 53 @@ -51,18 +49,10 @@ define float @test(i64 %x) nounwind readnone { ; CHECK-NO-ISEL-NEXT: xscvsxddp 0, 0 ; CHECK-NO-ISEL-NEXT: frsp 1, 0 ; CHECK-NO-ISEL-NEXT: blr -; -; CHECK-UNSAFE-LABEL: test: -; CHECK-UNSAFE: # %bb.0: # %entry -; CHECK-UNSAFE-NEXT: std 3, -8(1) -; CHECK-UNSAFE-NEXT: lfd 0, -8(1) -; CHECK-UNSAFE-NEXT: xscvsxddp 0, 0 -; CHECK-UNSAFE-NEXT: frsp 1, 0 -; CHECK-UNSAFE-NEXT: blr entry: %conv = sitofp i64 %x to float ret float %conv } - +; TODO: Add sitofp afn test. diff --git a/llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll b/llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll index 9e3eea1..a6f5c61 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll @@ -25,7 +25,7 @@ define dso_local zeroext i32 @testI8(i8 zeroext %val) local_unnamed_addr #0 { ; PWR7-NEXT: andc 8, 7, 3 ; PWR7-NEXT: or 8, 6, 8 ; PWR7-NEXT: stwcx. 8, 0, 5 -; PWR7-NEXT: bne 0, .LBB0_1 +; PWR7-NEXT: bne- 0, .LBB0_1 ; PWR7-NEXT: # %bb.2: # %entry ; PWR7-NEXT: srw 3, 7, 4 ; PWR7-NEXT: addis 4, 2, global_int@toc@ha @@ -44,7 +44,7 @@ define dso_local zeroext i32 @testI8(i8 zeroext %val) local_unnamed_addr #0 { ; PWR9-NEXT: # ; PWR9-NEXT: lbarx 4, 0, 5 ; PWR9-NEXT: stbcx. 3, 0, 5 -; PWR9-NEXT: bne 0, .LBB0_1 +; PWR9-NEXT: bne- 0, .LBB0_1 ; PWR9-NEXT: # %bb.2: # %entry ; PWR9-NEXT: addis 3, 2, global_int@toc@ha ; PWR9-NEXT: lwsync @@ -78,7 +78,7 @@ define dso_local zeroext i32 @testI16(i16 zeroext %val) local_unnamed_addr #0 { ; PWR7-NEXT: andc 8, 7, 3 ; PWR7-NEXT: or 8, 6, 8 ; PWR7-NEXT: stwcx. 8, 0, 5 -; PWR7-NEXT: bne 0, .LBB1_1 +; PWR7-NEXT: bne- 0, .LBB1_1 ; PWR7-NEXT: # %bb.2: # %entry ; PWR7-NEXT: srw 3, 7, 4 ; PWR7-NEXT: addis 4, 2, global_int@toc@ha @@ -97,7 +97,7 @@ define dso_local zeroext i32 @testI16(i16 zeroext %val) local_unnamed_addr #0 { ; PWR9-NEXT: # ; PWR9-NEXT: lharx 4, 0, 5 ; PWR9-NEXT: sthcx. 3, 0, 5 -; PWR9-NEXT: bne 0, .LBB1_1 +; PWR9-NEXT: bne- 0, .LBB1_1 ; PWR9-NEXT: # %bb.2: # %entry ; PWR9-NEXT: addis 3, 2, global_int@toc@ha ; PWR9-NEXT: lwsync diff --git a/llvm/test/CodeGen/PowerPC/pr61882.ll b/llvm/test/CodeGen/PowerPC/pr61882.ll index c649fe0..062d97c 100644 --- a/llvm/test/CodeGen/PowerPC/pr61882.ll +++ b/llvm/test/CodeGen/PowerPC/pr61882.ll @@ -27,7 +27,7 @@ define void @foo(ptr %a, i32 %x) { ; CHECK-NEXT: andc r8, r8, r6 ; CHECK-NEXT: or r8, r7, r8 ; CHECK-NEXT: stwcx. r8, 0, r3 -; CHECK-NEXT: bne cr0, .LBB0_1 +; CHECK-NEXT: bne- cr0, .LBB0_1 ; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -43,7 +43,7 @@ define void @foo(ptr %a, i32 %x) { ; PWR8-NEXT: bgt cr0, .LBB0_3 ; PWR8-NEXT: # %bb.2: ; PWR8-NEXT: stbcx. r4, 0, r3 -; PWR8-NEXT: bne cr0, .LBB0_1 +; PWR8-NEXT: bne- cr0, .LBB0_1 ; PWR8-NEXT: .LBB0_3: ; PWR8-NEXT: lwsync ; PWR8-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll b/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll index 2be370f..af48bf2 100644 --- a/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll +++ b/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll @@ -5,9 +5,6 @@ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s \ -; RUN: --enable-unsafe-fp-math | FileCheck %s --check-prefix=FAST define dso_local i64 @test_lrint(double %d) local_unnamed_addr { ; BE-LABEL: test_lrint: ; BE: # %bb.0: # %entry @@ -36,17 +33,36 @@ define dso_local i64 @test_lrint(double %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_lrint: -; FAST: # %bb.0: # %entry -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.lrint.i64.f64(double %d) ret i64 %0 } +define dso_local i64 @test_constrained_lrint(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_lrint: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl lrint +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_lrint: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fctid f0, f1 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.lrint(double %d, metadata !"round.dynamic", metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.lrint.i64.f64(double) define dso_local i64 @test_lrintf(float %f) local_unnamed_addr { @@ -77,17 +93,36 @@ define dso_local i64 @test_lrintf(float %f) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_lrintf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.lrint.i64.f32(float %f) ret i64 %0 } +define dso_local i64 @test_constrained_lrintf(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_lrintf: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl lrintf +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_lrintf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fctid f0, f1 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.lrint(float %f, metadata !"round.dynamic", metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.lrint.i64.f32(float) define dso_local i64 @test_llrint(double %d) local_unnamed_addr { @@ -118,17 +153,36 @@ define dso_local i64 @test_llrint(double %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_llrint: -; FAST: # %bb.0: # %entry -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.llrint.i64.f64(double %d) ret i64 %0 } +define dso_local i64 @test_constrained_llrint(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_llrint: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl llrint +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_llrint: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fctid f0, f1 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.llrint(double %d, metadata !"round.dynamic", metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.llrint.i64.f64(double) define dso_local i64 @test_llrintf(float %f) local_unnamed_addr { @@ -159,17 +213,36 @@ define dso_local i64 @test_llrintf(float %f) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_llrintf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.llrint.i64.f32(float %f) ret i64 %0 } +define dso_local i64 @test_constrained_llrintf(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_llrintf: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl llrintf +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_llrintf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fctid f0, f1 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.llrint(float %f, metadata !"round.dynamic", metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.llrint.i64.f32(float) define dso_local i64 @test_lround(double %d) local_unnamed_addr { @@ -200,18 +273,37 @@ define dso_local i64 @test_lround(double %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_lround: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f0, f1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.lround.i64.f64(double %d) ret i64 %0 } +define dso_local i64 @test_constrained_lround(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_lround: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl lround +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_lround: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f0, f1 +; CHECK-NEXT: fctid f0, f0 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.lround(double %d, metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.lround.i64.f64(double) define dso_local i32 @test_lroundi32f64(double %d) local_unnamed_addr { @@ -242,18 +334,37 @@ define dso_local i32 @test_lroundi32f64(double %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_lroundi32f64: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f0, f1 -; FAST-NEXT: fctiw f0, f0 -; FAST-NEXT: mffprwz r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i32 @llvm.lround.i32.f64(double %d) ret i32 %0 } +define dso_local i32 @test_constrained_lroundi32f64(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_lroundi32f64: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl lround +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_lroundi32f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f0, f1 +; CHECK-NEXT: fctiw f0, f0 +; CHECK-NEXT: mffprwz r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i32 @llvm.experimental.constrained.lround(double %d, metadata !"fpexcept.ignore") + ret i32 %0 +} + declare i32 @llvm.lround.i32.f64(double) define dso_local i64 @test_lroundf(float %f) local_unnamed_addr { @@ -284,18 +395,37 @@ define dso_local i64 @test_lroundf(float %f) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_lroundf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f0, f1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.lround.i64.f32(float %f) ret i64 %0 } +define dso_local i64 @test_constrained_lroundf(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_lroundf: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl lroundf +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_lroundf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f0, f1 +; CHECK-NEXT: fctid f0, f0 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.lround(float %f, metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.lround.i64.f32(float) define dso_local i32 @test_lroundi32f32(float %d) local_unnamed_addr { @@ -326,18 +456,37 @@ define dso_local i32 @test_lroundi32f32(float %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_lroundi32f32: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f0, f1 -; FAST-NEXT: fctiw f0, f0 -; FAST-NEXT: mffprwz r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i32 @llvm.lround.i32.f32(float %d) ret i32 %0 } +define dso_local i32 @test_constrained_lroundi32f32(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_lroundi32f32: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl lroundf +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_lroundi32f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f0, f1 +; CHECK-NEXT: fctiw f0, f0 +; CHECK-NEXT: mffprwz r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i32 @llvm.experimental.constrained.lround(float %f, metadata !"fpexcept.ignore") + ret i32 %0 +} + declare i32 @llvm.lround.i32.f32(float) define dso_local i64 @test_llround(double %d) local_unnamed_addr { @@ -368,18 +517,37 @@ define dso_local i64 @test_llround(double %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_llround: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f0, f1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.llround.i64.f64(double %d) ret i64 %0 } +define dso_local i64 @test_constrained_llround(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_llround: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl llround +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_llround: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f0, f1 +; CHECK-NEXT: fctid f0, f0 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.llround(double %d, metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.llround.i64.f64(double) define dso_local i64 @test_llroundf(float %f) local_unnamed_addr { @@ -410,18 +578,37 @@ define dso_local i64 @test_llroundf(float %f) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_llroundf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f0, f1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr entry: %0 = tail call i64 @llvm.llround.i64.f32(float %f) ret i64 %0 } +define dso_local i64 @test_constrained_llroundf(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_llroundf: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl llroundf +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_llroundf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f0, f1 +; CHECK-NEXT: fctid f0, f0 +; CHECK-NEXT: mffprd r3, f0 +; CHECK-NEXT: blr +entry: + %0 = tail call i64 @llvm.experimental.constrained.llround(float %f, metadata !"fpexcept.ignore") + ret i64 %0 +} + declare i64 @llvm.llround.i64.f32(float) define dso_local double @test_nearbyint(double %d) local_unnamed_addr { @@ -452,16 +639,26 @@ define dso_local double @test_nearbyint(double %d) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_nearbyint: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpic f1, f1 -; FAST-NEXT: blr entry: %0 = tail call double @llvm.nearbyint.f64(double %d) ret double %0 } +define dso_local double @test_constrained_nearbyint(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_nearbyint: +; BE: # %bb.0: # %entry +; BE-NEXT: xsrdpic f1, f1 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_nearbyint: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpic f1, f1 +; CHECK-NEXT: blr +entry: + %0 = tail call double @llvm.experimental.constrained.nearbyint(double %d, metadata !"round.dynamic", metadata !"fpexcept.ignore") + ret double %0 +} + declare double @llvm.nearbyint.f64(double) define dso_local float @test_nearbyintf(float %f) local_unnamed_addr { @@ -492,16 +689,26 @@ define dso_local float @test_nearbyintf(float %f) local_unnamed_addr { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_nearbyintf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpic f1, f1 -; FAST-NEXT: blr entry: %0 = tail call float @llvm.nearbyint.f32(float %f) ret float %0 } +define dso_local float @test_constrained_nearbyintf(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_nearbyintf: +; BE: # %bb.0: # %entry +; BE-NEXT: xsrdpic f1, f1 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_nearbyintf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpic f1, f1 +; CHECK-NEXT: blr +entry: + %0 = tail call float @llvm.experimental.constrained.nearbyint(float %f, metadata !"round.dynamic", metadata !"fpexcept.ignore") + ret float %0 +} + declare float @llvm.nearbyint.f32(float) define dso_local double @test_round(double %d) local_unnamed_addr { @@ -514,16 +721,26 @@ define dso_local double @test_round(double %d) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpi f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_round: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f1, f1 -; FAST-NEXT: blr entry: %0 = tail call double @llvm.round.f64(double %d) ret double %0 } +define dso_local double @test_constrained_round(double %d) local_unnamed_addr { +; BE-LABEL: test_constrained_round: +; BE: # %bb.0: # %entry +; BE-NEXT: xsrdpi f1, f1 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_round: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f1, f1 +; CHECK-NEXT: blr +entry: + %0 = tail call double @llvm.experimental.constrained.round(double %d, metadata !"fpexcept.ignore") + ret double %0 +} + declare double @llvm.round.f64(double) define dso_local float @test_roundf(float %f) local_unnamed_addr { @@ -536,16 +753,26 @@ define dso_local float @test_roundf(float %f) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpi f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_roundf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpi f1, f1 -; FAST-NEXT: blr entry: %0 = tail call float @llvm.round.f32(float %f) ret float %0 } +define dso_local float @test_constrained_roundf(float %f) local_unnamed_addr { +; BE-LABEL: test_constrained_roundf: +; BE: # %bb.0: # %entry +; BE-NEXT: xsrdpi f1, f1 +; BE-NEXT: blr +; +; CHECK-LABEL: test_constrained_roundf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsrdpi f1, f1 +; CHECK-NEXT: blr +entry: + %0 = tail call float @llvm.experimental.constrained.round(float %f, metadata !"fpexcept.ignore") + ret float %0 +} + declare float @llvm.round.f32(float) define dso_local double @test_trunc(double %d) local_unnamed_addr { @@ -558,11 +785,6 @@ define dso_local double @test_trunc(double %d) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpiz f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_trunc: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpiz f1, f1 -; FAST-NEXT: blr entry: %0 = tail call double @llvm.trunc.f64(double %d) ret double %0 @@ -580,11 +802,6 @@ define dso_local float @test_truncf(float %f) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpiz f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_truncf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpiz f1, f1 -; FAST-NEXT: blr entry: %0 = tail call float @llvm.trunc.f32(float %f) ret float %0 @@ -602,11 +819,6 @@ define dso_local double @test_floor(double %d) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpim f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_floor: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpim f1, f1 -; FAST-NEXT: blr entry: %0 = tail call double @llvm.floor.f64(double %d) ret double %0 @@ -624,11 +836,6 @@ define dso_local float @test_floorf(float %f) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpim f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_floorf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpim f1, f1 -; FAST-NEXT: blr entry: %0 = tail call float @llvm.floor.f32(float %f) ret float %0 @@ -646,11 +853,6 @@ define dso_local double @test_ceil(double %d) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpip f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_ceil: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpip f1, f1 -; FAST-NEXT: blr entry: %0 = tail call double @llvm.ceil.f64(double %d) ret double %0 @@ -668,11 +870,6 @@ define dso_local float @test_ceilf(float %f) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpip f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_ceilf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpip f1, f1 -; FAST-NEXT: blr entry: %0 = tail call float @llvm.ceil.f32(float %f) ret float %0 @@ -690,11 +887,6 @@ define dso_local double @test_rint(double %d) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpic f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_rint: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpic f1, f1 -; FAST-NEXT: blr entry: %0 = tail call double @llvm.rint.f64(double %d) ret double %0 @@ -712,11 +904,6 @@ define dso_local float @test_rintf(float %f) local_unnamed_addr { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xsrdpic f1, f1 ; CHECK-NEXT: blr -; -; FAST-LABEL: test_rintf: -; FAST: # %bb.0: # %entry -; FAST-NEXT: xsrdpic f1, f1 -; FAST-NEXT: blr entry: %0 = tail call float @llvm.rint.f32(float %f) ret float %0 diff --git a/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll b/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll index 128d546..da4c192 100644 --- a/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll +++ b/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll @@ -16,7 +16,7 @@ define i16 @SEXTParam(i16 signext %0) #0 { ; CHECK-NEXT: # %bb.2: # %top ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 3, 0, 4 -; CHECK-NEXT: bne 0, .LBB0_1 +; CHECK-NEXT: bne- 0, .LBB0_1 ; CHECK-NEXT: .LBB0_3: # %top ; CHECK-NEXT: lwsync ; CHECK-NEXT: lhz 3, -4(1) @@ -49,7 +49,7 @@ define i16 @noSEXTParam(i16 %0) #0 { ; CHECK-NEXT: # %bb.2: # %top ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 3, 0, 4 -; CHECK-NEXT: bne 0, .LBB1_1 +; CHECK-NEXT: bne- 0, .LBB1_1 ; CHECK-NEXT: .LBB1_3: # %top ; CHECK-NEXT: lwsync ; CHECK-NEXT: lhz 3, -4(1) @@ -82,7 +82,7 @@ define i16 @noSEXTLoad(ptr %p) #0 { ; CHECK-NEXT: # %bb.2: # %top ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 3, 0, 4 -; CHECK-NEXT: bne 0, .LBB2_1 +; CHECK-NEXT: bne- 0, .LBB2_1 ; CHECK-NEXT: .LBB2_3: # %top ; CHECK-NEXT: lwsync ; CHECK-NEXT: lhz 3, -4(1) diff --git a/llvm/test/CodeGen/PowerPC/vector-llrint.ll b/llvm/test/CodeGen/PowerPC/vector-llrint.ll index 8a9e48e..d2fb6ca 100644 --- a/llvm/test/CodeGen/PowerPC/vector-llrint.ll +++ b/llvm/test/CodeGen/PowerPC/vector-llrint.ll @@ -9,9 +9,6 @@ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s \ -; RUN: --enable-unsafe-fp-math | FileCheck %s --check-prefix=FAST define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind { ; BE-LABEL: llrint_v1i64_v1f16: @@ -47,23 +44,6 @@ define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v1i64_v1f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -32(r1) -; FAST-NEXT: std r0, 48(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: addi r1, r1, 32 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x) ret <1 x i64> %a } @@ -147,41 +127,6 @@ define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v1i64_v2f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -48(r1) -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: fmr f1, f2 -; FAST-NEXT: std r0, 64(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: fmr f1, f31 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: fctid f1, f30 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs1, vs0 -; FAST-NEXT: addi r1, r1, 48 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x) ret <2 x i64> %a } @@ -341,68 +286,6 @@ define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v4i64_v4f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -64(r1) -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f4 -; FAST-NEXT: std r0, 80(r1) -; FAST-NEXT: fmr f31, f3 -; FAST-NEXT: fmr f30, f2 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: fmr f1, f31 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: fmr f1, f30 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: fmr f1, f29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f30 -; FAST-NEXT: fctid f2, f31 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f0, f28 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v3, vs0, vs2 -; FAST-NEXT: addi r1, r1, 64 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload -; FAST-NEXT: blr %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x) ret <4 x i64> %a } @@ -714,122 +597,6 @@ define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v8i64_v8f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f24, -64(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f25, -56(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -96(r1) -; FAST-NEXT: fmr f24, f1 -; FAST-NEXT: fmr f1, f8 -; FAST-NEXT: std r0, 112(r1) -; FAST-NEXT: fmr f30, f7 -; FAST-NEXT: fmr f29, f6 -; FAST-NEXT: fmr f28, f5 -; FAST-NEXT: fmr f27, f4 -; FAST-NEXT: fmr f26, f3 -; FAST-NEXT: fmr f25, f2 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: fmr f1, f30 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: fmr f1, f29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f28 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: fmr f1, f27 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f27, f1 -; FAST-NEXT: fmr f1, f26 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f26, f1 -; FAST-NEXT: fmr f1, f25 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f25, f1 -; FAST-NEXT: fmr f1, f24 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f25 -; FAST-NEXT: fctid f2, f26 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: fctid f3, f27 -; FAST-NEXT: fctid f4, f28 -; FAST-NEXT: fctid f5, f29 -; FAST-NEXT: fctid f6, f30 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: mffprd r3, f3 -; FAST-NEXT: mtfprd f3, r3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: mtfprd f4, r3 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v3, vs3, vs2 -; FAST-NEXT: xxmrghd v4, vs5, vs4 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f0, f31 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v5, vs0, vs6 -; FAST-NEXT: addi r1, r1, 96 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f25, -56(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f24, -64(r1) # 8-byte Folded Reload -; FAST-NEXT: blr %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x) ret <8 x i64> %a } @@ -1439,228 +1206,6 @@ define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v16i64_v16f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f16, -128(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f17, -120(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f18, -112(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f19, -104(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f20, -96(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f21, -88(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f22, -80(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f23, -72(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f24, -64(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f25, -56(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -160(r1) -; FAST-NEXT: fmr f26, f1 -; FAST-NEXT: lfs f1, 312(r1) -; FAST-NEXT: std r0, 176(r1) -; FAST-NEXT: fmr f28, f13 -; FAST-NEXT: fmr f27, f12 -; FAST-NEXT: fmr f24, f11 -; FAST-NEXT: fmr f21, f10 -; FAST-NEXT: fmr f19, f9 -; FAST-NEXT: fmr f18, f8 -; FAST-NEXT: fmr f17, f7 -; FAST-NEXT: fmr f16, f6 -; FAST-NEXT: fmr f20, f5 -; FAST-NEXT: fmr f22, f4 -; FAST-NEXT: fmr f23, f3 -; FAST-NEXT: fmr f25, f2 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: lfs f1, 304(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: lfs f1, 296(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f28 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: fmr f1, f27 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f27, f1 -; FAST-NEXT: fmr f1, f24 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f24, f1 -; FAST-NEXT: fmr f1, f21 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f21, f1 -; FAST-NEXT: fmr f1, f19 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f19, f1 -; FAST-NEXT: fmr f1, f18 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f18, f1 -; FAST-NEXT: fmr f1, f17 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f17, f1 -; FAST-NEXT: fmr f1, f16 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f16, f1 -; FAST-NEXT: fmr f1, f20 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f20, f1 -; FAST-NEXT: fmr f1, f22 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f22, f1 -; FAST-NEXT: fmr f1, f23 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f23, f1 -; FAST-NEXT: fmr f1, f25 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f25, f1 -; FAST-NEXT: fmr f1, f26 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f25 -; FAST-NEXT: fctid f2, f23 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: fctid f3, f22 -; FAST-NEXT: fctid f4, f20 -; FAST-NEXT: fctid f5, f16 -; FAST-NEXT: fctid f6, f17 -; FAST-NEXT: fctid f7, f18 -; FAST-NEXT: fctid f8, f19 -; FAST-NEXT: fctid f9, f21 -; FAST-NEXT: fctid f10, f24 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: mffprd r3, f3 -; FAST-NEXT: mtfprd f3, r3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: mtfprd f4, r3 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f7 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: mffprd r3, f8 -; FAST-NEXT: mtfprd f8, r3 -; FAST-NEXT: mffprd r3, f9 -; FAST-NEXT: mtfprd f9, r3 -; FAST-NEXT: mffprd r3, f10 -; FAST-NEXT: mtfprd f10, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v3, vs3, vs2 -; FAST-NEXT: xxmrghd v4, vs5, vs4 -; FAST-NEXT: xxmrghd v5, vs7, vs6 -; FAST-NEXT: xxmrghd v6, vs9, vs8 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f0, f27 -; FAST-NEXT: fctid f1, f29 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v7, vs0, vs10 -; FAST-NEXT: fctid f0, f28 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v8, vs1, vs0 -; FAST-NEXT: fctid f0, f30 -; FAST-NEXT: fctid f1, f31 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v9, vs1, vs0 -; FAST-NEXT: addi r1, r1, 160 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f25, -56(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f24, -64(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f23, -72(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f22, -80(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f21, -88(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f20, -96(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f19, -104(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f18, -112(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f17, -120(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f16, -128(r1) # 8-byte Folded Reload -; FAST-NEXT: blr %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x) ret <16 x i64> %a } @@ -2839,523 +2384,6 @@ define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v32i64_v32f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -480(r1) -; FAST-NEXT: li r4, 128 -; FAST-NEXT: std r0, 496(r1) -; FAST-NEXT: std r30, 320(r1) # 8-byte Folded Spill -; FAST-NEXT: mr r30, r3 -; FAST-NEXT: stfd f14, 336(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f15, 344(r1) # 8-byte Folded Spill -; FAST-NEXT: fmr f14, f5 -; FAST-NEXT: stfd f16, 352(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 144 -; FAST-NEXT: fmr f16, f4 -; FAST-NEXT: stfd f17, 360(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f18, 368(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f19, 376(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f20, 384(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f21, 392(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 160 -; FAST-NEXT: stfd f22, 400(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f23, 408(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f24, 416(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f25, 424(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f26, 432(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f27, 440(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 176 -; FAST-NEXT: xxlor v22, f3, f3 -; FAST-NEXT: stfd f28, 448(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, 456(r1) # 8-byte Folded Spill -; FAST-NEXT: fmr f29, f9 -; FAST-NEXT: stfd f30, 464(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, 472(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 192 -; FAST-NEXT: xxlor v23, f2, f2 -; FAST-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 208 -; FAST-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 224 -; FAST-NEXT: xxlor v25, f13, f13 -; FAST-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 240 -; FAST-NEXT: xxlor v26, f12, f12 -; FAST-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 256 -; FAST-NEXT: xxlor v27, f11, f11 -; FAST-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 272 -; FAST-NEXT: xxlor v28, f10, f10 -; FAST-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 288 -; FAST-NEXT: xxlor v29, f8, f8 -; FAST-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 304 -; FAST-NEXT: xxlor v30, f7, f7 -; FAST-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 44 -; FAST-NEXT: xxlor v31, f6, f6 -; FAST-NEXT: stxsspx f1, r1, r4 # 4-byte Folded Spill -; FAST-NEXT: lfs f1, 768(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 120 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 760(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 112 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 752(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 104 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 744(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 96 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 736(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 88 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 728(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 80 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 720(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 72 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 712(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 704(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 56 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 696(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 48 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 688(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: xxlor v21, f1, f1 -; FAST-NEXT: lfs f1, 680(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: xxlor v20, f1, f1 -; FAST-NEXT: lfs f1, 672(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: xxlor v24, f1, f1 -; FAST-NEXT: lfs f1, 664(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: lfs f1, 656(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: lfs f1, 648(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: lfs f1, 640(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f27, f1 -; FAST-NEXT: lfs f1, 632(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f26, f1 -; FAST-NEXT: lfs f1, 624(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f25, f1 -; FAST-NEXT: xxlor f1, v25, v25 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f24, f1 -; FAST-NEXT: xxlor f1, v26, v26 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f23, f1 -; FAST-NEXT: xxlor f1, v27, v27 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f22, f1 -; FAST-NEXT: xxlor f1, v28, v28 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f21, f1 -; FAST-NEXT: fmr f1, f29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f20, f1 -; FAST-NEXT: xxlor f1, v29, v29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f19, f1 -; FAST-NEXT: xxlor f1, v30, v30 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f18, f1 -; FAST-NEXT: xxlor f1, v31, v31 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f14 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f14, f1 -; FAST-NEXT: fmr f1, f16 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f16, f1 -; FAST-NEXT: xxlor f1, v22, v22 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f17, f1 -; FAST-NEXT: xxlor f1, v23, v23 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 44 -; FAST-NEXT: fmr f15, f1 -; FAST-NEXT: lxsspx f1, r1, r3 # 4-byte Folded Reload -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f3, f15 -; FAST-NEXT: fctid f4, f17 -; FAST-NEXT: mffprd r3, f3 -; FAST-NEXT: fctid f5, f16 -; FAST-NEXT: fctid f6, f14 -; FAST-NEXT: fctid f7, f18 -; FAST-NEXT: fctid f8, f19 -; FAST-NEXT: fctid f13, f1 -; FAST-NEXT: fctid f9, f20 -; FAST-NEXT: fctid f10, f22 -; FAST-NEXT: fctid f11, f24 -; FAST-NEXT: fctid f12, f25 -; FAST-NEXT: fctid f2, f23 -; FAST-NEXT: fctid f0, f21 -; FAST-NEXT: mtvsrd v2, r3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: mtvsrd v3, r3 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: mffprd r3, f7 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f8 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: mffprd r3, f9 -; FAST-NEXT: mtfprd f3, r3 -; FAST-NEXT: mffprd r3, f10 -; FAST-NEXT: mtfprd f4, r3 -; FAST-NEXT: mffprd r3, f11 -; FAST-NEXT: fctid f11, f31 -; FAST-NEXT: lfd f31, 56(r1) # 8-byte Folded Reload -; FAST-NEXT: mtfprd f8, r3 -; FAST-NEXT: mffprd r3, f12 -; FAST-NEXT: xxlor f12, v24, v24 -; FAST-NEXT: fctid f31, f31 -; FAST-NEXT: fctid f12, f12 -; FAST-NEXT: mtfprd f9, r3 -; FAST-NEXT: mffprd r3, f13 -; FAST-NEXT: lfd f13, 48(r1) # 8-byte Folded Reload -; FAST-NEXT: mtfprd f10, r3 -; FAST-NEXT: fctid f13, f13 -; FAST-NEXT: xxmrghd v3, vs5, v3 -; FAST-NEXT: fctid f5, f26 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: xxmrghd v4, vs7, vs6 -; FAST-NEXT: fctid f6, f27 -; FAST-NEXT: fctid f7, f28 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: lfd f28, 96(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f7 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: xxmrghd v2, v2, vs10 -; FAST-NEXT: fctid f10, f30 -; FAST-NEXT: mffprd r3, f10 -; FAST-NEXT: lfd f30, 80(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f30, f30 -; FAST-NEXT: mtfprd f10, r3 -; FAST-NEXT: mffprd r3, f11 -; FAST-NEXT: mtfprd f11, r3 -; FAST-NEXT: mffprd r3, f12 -; FAST-NEXT: mtfprd f12, r3 -; FAST-NEXT: xxmrghd v5, vs12, vs11 -; FAST-NEXT: xxlor f11, v20, v20 -; FAST-NEXT: xxlor f12, v21, v21 -; FAST-NEXT: fctid f11, f11 -; FAST-NEXT: fctid f12, f12 -; FAST-NEXT: mffprd r3, f11 -; FAST-NEXT: mtfprd f11, r3 -; FAST-NEXT: mffprd r3, f12 -; FAST-NEXT: mtfprd f12, r3 -; FAST-NEXT: mffprd r3, f13 -; FAST-NEXT: mtfprd f13, r3 -; FAST-NEXT: mffprd r3, f31 -; FAST-NEXT: lfd f31, 64(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f31, f31 -; FAST-NEXT: mtvsrd v0, r3 -; FAST-NEXT: mffprd r3, f31 -; FAST-NEXT: lfd f31, 72(r1) # 8-byte Folded Reload -; FAST-NEXT: mtvsrd v1, r3 -; FAST-NEXT: mffprd r3, f30 -; FAST-NEXT: lfd f30, 88(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f31, f31 -; FAST-NEXT: mtvsrd v6, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: lfd f28, 104(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f30, f30 -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: mtvsrd v7, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: lfd f28, 112(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: mtvsrd v8, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: lfd f28, 120(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: xxmrghd v10, vs12, vs11 -; FAST-NEXT: xxmrghd v0, v0, vs13 -; FAST-NEXT: xxswapd vs12, v0 -; FAST-NEXT: xxmrghd v0, vs9, vs8 -; FAST-NEXT: xxmrghd v7, v8, v7 -; FAST-NEXT: mtvsrd v8, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: mtvsrd v9, r3 -; FAST-NEXT: mffprd r3, f30 -; FAST-NEXT: xxswapd v7, v7 -; FAST-NEXT: xxmrghd v8, v9, v8 -; FAST-NEXT: mtvsrd v9, r3 -; FAST-NEXT: mffprd r3, f31 -; FAST-NEXT: xxswapd v8, v8 -; FAST-NEXT: xxmrghd v6, v9, v6 -; FAST-NEXT: mtvsrd v9, r3 -; FAST-NEXT: li r3, 240 -; FAST-NEXT: stxvd2x v8, r30, r3 -; FAST-NEXT: li r3, 224 -; FAST-NEXT: stxvd2x v7, r30, r3 -; FAST-NEXT: li r3, 208 -; FAST-NEXT: xxswapd vs11, v6 -; FAST-NEXT: xxmrghd v6, vs10, vs7 -; FAST-NEXT: stxvd2x vs11, r30, r3 -; FAST-NEXT: li r3, 192 -; FAST-NEXT: xxmrghd v1, v9, v1 -; FAST-NEXT: xxswapd vs11, v1 -; FAST-NEXT: xxmrghd v1, vs6, vs5 -; FAST-NEXT: xxswapd vs5, v10 -; FAST-NEXT: xxswapd vs6, v5 -; FAST-NEXT: stxvd2x vs11, r30, r3 -; FAST-NEXT: li r3, 176 -; FAST-NEXT: stxvd2x vs12, r30, r3 -; FAST-NEXT: li r3, 160 -; FAST-NEXT: stxvd2x vs5, r30, r3 -; FAST-NEXT: li r3, 144 -; FAST-NEXT: stxvd2x vs6, r30, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: li r3, 128 -; FAST-NEXT: xxswapd vs5, v6 -; FAST-NEXT: stxvd2x vs5, r30, r3 -; FAST-NEXT: li r3, 112 -; FAST-NEXT: xxswapd vs2, v1 -; FAST-NEXT: xxswapd vs6, v0 -; FAST-NEXT: stxvd2x vs2, r30, r3 -; FAST-NEXT: li r3, 96 -; FAST-NEXT: fctid f2, f29 -; FAST-NEXT: stxvd2x vs6, r30, r3 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: li r3, 80 -; FAST-NEXT: xxmrghd v5, vs7, vs4 -; FAST-NEXT: xxswapd vs4, v2 -; FAST-NEXT: xxmrghd v0, vs0, vs3 -; FAST-NEXT: xxswapd vs0, v5 -; FAST-NEXT: xxswapd vs3, v3 -; FAST-NEXT: stxvd2x vs0, r30, r3 -; FAST-NEXT: li r3, 64 -; FAST-NEXT: xxswapd vs0, v0 -; FAST-NEXT: stxvd2x vs0, r30, r3 -; FAST-NEXT: li r3, 48 -; FAST-NEXT: xxmrghd v5, vs2, vs1 -; FAST-NEXT: xxswapd vs1, v4 -; FAST-NEXT: stxvd2x vs1, r30, r3 -; FAST-NEXT: li r3, 32 -; FAST-NEXT: xxswapd vs2, v5 -; FAST-NEXT: stxvd2x vs2, r30, r3 -; FAST-NEXT: li r3, 16 -; FAST-NEXT: stxvd2x vs3, r30, r3 -; FAST-NEXT: li r3, 304 -; FAST-NEXT: stxvd2x vs4, 0, r30 -; FAST-NEXT: lfd f31, 472(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, 464(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f29, 456(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, 448(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f27, 440(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f26, 432(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f25, 424(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f24, 416(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f23, 408(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f22, 400(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f21, 392(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f20, 384(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f19, 376(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f18, 368(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f17, 360(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f16, 352(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f15, 344(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f14, 336(r1) # 8-byte Folded Reload -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 288 -; FAST-NEXT: ld r30, 320(r1) # 8-byte Folded Reload -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 272 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 256 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 240 -; FAST-NEXT: lxvd2x v27, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 224 -; FAST-NEXT: lxvd2x v26, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 208 -; FAST-NEXT: lxvd2x v25, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 192 -; FAST-NEXT: lxvd2x v24, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 176 -; FAST-NEXT: lxvd2x v23, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 160 -; FAST-NEXT: lxvd2x v22, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 144 -; FAST-NEXT: lxvd2x v21, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 128 -; FAST-NEXT: lxvd2x v20, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 480 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x) ret <32 x i64> %a } @@ -3385,12 +2413,6 @@ define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v1i64_v1f32: -; FAST: # %bb.0: -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x) ret <1 x i64> %a } @@ -3444,21 +2466,6 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v2i64_v2f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xscvspdpn f1, vs1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs1, vs0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x) ret <2 x i64> %a } @@ -3537,32 +2544,6 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v4i64_v4f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xxsldwi vs2, v2, v2, 1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v4, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v2 -; FAST-NEXT: vmr v2, v4 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs2 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v3, vs1, vs0 -; FAST-NEXT: blr %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x) ret <4 x i64> %a } @@ -3695,54 +2676,6 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v8i64_v8f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xxsldwi vs2, v2, v2, 1 -; FAST-NEXT: xxsldwi vs3, v3, v3, 3 -; FAST-NEXT: xxswapd vs4, v3 -; FAST-NEXT: xxsldwi vs5, v3, v3, 1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v0, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v2 -; FAST-NEXT: vmr v2, v0 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs2 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v1, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, vs3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs4 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v4, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v3 -; FAST-NEXT: vmr v3, v1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs5 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v5, vs1, vs0 -; FAST-NEXT: blr %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x) ret <8 x i64> %a } @@ -3983,98 +2916,6 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v16i64_v16f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xxsldwi vs2, v2, v2, 1 -; FAST-NEXT: xxsldwi vs3, v3, v3, 3 -; FAST-NEXT: xxswapd vs4, v3 -; FAST-NEXT: xxsldwi vs5, v3, v3, 1 -; FAST-NEXT: xxsldwi vs6, v4, v4, 3 -; FAST-NEXT: xxswapd vs7, v4 -; FAST-NEXT: xxsldwi vs8, v4, v4, 1 -; FAST-NEXT: xxsldwi vs9, v5, v5, 3 -; FAST-NEXT: xxswapd vs10, v5 -; FAST-NEXT: xxsldwi vs11, v5, v5, 1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v0, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v2 -; FAST-NEXT: vmr v2, v0 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs2 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v1, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, vs3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs4 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v10, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v3 -; FAST-NEXT: vmr v3, v1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs5 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v11, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, vs6 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs7 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v6, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v4 -; FAST-NEXT: xscvspdpn f1, vs8 -; FAST-NEXT: vmr v4, v10 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v7, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, vs9 -; FAST-NEXT: xscvspdpn f1, vs10 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v8, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, v5 -; FAST-NEXT: xscvspdpn f1, vs11 -; FAST-NEXT: vmr v5, v11 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v9, vs0, vs1 -; FAST-NEXT: blr %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x) ret <16 x i64> %a } @@ -4104,12 +2945,6 @@ define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v1i64_v1f64: -; FAST: # %bb.0: -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x) ret <1 x i64> %a } @@ -4164,19 +2999,6 @@ define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v2i64_v2f64: -; FAST: # %bb.0: -; FAST-NEXT: xxlor f1, v2, v2 -; FAST-NEXT: xxswapd vs0, v2 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v2, vs1, vs0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x) ret <2 x i64> %a } @@ -4261,28 +3083,6 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v4i64_v4f64: -; FAST: # %bb.0: -; FAST-NEXT: xxswapd vs0, v2 -; FAST-NEXT: xxlor f2, v2, v2 -; FAST-NEXT: xxswapd vs1, v3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f2, f2 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r4, f0 -; FAST-NEXT: xxlor f0, v3, v3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mtfprd f2, r4 -; FAST-NEXT: mffprd r5, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs0, vs2 -; FAST-NEXT: mtfprd f0, r5 -; FAST-NEXT: xxmrghd v3, vs0, vs1 -; FAST-NEXT: blr %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x) ret <4 x i64> %a } @@ -4427,46 +3227,6 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v8i64_v8f64: -; FAST: # %bb.0: -; FAST-NEXT: xxswapd vs0, v2 -; FAST-NEXT: xxswapd vs1, v3 -; FAST-NEXT: xxlor f4, v2, v2 -; FAST-NEXT: xxswapd vs2, v4 -; FAST-NEXT: xxswapd vs3, v5 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f4, f4 -; FAST-NEXT: mffprd r4, f0 -; FAST-NEXT: xxlor f0, v3, v3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r5, f0 -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mtfprd f1, r4 -; FAST-NEXT: mffprd r6, f0 -; FAST-NEXT: xxlor f0, v4, v4 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mtfprd f4, r6 -; FAST-NEXT: mffprd r7, f0 -; FAST-NEXT: fctid f0, f2 -; FAST-NEXT: mtfprd f2, r5 -; FAST-NEXT: mtfprd f5, r7 -; FAST-NEXT: mffprd r8, f0 -; FAST-NEXT: xxlor f0, v5, v5 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mtfprd f6, r8 -; FAST-NEXT: mffprd r9, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v3, vs2, vs4 -; FAST-NEXT: xxmrghd v4, vs5, vs6 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f1, f3 -; FAST-NEXT: mtfprd f0, r9 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v5, vs0, vs1 -; FAST-NEXT: blr %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x) ret <8 x i64> %a } @@ -4496,18 +3256,6 @@ define <1 x i64> @llrint_v1i64_v1f128(<1 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v1i64_v1f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -32(r1) -; FAST-NEXT: std r0, 48(r1) -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: addi r1, r1, 32 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.llrint.v1i64.v1f128(<1 x fp128> %x) ret <1 x i64> %a } @@ -4565,33 +3313,6 @@ define <2 x i64> @llrint_v2i64_v2f128(<2 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v2i64_v2f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -80(r1) -; FAST-NEXT: li r3, 48 -; FAST-NEXT: std r0, 96(r1) -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: vmr v31, v3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: mtvsrd v30, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 48 -; FAST-NEXT: xxmrghd v2, vs0, v30 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 80 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128> %x) ret <2 x i64> %a } @@ -4689,53 +3410,6 @@ define <4 x i64> @llrint_v4i64_v4f128(<4 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v4i64_v4f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -112(r1) -; FAST-NEXT: li r3, 48 -; FAST-NEXT: std r0, 128(r1) -; FAST-NEXT: stxvd2x v28, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 80 -; FAST-NEXT: vmr v29, v3 -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 96 -; FAST-NEXT: vmr v30, v4 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: vmr v31, v5 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: mtvsrd v28, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v30 -; FAST-NEXT: xxmrghd v29, vs0, v28 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: mtvsrd v30, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 96 -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 80 -; FAST-NEXT: xxmrghd v3, vs0, v30 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 48 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 112 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128> %x) ret <4 x i64> %a } @@ -4913,93 +3587,6 @@ define <8 x i64> @llrint_v8i64_v8f128(<8 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: llrint_v8i64_v8f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -176(r1) -; FAST-NEXT: li r3, 48 -; FAST-NEXT: std r0, 192(r1) -; FAST-NEXT: stxvd2x v24, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v25, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 80 -; FAST-NEXT: vmr v25, v3 -; FAST-NEXT: stxvd2x v26, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 96 -; FAST-NEXT: vmr v26, v4 -; FAST-NEXT: stxvd2x v27, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 112 -; FAST-NEXT: vmr v27, v5 -; FAST-NEXT: stxvd2x v28, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 128 -; FAST-NEXT: vmr v28, v6 -; FAST-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 144 -; FAST-NEXT: vmr v29, v7 -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 160 -; FAST-NEXT: vmr v30, v8 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: vmr v31, v9 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v25 -; FAST-NEXT: mtvsrd v24, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v26 -; FAST-NEXT: xxmrghd v25, vs0, v24 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v27 -; FAST-NEXT: mtvsrd v26, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v28 -; FAST-NEXT: xxmrghd v27, vs0, v26 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: mtvsrd v28, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v30 -; FAST-NEXT: xxmrghd v29, vs0, v28 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: mtvsrd v30, r3 -; FAST-NEXT: bl llrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 160 -; FAST-NEXT: vmr v4, v29 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 144 -; FAST-NEXT: vmr v3, v27 -; FAST-NEXT: vmr v2, v25 -; FAST-NEXT: xxmrghd v5, vs0, v30 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 128 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 112 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 96 -; FAST-NEXT: lxvd2x v27, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 80 -; FAST-NEXT: lxvd2x v26, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v25, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 48 -; FAST-NEXT: lxvd2x v24, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 176 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128> %x) ret <8 x i64> %a } diff --git a/llvm/test/CodeGen/PowerPC/vector-lrint.ll b/llvm/test/CodeGen/PowerPC/vector-lrint.ll index f437536..af5704b 100644 --- a/llvm/test/CodeGen/PowerPC/vector-lrint.ll +++ b/llvm/test/CodeGen/PowerPC/vector-lrint.ll @@ -9,10 +9,6 @@ ; RUN: sed 's/iXLen/i32/g' %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i32/g' %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names \ -; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ -; RUN: -verify-machineinstrs --enable-unsafe-fp-math | \ -; RUN: FileCheck %s --check-prefixes=FAST ; FIXME: crash "Input type needs to be promoted!" ; SKIP: sed 's/iXLen/i64/g' %s | llc -ppc-asm-full-reg-names \ ; SKIP: -ppc-vsr-nums-as-vr -mtriple=powerpc-unknown-unknown \ @@ -23,10 +19,6 @@ ; RUN: sed 's/iXLen/i64/g' %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK -; RUN: sed 's/iXLen/i64/g' %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names \ -; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ -; RUN: -verify-machineinstrs --enable-unsafe-fp-math | \ -; RUN: FileCheck %s --check-prefixes=FAST define <1 x i64> @lrint_v1f16(<1 x half> %x) nounwind { ; BE-LABEL: lrint_v1f16: @@ -62,23 +54,6 @@ define <1 x i64> @lrint_v1f16(<1 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v1f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -32(r1) -; FAST-NEXT: std r0, 48(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: addi r1, r1, 32 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.lrint.v1i64.v1f16(<1 x half> %x) ret <1 x i64> %a } @@ -162,41 +137,6 @@ define <2 x i64> @lrint_v2f16(<2 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v2f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -48(r1) -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: fmr f1, f2 -; FAST-NEXT: std r0, 64(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: fmr f1, f31 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: fctid f1, f30 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs1, vs0 -; FAST-NEXT: addi r1, r1, 48 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> %x) ret <2 x i64> %a } @@ -356,68 +296,6 @@ define <4 x i64> @lrint_v4f16(<4 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v4f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -64(r1) -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f4 -; FAST-NEXT: std r0, 80(r1) -; FAST-NEXT: fmr f31, f3 -; FAST-NEXT: fmr f30, f2 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: fmr f1, f31 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: fmr f1, f30 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: fmr f1, f29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f30 -; FAST-NEXT: fctid f2, f31 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f0, f28 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v3, vs0, vs2 -; FAST-NEXT: addi r1, r1, 64 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload -; FAST-NEXT: blr %a = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> %x) ret <4 x i64> %a } @@ -729,122 +607,6 @@ define <8 x i64> @lrint_v8f16(<8 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v8f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f24, -64(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f25, -56(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -96(r1) -; FAST-NEXT: fmr f24, f1 -; FAST-NEXT: fmr f1, f8 -; FAST-NEXT: std r0, 112(r1) -; FAST-NEXT: fmr f30, f7 -; FAST-NEXT: fmr f29, f6 -; FAST-NEXT: fmr f28, f5 -; FAST-NEXT: fmr f27, f4 -; FAST-NEXT: fmr f26, f3 -; FAST-NEXT: fmr f25, f2 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: fmr f1, f30 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: fmr f1, f29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f28 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: fmr f1, f27 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f27, f1 -; FAST-NEXT: fmr f1, f26 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f26, f1 -; FAST-NEXT: fmr f1, f25 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f25, f1 -; FAST-NEXT: fmr f1, f24 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f25 -; FAST-NEXT: fctid f2, f26 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: fctid f3, f27 -; FAST-NEXT: fctid f4, f28 -; FAST-NEXT: fctid f5, f29 -; FAST-NEXT: fctid f6, f30 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: mffprd r3, f3 -; FAST-NEXT: mtfprd f3, r3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: mtfprd f4, r3 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v3, vs3, vs2 -; FAST-NEXT: xxmrghd v4, vs5, vs4 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f0, f31 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v5, vs0, vs6 -; FAST-NEXT: addi r1, r1, 96 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f25, -56(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f24, -64(r1) # 8-byte Folded Reload -; FAST-NEXT: blr %a = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> %x) ret <8 x i64> %a } @@ -1454,228 +1216,6 @@ define <16 x i64> @lrint_v16i64_v16f16(<16 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v16i64_v16f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stfd f16, -128(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f17, -120(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f18, -112(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f19, -104(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f20, -96(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f21, -88(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f22, -80(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f23, -72(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f24, -64(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f25, -56(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; FAST-NEXT: stdu r1, -160(r1) -; FAST-NEXT: fmr f26, f1 -; FAST-NEXT: lfs f1, 312(r1) -; FAST-NEXT: std r0, 176(r1) -; FAST-NEXT: fmr f28, f13 -; FAST-NEXT: fmr f27, f12 -; FAST-NEXT: fmr f24, f11 -; FAST-NEXT: fmr f21, f10 -; FAST-NEXT: fmr f19, f9 -; FAST-NEXT: fmr f18, f8 -; FAST-NEXT: fmr f17, f7 -; FAST-NEXT: fmr f16, f6 -; FAST-NEXT: fmr f20, f5 -; FAST-NEXT: fmr f22, f4 -; FAST-NEXT: fmr f23, f3 -; FAST-NEXT: fmr f25, f2 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: lfs f1, 304(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: lfs f1, 296(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f28 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: fmr f1, f27 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f27, f1 -; FAST-NEXT: fmr f1, f24 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f24, f1 -; FAST-NEXT: fmr f1, f21 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f21, f1 -; FAST-NEXT: fmr f1, f19 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f19, f1 -; FAST-NEXT: fmr f1, f18 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f18, f1 -; FAST-NEXT: fmr f1, f17 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f17, f1 -; FAST-NEXT: fmr f1, f16 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f16, f1 -; FAST-NEXT: fmr f1, f20 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f20, f1 -; FAST-NEXT: fmr f1, f22 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f22, f1 -; FAST-NEXT: fmr f1, f23 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f23, f1 -; FAST-NEXT: fmr f1, f25 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f25, f1 -; FAST-NEXT: fmr f1, f26 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f0, f25 -; FAST-NEXT: fctid f2, f23 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: fctid f3, f22 -; FAST-NEXT: fctid f4, f20 -; FAST-NEXT: fctid f5, f16 -; FAST-NEXT: fctid f6, f17 -; FAST-NEXT: fctid f7, f18 -; FAST-NEXT: fctid f8, f19 -; FAST-NEXT: fctid f9, f21 -; FAST-NEXT: fctid f10, f24 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: mffprd r3, f3 -; FAST-NEXT: mtfprd f3, r3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: mtfprd f4, r3 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f7 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: mffprd r3, f8 -; FAST-NEXT: mtfprd f8, r3 -; FAST-NEXT: mffprd r3, f9 -; FAST-NEXT: mtfprd f9, r3 -; FAST-NEXT: mffprd r3, f10 -; FAST-NEXT: mtfprd f10, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v3, vs3, vs2 -; FAST-NEXT: xxmrghd v4, vs5, vs4 -; FAST-NEXT: xxmrghd v5, vs7, vs6 -; FAST-NEXT: xxmrghd v6, vs9, vs8 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f0, f27 -; FAST-NEXT: fctid f1, f29 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v7, vs0, vs10 -; FAST-NEXT: fctid f0, f28 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v8, vs1, vs0 -; FAST-NEXT: fctid f0, f30 -; FAST-NEXT: fctid f1, f31 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v9, vs1, vs0 -; FAST-NEXT: addi r1, r1, 160 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload -; FAST-NEXT: mtlr r0 -; FAST-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f25, -56(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f24, -64(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f23, -72(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f22, -80(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f21, -88(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f20, -96(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f19, -104(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f18, -112(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f17, -120(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f16, -128(r1) # 8-byte Folded Reload -; FAST-NEXT: blr %a = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> %x) ret <16 x i64> %a } @@ -2854,523 +2394,6 @@ define <32 x i64> @lrint_v32i64_v32f16(<32 x half> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v32i64_v32f16: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -480(r1) -; FAST-NEXT: li r4, 128 -; FAST-NEXT: std r0, 496(r1) -; FAST-NEXT: std r30, 320(r1) # 8-byte Folded Spill -; FAST-NEXT: mr r30, r3 -; FAST-NEXT: stfd f14, 336(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f15, 344(r1) # 8-byte Folded Spill -; FAST-NEXT: fmr f14, f5 -; FAST-NEXT: stfd f16, 352(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 144 -; FAST-NEXT: fmr f16, f4 -; FAST-NEXT: stfd f17, 360(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f18, 368(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f19, 376(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f20, 384(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f21, 392(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 160 -; FAST-NEXT: stfd f22, 400(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f23, 408(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f24, 416(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f25, 424(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f26, 432(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f27, 440(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 176 -; FAST-NEXT: xxlor v22, f3, f3 -; FAST-NEXT: stfd f28, 448(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f29, 456(r1) # 8-byte Folded Spill -; FAST-NEXT: fmr f29, f9 -; FAST-NEXT: stfd f30, 464(r1) # 8-byte Folded Spill -; FAST-NEXT: stfd f31, 472(r1) # 8-byte Folded Spill -; FAST-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 192 -; FAST-NEXT: xxlor v23, f2, f2 -; FAST-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 208 -; FAST-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 224 -; FAST-NEXT: xxlor v25, f13, f13 -; FAST-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 240 -; FAST-NEXT: xxlor v26, f12, f12 -; FAST-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 256 -; FAST-NEXT: xxlor v27, f11, f11 -; FAST-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 272 -; FAST-NEXT: xxlor v28, f10, f10 -; FAST-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 288 -; FAST-NEXT: xxlor v29, f8, f8 -; FAST-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 304 -; FAST-NEXT: xxlor v30, f7, f7 -; FAST-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill -; FAST-NEXT: li r4, 44 -; FAST-NEXT: xxlor v31, f6, f6 -; FAST-NEXT: stxsspx f1, r1, r4 # 4-byte Folded Spill -; FAST-NEXT: lfs f1, 768(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 120 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 760(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 112 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 752(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 104 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 744(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 96 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 736(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 88 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 728(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 80 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 720(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 72 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 712(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 704(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 56 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 696(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 48 -; FAST-NEXT: stxsdx f1, r1, r3 # 8-byte Folded Spill -; FAST-NEXT: lfs f1, 688(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: xxlor v21, f1, f1 -; FAST-NEXT: lfs f1, 680(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: xxlor v20, f1, f1 -; FAST-NEXT: lfs f1, 672(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: xxlor v24, f1, f1 -; FAST-NEXT: lfs f1, 664(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f31, f1 -; FAST-NEXT: lfs f1, 656(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f30, f1 -; FAST-NEXT: lfs f1, 648(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f28, f1 -; FAST-NEXT: lfs f1, 640(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f27, f1 -; FAST-NEXT: lfs f1, 632(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f26, f1 -; FAST-NEXT: lfs f1, 624(r1) -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f25, f1 -; FAST-NEXT: xxlor f1, v25, v25 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f24, f1 -; FAST-NEXT: xxlor f1, v26, v26 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f23, f1 -; FAST-NEXT: xxlor f1, v27, v27 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f22, f1 -; FAST-NEXT: xxlor f1, v28, v28 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f21, f1 -; FAST-NEXT: fmr f1, f29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f20, f1 -; FAST-NEXT: xxlor f1, v29, v29 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f19, f1 -; FAST-NEXT: xxlor f1, v30, v30 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f18, f1 -; FAST-NEXT: xxlor f1, v31, v31 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f29, f1 -; FAST-NEXT: fmr f1, f14 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f14, f1 -; FAST-NEXT: fmr f1, f16 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f16, f1 -; FAST-NEXT: xxlor f1, v22, v22 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fmr f17, f1 -; FAST-NEXT: xxlor f1, v23, v23 -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: li r3, 44 -; FAST-NEXT: fmr f15, f1 -; FAST-NEXT: lxsspx f1, r1, r3 # 4-byte Folded Reload -; FAST-NEXT: bl __truncsfhf2 -; FAST-NEXT: nop -; FAST-NEXT: clrldi r3, r3, 48 -; FAST-NEXT: bl __extendhfsf2 -; FAST-NEXT: nop -; FAST-NEXT: fctid f3, f15 -; FAST-NEXT: fctid f4, f17 -; FAST-NEXT: mffprd r3, f3 -; FAST-NEXT: fctid f5, f16 -; FAST-NEXT: fctid f6, f14 -; FAST-NEXT: fctid f7, f18 -; FAST-NEXT: fctid f8, f19 -; FAST-NEXT: fctid f13, f1 -; FAST-NEXT: fctid f9, f20 -; FAST-NEXT: fctid f10, f22 -; FAST-NEXT: fctid f11, f24 -; FAST-NEXT: fctid f12, f25 -; FAST-NEXT: fctid f2, f23 -; FAST-NEXT: fctid f0, f21 -; FAST-NEXT: mtvsrd v2, r3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: mtvsrd v3, r3 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: mffprd r3, f7 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f8 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: mffprd r3, f9 -; FAST-NEXT: mtfprd f3, r3 -; FAST-NEXT: mffprd r3, f10 -; FAST-NEXT: mtfprd f4, r3 -; FAST-NEXT: mffprd r3, f11 -; FAST-NEXT: fctid f11, f31 -; FAST-NEXT: lfd f31, 56(r1) # 8-byte Folded Reload -; FAST-NEXT: mtfprd f8, r3 -; FAST-NEXT: mffprd r3, f12 -; FAST-NEXT: xxlor f12, v24, v24 -; FAST-NEXT: fctid f31, f31 -; FAST-NEXT: fctid f12, f12 -; FAST-NEXT: mtfprd f9, r3 -; FAST-NEXT: mffprd r3, f13 -; FAST-NEXT: lfd f13, 48(r1) # 8-byte Folded Reload -; FAST-NEXT: mtfprd f10, r3 -; FAST-NEXT: fctid f13, f13 -; FAST-NEXT: xxmrghd v3, vs5, v3 -; FAST-NEXT: fctid f5, f26 -; FAST-NEXT: mffprd r3, f5 -; FAST-NEXT: mtfprd f5, r3 -; FAST-NEXT: xxmrghd v4, vs7, vs6 -; FAST-NEXT: fctid f6, f27 -; FAST-NEXT: fctid f7, f28 -; FAST-NEXT: mffprd r3, f6 -; FAST-NEXT: lfd f28, 96(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: mtfprd f6, r3 -; FAST-NEXT: mffprd r3, f7 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: xxmrghd v2, v2, vs10 -; FAST-NEXT: fctid f10, f30 -; FAST-NEXT: mffprd r3, f10 -; FAST-NEXT: lfd f30, 80(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f30, f30 -; FAST-NEXT: mtfprd f10, r3 -; FAST-NEXT: mffprd r3, f11 -; FAST-NEXT: mtfprd f11, r3 -; FAST-NEXT: mffprd r3, f12 -; FAST-NEXT: mtfprd f12, r3 -; FAST-NEXT: xxmrghd v5, vs12, vs11 -; FAST-NEXT: xxlor f11, v20, v20 -; FAST-NEXT: xxlor f12, v21, v21 -; FAST-NEXT: fctid f11, f11 -; FAST-NEXT: fctid f12, f12 -; FAST-NEXT: mffprd r3, f11 -; FAST-NEXT: mtfprd f11, r3 -; FAST-NEXT: mffprd r3, f12 -; FAST-NEXT: mtfprd f12, r3 -; FAST-NEXT: mffprd r3, f13 -; FAST-NEXT: mtfprd f13, r3 -; FAST-NEXT: mffprd r3, f31 -; FAST-NEXT: lfd f31, 64(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f31, f31 -; FAST-NEXT: mtvsrd v0, r3 -; FAST-NEXT: mffprd r3, f31 -; FAST-NEXT: lfd f31, 72(r1) # 8-byte Folded Reload -; FAST-NEXT: mtvsrd v1, r3 -; FAST-NEXT: mffprd r3, f30 -; FAST-NEXT: lfd f30, 88(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f31, f31 -; FAST-NEXT: mtvsrd v6, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: lfd f28, 104(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f30, f30 -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: mtvsrd v7, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: lfd f28, 112(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: mtvsrd v8, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: lfd f28, 120(r1) # 8-byte Folded Reload -; FAST-NEXT: fctid f28, f28 -; FAST-NEXT: xxmrghd v10, vs12, vs11 -; FAST-NEXT: xxmrghd v0, v0, vs13 -; FAST-NEXT: xxswapd vs12, v0 -; FAST-NEXT: xxmrghd v0, vs9, vs8 -; FAST-NEXT: xxmrghd v7, v8, v7 -; FAST-NEXT: mtvsrd v8, r3 -; FAST-NEXT: mffprd r3, f28 -; FAST-NEXT: mtvsrd v9, r3 -; FAST-NEXT: mffprd r3, f30 -; FAST-NEXT: xxswapd v7, v7 -; FAST-NEXT: xxmrghd v8, v9, v8 -; FAST-NEXT: mtvsrd v9, r3 -; FAST-NEXT: mffprd r3, f31 -; FAST-NEXT: xxswapd v8, v8 -; FAST-NEXT: xxmrghd v6, v9, v6 -; FAST-NEXT: mtvsrd v9, r3 -; FAST-NEXT: li r3, 240 -; FAST-NEXT: stxvd2x v8, r30, r3 -; FAST-NEXT: li r3, 224 -; FAST-NEXT: stxvd2x v7, r30, r3 -; FAST-NEXT: li r3, 208 -; FAST-NEXT: xxswapd vs11, v6 -; FAST-NEXT: xxmrghd v6, vs10, vs7 -; FAST-NEXT: stxvd2x vs11, r30, r3 -; FAST-NEXT: li r3, 192 -; FAST-NEXT: xxmrghd v1, v9, v1 -; FAST-NEXT: xxswapd vs11, v1 -; FAST-NEXT: xxmrghd v1, vs6, vs5 -; FAST-NEXT: xxswapd vs5, v10 -; FAST-NEXT: xxswapd vs6, v5 -; FAST-NEXT: stxvd2x vs11, r30, r3 -; FAST-NEXT: li r3, 176 -; FAST-NEXT: stxvd2x vs12, r30, r3 -; FAST-NEXT: li r3, 160 -; FAST-NEXT: stxvd2x vs5, r30, r3 -; FAST-NEXT: li r3, 144 -; FAST-NEXT: stxvd2x vs6, r30, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f7, r3 -; FAST-NEXT: li r3, 128 -; FAST-NEXT: xxswapd vs5, v6 -; FAST-NEXT: stxvd2x vs5, r30, r3 -; FAST-NEXT: li r3, 112 -; FAST-NEXT: xxswapd vs2, v1 -; FAST-NEXT: xxswapd vs6, v0 -; FAST-NEXT: stxvd2x vs2, r30, r3 -; FAST-NEXT: li r3, 96 -; FAST-NEXT: fctid f2, f29 -; FAST-NEXT: stxvd2x vs6, r30, r3 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: mtfprd f2, r3 -; FAST-NEXT: li r3, 80 -; FAST-NEXT: xxmrghd v5, vs7, vs4 -; FAST-NEXT: xxswapd vs4, v2 -; FAST-NEXT: xxmrghd v0, vs0, vs3 -; FAST-NEXT: xxswapd vs0, v5 -; FAST-NEXT: xxswapd vs3, v3 -; FAST-NEXT: stxvd2x vs0, r30, r3 -; FAST-NEXT: li r3, 64 -; FAST-NEXT: xxswapd vs0, v0 -; FAST-NEXT: stxvd2x vs0, r30, r3 -; FAST-NEXT: li r3, 48 -; FAST-NEXT: xxmrghd v5, vs2, vs1 -; FAST-NEXT: xxswapd vs1, v4 -; FAST-NEXT: stxvd2x vs1, r30, r3 -; FAST-NEXT: li r3, 32 -; FAST-NEXT: xxswapd vs2, v5 -; FAST-NEXT: stxvd2x vs2, r30, r3 -; FAST-NEXT: li r3, 16 -; FAST-NEXT: stxvd2x vs3, r30, r3 -; FAST-NEXT: li r3, 304 -; FAST-NEXT: stxvd2x vs4, 0, r30 -; FAST-NEXT: lfd f31, 472(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f30, 464(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f29, 456(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f28, 448(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f27, 440(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f26, 432(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f25, 424(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f24, 416(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f23, 408(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f22, 400(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f21, 392(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f20, 384(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f19, 376(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f18, 368(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f17, 360(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f16, 352(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f15, 344(r1) # 8-byte Folded Reload -; FAST-NEXT: lfd f14, 336(r1) # 8-byte Folded Reload -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 288 -; FAST-NEXT: ld r30, 320(r1) # 8-byte Folded Reload -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 272 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 256 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 240 -; FAST-NEXT: lxvd2x v27, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 224 -; FAST-NEXT: lxvd2x v26, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 208 -; FAST-NEXT: lxvd2x v25, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 192 -; FAST-NEXT: lxvd2x v24, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 176 -; FAST-NEXT: lxvd2x v23, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 160 -; FAST-NEXT: lxvd2x v22, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 144 -; FAST-NEXT: lxvd2x v21, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 128 -; FAST-NEXT: lxvd2x v20, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 480 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <32 x i64> @llvm.lrint.v32i64.v32f16(<32 x half> %x) ret <32 x i64> %a } @@ -3400,12 +2423,6 @@ define <1 x i64> @lrint_v1f32(<1 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v1f32: -; FAST: # %bb.0: -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.lrint.v1i64.v1f32(<1 x float> %x) ret <1 x i64> %a } @@ -3459,21 +2476,6 @@ define <2 x i64> @lrint_v2f32(<2 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v2f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xscvspdpn f1, vs1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs1, vs0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.lrint.v2i64.v2f32(<2 x float> %x) ret <2 x i64> %a } @@ -3552,32 +2554,6 @@ define <4 x i64> @lrint_v4f32(<4 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v4f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xxsldwi vs2, v2, v2, 1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v4, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v2 -; FAST-NEXT: vmr v2, v4 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs2 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v3, vs1, vs0 -; FAST-NEXT: blr %a = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> %x) ret <4 x i64> %a } @@ -3710,54 +2686,6 @@ define <8 x i64> @lrint_v8f32(<8 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v8f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xxsldwi vs2, v2, v2, 1 -; FAST-NEXT: xxsldwi vs3, v3, v3, 3 -; FAST-NEXT: xxswapd vs4, v3 -; FAST-NEXT: xxsldwi vs5, v3, v3, 1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v0, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v2 -; FAST-NEXT: vmr v2, v0 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs2 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v1, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, vs3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs4 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v4, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v3 -; FAST-NEXT: vmr v3, v1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs5 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v5, vs1, vs0 -; FAST-NEXT: blr %a = call <8 x i64> @llvm.lrint.v8i64.v8f32(<8 x float> %x) ret <8 x i64> %a } @@ -3998,98 +2926,6 @@ define <16 x i64> @lrint_v16i64_v16f32(<16 x float> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v16i64_v16f32: -; FAST: # %bb.0: -; FAST-NEXT: xxsldwi vs0, v2, v2, 3 -; FAST-NEXT: xxswapd vs1, v2 -; FAST-NEXT: xscvspdpn f0, vs0 -; FAST-NEXT: xxsldwi vs2, v2, v2, 1 -; FAST-NEXT: xxsldwi vs3, v3, v3, 3 -; FAST-NEXT: xxswapd vs4, v3 -; FAST-NEXT: xxsldwi vs5, v3, v3, 1 -; FAST-NEXT: xxsldwi vs6, v4, v4, 3 -; FAST-NEXT: xxswapd vs7, v4 -; FAST-NEXT: xxsldwi vs8, v4, v4, 1 -; FAST-NEXT: xxsldwi vs9, v5, v5, 3 -; FAST-NEXT: xxswapd vs10, v5 -; FAST-NEXT: xxsldwi vs11, v5, v5, 1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v0, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v2 -; FAST-NEXT: vmr v2, v0 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs2 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v1, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, vs3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs4 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v10, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v3 -; FAST-NEXT: vmr v3, v1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs5 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v11, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, vs6 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: xscvspdpn f0, vs7 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v6, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, v4 -; FAST-NEXT: xscvspdpn f1, vs8 -; FAST-NEXT: vmr v4, v10 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v7, vs0, vs1 -; FAST-NEXT: xscvspdpn f0, vs9 -; FAST-NEXT: xscvspdpn f1, vs10 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v8, vs1, vs0 -; FAST-NEXT: xscvspdpn f0, v5 -; FAST-NEXT: xscvspdpn f1, vs11 -; FAST-NEXT: vmr v5, v11 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v9, vs0, vs1 -; FAST-NEXT: blr %a = call <16 x i64> @llvm.lrint.v16i64.v16f32(<16 x float> %x) ret <16 x i64> %a } @@ -4119,12 +2955,6 @@ define <1 x i64> @lrint_v1f64(<1 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v1f64: -; FAST: # %bb.0: -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.lrint.v1i64.v1f64(<1 x double> %x) ret <1 x i64> %a } @@ -4179,19 +3009,6 @@ define <2 x i64> @lrint_v2f64(<2 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v2f64: -; FAST: # %bb.0: -; FAST-NEXT: xxlor f1, v2, v2 -; FAST-NEXT: xxswapd vs0, v2 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: mffprd r3, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v2, vs1, vs0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.lrint.v2i64.v2f64(<2 x double> %x) ret <2 x i64> %a } @@ -4276,28 +3093,6 @@ define <4 x i64> @lrint_v4f64(<4 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v4f64: -; FAST: # %bb.0: -; FAST-NEXT: xxswapd vs0, v2 -; FAST-NEXT: xxlor f2, v2, v2 -; FAST-NEXT: xxswapd vs1, v3 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f2, f2 -; FAST-NEXT: fctid f1, f1 -; FAST-NEXT: mffprd r4, f0 -; FAST-NEXT: xxlor f0, v3, v3 -; FAST-NEXT: mffprd r3, f2 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mtfprd f2, r4 -; FAST-NEXT: mffprd r5, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v2, vs0, vs2 -; FAST-NEXT: mtfprd f0, r5 -; FAST-NEXT: xxmrghd v3, vs0, vs1 -; FAST-NEXT: blr %a = call <4 x i64> @llvm.lrint.v4i64.v4f64(<4 x double> %x) ret <4 x i64> %a } @@ -4442,46 +3237,6 @@ define <8 x i64> @lrint_v8f64(<8 x double> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v8f64: -; FAST: # %bb.0: -; FAST-NEXT: xxswapd vs0, v2 -; FAST-NEXT: xxswapd vs1, v3 -; FAST-NEXT: xxlor f4, v2, v2 -; FAST-NEXT: xxswapd vs2, v4 -; FAST-NEXT: xxswapd vs3, v5 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: fctid f4, f4 -; FAST-NEXT: mffprd r4, f0 -; FAST-NEXT: xxlor f0, v3, v3 -; FAST-NEXT: mffprd r3, f4 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mffprd r5, f0 -; FAST-NEXT: fctid f0, f1 -; FAST-NEXT: mtfprd f1, r4 -; FAST-NEXT: mffprd r6, f0 -; FAST-NEXT: xxlor f0, v4, v4 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mtfprd f4, r6 -; FAST-NEXT: mffprd r7, f0 -; FAST-NEXT: fctid f0, f2 -; FAST-NEXT: mtfprd f2, r5 -; FAST-NEXT: mtfprd f5, r7 -; FAST-NEXT: mffprd r8, f0 -; FAST-NEXT: xxlor f0, v5, v5 -; FAST-NEXT: fctid f0, f0 -; FAST-NEXT: mtfprd f6, r8 -; FAST-NEXT: mffprd r9, f0 -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: xxmrghd v3, vs2, vs4 -; FAST-NEXT: xxmrghd v4, vs5, vs6 -; FAST-NEXT: xxmrghd v2, vs0, vs1 -; FAST-NEXT: fctid f1, f3 -; FAST-NEXT: mtfprd f0, r9 -; FAST-NEXT: mffprd r3, f1 -; FAST-NEXT: mtfprd f1, r3 -; FAST-NEXT: xxmrghd v5, vs0, vs1 -; FAST-NEXT: blr %a = call <8 x i64> @llvm.lrint.v8i64.v8f64(<8 x double> %x) ret <8 x i64> %a } @@ -4511,18 +3266,6 @@ define <1 x i64> @lrint_v1f128(<1 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v1f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -32(r1) -; FAST-NEXT: std r0, 48(r1) -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: addi r1, r1, 32 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <1 x i64> @llvm.lrint.v1i64.v1f128(<1 x fp128> %x) ret <1 x i64> %a } @@ -4580,33 +3323,6 @@ define <2 x i64> @lrint_v2f128(<2 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v2f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -80(r1) -; FAST-NEXT: li r3, 48 -; FAST-NEXT: std r0, 96(r1) -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: vmr v31, v3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: mtvsrd v30, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 48 -; FAST-NEXT: xxmrghd v2, vs0, v30 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 80 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <2 x i64> @llvm.lrint.v2i64.v2f128(<2 x fp128> %x) ret <2 x i64> %a } @@ -4704,53 +3420,6 @@ define <4 x i64> @lrint_v4f128(<4 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v4f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -112(r1) -; FAST-NEXT: li r3, 48 -; FAST-NEXT: std r0, 128(r1) -; FAST-NEXT: stxvd2x v28, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 80 -; FAST-NEXT: vmr v29, v3 -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 96 -; FAST-NEXT: vmr v30, v4 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: vmr v31, v5 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: mtvsrd v28, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v30 -; FAST-NEXT: xxmrghd v29, vs0, v28 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: mtvsrd v30, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 96 -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 80 -; FAST-NEXT: xxmrghd v3, vs0, v30 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 48 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 112 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <4 x i64> @llvm.lrint.v4i64.v4f128(<4 x fp128> %x) ret <4 x i64> %a } @@ -4928,93 +3597,6 @@ define <8 x i64> @lrint_v8f128(<8 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v8f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -176(r1) -; FAST-NEXT: li r3, 48 -; FAST-NEXT: std r0, 192(r1) -; FAST-NEXT: stxvd2x v24, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v25, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 80 -; FAST-NEXT: vmr v25, v3 -; FAST-NEXT: stxvd2x v26, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 96 -; FAST-NEXT: vmr v26, v4 -; FAST-NEXT: stxvd2x v27, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 112 -; FAST-NEXT: vmr v27, v5 -; FAST-NEXT: stxvd2x v28, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 128 -; FAST-NEXT: vmr v28, v6 -; FAST-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 144 -; FAST-NEXT: vmr v29, v7 -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 160 -; FAST-NEXT: vmr v30, v8 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: vmr v31, v9 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v25 -; FAST-NEXT: mtvsrd v24, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v26 -; FAST-NEXT: xxmrghd v25, vs0, v24 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v27 -; FAST-NEXT: mtvsrd v26, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v28 -; FAST-NEXT: xxmrghd v27, vs0, v26 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: mtvsrd v28, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v30 -; FAST-NEXT: xxmrghd v29, vs0, v28 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: mtvsrd v30, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 160 -; FAST-NEXT: vmr v4, v29 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 144 -; FAST-NEXT: vmr v3, v27 -; FAST-NEXT: vmr v2, v25 -; FAST-NEXT: xxmrghd v5, vs0, v30 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 128 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 112 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 96 -; FAST-NEXT: lxvd2x v27, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 80 -; FAST-NEXT: lxvd2x v26, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v25, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 48 -; FAST-NEXT: lxvd2x v24, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 176 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <8 x i64> @llvm.lrint.v8i64.v8f128(<8 x fp128> %x) ret <8 x i64> %a } @@ -5355,176 +3937,6 @@ define <16 x i64> @lrint_v16i64_v16f128(<16 x fp128> %x) nounwind { ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr -; -; FAST-LABEL: lrint_v16i64_v16f128: -; FAST: # %bb.0: -; FAST-NEXT: mflr r0 -; FAST-NEXT: stdu r1, -304(r1) -; FAST-NEXT: li r3, 112 -; FAST-NEXT: std r0, 320(r1) -; FAST-NEXT: stxvd2x v20, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 128 -; FAST-NEXT: stxvd2x v21, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 144 -; FAST-NEXT: vmr v21, v4 -; FAST-NEXT: stxvd2x v22, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 160 -; FAST-NEXT: vmr v22, v6 -; FAST-NEXT: stxvd2x v23, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 176 -; FAST-NEXT: vmr v23, v8 -; FAST-NEXT: stxvd2x v24, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 192 -; FAST-NEXT: vmr v24, v9 -; FAST-NEXT: stxvd2x v25, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 208 -; FAST-NEXT: vmr v25, v7 -; FAST-NEXT: stxvd2x v26, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 224 -; FAST-NEXT: vmr v26, v10 -; FAST-NEXT: stxvd2x v27, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 240 -; FAST-NEXT: vmr v27, v5 -; FAST-NEXT: stxvd2x v28, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 256 -; FAST-NEXT: vmr v28, v11 -; FAST-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 272 -; FAST-NEXT: vmr v29, v12 -; FAST-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 288 -; FAST-NEXT: vmr v30, v3 -; FAST-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 64 -; FAST-NEXT: stxvd2x v13, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: addi r3, r1, 576 -; FAST-NEXT: lxvd2x vs0, 0, r3 -; FAST-NEXT: addi r3, r1, 560 -; FAST-NEXT: lxvd2x vs1, 0, r3 -; FAST-NEXT: addi r3, r1, 544 -; FAST-NEXT: lxvd2x vs2, 0, r3 -; FAST-NEXT: li r3, 96 -; FAST-NEXT: xxswapd vs0, vs0 -; FAST-NEXT: stxvd2x vs0, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 80 -; FAST-NEXT: xxswapd vs0, vs1 -; FAST-NEXT: stxvd2x vs0, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: li r3, 48 -; FAST-NEXT: xxswapd vs0, vs2 -; FAST-NEXT: stxvd2x vs0, r1, r3 # 16-byte Folded Spill -; FAST-NEXT: addi r3, r1, 528 -; FAST-NEXT: lxvd2x vs0, 0, r3 -; FAST-NEXT: xxswapd v31, vs0 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v30 -; FAST-NEXT: mtvsrd v20, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v21 -; FAST-NEXT: xxmrghd v30, vs0, v20 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v27 -; FAST-NEXT: mtvsrd v21, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v22 -; FAST-NEXT: xxmrghd v27, vs0, v21 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v25 -; FAST-NEXT: mtvsrd v22, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v23 -; FAST-NEXT: xxmrghd v25, vs0, v22 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v24 -; FAST-NEXT: mtvsrd v23, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v26 -; FAST-NEXT: xxmrghd v24, vs0, v23 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: vmr v2, v28 -; FAST-NEXT: mtvsrd v26, r3 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v29 -; FAST-NEXT: xxmrghd v28, vs0, v26 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtvsrd v29, r3 -; FAST-NEXT: li r3, 64 -; FAST-NEXT: lxvd2x v2, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: vmr v2, v31 -; FAST-NEXT: xxmrghd v29, vs0, v29 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtvsrd v31, r3 -; FAST-NEXT: li r3, 48 -; FAST-NEXT: lxvd2x v2, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 80 -; FAST-NEXT: lxvd2x v2, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: xxmrghd v31, vs0, v31 -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtvsrd v26, r3 -; FAST-NEXT: li r3, 96 -; FAST-NEXT: lxvd2x v2, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: bl lrintf128 -; FAST-NEXT: nop -; FAST-NEXT: mtfprd f0, r3 -; FAST-NEXT: li r3, 288 -; FAST-NEXT: vmr v8, v31 -; FAST-NEXT: lxvd2x v31, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 272 -; FAST-NEXT: vmr v2, v30 -; FAST-NEXT: vmr v7, v29 -; FAST-NEXT: vmr v6, v28 -; FAST-NEXT: vmr v3, v27 -; FAST-NEXT: lxvd2x v30, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 256 -; FAST-NEXT: vmr v4, v25 -; FAST-NEXT: vmr v5, v24 -; FAST-NEXT: lxvd2x v29, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 240 -; FAST-NEXT: lxvd2x v28, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 224 -; FAST-NEXT: lxvd2x v27, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 208 -; FAST-NEXT: xxmrghd v9, vs0, v26 -; FAST-NEXT: lxvd2x v26, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 192 -; FAST-NEXT: lxvd2x v25, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 176 -; FAST-NEXT: lxvd2x v24, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 160 -; FAST-NEXT: lxvd2x v23, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 144 -; FAST-NEXT: lxvd2x v22, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 128 -; FAST-NEXT: lxvd2x v21, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: li r3, 112 -; FAST-NEXT: lxvd2x v20, r1, r3 # 16-byte Folded Reload -; FAST-NEXT: addi r1, r1, 304 -; FAST-NEXT: ld r0, 16(r1) -; FAST-NEXT: mtlr r0 -; FAST-NEXT: blr %a = call <16 x i64> @llvm.lrint.v16i64.v16f128(<16 x fp128> %x) ret <16 x i64> %a } diff --git a/llvm/test/CodeGen/RISCV/atomic-fence.ll b/llvm/test/CodeGen/RISCV/atomic-fence.ll index 7103345..77148f6 100644 --- a/llvm/test/CodeGen/RISCV/atomic-fence.ll +++ b/llvm/test/CodeGen/RISCV/atomic-fence.ll @@ -1,12 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s +; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,TSO %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s +; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll index 7e3abc7..c6234de 100644 --- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -1,12 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32I-ZALRSC %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s +; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I-ZALRSC %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ @@ -44,6 +48,11 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i8_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lb a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i8_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lb a0, 0(a0) @@ -59,6 +68,11 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i8_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lb a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i8_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lb a0, 0(a0) @@ -78,6 +92,11 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lb a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i8_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lb a0, 0(a0) @@ -93,6 +112,11 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lb a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i8_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lb a0, 0(a0) @@ -112,6 +136,12 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lb a0, 0(a0) +; RV32I-ZALRSC-NEXT: fence r, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_load_i8_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: lb a0, 0(a0) @@ -133,6 +163,12 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lb a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i8_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: lb a0, 0(a0) @@ -200,6 +236,13 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, rw +; RV32I-ZALRSC-NEXT: lb a0, 0(a0) +; RV32I-ZALRSC-NEXT: fence r, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_load_i8_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, rw @@ -223,6 +266,13 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: lb a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i8_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, rw @@ -286,6 +336,11 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i16_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lh a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i16_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lh a0, 0(a0) @@ -301,6 +356,11 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i16_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lh a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i16_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lh a0, 0(a0) @@ -320,6 +380,11 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lh a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i16_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lh a0, 0(a0) @@ -335,6 +400,11 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lh a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i16_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lh a0, 0(a0) @@ -354,6 +424,12 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lh a0, 0(a0) +; RV32I-ZALRSC-NEXT: fence r, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_load_i16_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: lh a0, 0(a0) @@ -375,6 +451,12 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lh a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i16_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: lh a0, 0(a0) @@ -442,6 +524,13 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, rw +; RV32I-ZALRSC-NEXT: lh a0, 0(a0) +; RV32I-ZALRSC-NEXT: fence r, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_load_i16_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, rw @@ -465,6 +554,13 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: lh a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i16_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, rw @@ -528,6 +624,11 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i32_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lw a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i32_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lw a0, 0(a0) @@ -543,6 +644,11 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i32_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lw a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i32_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lw a0, 0(a0) @@ -562,6 +668,11 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lw a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lw a0, 0(a0) @@ -577,6 +688,11 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lw a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lw a0, 0(a0) @@ -596,6 +712,12 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lw a0, 0(a0) +; RV32I-ZALRSC-NEXT: fence r, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_load_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: lw a0, 0(a0) @@ -617,6 +739,12 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lw a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: lw a0, 0(a0) @@ -684,6 +812,13 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, rw +; RV32I-ZALRSC-NEXT: lw a0, 0(a0) +; RV32I-ZALRSC-NEXT: fence r, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_load_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, rw @@ -707,6 +842,13 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: lw a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, rw @@ -770,6 +912,16 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i64_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a1, 0 +; RV32I-ZALRSC-NEXT: call __atomic_load_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i64_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -790,6 +942,11 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i64_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: ld a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i64_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: ld a0, 0(a0) @@ -809,6 +966,16 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a1, 0 +; RV32I-ZALRSC-NEXT: call __atomic_load_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -829,6 +996,11 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: ld a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_load_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: ld a0, 0(a0) @@ -848,6 +1020,16 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a1, 2 +; RV32I-ZALRSC-NEXT: call __atomic_load_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -868,6 +1050,12 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: ld a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: ld a0, 0(a0) @@ -914,6 +1102,16 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a1, 5 +; RV32I-ZALRSC-NEXT: call __atomic_load_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_load_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -934,6 +1132,13 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_load_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: ld a0, 0(a0) +; RV64I-ZALRSC-NEXT: fence r, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_load_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, rw @@ -979,6 +1184,11 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i8_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sb a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i8_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: sb a1, 0(a0) @@ -994,6 +1204,11 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i8_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sb a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i8_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sb a1, 0(a0) @@ -1013,6 +1228,11 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sb a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i8_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: sb a1, 0(a0) @@ -1028,6 +1248,11 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sb a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i8_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sb a1, 0(a0) @@ -1047,6 +1272,12 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, w +; RV32I-ZALRSC-NEXT: sb a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_store_i8_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w @@ -1068,6 +1299,12 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sb a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i8_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1135,6 +1372,13 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, w +; RV32I-ZALRSC-NEXT: sb a1, 0(a0) +; RV32I-ZALRSC-NEXT: fence rw, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_store_i8_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w @@ -1157,6 +1401,13 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sb a1, 0(a0) +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i8_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1219,6 +1470,11 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i16_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sh a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i16_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: sh a1, 0(a0) @@ -1234,6 +1490,11 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i16_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sh a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i16_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sh a1, 0(a0) @@ -1253,6 +1514,11 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sh a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i16_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: sh a1, 0(a0) @@ -1268,6 +1534,11 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sh a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i16_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sh a1, 0(a0) @@ -1287,6 +1558,12 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, w +; RV32I-ZALRSC-NEXT: sh a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_store_i16_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w @@ -1308,6 +1585,12 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sh a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i16_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1375,6 +1658,13 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, w +; RV32I-ZALRSC-NEXT: sh a1, 0(a0) +; RV32I-ZALRSC-NEXT: fence rw, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_store_i16_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w @@ -1397,6 +1687,13 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sh a1, 0(a0) +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i16_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1459,6 +1756,11 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i32_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sw a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i32_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: sw a1, 0(a0) @@ -1474,6 +1776,11 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i32_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sw a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i32_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sw a1, 0(a0) @@ -1493,6 +1800,11 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sw a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: sw a1, 0(a0) @@ -1508,6 +1820,11 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sw a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sw a1, 0(a0) @@ -1527,6 +1844,12 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, w +; RV32I-ZALRSC-NEXT: sw a1, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_store_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w @@ -1548,6 +1871,12 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sw a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1615,6 +1944,13 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: fence rw, w +; RV32I-ZALRSC-NEXT: sw a1, 0(a0) +; RV32I-ZALRSC-NEXT: fence rw, rw +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomic_store_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w @@ -1637,6 +1973,13 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sw a1, 0(a0) +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1699,6 +2042,16 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i64_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_store_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i64_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -1719,6 +2072,11 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i64_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sd a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i64_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sd a1, 0(a0) @@ -1738,6 +2096,16 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_store_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -1758,6 +2126,11 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sd a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomic_store_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: sd a1, 0(a0) @@ -1777,6 +2150,16 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_store_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -1797,6 +2180,12 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sd a1, 0(a0) +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w @@ -1843,6 +2232,16 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_store_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_store_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomic_store_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -1863,6 +2262,13 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomic_store_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: fence rw, w +; RV64I-ZALRSC-NEXT: sd a1, 0(a0) +; RV64I-ZALRSC-NEXT: fence rw, rw +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomic_store_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll b/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll index 4dafd6a..d5238ab 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll @@ -3,10 +3,14 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA %s +; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA %s +; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind { ; RV32I-LABEL: atomicrmw_sub_i32_constant: @@ -26,6 +30,18 @@ define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind { ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_constant: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a1, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB0_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a1 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i32_constant: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -42,6 +58,18 @@ define i32 @atomicrmw_sub_i32_constant(ptr %a) nounwind { ; RV64IA-NEXT: li a1, -1 ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_constant: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB0_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw sub ptr %a, i32 1 seq_cst ret i32 %1 } @@ -71,6 +99,18 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_constant: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a1, 1 +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: li a2, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i64_constant: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -87,6 +127,18 @@ define i64 @atomicrmw_sub_i64_constant(ptr %a) nounwind { ; RV64IA-NEXT: li a1, -1 ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_constant: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB1_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw sub ptr %a, i64 1 seq_cst ret i64 %1 } @@ -109,6 +161,18 @@ define i32 @atomicrmw_sub_i32_neg(ptr %a, i32 %x, i32 %y) nounwind { ; RV32IA-NEXT: amoadd.w.aqrl a0, a2, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_neg: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: sub a2, a1, a2 +; RV32I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a1, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB2_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a1 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i32_neg: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -125,6 +189,18 @@ define i32 @atomicrmw_sub_i32_neg(ptr %a, i32 %x, i32 %y) nounwind { ; RV64IA-NEXT: sub a2, a2, a1 ; RV64IA-NEXT: amoadd.w.aqrl a0, a2, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_neg: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: subw a2, a1, a2 +; RV64I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB2_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %b = sub i32 %x, %y %1 = atomicrmw sub ptr %a, i32 %b seq_cst ret i32 %1 @@ -159,6 +235,20 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_neg: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sltu a5, a1, a3 +; RV32I-ZALRSC-NEXT: sub a2, a2, a4 +; RV32I-ZALRSC-NEXT: sub a2, a2, a5 +; RV32I-ZALRSC-NEXT: sub a1, a1, a3 +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i64_neg: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -175,6 +265,18 @@ define i64 @atomicrmw_sub_i64_neg(ptr %a, i64 %x, i64 %y) nounwind { ; RV64IA-NEXT: sub a2, a2, a1 ; RV64IA-NEXT: amoadd.d.aqrl a0, a2, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_neg: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sub a2, a1, a2 +; RV64I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB3_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %b = sub i64 %x, %y %1 = atomicrmw sub ptr %a, i64 %b seq_cst ret i64 %1 diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll index 1213256..26feb83 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -1,12 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS,RV32IA-WMO,RV32IA-WMO-NOZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS,RV32IA-TSO,RV32IA-TSO-NOZACAS %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s +; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-NOZACAS,RV64IA-WMO,RV64IA-WMO-NOZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ @@ -50,6 +54,26 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB0_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -80,6 +104,26 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB0_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -174,6 +218,26 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB1_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -224,6 +288,26 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB1_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -378,6 +462,26 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB2_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -428,6 +532,26 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB2_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -582,6 +706,26 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB3_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -632,6 +776,26 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB3_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -786,6 +950,26 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB4_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -816,6 +1000,26 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB4_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -914,6 +1118,22 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB5_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -936,6 +1156,22 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB5_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -1004,6 +1240,22 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB6_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1037,6 +1289,22 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB6_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1138,6 +1406,22 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB7_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1171,6 +1455,22 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB7_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1272,6 +1572,22 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB8_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1305,6 +1621,22 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB8_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1406,6 +1738,22 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB9_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1439,6 +1787,22 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB9_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1540,6 +1904,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB10_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -1561,6 +1940,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB10_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -1630,6 +2024,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB11_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1661,6 +2070,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB11_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1760,6 +2184,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB12_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1791,6 +2230,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB12_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1890,6 +2344,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB13_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -1921,6 +2390,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB13_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -2020,6 +2504,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a2, 255 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB14_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -2051,6 +2550,21 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a2, 255 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB14_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -2149,6 +2663,26 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: add a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB15_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -2179,6 +2713,26 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: add a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB15_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -2273,6 +2827,26 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: add a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB16_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -2323,6 +2897,26 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: add a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB16_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -2477,6 +3071,26 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: add a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB17_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -2527,6 +3141,26 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: add a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB17_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -2681,6 +3315,26 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: add a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB18_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -2731,6 +3385,26 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: add a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB18_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -2885,6 +3559,26 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV32I-ZALRSC-NEXT: add a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB19_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -2915,6 +3609,26 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV64I-ZALRSC-NEXT: add a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB19_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3009,6 +3723,26 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB20_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3039,6 +3773,26 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB20_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3137,6 +3891,26 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB21_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -3187,6 +3961,26 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB21_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -3345,6 +4139,26 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB22_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -3395,6 +4209,26 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB22_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -3553,6 +4387,26 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB23_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -3603,6 +4457,26 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB23_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -3761,6 +4635,26 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB24_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3791,6 +4685,26 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB24_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3889,6 +4803,25 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB25_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3913,6 +4846,25 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB25_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3989,6 +4941,25 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB26_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4027,6 +4998,25 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB26_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4145,6 +5135,25 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB27_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4183,6 +5192,25 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB27_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4301,6 +5329,25 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB28_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4339,6 +5386,25 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB28_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4457,6 +5523,25 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB29_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4495,6 +5580,25 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB29_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4613,6 +5717,27 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a5, a4, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB30_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -4644,6 +5769,27 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a5, a4, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB30_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -4865,6 +6011,27 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: and a5, a4, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB31_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -4917,6 +6084,27 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: and a5, a4, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB31_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -5201,6 +6389,27 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a5, a4, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB32_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -5253,6 +6462,27 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a5, a4, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB32_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -5537,6 +6767,27 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: and a5, a4, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB33_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -5589,6 +6840,27 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: and a5, a4, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB33_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -5873,6 +7145,27 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV32I-ZALRSC-NEXT: and a5, a4, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB34_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -5904,6 +7197,27 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV64I-ZALRSC-NEXT: and a5, a4, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB34_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -6129,6 +7443,21 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB35_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -6149,6 +7478,21 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB35_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -6213,6 +7557,21 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB36_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6243,6 +7602,21 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB36_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6337,6 +7711,21 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB37_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6367,6 +7756,21 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB37_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6461,6 +7865,21 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB38_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6491,6 +7910,21 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB38_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6585,6 +8019,21 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB39_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6615,6 +8064,21 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB39_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6709,6 +8173,21 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB40_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -6729,6 +8208,21 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB40_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -6793,6 +8287,21 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB41_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6823,6 +8332,21 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB41_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6917,6 +8441,21 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB42_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -6947,6 +8486,21 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB42_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7041,6 +8595,21 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB43_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7071,6 +8640,21 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB43_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7165,6 +8749,21 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB44_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7195,6 +8794,21 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB44_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7321,6 +8935,35 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB45_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB45_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -7392,6 +9035,35 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB45_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB45_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -7545,6 +9217,35 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB46_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB46_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7645,6 +9346,35 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB46_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB46_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7885,6 +9615,35 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB47_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB47_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -7985,6 +9744,35 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB47_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB47_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -8225,6 +10013,35 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB48_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB48_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -8325,6 +10142,35 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB48_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB48_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -8565,6 +10411,35 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB49_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB49_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -8636,6 +10511,35 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB49_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB49_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -8789,6 +10693,35 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB50_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB50_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -8860,6 +10793,35 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB50_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB50_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -9013,6 +10975,35 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB51_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB51_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -9113,6 +11104,35 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB51_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB51_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -9353,6 +11373,35 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB52_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB52_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -9453,6 +11502,35 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB52_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB52_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -9693,6 +11771,35 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB53_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB53_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -9793,6 +11900,35 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB53_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB53_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -10033,6 +12169,35 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB54_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB54_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -10104,6 +12269,35 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB54_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB54_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -10255,6 +12449,30 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB55_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB55_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -10319,6 +12537,30 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB55_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB55_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -10455,6 +12697,30 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB56_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB56_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -10543,6 +12809,30 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB56_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB56_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -10751,6 +13041,30 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB57_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB57_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -10839,6 +13153,30 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB57_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB57_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -11047,6 +13385,30 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB58_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB58_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -11135,6 +13497,30 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB58_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB58_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -11343,6 +13729,30 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB59_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB59_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -11407,6 +13817,30 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB59_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB59_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -11543,6 +13977,30 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB60_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB60_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -11607,6 +14065,30 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB60_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB60_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -11743,6 +14225,30 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB61_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB61_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -11831,6 +14337,30 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB61_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB61_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -12039,6 +14569,30 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB62_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB62_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -12127,6 +14681,30 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB62_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB62_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -12335,6 +14913,30 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB63_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB63_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -12423,6 +15025,30 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB63_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB63_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -12631,6 +15257,30 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB64_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB64_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -12695,6 +15345,30 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB64_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB64_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -12801,6 +15475,27 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB65_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -12832,6 +15527,27 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB65_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -12929,6 +15645,27 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB66_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -12981,6 +15718,27 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB66_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -13141,6 +15899,27 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB67_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -13193,6 +15972,27 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB67_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -13353,6 +16153,27 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB68_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -13405,6 +16226,27 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB68_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -13565,6 +16407,27 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB69_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -13596,6 +16459,27 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB69_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -13697,6 +16581,23 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB70_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB70_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -13720,6 +16621,23 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB70_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB70_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -13791,6 +16709,23 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB71_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB71_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -13826,6 +16761,23 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB71_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB71_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -13933,6 +16885,23 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB72_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB72_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -13968,6 +16937,23 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB72_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB72_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14075,6 +17061,23 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB73_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB73_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14110,6 +17113,23 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB73_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB73_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14217,6 +17237,23 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: not a2, a2 +; RV32I-ZALRSC-NEXT: .LBB74_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV32I-ZALRSC-NEXT: and a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB74_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14252,6 +17289,23 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: not a2, a2 +; RV64I-ZALRSC-NEXT: .LBB74_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV64I-ZALRSC-NEXT: and a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB74_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14360,6 +17414,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB75_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -14383,6 +17453,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB75_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a1, a0, -4 @@ -14456,6 +17542,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB76_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14490,6 +17592,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB76_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14596,6 +17714,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB77_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14630,6 +17764,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB77_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14736,6 +17886,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB78_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14770,6 +17936,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB78_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14876,6 +18058,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a1, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a2, 16 +; RV32I-ZALRSC-NEXT: addi a2, a2, -1 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV32I-ZALRSC-NEXT: or a4, a3, a2 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB79_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -14910,6 +18108,22 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a2, 16 +; RV64I-ZALRSC-NEXT: addi a2, a2, -1 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a1) +; RV64I-ZALRSC-NEXT: or a4, a3, a2 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a1) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB79_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 @@ -15014,6 +18228,27 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: add a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB80_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -15045,6 +18280,27 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: add a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB80_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -15142,6 +18398,27 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: add a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB81_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -15194,6 +18471,27 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: add a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB81_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -15354,6 +18652,27 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: add a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB82_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -15406,6 +18725,27 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: add a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB82_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -15566,6 +18906,27 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: add a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB83_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -15618,6 +18979,27 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: add a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB83_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -15778,6 +19160,27 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: add a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB84_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -15809,6 +19212,27 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: add a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB84_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -15906,6 +19330,27 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB85_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -15937,6 +19382,27 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB85_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -16038,6 +19504,27 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB86_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16090,6 +19577,27 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB86_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16254,6 +19762,27 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB87_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16306,6 +19835,27 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB87_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16470,6 +20020,27 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB88_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16522,6 +20093,27 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB88_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16686,6 +20278,27 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB89_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -16717,6 +20330,27 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB89_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -16818,6 +20452,26 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: not a3, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB90_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -16843,6 +20497,26 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: not a3, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB90_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -16922,6 +20596,26 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: not a3, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB91_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -16962,6 +20656,26 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: not a3, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB91_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17086,6 +20800,26 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: not a3, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB92_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17126,6 +20860,26 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: not a3, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB92_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17250,6 +21004,26 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: not a3, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB93_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17290,6 +21064,26 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: not a3, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB93_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17414,6 +21208,26 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: not a3, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB94_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17454,6 +21268,26 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: not a3, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB94_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17578,6 +21412,28 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a5, a3, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB95_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -17610,6 +21466,28 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a5, a3, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB95_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -17838,6 +21716,28 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a5, a3, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB96_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -17892,6 +21792,28 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a5, a3, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB96_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -18186,6 +22108,28 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a5, a3, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB97_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -18240,6 +22184,28 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a5, a3, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB97_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -18534,6 +22500,28 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a5, a3, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB98_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -18588,6 +22576,28 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a5, a3, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB98_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -18882,6 +22892,28 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: and a5, a3, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB99_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -18914,6 +22946,28 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: and a5, a3, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB99_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -19146,6 +23200,22 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB100_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -19167,6 +23237,22 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB100_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -19234,6 +23320,22 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB101_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19266,6 +23368,22 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB101_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19366,6 +23484,22 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB102_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19398,6 +23532,22 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB102_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19498,6 +23648,22 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB103_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19530,6 +23696,22 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB103_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19630,6 +23812,22 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB104_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19662,6 +23860,22 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB104_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19762,6 +23976,22 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB105_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -19783,6 +24013,22 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB105_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -19850,6 +24096,22 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB106_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19882,6 +24144,22 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB106_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -19982,6 +24260,22 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB107_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20014,6 +24308,22 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB107_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20114,6 +24424,22 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB108_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20146,6 +24472,22 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB108_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20246,6 +24588,22 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB109_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20278,6 +24636,22 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB109_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20410,6 +24784,37 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB110_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB110_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -20483,6 +24888,37 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB110_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB110_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -20642,6 +25078,37 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB111_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB111_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20746,6 +25213,37 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB111_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB111_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -20998,6 +25496,37 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB112_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB112_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -21102,6 +25631,37 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB112_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB112_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -21354,6 +25914,37 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB113_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB113_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -21458,6 +26049,37 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB113_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB113_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -21710,6 +26332,37 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB114_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB114_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -21783,6 +26436,37 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB114_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB114_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -21942,6 +26626,37 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB115_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB115_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -22015,6 +26730,37 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB115_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB115_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -22174,6 +26920,37 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB116_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB116_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -22278,6 +27055,37 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB116_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB116_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -22530,6 +27338,37 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB117_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB117_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -22634,6 +27473,37 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB117_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB117_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -22886,6 +27756,37 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB118_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB118_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -22990,6 +27891,37 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB118_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB118_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -23242,6 +28174,37 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB119_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB119_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -23315,6 +28278,37 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB119_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB119_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -23476,6 +28470,31 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB120_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB120_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -23545,6 +28564,31 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB120_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB120_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -23688,6 +28732,31 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB121_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB121_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -23782,6 +28851,31 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB121_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB121_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -24000,6 +29094,31 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB122_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB122_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -24094,6 +29213,31 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB122_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB122_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -24312,6 +29456,31 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB123_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB123_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -24406,6 +29575,31 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB123_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB123_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -24624,6 +29818,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB124_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB124_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -24693,6 +29912,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB124_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB124_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -24836,6 +30080,31 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB125_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB125_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -24905,6 +30174,31 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB125_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB125_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -25048,6 +30342,31 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB126_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB126_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -25142,6 +30461,31 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB126_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB126_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -25360,6 +30704,31 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB127_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB127_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -25454,6 +30823,31 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB127_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB127_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -25672,6 +31066,31 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB128_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB128_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -25766,6 +31185,31 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB128_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB128_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 @@ -25984,6 +31428,31 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB129_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB129_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -26053,6 +31522,31 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB129_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB129_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a0, -4 @@ -26162,6 +31656,17 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB130_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amoswap.w a0, a1, (a0) @@ -26177,6 +31682,17 @@ define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB130_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoswap.w a0, a1, (a0) @@ -26196,6 +31712,17 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB131_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoswap.w.aq a0, a1, (a0) @@ -26216,6 +31743,17 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB131_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.w.aq a0, a1, (a0) @@ -26240,6 +31778,17 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB132_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoswap.w.rl a0, a1, (a0) @@ -26260,6 +31809,17 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB132_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.w.rl a0, a1, (a0) @@ -26284,6 +31844,17 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB133_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0) @@ -26304,6 +31875,17 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB133_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0) @@ -26328,6 +31910,17 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB134_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0) @@ -26348,6 +31941,17 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB134_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0) @@ -26372,6 +31976,17 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB135_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: add a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB135_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_add_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amoadd.w a0, a1, (a0) @@ -26387,6 +32002,17 @@ define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB135_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB135_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_add_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoadd.w a0, a1, (a0) @@ -26406,6 +32032,17 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB136_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: add a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB136_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_add_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0) @@ -26426,6 +32063,17 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB136_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB136_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0) @@ -26450,6 +32098,17 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB137_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: add a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB137_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_add_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0) @@ -26470,6 +32129,17 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB137_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB137_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0) @@ -26494,6 +32164,17 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB138_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: add a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB138_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_add_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0) @@ -26514,6 +32195,17 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB138_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB138_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0) @@ -26538,6 +32230,17 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB139_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: add a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB139_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_add_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0) @@ -26558,6 +32261,17 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB139_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB139_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0) @@ -26582,6 +32296,17 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB140_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB140_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_sub_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: neg a1, a1 @@ -26598,6 +32323,17 @@ define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB140_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB140_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_sub_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: neg a1, a1 @@ -26618,6 +32354,17 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB141_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB141_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_sub_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: neg a1, a1 @@ -26640,6 +32387,17 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB141_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB141_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -26666,6 +32424,17 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB142_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB142_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_sub_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: neg a1, a1 @@ -26688,6 +32457,17 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB142_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB142_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -26714,6 +32494,17 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB143_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB143_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_sub_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: neg a1, a1 @@ -26736,6 +32527,17 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB143_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB143_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -26762,6 +32564,17 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB144_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB144_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_sub_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: neg a1, a1 @@ -26784,6 +32597,17 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB144_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB144_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -26810,6 +32634,17 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB145_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB145_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_and_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amoand.w a0, a1, (a0) @@ -26825,6 +32660,17 @@ define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB145_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB145_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_and_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoand.w a0, a1, (a0) @@ -26844,6 +32690,17 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB146_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB146_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_and_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoand.w.aq a0, a1, (a0) @@ -26864,6 +32721,17 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB146_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB146_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.w.aq a0, a1, (a0) @@ -26888,6 +32756,17 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB147_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB147_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_and_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoand.w.rl a0, a1, (a0) @@ -26908,6 +32787,17 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB147_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB147_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.w.rl a0, a1, (a0) @@ -26932,6 +32822,17 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB148_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB148_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_and_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0) @@ -26952,6 +32853,17 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB148_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB148_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0) @@ -26976,6 +32888,17 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB149_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB149_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_and_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0) @@ -26996,6 +32919,17 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB149_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB149_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0) @@ -27020,6 +32954,18 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB150_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 @@ -27042,6 +32988,18 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB150_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 @@ -27200,6 +33158,18 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB151_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acquire: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 @@ -27234,6 +33204,18 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB151_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 @@ -27432,6 +33414,18 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB152_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_release: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 @@ -27466,6 +33460,18 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB152_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 @@ -27664,6 +33670,18 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB153_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel: ; RV32IA-WMO-NOZACAS: # %bb.0: ; RV32IA-WMO-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 @@ -27698,6 +33716,18 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB153_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 @@ -27896,6 +33926,18 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB154_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 @@ -27918,6 +33960,18 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB154_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 @@ -28112,6 +34166,17 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB155_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: or a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB155_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_or_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amoor.w a0, a1, (a0) @@ -28127,6 +34192,17 @@ define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB155_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB155_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_or_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoor.w a0, a1, (a0) @@ -28146,6 +34222,17 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB156_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: or a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB156_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_or_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoor.w.aq a0, a1, (a0) @@ -28166,6 +34253,17 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB156_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB156_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.w.aq a0, a1, (a0) @@ -28190,6 +34288,17 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB157_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: or a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB157_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_or_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoor.w.rl a0, a1, (a0) @@ -28210,6 +34319,17 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB157_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB157_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.w.rl a0, a1, (a0) @@ -28234,6 +34354,17 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB158_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: or a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB158_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_or_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0) @@ -28254,6 +34385,17 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB158_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB158_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0) @@ -28278,6 +34420,17 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB159_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: or a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB159_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_or_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0) @@ -28298,6 +34451,17 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB159_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB159_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0) @@ -28322,6 +34486,17 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB160_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: xor a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB160_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amoxor.w a0, a1, (a0) @@ -28337,6 +34512,17 @@ define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB160_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB160_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoxor.w a0, a1, (a0) @@ -28356,6 +34542,17 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB161_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: xor a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB161_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xor_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoxor.w.aq a0, a1, (a0) @@ -28376,6 +34573,17 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB161_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB161_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.w.aq a0, a1, (a0) @@ -28400,6 +34608,17 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB162_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: xor a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB162_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xor_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoxor.w.rl a0, a1, (a0) @@ -28420,6 +34639,17 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB162_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB162_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.w.rl a0, a1, (a0) @@ -28444,6 +34674,17 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB163_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: xor a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB163_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xor_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0) @@ -28464,6 +34705,17 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB163_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB163_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0) @@ -28488,6 +34740,17 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB164_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: xor a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB164_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_xor_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0) @@ -28508,6 +34771,17 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB164_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB164_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0) @@ -28558,6 +34832,21 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB165_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB165_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB165_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB165_3: # in Loop: Header=BB165_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB165_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_max_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amomax.w a0, a1, (a0) @@ -28602,6 +34891,22 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB165_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB165_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB165_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB165_3: # in Loop: Header=BB165_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB165_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_max_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomax.w a0, a1, (a0) @@ -28647,6 +34952,21 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB166_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB166_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB166_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB166_3: # in Loop: Header=BB166_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB166_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_max_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomax.w.aq a0, a1, (a0) @@ -28696,6 +35016,22 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB166_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB166_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB166_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB166_3: # in Loop: Header=BB166_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB166_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.w.aq a0, a1, (a0) @@ -28746,6 +35082,21 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB167_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB167_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB167_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB167_3: # in Loop: Header=BB167_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB167_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_max_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomax.w.rl a0, a1, (a0) @@ -28795,6 +35146,22 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB167_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB167_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB167_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB167_3: # in Loop: Header=BB167_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB167_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.w.rl a0, a1, (a0) @@ -28845,6 +35212,21 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB168_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB168_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB168_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB168_3: # in Loop: Header=BB168_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB168_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_max_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0) @@ -28894,6 +35276,22 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB168_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB168_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB168_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB168_3: # in Loop: Header=BB168_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB168_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0) @@ -28944,6 +35342,21 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB169_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB169_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB169_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB169_3: # in Loop: Header=BB169_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB169_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_max_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0) @@ -28993,6 +35406,22 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB169_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB169_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB169_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB169_3: # in Loop: Header=BB169_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB169_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0) @@ -29043,6 +35472,21 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB170_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB170_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB170_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB170_3: # in Loop: Header=BB170_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB170_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_min_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amomin.w a0, a1, (a0) @@ -29087,6 +35531,22 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB170_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB170_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB170_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB170_3: # in Loop: Header=BB170_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB170_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_min_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomin.w a0, a1, (a0) @@ -29132,6 +35592,21 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB171_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB171_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB171_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB171_3: # in Loop: Header=BB171_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB171_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_min_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomin.w.aq a0, a1, (a0) @@ -29181,6 +35656,22 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB171_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB171_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB171_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB171_3: # in Loop: Header=BB171_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB171_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.w.aq a0, a1, (a0) @@ -29231,6 +35722,21 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB172_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB172_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB172_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB172_3: # in Loop: Header=BB172_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB172_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_min_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomin.w.rl a0, a1, (a0) @@ -29280,6 +35786,22 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB172_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB172_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB172_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB172_3: # in Loop: Header=BB172_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB172_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.w.rl a0, a1, (a0) @@ -29330,6 +35852,21 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB173_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB173_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB173_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB173_3: # in Loop: Header=BB173_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB173_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_min_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0) @@ -29379,6 +35916,22 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB173_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB173_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB173_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB173_3: # in Loop: Header=BB173_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB173_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0) @@ -29429,6 +35982,21 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB174_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB174_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB174_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB174_3: # in Loop: Header=BB174_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB174_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_min_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0) @@ -29478,6 +36046,22 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB174_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB174_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB174_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB174_3: # in Loop: Header=BB174_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB174_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0) @@ -29528,6 +36112,21 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB175_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB175_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB175_3: # in Loop: Header=BB175_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB175_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amomaxu.w a0, a1, (a0) @@ -29572,6 +36171,22 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB175_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB175_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB175_3: # in Loop: Header=BB175_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB175_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomaxu.w a0, a1, (a0) @@ -29617,6 +36232,21 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB176_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB176_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB176_3: # in Loop: Header=BB176_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB176_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umax_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomaxu.w.aq a0, a1, (a0) @@ -29666,6 +36296,22 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB176_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB176_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB176_3: # in Loop: Header=BB176_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB176_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.w.aq a0, a1, (a0) @@ -29716,6 +36362,21 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB177_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB177_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB177_3: # in Loop: Header=BB177_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB177_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umax_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomaxu.w.rl a0, a1, (a0) @@ -29765,6 +36426,22 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB177_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB177_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB177_3: # in Loop: Header=BB177_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB177_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.w.rl a0, a1, (a0) @@ -29815,6 +36492,21 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB178_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB178_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB178_3: # in Loop: Header=BB178_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB178_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0) @@ -29864,6 +36556,22 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB178_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB178_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB178_3: # in Loop: Header=BB178_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB178_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0) @@ -29914,6 +36622,21 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB179_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB179_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB179_3: # in Loop: Header=BB179_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB179_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0) @@ -29963,6 +36686,22 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB179_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB179_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB179_3: # in Loop: Header=BB179_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB179_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0) @@ -30013,6 +36752,21 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB180_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB180_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB180_3: # in Loop: Header=BB180_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB180_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: amominu.w a0, a1, (a0) @@ -30057,6 +36811,22 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB180_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB180_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB180_3: # in Loop: Header=BB180_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB180_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amominu.w a0, a1, (a0) @@ -30102,6 +36872,21 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB181_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB181_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB181_3: # in Loop: Header=BB181_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB181_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umin_i32_acquire: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amominu.w.aq a0, a1, (a0) @@ -30151,6 +36936,22 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB181_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB181_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB181_3: # in Loop: Header=BB181_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB181_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.w.aq a0, a1, (a0) @@ -30201,6 +37002,21 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB182_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB182_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB182_3: # in Loop: Header=BB182_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB182_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umin_i32_release: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amominu.w.rl a0, a1, (a0) @@ -30250,6 +37066,22 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB182_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB182_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB182_3: # in Loop: Header=BB182_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB182_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i32_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.w.rl a0, a1, (a0) @@ -30300,6 +37132,21 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB183_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aq a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB183_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB183_3: # in Loop: Header=BB183_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB183_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0) @@ -30349,6 +37196,22 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB183_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB183_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB183_3: # in Loop: Header=BB183_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB183_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0) @@ -30399,6 +37262,21 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB184_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB184_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB184_3: # in Loop: Header=BB184_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB184_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0) @@ -30448,6 +37326,22 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB184_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB184_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB184_3: # in Loop: Header=BB184_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB184_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0) @@ -30472,6 +37366,16 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_exchange_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xchg_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30492,6 +37396,17 @@ define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB185_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB185_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoswap.d a0, a1, (a0) @@ -30511,6 +37426,16 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_exchange_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xchg_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30531,6 +37456,17 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB186_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB186_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.d.aq a0, a1, (a0) @@ -30555,6 +37491,16 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_exchange_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xchg_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30575,6 +37521,17 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB187_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB187_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.d.rl a0, a1, (a0) @@ -30599,6 +37556,16 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_exchange_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30619,6 +37586,17 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB188_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB188_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.d.aqrl a0, a1, (a0) @@ -30643,6 +37621,16 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_exchange_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30663,6 +37651,17 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB189_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoswap.d.aqrl a0, a1, (a0) @@ -30687,6 +37686,16 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_add_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30707,6 +37716,17 @@ define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB190_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB190_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_add_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoadd.d a0, a1, (a0) @@ -30726,6 +37746,16 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_add_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30746,6 +37776,17 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB191_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB191_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.d.aq a0, a1, (a0) @@ -30770,6 +37811,16 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_add_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30790,6 +37841,17 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB192_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB192_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.d.rl a0, a1, (a0) @@ -30814,6 +37876,16 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_add_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30834,6 +37906,17 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB193_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB193_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0) @@ -30858,6 +37941,16 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_add_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30878,6 +37971,17 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB194_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB194_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_add_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0) @@ -30902,6 +38006,16 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_sub_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30922,6 +38036,17 @@ define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB195_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB195_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_sub_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: neg a1, a1 @@ -30942,6 +38067,16 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_sub_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -30962,6 +38097,17 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB196_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB196_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -30988,6 +38134,16 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_sub_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31008,6 +38164,17 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB197_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB197_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -31034,6 +38201,16 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_sub_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31054,6 +38231,17 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB198_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB198_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -31080,6 +38268,16 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_sub_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31100,6 +38298,17 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB199_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB199_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_sub_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: neg a1, a1 @@ -31126,6 +38335,16 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_and_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31146,6 +38365,17 @@ define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB200_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB200_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_and_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoand.d a0, a1, (a0) @@ -31165,6 +38395,16 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_and_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31185,6 +38425,17 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB201_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB201_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.d.aq a0, a1, (a0) @@ -31209,6 +38460,16 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_and_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31229,6 +38490,17 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB202_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB202_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.d.rl a0, a1, (a0) @@ -31253,6 +38525,16 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_and_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31273,6 +38555,17 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB203_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB203_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.d.aqrl a0, a1, (a0) @@ -31297,6 +38590,16 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_and_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31317,6 +38620,17 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB204_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB204_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_and_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoand.d.aqrl a0, a1, (a0) @@ -31341,6 +38655,16 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_nand_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31361,6 +38685,18 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB205_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i64_monotonic: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1 @@ -31453,6 +38789,16 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_nand_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31473,6 +38819,18 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB206_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i64_acquire: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1 @@ -31591,6 +38949,16 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_nand_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31611,6 +38979,18 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB207_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i64_release: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1 @@ -31729,6 +39109,16 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_nand_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31749,6 +39139,18 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB208_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i64_acq_rel: ; RV64IA-WMO-NOZACAS: # %bb.0: ; RV64IA-WMO-NOZACAS-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1 @@ -31867,6 +39269,16 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_nand_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -31887,6 +39299,18 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB209_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i64_seq_cst: ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1 @@ -31997,6 +39421,16 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_or_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32017,6 +39451,17 @@ define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB210_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB210_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_or_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoor.d a0, a1, (a0) @@ -32036,6 +39481,16 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_or_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32056,6 +39511,17 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB211_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB211_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.d.aq a0, a1, (a0) @@ -32080,6 +39546,16 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_or_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32100,6 +39576,17 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB212_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB212_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.d.rl a0, a1, (a0) @@ -32124,6 +39611,16 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_or_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32144,6 +39641,17 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB213_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB213_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.d.aqrl a0, a1, (a0) @@ -32168,6 +39676,16 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_or_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32188,6 +39706,17 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB214_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB214_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_or_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoor.d.aqrl a0, a1, (a0) @@ -32212,6 +39741,16 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xor_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32232,6 +39771,17 @@ define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB215_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB215_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_xor_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoxor.d a0, a1, (a0) @@ -32251,6 +39801,16 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 2 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xor_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32271,6 +39831,17 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB216_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB216_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.d.aq a0, a1, (a0) @@ -32295,6 +39866,16 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 3 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xor_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32315,6 +39896,17 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB217_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB217_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.d.rl a0, a1, (a0) @@ -32339,6 +39931,16 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 4 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xor_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32359,6 +39961,17 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB218_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB218_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.d.aqrl a0, a1, (a0) @@ -32383,6 +39996,16 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 5 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_xor_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -16 @@ -32403,6 +40026,17 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB219_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB219_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_xor_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amoxor.d.aqrl a0, a1, (a0) @@ -32471,6 +40105,60 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB220_2 +; RV32I-ZALRSC-NEXT: .LBB220_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB220_7 +; RV32I-ZALRSC-NEXT: .LBB220_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB220_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB220_5 +; RV32I-ZALRSC-NEXT: .LBB220_4: # in Loop: Header=BB220_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB220_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB220_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB220_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB220_1 +; RV32I-ZALRSC-NEXT: .LBB220_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_max_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -32561,6 +40249,21 @@ define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB220_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB220_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB220_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB220_3: # in Loop: Header=BB220_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB220_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_max_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomax.d a0, a1, (a0) @@ -32624,6 +40327,60 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB221_2 +; RV32I-ZALRSC-NEXT: .LBB221_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 2 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB221_7 +; RV32I-ZALRSC-NEXT: .LBB221_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB221_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB221_5 +; RV32I-ZALRSC-NEXT: .LBB221_4: # in Loop: Header=BB221_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB221_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB221_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB221_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB221_1 +; RV32I-ZALRSC-NEXT: .LBB221_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_max_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -32714,6 +40471,21 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB221_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB221_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB221_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB221_3: # in Loop: Header=BB221_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB221_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.d.aq a0, a1, (a0) @@ -32782,6 +40554,60 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB222_2 +; RV32I-ZALRSC-NEXT: .LBB222_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 3 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB222_7 +; RV32I-ZALRSC-NEXT: .LBB222_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB222_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB222_5 +; RV32I-ZALRSC-NEXT: .LBB222_4: # in Loop: Header=BB222_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB222_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB222_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB222_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB222_1 +; RV32I-ZALRSC-NEXT: .LBB222_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_max_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -32872,6 +40698,21 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB222_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB222_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB222_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB222_3: # in Loop: Header=BB222_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB222_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.d.rl a0, a1, (a0) @@ -32940,6 +40781,60 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB223_2 +; RV32I-ZALRSC-NEXT: .LBB223_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 4 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB223_7 +; RV32I-ZALRSC-NEXT: .LBB223_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB223_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB223_5 +; RV32I-ZALRSC-NEXT: .LBB223_4: # in Loop: Header=BB223_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB223_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB223_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB223_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB223_1 +; RV32I-ZALRSC-NEXT: .LBB223_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33030,6 +40925,21 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB223_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB223_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB223_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB223_3: # in Loop: Header=BB223_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB223_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.d.aqrl a0, a1, (a0) @@ -33098,6 +41008,60 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB224_2 +; RV32I-ZALRSC-NEXT: .LBB224_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 5 +; RV32I-ZALRSC-NEXT: li a5, 5 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB224_7 +; RV32I-ZALRSC-NEXT: .LBB224_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB224_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB224_5 +; RV32I-ZALRSC-NEXT: .LBB224_4: # in Loop: Header=BB224_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB224_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB224_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB224_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB224_1 +; RV32I-ZALRSC-NEXT: .LBB224_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_max_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33188,6 +41152,21 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB224_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB224_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB224_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB224_3: # in Loop: Header=BB224_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB224_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_max_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomax.d.aqrl a0, a1, (a0) @@ -33256,6 +41235,60 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB225_2 +; RV32I-ZALRSC-NEXT: .LBB225_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB225_7 +; RV32I-ZALRSC-NEXT: .LBB225_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB225_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB225_5 +; RV32I-ZALRSC-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB225_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB225_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB225_1 +; RV32I-ZALRSC-NEXT: .LBB225_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_min_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33346,6 +41379,21 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB225_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB225_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB225_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB225_3: # in Loop: Header=BB225_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB225_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_min_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomin.d a0, a1, (a0) @@ -33409,6 +41457,60 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB226_2 +; RV32I-ZALRSC-NEXT: .LBB226_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 2 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB226_7 +; RV32I-ZALRSC-NEXT: .LBB226_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB226_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB226_5 +; RV32I-ZALRSC-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB226_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB226_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB226_1 +; RV32I-ZALRSC-NEXT: .LBB226_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_min_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33499,6 +41601,21 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB226_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB226_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB226_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB226_3: # in Loop: Header=BB226_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB226_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.d.aq a0, a1, (a0) @@ -33567,6 +41684,60 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB227_2 +; RV32I-ZALRSC-NEXT: .LBB227_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 3 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB227_7 +; RV32I-ZALRSC-NEXT: .LBB227_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB227_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB227_5 +; RV32I-ZALRSC-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB227_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB227_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB227_1 +; RV32I-ZALRSC-NEXT: .LBB227_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_min_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33657,6 +41828,21 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB227_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB227_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB227_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB227_3: # in Loop: Header=BB227_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB227_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.d.rl a0, a1, (a0) @@ -33725,6 +41911,60 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB228_2 +; RV32I-ZALRSC-NEXT: .LBB228_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 4 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB228_7 +; RV32I-ZALRSC-NEXT: .LBB228_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB228_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB228_5 +; RV32I-ZALRSC-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB228_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB228_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB228_1 +; RV32I-ZALRSC-NEXT: .LBB228_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_min_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33815,6 +42055,21 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB228_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB228_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB228_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB228_3: # in Loop: Header=BB228_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB228_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.d.aqrl a0, a1, (a0) @@ -33883,6 +42138,60 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB229_2 +; RV32I-ZALRSC-NEXT: .LBB229_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 5 +; RV32I-ZALRSC-NEXT: li a5, 5 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB229_7 +; RV32I-ZALRSC-NEXT: .LBB229_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB229_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB229_5 +; RV32I-ZALRSC-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB229_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB229_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB229_1 +; RV32I-ZALRSC-NEXT: .LBB229_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_min_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -33973,6 +42282,21 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB229_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB229_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB229_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB229_3: # in Loop: Header=BB229_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB229_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_min_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomin.d.aqrl a0, a1, (a0) @@ -34041,6 +42365,60 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB230_2 +; RV32I-ZALRSC-NEXT: .LBB230_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB230_7 +; RV32I-ZALRSC-NEXT: .LBB230_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB230_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB230_5 +; RV32I-ZALRSC-NEXT: .LBB230_4: # in Loop: Header=BB230_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB230_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB230_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB230_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB230_1 +; RV32I-ZALRSC-NEXT: .LBB230_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umax_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -34131,6 +42509,21 @@ define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB230_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB230_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB230_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB230_3: # in Loop: Header=BB230_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB230_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_umax_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomaxu.d a0, a1, (a0) @@ -34194,6 +42587,60 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB231_2 +; RV32I-ZALRSC-NEXT: .LBB231_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 2 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB231_7 +; RV32I-ZALRSC-NEXT: .LBB231_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB231_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB231_5 +; RV32I-ZALRSC-NEXT: .LBB231_4: # in Loop: Header=BB231_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB231_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB231_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB231_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB231_1 +; RV32I-ZALRSC-NEXT: .LBB231_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umax_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -34284,6 +42731,21 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB231_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB231_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB231_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB231_3: # in Loop: Header=BB231_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB231_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.d.aq a0, a1, (a0) @@ -34352,6 +42814,60 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB232_2 +; RV32I-ZALRSC-NEXT: .LBB232_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 3 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB232_7 +; RV32I-ZALRSC-NEXT: .LBB232_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB232_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB232_5 +; RV32I-ZALRSC-NEXT: .LBB232_4: # in Loop: Header=BB232_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB232_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB232_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB232_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB232_1 +; RV32I-ZALRSC-NEXT: .LBB232_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umax_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -34442,6 +42958,21 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB232_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB232_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB232_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB232_3: # in Loop: Header=BB232_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB232_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.d.rl a0, a1, (a0) @@ -34510,6 +43041,60 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB233_2 +; RV32I-ZALRSC-NEXT: .LBB233_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 4 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB233_7 +; RV32I-ZALRSC-NEXT: .LBB233_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB233_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB233_5 +; RV32I-ZALRSC-NEXT: .LBB233_4: # in Loop: Header=BB233_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB233_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB233_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB233_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB233_1 +; RV32I-ZALRSC-NEXT: .LBB233_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -34600,6 +43185,21 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB233_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB233_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB233_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB233_3: # in Loop: Header=BB233_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB233_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.d.aqrl a0, a1, (a0) @@ -34668,6 +43268,60 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB234_2 +; RV32I-ZALRSC-NEXT: .LBB234_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 5 +; RV32I-ZALRSC-NEXT: li a5, 5 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB234_7 +; RV32I-ZALRSC-NEXT: .LBB234_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB234_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB234_5 +; RV32I-ZALRSC-NEXT: .LBB234_4: # in Loop: Header=BB234_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB234_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB234_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB234_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB234_1 +; RV32I-ZALRSC-NEXT: .LBB234_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umax_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -34758,6 +43412,21 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB234_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB234_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB234_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB234_3: # in Loop: Header=BB234_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB234_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umax_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amomaxu.d.aqrl a0, a1, (a0) @@ -34826,6 +43495,60 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB235_2 +; RV32I-ZALRSC-NEXT: .LBB235_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB235_7 +; RV32I-ZALRSC-NEXT: .LBB235_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB235_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB235_5 +; RV32I-ZALRSC-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB235_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB235_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB235_1 +; RV32I-ZALRSC-NEXT: .LBB235_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umin_i64_monotonic: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -34916,6 +43639,21 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB235_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB235_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB235_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB235_3: # in Loop: Header=BB235_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB235_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-LABEL: atomicrmw_umin_i64_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amominu.d a0, a1, (a0) @@ -34979,6 +43717,60 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_acquire: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB236_2 +; RV32I-ZALRSC-NEXT: .LBB236_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 2 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB236_7 +; RV32I-ZALRSC-NEXT: .LBB236_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB236_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB236_5 +; RV32I-ZALRSC-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB236_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB236_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB236_1 +; RV32I-ZALRSC-NEXT: .LBB236_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umin_i64_acquire: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -35069,6 +43861,21 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_acquire: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB236_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB236_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB236_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB236_3: # in Loop: Header=BB236_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB236_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i64_acquire: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.d.aq a0, a1, (a0) @@ -35137,6 +43944,60 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_release: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB237_2 +; RV32I-ZALRSC-NEXT: .LBB237_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 3 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB237_7 +; RV32I-ZALRSC-NEXT: .LBB237_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB237_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB237_5 +; RV32I-ZALRSC-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB237_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB237_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB237_1 +; RV32I-ZALRSC-NEXT: .LBB237_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umin_i64_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -35227,6 +44088,21 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_release: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB237_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB237_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB237_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB237_3: # in Loop: Header=BB237_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB237_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i64_release: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.d.rl a0, a1, (a0) @@ -35295,6 +44171,60 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_acq_rel: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB238_2 +; RV32I-ZALRSC-NEXT: .LBB238_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 4 +; RV32I-ZALRSC-NEXT: li a5, 2 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB238_7 +; RV32I-ZALRSC-NEXT: .LBB238_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB238_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB238_5 +; RV32I-ZALRSC-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB238_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB238_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB238_1 +; RV32I-ZALRSC-NEXT: .LBB238_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -35385,6 +44315,21 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_acq_rel: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB238_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aq a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB238_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB238_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB238_3: # in Loop: Header=BB238_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB238_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i64_acq_rel: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.d.aqrl a0, a1, (a0) @@ -35453,6 +44398,60 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_seq_cst: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB239_2 +; RV32I-ZALRSC-NEXT: .LBB239_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: li a4, 5 +; RV32I-ZALRSC-NEXT: li a5, 5 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB239_7 +; RV32I-ZALRSC-NEXT: .LBB239_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB239_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB239_5 +; RV32I-ZALRSC-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB239_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB239_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB239_1 +; RV32I-ZALRSC-NEXT: .LBB239_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV32IA-LABEL: atomicrmw_umin_i64_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: addi sp, sp, -32 @@ -35543,6 +44542,21 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_seq_cst: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB239_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d.aqrl a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB239_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB239_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB239_3: # in Loop: Header=BB239_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d.rl a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB239_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret +; ; RV64IA-WMO-LABEL: atomicrmw_umin_i64_seq_cst: ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: amominu.d.aqrl a0, a1, (a0) diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll index 7d29ac9..7fe5fa7 100644 --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -5,12 +5,16 @@ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS %s +; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-NOZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS %s +; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV32I-LABEL: atomic_load_i8_unordered: @@ -30,6 +34,11 @@ define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i8_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lb a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomic_load_i8_unordered: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -46,6 +55,11 @@ define signext i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomic_load_i8_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lb a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret %1 = load atomic i8, ptr %a unordered, align 1 ret i8 %1 } @@ -68,6 +82,11 @@ define signext i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i16_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lh a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomic_load_i16_unordered: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -84,6 +103,11 @@ define signext i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomic_load_i16_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lh a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret %1 = load atomic i16, ptr %a unordered, align 2 ret i16 %1 } @@ -104,6 +128,11 @@ define signext i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomic_load_i32_unordered: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: lw a0, 0(a0) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomic_load_i32_unordered: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -119,6 +148,11 @@ define signext i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomic_load_i32_unordered: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: lw a0, 0(a0) +; RV64I-ZALRSC-NEXT: ret %1 = load atomic i32, ptr %a unordered, align 4 ret i32 %1 } @@ -159,6 +193,28 @@ define signext i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB3_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -192,6 +248,28 @@ define signext i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB3_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xchg ptr %a, i8 %b monotonic ret i8 %1 } @@ -231,6 +309,28 @@ define signext i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: add a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB4_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_add_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -264,6 +364,28 @@ define signext i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: add a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB4_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw add ptr %a, i8 %b monotonic ret i8 %1 } @@ -303,6 +425,28 @@ define signext i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a4, a1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB5_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -336,6 +480,28 @@ define signext i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a4, a1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB5_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw sub ptr %a, i8 %b monotonic ret i8 %1 } @@ -369,6 +535,27 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB6_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_and_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -396,6 +583,27 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB6_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw and ptr %a, i8 %b monotonic ret i8 %1 } @@ -436,6 +644,29 @@ define signext i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a5, a4, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB7_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_nand_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -470,6 +701,29 @@ define signext i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a5, a4, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB7_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw nand ptr %a, i8 %b monotonic ret i8 %1 } @@ -499,6 +753,23 @@ define signext i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB8_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_or_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -522,6 +793,23 @@ define signext i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB8_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw or ptr %a, i8 %b monotonic ret i8 %1 } @@ -551,6 +839,23 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB9_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xor_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -574,6 +879,23 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB9_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xor ptr %a, i8 %b monotonic ret i8 %1 } @@ -653,6 +975,37 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB10_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB10_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -726,6 +1079,37 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB10_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB10_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw max ptr %a, i8 %b monotonic ret i8 %1 } @@ -805,6 +1189,37 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: slli a1, a1, 24 +; RV32I-ZALRSC-NEXT: andi a4, a0, 24 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: srai a1, a1, 24 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: xori a4, a4, 24 +; RV32I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB11_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB11_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -878,6 +1293,37 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: slli a1, a1, 56 +; RV64I-ZALRSC-NEXT: andi a4, a0, 24 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: srai a1, a1, 56 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: xori a4, a4, 56 +; RV64I-ZALRSC-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB11_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB11_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw min ptr %a, i8 %b monotonic ret i8 %1 } @@ -950,6 +1396,32 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB12_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB12_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -1016,6 +1488,32 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB12_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB12_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umax ptr %a, i8 %b monotonic ret i8 %1 } @@ -1088,6 +1586,32 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a3, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a2) +; RV32I-ZALRSC-NEXT: and a6, a4, a3 +; RV32I-ZALRSC-NEXT: mv a5, a4 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB13_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a4, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a3 +; RV32I-ZALRSC-NEXT: xor a5, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB13_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -1154,6 +1678,32 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a3, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a2) +; RV64I-ZALRSC-NEXT: and a6, a4, a3 +; RV64I-ZALRSC-NEXT: mv a5, a4 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB13_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a4, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a3 +; RV64I-ZALRSC-NEXT: xor a5, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB13_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umin ptr %a, i8 %b monotonic ret i8 %1 } @@ -1194,6 +1744,29 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: mv a5, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB14_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1228,6 +1801,29 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: mv a5, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB14_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xchg ptr %a, i16 %b monotonic ret i16 %1 } @@ -1268,6 +1864,29 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: add a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB15_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_add_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1302,6 +1921,29 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: add a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB15_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw add ptr %a, i16 %b monotonic ret i16 %1 } @@ -1342,6 +1984,29 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: sub a5, a3, a1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB16_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1376,6 +2041,29 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: sub a5, a3, a1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB16_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw sub ptr %a, i16 %b monotonic ret i16 %1 } @@ -1410,6 +2098,28 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: not a3, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: or a1, a1, a3 +; RV32I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB17_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_and_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1438,6 +2148,28 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: not a3, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: or a1, a1, a3 +; RV64I-ZALRSC-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB17_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw and ptr %a, i16 %b monotonic ret i16 %1 } @@ -1479,6 +2211,30 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a5, a3, a1 +; RV32I-ZALRSC-NEXT: not a5, a5 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB18_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_nand_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1514,6 +2270,30 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a5, a3, a1 +; RV64I-ZALRSC-NEXT: not a5, a5 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB18_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw nand ptr %a, i16 %b monotonic ret i16 %1 } @@ -1544,6 +2324,24 @@ define signext i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: or a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB19_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_or_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1568,6 +2366,24 @@ define signext i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: or a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB19_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw or ptr %a, i16 %b monotonic ret i16 %1 } @@ -1598,6 +2414,24 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: srli a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: xor a4, a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB20_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xor_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -1622,6 +2456,24 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: srli a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: xor a4, a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a2) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB20_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xor ptr %a, i16 %b monotonic ret i16 %1 } @@ -1703,6 +2555,39 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a7, a1, .LBB21_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB21_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -1778,6 +2663,39 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a7, a1, .LBB21_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB21_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw max ptr %a, i16 %b monotonic ret i16 %1 } @@ -1859,6 +2777,39 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: slli a1, a1, 16 +; RV32I-ZALRSC-NEXT: li a4, 16 +; RV32I-ZALRSC-NEXT: andi a5, a0, 24 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: srai a1, a1, 16 +; RV32I-ZALRSC-NEXT: sll a3, a3, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sub a4, a4, a5 +; RV32I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a2) +; RV32I-ZALRSC-NEXT: and a7, a5, a3 +; RV32I-ZALRSC-NEXT: mv a6, a5 +; RV32I-ZALRSC-NEXT: sll a7, a7, a4 +; RV32I-ZALRSC-NEXT: sra a7, a7, a4 +; RV32I-ZALRSC-NEXT: bge a1, a7, .LBB22_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a1 +; RV32I-ZALRSC-NEXT: and a6, a6, a3 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB22_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -1934,6 +2885,39 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: slli a1, a1, 48 +; RV64I-ZALRSC-NEXT: li a4, 48 +; RV64I-ZALRSC-NEXT: andi a5, a0, 24 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: srai a1, a1, 48 +; RV64I-ZALRSC-NEXT: sllw a3, a3, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sub a4, a4, a5 +; RV64I-ZALRSC-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a2) +; RV64I-ZALRSC-NEXT: and a7, a5, a3 +; RV64I-ZALRSC-NEXT: mv a6, a5 +; RV64I-ZALRSC-NEXT: sll a7, a7, a4 +; RV64I-ZALRSC-NEXT: sra a7, a7, a4 +; RV64I-ZALRSC-NEXT: bge a1, a7, .LBB22_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a1 +; RV64I-ZALRSC-NEXT: and a6, a6, a3 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a2) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB22_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw min ptr %a, i16 %b monotonic ret i16 %1 } @@ -2011,6 +2995,33 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a6, a1, .LBB23_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB23_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -2082,6 +3093,33 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a6, a1, .LBB23_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB23_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umax ptr %a, i16 %b monotonic ret i16 %1 } @@ -2159,6 +3197,33 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a3, 16 +; RV32I-ZALRSC-NEXT: addi a3, a3, -1 +; RV32I-ZALRSC-NEXT: sll a4, a3, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a3 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a2) +; RV32I-ZALRSC-NEXT: and a6, a3, a4 +; RV32I-ZALRSC-NEXT: mv a5, a3 +; RV32I-ZALRSC-NEXT: bgeu a1, a6, .LBB24_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a3, a1 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a3, a5 +; RV32I-ZALRSC-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB24_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: srl a0, a3, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -2230,6 +3295,33 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i16_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a3, 16 +; RV64I-ZALRSC-NEXT: addi a3, a3, -1 +; RV64I-ZALRSC-NEXT: sllw a4, a3, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a3 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a2) +; RV64I-ZALRSC-NEXT: and a6, a3, a4 +; RV64I-ZALRSC-NEXT: mv a5, a3 +; RV64I-ZALRSC-NEXT: bgeu a1, a6, .LBB24_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a3, a1 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a3, a5 +; RV64I-ZALRSC-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a2) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB24_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: srlw a0, a3, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umin ptr %a, i16 %b monotonic ret i16 %1 } @@ -2250,6 +3342,17 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amoswap.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB25_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2265,6 +3368,17 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoswap.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB25_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xchg ptr %a, i32 %b monotonic ret i32 %1 } @@ -2285,6 +3399,17 @@ define signext i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amoadd.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: add a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB26_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_add_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2300,6 +3425,17 @@ define signext i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoadd.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB26_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw add ptr %a, i32 %b monotonic ret i32 %1 } @@ -2321,6 +3457,17 @@ define signext i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amoadd.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: sub a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB27_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2337,6 +3484,17 @@ define signext i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: amoadd.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB27_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw sub ptr %a, i32 %b monotonic ret i32 %1 } @@ -2357,6 +3515,17 @@ define signext i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amoand.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB28_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_and_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2372,6 +3541,17 @@ define signext i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoand.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB28_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw and ptr %a, i32 %b monotonic ret i32 %1 } @@ -2413,6 +3593,18 @@ define signext i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV32IA-ZACAS-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: and a3, a2, a1 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB29_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_nand_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2449,6 +3641,18 @@ define signext i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB29_1 ; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-ZACAS-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB29_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw nand ptr %a, i32 %b monotonic ret i32 %1 } @@ -2469,6 +3673,17 @@ define signext i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amoor.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: or a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB30_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_or_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2484,6 +3699,17 @@ define signext i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoor.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB30_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw or ptr %a, i32 %b monotonic ret i32 %1 } @@ -2504,6 +3730,17 @@ define signext i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amoxor.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: xor a3, a2, a1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB31_1 +; RV32I-ZALRSC-NEXT: # %bb.2: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xor_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2519,6 +3756,17 @@ define signext i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoxor.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB31_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xor ptr %a, i32 %b monotonic ret i32 %1 } @@ -2565,6 +3813,21 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amomax.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB32_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB32_3: # in Loop: Header=BB32_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB32_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_max_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -2608,6 +3871,22 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomax.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB32_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB32_3: # in Loop: Header=BB32_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB32_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw max ptr %a, i32 %b monotonic ret i32 %1 } @@ -2654,6 +3933,21 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amomin.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB33_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB33_3: # in Loop: Header=BB33_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB33_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_min_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -2697,6 +3991,22 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomin.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB33_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB33_3: # in Loop: Header=BB33_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB33_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw min ptr %a, i32 %b monotonic ret i32 %1 } @@ -2743,6 +4053,21 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amomaxu.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB34_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB34_3: # in Loop: Header=BB34_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB34_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umax_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -2786,6 +4111,22 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomaxu.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB34_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB34_3: # in Loop: Header=BB34_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB34_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umax ptr %a, i32 %b monotonic ret i32 %1 } @@ -2832,6 +4173,21 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV32IA-NEXT: amominu.w a0, a1, (a0) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a0) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: bgeu a1, a3, .LBB35_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a1 +; RV32I-ZALRSC-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB35_1 +; RV32I-ZALRSC-NEXT: # %bb.4: +; RV32I-ZALRSC-NEXT: mv a0, a2 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umin_i32_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 @@ -2875,6 +4231,22 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amominu.w a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: sext.w a2, a1 +; RV64I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB35_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB35_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umin ptr %a, i32 %b monotonic ret i32 %1 } @@ -2900,6 +4272,16 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_exchange_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xchg_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2914,6 +4296,17 @@ define signext i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoswap.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB36_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xchg ptr %a, i64 %b monotonic ret i64 %1 } @@ -2939,6 +4332,16 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_add_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_add_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2953,6 +4356,17 @@ define signext i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoadd.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: add a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB37_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw add ptr %a, i64 %b monotonic ret i64 %1 } @@ -2978,6 +4392,16 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_sub_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -2993,6 +4417,17 @@ define signext i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: amoadd.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB38_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw sub ptr %a, i64 %b monotonic ret i64 %1 } @@ -3018,6 +4453,16 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_and_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_and_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -3032,6 +4477,17 @@ define signext i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoand.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB39_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw and ptr %a, i64 %b monotonic ret i64 %1 } @@ -3057,6 +4513,16 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_nand_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_nand_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -3092,6 +4558,18 @@ define signext i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB40_1 ; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-ZACAS-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: and a3, a2, a1 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB40_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw nand ptr %a, i64 %b monotonic ret i64 %1 } @@ -3117,6 +4595,16 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_or_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_or_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -3131,6 +4619,17 @@ define signext i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoor.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: or a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB41_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw or ptr %a, i64 %b monotonic ret i64 %1 } @@ -3156,6 +4655,16 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -16 +; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: li a3, 0 +; RV32I-ZALRSC-NEXT: call __atomic_fetch_xor_8 +; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xor_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -3170,6 +4679,17 @@ define signext i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoxor.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a2, a1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB42_1 +; RV64I-ZALRSC-NEXT: # %bb.2: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw xor ptr %a, i64 %b monotonic ret i64 %1 } @@ -3283,6 +4803,60 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB43_2 +; RV32I-ZALRSC-NEXT: .LBB43_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB43_7 +; RV32I-ZALRSC-NEXT: .LBB43_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB43_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB43_5 +; RV32I-ZALRSC-NEXT: .LBB43_4: # in Loop: Header=BB43_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB43_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB43_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB43_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB43_1 +; RV32I-ZALRSC-NEXT: .LBB43_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_max_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -3323,6 +4897,21 @@ define signext i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomax.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a3, a1, .LBB43_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB43_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw max ptr %a, i64 %b monotonic ret i64 %1 } @@ -3436,6 +5025,60 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB44_2 +; RV32I-ZALRSC-NEXT: .LBB44_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB44_7 +; RV32I-ZALRSC-NEXT: .LBB44_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB44_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; RV32I-ZALRSC-NEXT: slt a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB44_5 +; RV32I-ZALRSC-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB44_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB44_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB44_1 +; RV32I-ZALRSC-NEXT: .LBB44_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_min_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -3476,6 +5119,21 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomin.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bge a1, a3, .LBB44_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB44_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw min ptr %a, i64 %b monotonic ret i64 %1 } @@ -3589,6 +5247,60 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB45_2 +; RV32I-ZALRSC-NEXT: .LBB45_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB45_7 +; RV32I-ZALRSC-NEXT: .LBB45_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB45_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB45_5 +; RV32I-ZALRSC-NEXT: .LBB45_4: # in Loop: Header=BB45_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB45_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: bnez a0, .LBB45_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB45_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB45_1 +; RV32I-ZALRSC-NEXT: .LBB45_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umax_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -3629,6 +5341,21 @@ define signext i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomaxu.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a3, a1, .LBB45_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB45_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umax ptr %a, i64 %b monotonic ret i64 %1 } @@ -3742,6 +5469,60 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: addi sp, sp, -32 +; RV32I-ZALRSC-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-ZALRSC-NEXT: mv s0, a2 +; RV32I-ZALRSC-NEXT: mv s1, a0 +; RV32I-ZALRSC-NEXT: lw a4, 0(a0) +; RV32I-ZALRSC-NEXT: lw a5, 4(a0) +; RV32I-ZALRSC-NEXT: mv s2, a1 +; RV32I-ZALRSC-NEXT: j .LBB46_2 +; RV32I-ZALRSC-NEXT: .LBB46_1: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; RV32I-ZALRSC-NEXT: sw a4, 8(sp) +; RV32I-ZALRSC-NEXT: sw a5, 12(sp) +; RV32I-ZALRSC-NEXT: addi a1, sp, 8 +; RV32I-ZALRSC-NEXT: mv a0, s1 +; RV32I-ZALRSC-NEXT: li a4, 0 +; RV32I-ZALRSC-NEXT: li a5, 0 +; RV32I-ZALRSC-NEXT: call __atomic_compare_exchange_8 +; RV32I-ZALRSC-NEXT: lw a4, 8(sp) +; RV32I-ZALRSC-NEXT: lw a5, 12(sp) +; RV32I-ZALRSC-NEXT: bnez a0, .LBB46_7 +; RV32I-ZALRSC-NEXT: .LBB46_2: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: beq a5, s0, .LBB46_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s0, a5 +; RV32I-ZALRSC-NEXT: j .LBB46_5 +; RV32I-ZALRSC-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1 +; RV32I-ZALRSC-NEXT: sltu a0, s2, a4 +; RV32I-ZALRSC-NEXT: .LBB46_5: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, a4 +; RV32I-ZALRSC-NEXT: mv a3, a5 +; RV32I-ZALRSC-NEXT: beqz a0, .LBB46_1 +; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1 +; RV32I-ZALRSC-NEXT: mv a2, s2 +; RV32I-ZALRSC-NEXT: mv a3, s0 +; RV32I-ZALRSC-NEXT: j .LBB46_1 +; RV32I-ZALRSC-NEXT: .LBB46_7: # %atomicrmw.end +; RV32I-ZALRSC-NEXT: mv a0, a4 +; RV32I-ZALRSC-NEXT: mv a1, a5 +; RV32I-ZALRSC-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-ZALRSC-NEXT: addi sp, sp, 32 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umin_i64_monotonic: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -3782,6 +5563,21 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: amominu.d a0, a1, (a0) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i64_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.d a2, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: bgeu a1, a3, .LBB46_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.d a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB46_1 +; RV64I-ZALRSC-NEXT: # %bb.4: +; RV64I-ZALRSC-NEXT: mv a0, a2 +; RV64I-ZALRSC-NEXT: ret %1 = atomicrmw umin ptr %a, i64 %b monotonic ret i64 %1 } @@ -3827,6 +5623,32 @@ define signext i8 @cmpxchg_i8_monotonic_monotonic_val0(ptr %ptr, i8 signext %cmp ; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val0: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a3, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a4, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: zext.b a2, a2 +; RV32I-ZALRSC-NEXT: sll a4, a4, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a5, (a3) +; RV32I-ZALRSC-NEXT: and a6, a5, a4 +; RV32I-ZALRSC-NEXT: bne a6, a1, .LBB47_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a5, a2 +; RV32I-ZALRSC-NEXT: and a6, a6, a4 +; RV32I-ZALRSC-NEXT: xor a6, a5, a6 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a3) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB47_1 +; RV32I-ZALRSC-NEXT: .LBB47_3: +; RV32I-ZALRSC-NEXT: srl a0, a5, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 24 +; RV32I-ZALRSC-NEXT: srai a0, a0, 24 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic_val0: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -3866,6 +5688,32 @@ define signext i8 @cmpxchg_i8_monotonic_monotonic_val0(ptr %ptr, i8 signext %cmp ; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val0: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a3, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a4, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: zext.b a2, a2 +; RV64I-ZALRSC-NEXT: sllw a4, a4, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a5, (a3) +; RV64I-ZALRSC-NEXT: and a6, a5, a4 +; RV64I-ZALRSC-NEXT: bne a6, a1, .LBB47_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a5, a2 +; RV64I-ZALRSC-NEXT: and a6, a6, a4 +; RV64I-ZALRSC-NEXT: xor a6, a5, a6 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a3) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB47_1 +; RV64I-ZALRSC-NEXT: .LBB47_3: +; RV64I-ZALRSC-NEXT: srlw a0, a5, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 56 +; RV64I-ZALRSC-NEXT: srai a0, a0, 56 +; RV64I-ZALRSC-NEXT: ret %1 = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic %2 = extractvalue { i8, i1 } %1, 0 ret i8 %2 @@ -3911,6 +5759,32 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(ptr %ptr, i8 signext %cmp, i8 sig ; RV32IA-NEXT: seqz a0, a1 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val1: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a3, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: li a4, 255 +; RV32I-ZALRSC-NEXT: zext.b a1, a1 +; RV32I-ZALRSC-NEXT: zext.b a2, a2 +; RV32I-ZALRSC-NEXT: sll a4, a4, a0 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sll a0, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a3) +; RV32I-ZALRSC-NEXT: and a5, a2, a4 +; RV32I-ZALRSC-NEXT: bne a5, a1, .LBB48_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a5, a2, a0 +; RV32I-ZALRSC-NEXT: and a5, a5, a4 +; RV32I-ZALRSC-NEXT: xor a5, a2, a5 +; RV32I-ZALRSC-NEXT: sc.w a5, a5, (a3) +; RV32I-ZALRSC-NEXT: bnez a5, .LBB48_1 +; RV32I-ZALRSC-NEXT: .LBB48_3: +; RV32I-ZALRSC-NEXT: and a2, a2, a4 +; RV32I-ZALRSC-NEXT: xor a1, a1, a2 +; RV32I-ZALRSC-NEXT: seqz a0, a1 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic_val1: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -3949,6 +5823,32 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(ptr %ptr, i8 signext %cmp, i8 sig ; RV64IA-NEXT: xor a1, a1, a2 ; RV64IA-NEXT: seqz a0, a1 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i8_monotonic_monotonic_val1: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a3, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: li a4, 255 +; RV64I-ZALRSC-NEXT: zext.b a1, a1 +; RV64I-ZALRSC-NEXT: zext.b a2, a2 +; RV64I-ZALRSC-NEXT: sllw a4, a4, a0 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sllw a0, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a3) +; RV64I-ZALRSC-NEXT: and a5, a2, a4 +; RV64I-ZALRSC-NEXT: bne a5, a1, .LBB48_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a5, a2, a0 +; RV64I-ZALRSC-NEXT: and a5, a5, a4 +; RV64I-ZALRSC-NEXT: xor a5, a2, a5 +; RV64I-ZALRSC-NEXT: sc.w a5, a5, (a3) +; RV64I-ZALRSC-NEXT: bnez a5, .LBB48_1 +; RV64I-ZALRSC-NEXT: .LBB48_3: +; RV64I-ZALRSC-NEXT: and a2, a2, a4 +; RV64I-ZALRSC-NEXT: xor a1, a1, a2 +; RV64I-ZALRSC-NEXT: seqz a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic %2 = extractvalue { i8, i1 } %1, 1 ret i1 %2 @@ -3996,6 +5896,33 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext % ; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val0: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a3, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a4, 16 +; RV32I-ZALRSC-NEXT: addi a4, a4, -1 +; RV32I-ZALRSC-NEXT: sll a5, a4, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a4 +; RV32I-ZALRSC-NEXT: and a2, a2, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sll a2, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a4, (a3) +; RV32I-ZALRSC-NEXT: and a6, a4, a5 +; RV32I-ZALRSC-NEXT: bne a6, a1, .LBB49_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a6, a4, a2 +; RV32I-ZALRSC-NEXT: and a6, a6, a5 +; RV32I-ZALRSC-NEXT: xor a6, a4, a6 +; RV32I-ZALRSC-NEXT: sc.w a6, a6, (a3) +; RV32I-ZALRSC-NEXT: bnez a6, .LBB49_1 +; RV32I-ZALRSC-NEXT: .LBB49_3: +; RV32I-ZALRSC-NEXT: srl a0, a4, a0 +; RV32I-ZALRSC-NEXT: slli a0, a0, 16 +; RV32I-ZALRSC-NEXT: srai a0, a0, 16 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic_val0: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -4036,6 +5963,33 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext % ; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val0: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a3, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a4, 16 +; RV64I-ZALRSC-NEXT: addi a4, a4, -1 +; RV64I-ZALRSC-NEXT: sllw a5, a4, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a4 +; RV64I-ZALRSC-NEXT: and a2, a2, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sllw a2, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a4, (a3) +; RV64I-ZALRSC-NEXT: and a6, a4, a5 +; RV64I-ZALRSC-NEXT: bne a6, a1, .LBB49_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a6, a4, a2 +; RV64I-ZALRSC-NEXT: and a6, a6, a5 +; RV64I-ZALRSC-NEXT: xor a6, a4, a6 +; RV64I-ZALRSC-NEXT: sc.w a6, a6, (a3) +; RV64I-ZALRSC-NEXT: bnez a6, .LBB49_1 +; RV64I-ZALRSC-NEXT: .LBB49_3: +; RV64I-ZALRSC-NEXT: srlw a0, a4, a0 +; RV64I-ZALRSC-NEXT: slli a0, a0, 48 +; RV64I-ZALRSC-NEXT: srai a0, a0, 48 +; RV64I-ZALRSC-NEXT: ret %1 = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic %2 = extractvalue { i16, i1 } %1, 0 ret i16 %2 @@ -4082,6 +6036,33 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16 ; RV32IA-NEXT: seqz a0, a1 ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val1: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a3, a0, -4 +; RV32I-ZALRSC-NEXT: slli a0, a0, 3 +; RV32I-ZALRSC-NEXT: lui a4, 16 +; RV32I-ZALRSC-NEXT: addi a4, a4, -1 +; RV32I-ZALRSC-NEXT: sll a5, a4, a0 +; RV32I-ZALRSC-NEXT: and a1, a1, a4 +; RV32I-ZALRSC-NEXT: and a2, a2, a4 +; RV32I-ZALRSC-NEXT: sll a1, a1, a0 +; RV32I-ZALRSC-NEXT: sll a0, a2, a0 +; RV32I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a2, (a3) +; RV32I-ZALRSC-NEXT: and a4, a2, a5 +; RV32I-ZALRSC-NEXT: bne a4, a1, .LBB50_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 +; RV32I-ZALRSC-NEXT: xor a4, a2, a0 +; RV32I-ZALRSC-NEXT: and a4, a4, a5 +; RV32I-ZALRSC-NEXT: xor a4, a2, a4 +; RV32I-ZALRSC-NEXT: sc.w a4, a4, (a3) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB50_1 +; RV32I-ZALRSC-NEXT: .LBB50_3: +; RV32I-ZALRSC-NEXT: and a2, a2, a5 +; RV32I-ZALRSC-NEXT: xor a1, a1, a2 +; RV32I-ZALRSC-NEXT: seqz a0, a1 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic_val1: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -4121,6 +6102,33 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16 ; RV64IA-NEXT: xor a1, a1, a2 ; RV64IA-NEXT: seqz a0, a1 ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i16_monotonic_monotonic_val1: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a3, a0, -4 +; RV64I-ZALRSC-NEXT: slli a0, a0, 3 +; RV64I-ZALRSC-NEXT: lui a4, 16 +; RV64I-ZALRSC-NEXT: addi a4, a4, -1 +; RV64I-ZALRSC-NEXT: sllw a5, a4, a0 +; RV64I-ZALRSC-NEXT: and a1, a1, a4 +; RV64I-ZALRSC-NEXT: and a2, a2, a4 +; RV64I-ZALRSC-NEXT: sllw a1, a1, a0 +; RV64I-ZALRSC-NEXT: sllw a0, a2, a0 +; RV64I-ZALRSC-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a2, (a3) +; RV64I-ZALRSC-NEXT: and a4, a2, a5 +; RV64I-ZALRSC-NEXT: bne a4, a1, .LBB50_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 +; RV64I-ZALRSC-NEXT: xor a4, a2, a0 +; RV64I-ZALRSC-NEXT: and a4, a4, a5 +; RV64I-ZALRSC-NEXT: xor a4, a2, a4 +; RV64I-ZALRSC-NEXT: sc.w a4, a4, (a3) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB50_1 +; RV64I-ZALRSC-NEXT: .LBB50_3: +; RV64I-ZALRSC-NEXT: and a2, a2, a5 +; RV64I-ZALRSC-NEXT: xor a1, a1, a2 +; RV64I-ZALRSC-NEXT: seqz a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic %2 = extractvalue { i16, i1 } %1, 1 ret i1 %2 @@ -4159,6 +6167,18 @@ define signext i32 @cmpxchg_i32_monotonic_monotonic_val0(ptr %ptr, i32 signext % ; RV32IA-ZACAS-NEXT: mv a0, a1 ; RV32IA-ZACAS-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val0: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a0) +; RV32I-ZALRSC-NEXT: bne a3, a1, .LBB51_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a4, a2, (a0) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB51_1 +; RV32I-ZALRSC-NEXT: .LBB51_3: +; RV32I-ZALRSC-NEXT: mv a0, a3 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic_val0: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -4190,6 +6210,18 @@ define signext i32 @cmpxchg_i32_monotonic_monotonic_val0(ptr %ptr, i32 signext % ; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0) ; RV64IA-ZACAS-NEXT: mv a0, a1 ; RV64IA-ZACAS-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val0: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a0) +; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB51_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a4, a2, (a0) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB51_1 +; RV64I-ZALRSC-NEXT: .LBB51_3: +; RV64I-ZALRSC-NEXT: mv a0, a3 +; RV64I-ZALRSC-NEXT: ret %1 = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic %2 = extractvalue { i32, i1 } %1, 0 ret i32 %2 @@ -4230,6 +6262,19 @@ define i1 @cmpxchg_i32_monotonic_monotonic_val1(ptr %ptr, i32 signext %cmp, i32 ; RV32IA-ZACAS-NEXT: seqz a0, a1 ; RV32IA-ZACAS-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val1: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a3, (a0) +; RV32I-ZALRSC-NEXT: bne a3, a1, .LBB52_3 +; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a4, a2, (a0) +; RV32I-ZALRSC-NEXT: bnez a4, .LBB52_1 +; RV32I-ZALRSC-NEXT: .LBB52_3: +; RV32I-ZALRSC-NEXT: xor a1, a3, a1 +; RV32I-ZALRSC-NEXT: seqz a0, a1 +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic_val1: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -4263,6 +6308,19 @@ define i1 @cmpxchg_i32_monotonic_monotonic_val1(ptr %ptr, i32 signext %cmp, i32 ; RV64IA-ZACAS-NEXT: xor a1, a3, a1 ; RV64IA-ZACAS-NEXT: seqz a0, a1 ; RV64IA-ZACAS-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_monotonic_val1: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a3, (a0) +; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB52_3 +; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a4, a2, (a0) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB52_1 +; RV64I-ZALRSC-NEXT: .LBB52_3: +; RV64I-ZALRSC-NEXT: xor a1, a3, a1 +; RV64I-ZALRSC-NEXT: seqz a0, a1 +; RV64I-ZALRSC-NEXT: ret %1 = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic %2 = extractvalue { i32, i1 } %1, 1 ret i1 %2 @@ -4304,6 +6362,27 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB53_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB53_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB53_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB53_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xchg_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4339,6 +6418,28 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: li a2, 1 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB53_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB53_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB53_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB53_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -4391,6 +6492,27 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB54_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB54_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: add a3, a0, a2 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB54_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB54_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: addi a2, a0, 1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_add_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4426,6 +6548,28 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: addi a2, a0, 1 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB54_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB54_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: add a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB54_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB54_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: addi a2, a1, 1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -4479,6 +6623,27 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB55_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB55_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: sub a3, a0, a2 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB55_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB55_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: addi a2, a0, -1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_sub_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4514,6 +6679,28 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: addi a2, a0, -1 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB55_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB55_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: sub a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB55_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB55_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: addi a2, a1, -1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -4567,6 +6754,27 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB56_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB56_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: and a3, a0, a2 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB56_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB56_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: andi a2, a0, 1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_and_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4602,6 +6810,28 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: andi a2, a0, 1 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB56_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB56_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: and a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB56_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB56_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: andi a2, a1, 1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -4685,6 +6915,28 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-ZACAS-NEXT: mv a0, a1 ; RV32IA-ZACAS-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB57_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB57_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: and a3, a0, a2 +; RV32I-ZALRSC-NEXT: not a3, a3 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB57_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB57_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: andi a2, a0, 1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_nand_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4750,6 +7002,28 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-ZACAS-NEXT: sw a2, 0(a0) ; RV64IA-ZACAS-NEXT: mv a0, a1 ; RV64IA-ZACAS-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_nand_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a1, 1 +; RV64I-ZALRSC-NEXT: mv a1, a0 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB57_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB57_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a0, (a1) +; RV64I-ZALRSC-NEXT: and a3, a0, a2 +; RV64I-ZALRSC-NEXT: not a3, a3 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB57_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB57_2: # %else +; RV64I-ZALRSC-NEXT: lw a0, 0(a1) +; RV64I-ZALRSC-NEXT: andi a2, a0, 1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a1) +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -4803,6 +7077,27 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind { ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB58_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB58_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: or a3, a0, a2 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB58_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB58_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: ori a2, a0, 1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_or_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4838,6 +7133,28 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind { ; RV64IA-NEXT: ori a2, a0, 1 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB58_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB58_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: or a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB58_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB58_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: ori a2, a1, 1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -4891,6 +7208,27 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB59_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB59_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: xor a3, a0, a2 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB59_3 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB59_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: xori a2, a0, 1 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_xor_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a1, a1, 1 @@ -4926,6 +7264,28 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: xori a2, a0, 1 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB59_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB59_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: xor a3, a1, a2 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB59_3 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB59_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: xori a2, a1, 1 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -5007,6 +7367,37 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB60_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB60_5: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: mv a3, a0 +; RV32I-ZALRSC-NEXT: bge a3, a2, .LBB60_7 +; RV32I-ZALRSC-NEXT: # %bb.6: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: .LBB60_7: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB60_5 +; RV32I-ZALRSC-NEXT: # %bb.8: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB60_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: mv a2, a0 +; RV32I-ZALRSC-NEXT: bgtz a0, .LBB60_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %else +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB60_4: # %else +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_max_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -5070,6 +7461,37 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: .LBB60_4: # %else ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a1, 1 +; RV64I-ZALRSC-NEXT: mv a1, a0 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB60_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB60_5: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a0, (a1) +; RV64I-ZALRSC-NEXT: mv a3, a0 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB60_7 +; RV64I-ZALRSC-NEXT: # %bb.6: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB60_7: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB60_5 +; RV64I-ZALRSC-NEXT: # %bb.8: # %then +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB60_2: # %else +; RV64I-ZALRSC-NEXT: lw a0, 0(a1) +; RV64I-ZALRSC-NEXT: mv a2, a0 +; RV64I-ZALRSC-NEXT: bgtz a0, .LBB60_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %else +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB60_4: # %else +; RV64I-ZALRSC-NEXT: sw a2, 0(a1) +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -5155,6 +7577,37 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB61_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB61_5: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: mv a3, a0 +; RV32I-ZALRSC-NEXT: bge a2, a3, .LBB61_7 +; RV32I-ZALRSC-NEXT: # %bb.6: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: .LBB61_7: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB61_5 +; RV32I-ZALRSC-NEXT: # %bb.8: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB61_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: mv a2, a0 +; RV32I-ZALRSC-NEXT: blez a0, .LBB61_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %else +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB61_4: # %else +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_min_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -5220,6 +7673,37 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: .LBB61_4: # %else ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a1, 1 +; RV64I-ZALRSC-NEXT: mv a1, a0 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB61_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB61_5: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a0, (a1) +; RV64I-ZALRSC-NEXT: mv a3, a0 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB61_7 +; RV64I-ZALRSC-NEXT: # %bb.6: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB61_7: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB61_5 +; RV64I-ZALRSC-NEXT: # %bb.8: # %then +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB61_2: # %else +; RV64I-ZALRSC-NEXT: lw a0, 0(a1) +; RV64I-ZALRSC-NEXT: mv a2, a0 +; RV64I-ZALRSC-NEXT: blez a0, .LBB61_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %else +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB61_4: # %else +; RV64I-ZALRSC-NEXT: sw a2, 0(a1) +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -5290,6 +7774,34 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB62_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB62_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: mv a3, a0 +; RV32I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: .LBB62_5: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB62_3 +; RV32I-ZALRSC-NEXT: # %bb.6: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB62_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: seqz a2, a0 +; RV32I-ZALRSC-NEXT: add a2, a0, a2 +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umax_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -5347,6 +7859,35 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: add a2, a0, a2 ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a1, a1, 1 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB62_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB62_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a1, (a0) +; RV64I-ZALRSC-NEXT: mv a3, a1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB62_5: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB62_3 +; RV64I-ZALRSC-NEXT: # %bb.6: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB62_2: # %else +; RV64I-ZALRSC-NEXT: lw a1, 0(a0) +; RV64I-ZALRSC-NEXT: seqz a2, a1 +; RV64I-ZALRSC-NEXT: add a2, a1, a2 +; RV64I-ZALRSC-NEXT: sw a2, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a1 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -5434,6 +7975,38 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret ; +; RV32I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: andi a2, a1, 1 +; RV32I-ZALRSC-NEXT: mv a1, a0 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB63_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB63_5: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w a0, (a1) +; RV32I-ZALRSC-NEXT: mv a3, a0 +; RV32I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7 +; RV32I-ZALRSC-NEXT: # %bb.6: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV32I-ZALRSC-NEXT: mv a3, a2 +; RV32I-ZALRSC-NEXT: .LBB63_7: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB63_5 +; RV32I-ZALRSC-NEXT: # %bb.8: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB63_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a1) +; RV32I-ZALRSC-NEXT: li a3, 1 +; RV32I-ZALRSC-NEXT: mv a2, a0 +; RV32I-ZALRSC-NEXT: bltu a0, a3, .LBB63_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %else +; RV32I-ZALRSC-NEXT: li a2, 1 +; RV32I-ZALRSC-NEXT: .LBB63_4: # %else +; RV32I-ZALRSC-NEXT: sw a2, 0(a1) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: atomicrmw_umin_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -5501,6 +8074,38 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NEXT: .LBB63_4: # %else ; RV64IA-NEXT: sw a2, 0(a1) ; RV64IA-NEXT: ret +; +; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: andi a2, a1, 1 +; RV64I-ZALRSC-NEXT: mv a1, a0 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB63_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB63_5: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w a0, (a1) +; RV64I-ZALRSC-NEXT: mv a3, a0 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7 +; RV64I-ZALRSC-NEXT: # %bb.6: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV64I-ZALRSC-NEXT: mv a3, a2 +; RV64I-ZALRSC-NEXT: .LBB63_7: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) +; RV64I-ZALRSC-NEXT: bnez a3, .LBB63_5 +; RV64I-ZALRSC-NEXT: # %bb.8: # %then +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB63_2: # %else +; RV64I-ZALRSC-NEXT: lw a0, 0(a1) +; RV64I-ZALRSC-NEXT: li a3, 1 +; RV64I-ZALRSC-NEXT: mv a2, a0 +; RV64I-ZALRSC-NEXT: bltu a0, a3, .LBB63_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %else +; RV64I-ZALRSC-NEXT: li a2, 1 +; RV64I-ZALRSC-NEXT: .LBB63_4: # %else +; RV64I-ZALRSC-NEXT: sw a2, 0(a1) +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: @@ -5570,6 +8175,25 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3 ; RV32IA-ZACAS-NEXT: lw a0, 0(a0) ; RV32IA-ZACAS-NEXT: ret ; +; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_crossbb: +; RV32I-ZALRSC: # %bb.0: +; RV32I-ZALRSC-NEXT: mv a4, a0 +; RV32I-ZALRSC-NEXT: beqz a3, .LBB64_2 +; RV32I-ZALRSC-NEXT: # %bb.1: # %then +; RV32I-ZALRSC-NEXT: .LBB64_3: # %then +; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32I-ZALRSC-NEXT: lr.w.aqrl a0, (a4) +; RV32I-ZALRSC-NEXT: bne a0, a1, .LBB64_5 +; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB64_3 Depth=1 +; RV32I-ZALRSC-NEXT: sc.w.rl a3, a2, (a4) +; RV32I-ZALRSC-NEXT: bnez a3, .LBB64_3 +; RV32I-ZALRSC-NEXT: .LBB64_5: # %then +; RV32I-ZALRSC-NEXT: ret +; RV32I-ZALRSC-NEXT: .LBB64_2: # %else +; RV32I-ZALRSC-NEXT: lw a0, 0(a4) +; RV32I-ZALRSC-NEXT: ret +; ; RV64I-LABEL: cmpxchg_i32_monotonic_crossbb: ; RV64I: # %bb.0: ; RV64I-NEXT: beqz a3, .LBB64_2 @@ -5620,6 +8244,26 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3 ; RV64IA-ZACAS-NEXT: .LBB64_2: # %else ; RV64IA-ZACAS-NEXT: lw a0, 0(a0) ; RV64IA-ZACAS-NEXT: ret +; +; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_crossbb: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: beqz a3, .LBB64_2 +; RV64I-ZALRSC-NEXT: # %bb.1: # %then +; RV64I-ZALRSC-NEXT: .LBB64_3: # %then +; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a0) +; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB64_5 +; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB64_3 Depth=1 +; RV64I-ZALRSC-NEXT: sc.w.rl a4, a2, (a0) +; RV64I-ZALRSC-NEXT: bnez a4, .LBB64_3 +; RV64I-ZALRSC-NEXT: .LBB64_5: # %then +; RV64I-ZALRSC-NEXT: sext.w a0, a3 +; RV64I-ZALRSC-NEXT: ret +; RV64I-ZALRSC-NEXT: .LBB64_2: # %else +; RV64I-ZALRSC-NEXT: lw a3, 0(a0) +; RV64I-ZALRSC-NEXT: sext.w a0, a3 +; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else then: diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 693a40d..5e5f2b7 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -217,6 +217,11 @@ ; CHECK-NEXT: xsfmm64t - 'XSfmm64t' (TE=64 configuration). ; CHECK-NEXT: xsfmmbase - 'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero). ; CHECK-NEXT: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions). +; CHECK-NEXT: xsfvfbfexp16e - 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16). +; CHECK-NEXT: xsfvfexp16e - 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision). +; CHECK-NEXT: xsfvfexp32e - 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision). +; CHECK-NEXT: xsfvfexpa - 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction). +; CHECK-NEXT: xsfvfexpa64e - 'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision). ; CHECK-NEXT: xsfvfnrclipxfqf - 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions). ; CHECK-NEXT: xsfvfwmaccqqq - 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4)). ; CHECK-NEXT: xsfvqmaccdod - 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)). diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll index dcb70f8..f9527ef 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -45,6 +45,32 @@ define i32 @bclr_i32_no_mask(i32 %a, i32 %b) nounwind { ret i32 %and1 } +define i32 @bclr_i32_mask_multiple(i32 %a, i32 %b, i32 %shamt) nounwind { +; RV32I-LABEL: bclr_i32_mask_multiple: +; RV32I: # %bb.0: +; RV32I-NEXT: li a3, 1 +; RV32I-NEXT: sll a2, a3, a2 +; RV32I-NEXT: not a3, a2 +; RV32I-NEXT: and a0, a3, a0 +; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBS-LABEL: bclr_i32_mask_multiple: +; RV32ZBS: # %bb.0: +; RV32ZBS-NEXT: bclr a0, a0, a2 +; RV32ZBS-NEXT: bset a1, a1, a2 +; RV32ZBS-NEXT: add a0, a0, a1 +; RV32ZBS-NEXT: ret + %shamt_masked = and i32 %shamt, 63 + %shl = shl nuw i32 1, %shamt_masked + %neg = xor i32 %shl, -1 + %and = and i32 %neg, %a + %or = or i32 %b, %shl + %c = add i32 %and, %or + ret i32 %c +} + define i64 @bclr_i64(i64 %a, i64 %b) nounwind { ; RV32I-LABEL: bclr_i64: ; RV32I: # %bb.0: @@ -301,17 +327,17 @@ define i64 @bext_i64(i64 %a, i64 %b) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a3, a2, 63 ; CHECK-NEXT: addi a4, a3, -32 -; CHECK-NEXT: bltz a4, .LBB12_2 +; CHECK-NEXT: bltz a4, .LBB13_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: srl a0, a1, a3 -; CHECK-NEXT: j .LBB12_3 -; CHECK-NEXT: .LBB12_2: +; CHECK-NEXT: j .LBB13_3 +; CHECK-NEXT: .LBB13_2: ; CHECK-NEXT: srl a0, a0, a2 ; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: not a2, a3 ; CHECK-NEXT: sll a1, a1, a2 ; CHECK-NEXT: or a0, a0, a1 -; CHECK-NEXT: .LBB12_3: +; CHECK-NEXT: .LBB13_3: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: ret @@ -789,17 +815,17 @@ define i64 @bset_trailing_ones_i64_mask(i64 %a) nounwind { ; CHECK-NEXT: li a3, -1 ; CHECK-NEXT: addi a1, a2, -32 ; CHECK-NEXT: sll a0, a3, a0 -; CHECK-NEXT: bltz a1, .LBB43_2 +; CHECK-NEXT: bltz a1, .LBB44_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sll a2, a3, a2 -; CHECK-NEXT: j .LBB43_3 -; CHECK-NEXT: .LBB43_2: +; CHECK-NEXT: j .LBB44_3 +; CHECK-NEXT: .LBB44_2: ; CHECK-NEXT: not a2, a2 ; CHECK-NEXT: lui a3, 524288 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: srl a2, a3, a2 ; CHECK-NEXT: or a2, a0, a2 -; CHECK-NEXT: .LBB43_3: +; CHECK-NEXT: .LBB44_3: ; CHECK-NEXT: srai a1, a1, 31 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: not a1, a2 @@ -817,17 +843,17 @@ define i64 @bset_trailing_ones_i64_no_mask(i64 %a) nounwind { ; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: addi a2, a0, -32 ; CHECK-NEXT: sll a1, a1, a0 -; CHECK-NEXT: bltz a2, .LBB44_2 +; CHECK-NEXT: bltz a2, .LBB45_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 -; CHECK-NEXT: j .LBB44_3 -; CHECK-NEXT: .LBB44_2: +; CHECK-NEXT: j .LBB45_3 +; CHECK-NEXT: .LBB45_2: ; CHECK-NEXT: not a0, a0 ; CHECK-NEXT: lui a3, 524288 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: srl a0, a3, a0 ; CHECK-NEXT: or a0, a1, a0 -; CHECK-NEXT: .LBB44_3: +; CHECK-NEXT: .LBB45_3: ; CHECK-NEXT: srai a2, a2, 31 ; CHECK-NEXT: and a2, a2, a1 ; CHECK-NEXT: not a1, a0 diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll index b4edcf6c..d42bc8e 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll @@ -110,6 +110,32 @@ define i64 @bclr_i64_no_mask(i64 %a, i64 %b) nounwind { ret i64 %and1 } +define i64 @bclr_i64_mask_multiple(i64 %a, i64 %b, i64 %shamt) nounwind { +; RV64I-LABEL: bclr_i64_mask_multiple: +; RV64I: # %bb.0: +; RV64I-NEXT: li a3, 1 +; RV64I-NEXT: sll a2, a3, a2 +; RV64I-NEXT: not a3, a2 +; RV64I-NEXT: and a0, a3, a0 +; RV64I-NEXT: or a1, a1, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBS-LABEL: bclr_i64_mask_multiple: +; RV64ZBS: # %bb.0: +; RV64ZBS-NEXT: bclr a0, a0, a2 +; RV64ZBS-NEXT: bset a1, a1, a2 +; RV64ZBS-NEXT: add a0, a0, a1 +; RV64ZBS-NEXT: ret + %shamt_masked = and i64 %shamt, 63 + %shl = shl nuw i64 1, %shamt_masked + %neg = xor i64 %shl, -1 + %and = and i64 %neg, %a + %or = or i64 %b, %shl + %c = add i64 %and, %or + ret i64 %c +} + define signext i32 @bset_i32(i32 signext %a, i32 signext %b) nounwind { ; RV64I-LABEL: bset_i32: ; RV64I: # %bb.0: @@ -372,19 +398,19 @@ define void @bext_i32_trunc(i32 signext %0, i32 signext %1) { ; RV64I: # %bb.0: ; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: andi a0, a0, 1 -; RV64I-NEXT: beqz a0, .LBB19_2 +; RV64I-NEXT: beqz a0, .LBB20_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB19_2: +; RV64I-NEXT: .LBB20_2: ; RV64I-NEXT: tail bar ; ; RV64ZBS-LABEL: bext_i32_trunc: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bext a0, a0, a1 -; RV64ZBS-NEXT: beqz a0, .LBB19_2 +; RV64ZBS-NEXT: beqz a0, .LBB20_2 ; RV64ZBS-NEXT: # %bb.1: ; RV64ZBS-NEXT: ret -; RV64ZBS-NEXT: .LBB19_2: +; RV64ZBS-NEXT: .LBB20_2: ; RV64ZBS-NEXT: tail bar %3 = shl i32 1, %1 %4 = and i32 %3, %0 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWBufferDynamicIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWBufferDynamicIdx.ll index cce1eda..1aee688 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWBufferDynamicIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWBufferDynamicIdx.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %} %"__cblayout_$Globals" = type <{ i32 }> @@ -9,7 +10,6 @@ ; CHECK: OpCapability Shader ; CHECK: OpCapability StorageTexelBufferArrayDynamicIndexingEXT - define void @main() local_unnamed_addr #0 { entry: %"$Globals.cb_h.i.i" = tail call target("spirv.VulkanBuffer", target("spirv.Layout", %"__cblayout_$Globals", 4, 0), 2, 0) @"llvm.spv.resource.handlefromimplicitbinding.tspirv.VulkanBuffer_tspirv.Layout_s___cblayout_$Globalss_4_0t_2_0t"(i32 1, i32 0, i32 1, i32 0, ptr nonnull @"$Globals.str") @@ -19,4 +19,8 @@ entry: %2 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %1, i32 98) store i32 99, ptr addrspace(11) %2, align 4 ret void -}
\ No newline at end of file +} + +!hlsl.cbs = !{!0} + +!0 = !{ptr @"$Globals.cb", ptr addrspace(12) @i} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWStructuredBufferDynamicIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWStructuredBufferDynamicIdx.ll index da69a2f..163fc9d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWStructuredBufferDynamicIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/DynamicIdx/RWStructuredBufferDynamicIdx.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %} %"__cblayout_$Globals" = type <{ i32 }> @@ -19,3 +20,7 @@ entry: store i32 98, ptr addrspace(11) %2, align 4 ret void } + +!hlsl.cbs = !{!0} + +!0 = !{ptr @"$Globals.cb", ptr addrspace(12) @i} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/TypedBufferLoad.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/TypedBufferLoad.ll new file mode 100644 index 0000000..7c44b6d --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/TypedBufferLoad.ll @@ -0,0 +1,43 @@ +; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %} + +; When accessing read-only `Buffer` types, SPIR-V should use `OpImageFetch` instead of `OpImageRead`. +; https://github.com/llvm/llvm-project/issues/162891 + +; CHECK-DAG: OpCapability SampledBuffer +; CHECK-DAG: OpCapability ImageBuffer +; CHECK-DAG: [[TypeInt:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[TypeImageBuffer:%[0-9]+]] = OpTypeImage [[TypeInt]] Buffer 2 0 0 1 Unknown +; CHECK-DAG: [[TypePtrImageBuffer:%[0-9]+]] = OpTypePointer UniformConstant [[TypeImageBuffer]] +; CHECK-DAG: [[TypeVector:%[0-9]+]] = OpTypeVector [[TypeInt]] 4 +; CHECK-DAG: [[Index:%[0-9]+]] = OpConstant [[TypeInt]] 98 +; CHECK-DAG: [[Variable:%[0-9]+]] = OpVariable [[TypePtrImageBuffer]] UniformConstant +@.str = private unnamed_addr constant [7 x i8] c"rwbuff\00", align 1 +@.str.2 = private unnamed_addr constant [5 x i8] c"buff\00", align 1 +@.str.4 = private unnamed_addr constant [8 x i8] c"unknown\00", align 1 + +define void @main() local_unnamed_addr #0 { + %1 = tail call target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) @llvm.spv.resource.handlefromimplicitbinding.tspirv.Image_i32_5_2_0_0_2_33t(i32 0, i32 0, i32 1, i32 0, ptr nonnull @.str) + %2 = tail call target("spirv.Image", i32, 5, 2, 0, 0, 1, 0) @llvm.spv.resource.handlefromimplicitbinding.tspirv.Image_i32_5_2_0_0_1_0t(i32 1, i32 0, i32 1, i32 0, ptr nonnull @.str.2) + %3 = tail call target("spirv.Image", i32, 5, 2, 0, 0, 0, 0) @llvm.spv.resource.handlefromimplicitbinding.tspirv.Image_i32_5_2_0_0_0_0t(i32 2, i32 0, i32 1, i32 0, ptr nonnull @.str.4) + %4 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_1_0t(target("spirv.Image", i32, 5, 2, 0, 0, 1, 0) %2, i32 98) +; CHECK: [[Load:%[0-9]+]] = OpLoad [[TypeImageBuffer]] [[Variable]] +; CHECK: [[ImageFetch:%[0-9]+]] = OpImageFetch [[TypeVector]] [[Load]] [[Index]] +; CHECK: {{.*}} = OpCompositeExtract [[TypeInt]] [[ImageFetch]] 0 + %5 = load i32, ptr addrspace(11) %4, align 4 + %6 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %1, i32 99) + store i32 %5, ptr addrspace(11) %6, align 4 + %7 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %1, i32 96) +; CHECK: {{%[0-9]+}} = OpLoad {{.*}} +; CHECK: {{%[0-9]+}} = OpImageRead {{.*}} + %8 = load i32, ptr addrspace(11) %7, align 4 + %9 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %1, i32 97) + store i32 %8, ptr addrspace(11) %9, align 4 + %10 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_0_0t(target("spirv.Image", i32, 5, 2, 0, 0, 0, 0) %3, i32 94) +; CHECK: {{%[0-9]+}} = OpLoad {{.*}} +; CHECK: {{%[0-9]+}} = OpImageRead {{.*}} + %11 = load i32, ptr addrspace(11) %10, align 4 + %12 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %1, i32 95) + store i32 %11, ptr addrspace(11) %12, align 4 + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/int-conv-14.ll b/llvm/test/CodeGen/SystemZ/int-conv-14.ll index 98dc88f..baab5ac 100644 --- a/llvm/test/CodeGen/SystemZ/int-conv-14.ll +++ b/llvm/test/CodeGen/SystemZ/int-conv-14.ll @@ -55,14 +55,15 @@ define i128 @f4(ptr %ptr) { } ; Truncation to i64. -define i64 @f5(i128 %a) { +define i64 @f5(i128 %a, i128 %b) { ; CHECK-LABEL: f5: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvg %r2, %v0, 1 ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i64 ret i64 %res } @@ -134,15 +135,16 @@ define i128 @f10(ptr %ptr) { } ; Truncation to i32. -define i32 @f11(i128 %a) { +define i32 @f11(i128 %a, i128 %b) { ; CHECK-LABEL: f11: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i32 ret i32 %res } @@ -215,15 +217,16 @@ define i128 @f16(ptr %ptr) { } ; Truncation to i16. -define i16 @f17(i128 %a) { +define i16 @f17(i128 %a, i128 %b) { ; CHECK-LABEL: f17: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i16 ret i16 %res } @@ -296,15 +299,16 @@ define i128 @f22(ptr %ptr) { } ; Truncation to i8. -define i8 @f23(i128 %a) { +define i8 @f23(i128 %a, i128 %b) { ; CHECK-LABEL: f23: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i8 ret i8 %res } @@ -385,15 +389,16 @@ define i128 @f28(ptr %ptr) { } ; Truncation to i1. -define i1 @f29(i128 %a) { +define i1 @f29(i128 %a, i128 %b) { ; CHECK-LABEL: f29: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i1 ret i1 %res } diff --git a/llvm/test/CodeGen/SystemZ/int-conv-15.ll b/llvm/test/CodeGen/SystemZ/int-conv-15.ll index 0d8ee75..f2c9ee5 100644 --- a/llvm/test/CodeGen/SystemZ/int-conv-15.ll +++ b/llvm/test/CodeGen/SystemZ/int-conv-15.ll @@ -55,14 +55,15 @@ define i128 @f4(ptr %ptr) { } ; Truncation to i64. -define i64 @f5(i128 %a) { +define i64 @f5(i128 %a, i128 %b) { ; CHECK-LABEL: f5: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvg %r2, %v0, 1 ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i64 ret i64 %res } @@ -134,15 +135,16 @@ define i128 @f10(ptr %ptr) { } ; Truncation to i32. -define i32 @f11(i128 %a) { +define i32 @f11(i128 %a, i128 %b) { ; CHECK-LABEL: f11: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i32 ret i32 %res } @@ -215,15 +217,16 @@ define i128 @f16(ptr %ptr) { } ; Truncation to i16. -define i16 @f17(i128 %a) { +define i16 @f17(i128 %a, i128 %b) { ; CHECK-LABEL: f17: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i16 ret i16 %res } @@ -296,15 +299,16 @@ define i128 @f22(ptr %ptr) { } ; Truncation to i8. -define i8 @f23(i128 %a) { +define i8 @f23(i128 %a, i128 %b) { ; CHECK-LABEL: f23: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i8 ret i8 %res } @@ -383,15 +387,16 @@ define i128 @f28(ptr %ptr) { } ; Truncation to i1. -define i1 @f29(i128 %a) { +define i1 @f29(i128 %a, i128 %b) { ; CHECK-LABEL: f29: ; CHECK: # %bb.0: -; CHECK-NEXT: vl %v0, 0(%r2), 3 -; CHECK-NEXT: vaq %v0, %v0, %v0 +; CHECK-NEXT: vl %v0, 0(%r3), 3 +; CHECK-NEXT: vl %v1, 0(%r2), 3 +; CHECK-NEXT: vaq %v0, %v1, %v0 ; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: br %r14 - %op = add i128 %a, %a + %op = add i128 %a, %b %res = trunc i128 %op to i1 ret i1 %res } diff --git a/llvm/test/CodeGen/X86/bitcnt-big-integer.ll b/llvm/test/CodeGen/X86/bitcnt-big-integer.ll new file mode 100644 index 0000000..13149d7 --- /dev/null +++ b/llvm/test/CodeGen/X86/bitcnt-big-integer.ll @@ -0,0 +1,3021 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 -mattr=+avx512vpopcntdq | FileCheck %s --check-prefixes=CHECK,AVX512 + +; +; CTPOP +; + +define i32 @test_ctpop_i128(i128 %a0) nounwind { +; CHECK-LABEL: test_ctpop_i128: +; CHECK: # %bb.0: +; CHECK-NEXT: popcntq %rsi, %rcx +; CHECK-NEXT: popcntq %rdi, %rax +; CHECK-NEXT: addl %ecx, %eax +; CHECK-NEXT: # kill: def $eax killed $eax killed $rax +; CHECK-NEXT: retq + %cnt = call i128 @llvm.ctpop.i128(i128 %a0) + %res = trunc i128 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctpop_i128(ptr %p0) nounwind { +; CHECK-LABEL: load_ctpop_i128: +; CHECK: # %bb.0: +; CHECK-NEXT: popcntq 8(%rdi), %rcx +; CHECK-NEXT: popcntq (%rdi), %rax +; CHECK-NEXT: addl %ecx, %eax +; CHECK-NEXT: # kill: def $eax killed $eax killed $rax +; CHECK-NEXT: retq + %a0 = load i128, ptr %p0 + %cnt = call i128 @llvm.ctpop.i128(i128 %a0) + %res = trunc i128 %cnt to i32 + ret i32 %res +} + +define i32 @test_ctpop_i256(i256 %a0) nounwind { +; CHECK-LABEL: test_ctpop_i256: +; CHECK: # %bb.0: +; CHECK-NEXT: popcntq %rcx, %rax +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: popcntq %rdx, %rcx +; CHECK-NEXT: addl %eax, %ecx +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: popcntq %rsi, %rdx +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: popcntq %rdi, %rax +; CHECK-NEXT: addl %edx, %eax +; CHECK-NEXT: addl %ecx, %eax +; CHECK-NEXT: # kill: def $eax killed $eax killed $rax +; CHECK-NEXT: retq + %cnt = call i256 @llvm.ctpop.i256(i256 %a0) + %res = trunc i256 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctpop_i256(ptr %p0) nounwind { +; SSE-LABEL: load_ctpop_i256: +; SSE: # %bb.0: +; SSE-NEXT: popcntq 24(%rdi), %rcx +; SSE-NEXT: popcntq 16(%rdi), %rdx +; SSE-NEXT: popcntq 8(%rdi), %rsi +; SSE-NEXT: popcntq (%rdi), %rax +; SSE-NEXT: addl %ecx, %edx +; SSE-NEXT: addl %esi, %eax +; SSE-NEXT: addl %edx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctpop_i256: +; AVX2: # %bb.0: +; AVX2-NEXT: popcntq 24(%rdi), %rax +; AVX2-NEXT: popcntq 16(%rdi), %rcx +; AVX2-NEXT: addl %eax, %ecx +; AVX2-NEXT: popcntq 8(%rdi), %rdx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq (%rdi), %rax +; AVX2-NEXT: addl %edx, %eax +; AVX2-NEXT: addl %ecx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctpop_i256: +; AVX512: # %bb.0: +; AVX512-NEXT: popcntq 24(%rdi), %rax +; AVX512-NEXT: popcntq 16(%rdi), %rcx +; AVX512-NEXT: addl %eax, %ecx +; AVX512-NEXT: popcntq 8(%rdi), %rdx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq (%rdi), %rax +; AVX512-NEXT: addl %edx, %eax +; AVX512-NEXT: addl %ecx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i256, ptr %p0 + %cnt = call i256 @llvm.ctpop.i256(i256 %a0) + %res = trunc i256 %cnt to i32 + ret i32 %res +} + +define i32 @test_ctpop_i512(i512 %a0) nounwind { +; CHECK-LABEL: test_ctpop_i512: +; CHECK: # %bb.0: +; CHECK-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; CHECK-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; CHECK-NEXT: addl %eax, %r10d +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: popcntq %r9, %rax +; CHECK-NEXT: popcntq %r8, %r8 +; CHECK-NEXT: addl %eax, %r8d +; CHECK-NEXT: addl %r10d, %r8d +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: popcntq %rcx, %rax +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: popcntq %rdx, %rcx +; CHECK-NEXT: addl %eax, %ecx +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: popcntq %rsi, %rdx +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: popcntq %rdi, %rax +; CHECK-NEXT: addl %edx, %eax +; CHECK-NEXT: addl %ecx, %eax +; CHECK-NEXT: addl %r8d, %eax +; CHECK-NEXT: # kill: def $eax killed $eax killed $rax +; CHECK-NEXT: retq + %cnt = call i512 @llvm.ctpop.i512(i512 %a0) + %res = trunc i512 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctpop_i512(ptr %p0) nounwind { +; SSE-LABEL: load_ctpop_i512: +; SSE: # %bb.0: +; SSE-NEXT: popcntq 56(%rdi), %rax +; SSE-NEXT: popcntq 48(%rdi), %rcx +; SSE-NEXT: popcntq 40(%rdi), %rdx +; SSE-NEXT: popcntq 32(%rdi), %rsi +; SSE-NEXT: addl %eax, %ecx +; SSE-NEXT: addl %edx, %esi +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq 24(%rdi), %rax +; SSE-NEXT: addl %ecx, %esi +; SSE-NEXT: xorl %ecx, %ecx +; SSE-NEXT: popcntq 16(%rdi), %rcx +; SSE-NEXT: addl %eax, %ecx +; SSE-NEXT: xorl %edx, %edx +; SSE-NEXT: popcntq 8(%rdi), %rdx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq (%rdi), %rax +; SSE-NEXT: addl %edx, %eax +; SSE-NEXT: addl %ecx, %eax +; SSE-NEXT: addl %esi, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctpop_i512: +; AVX2: # %bb.0: +; AVX2-NEXT: popcntq 56(%rdi), %rax +; AVX2-NEXT: popcntq 48(%rdi), %rcx +; AVX2-NEXT: addl %eax, %ecx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq 40(%rdi), %rax +; AVX2-NEXT: popcntq 32(%rdi), %rdx +; AVX2-NEXT: addl %eax, %edx +; AVX2-NEXT: addl %ecx, %edx +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: popcntq 24(%rdi), %rcx +; AVX2-NEXT: popcntq 16(%rdi), %rsi +; AVX2-NEXT: popcntq 8(%rdi), %r8 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq (%rdi), %rax +; AVX2-NEXT: addl %ecx, %esi +; AVX2-NEXT: addl %r8d, %eax +; AVX2-NEXT: addl %esi, %eax +; AVX2-NEXT: addl %edx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctpop_i512: +; AVX512: # %bb.0: +; AVX512-NEXT: popcntq 56(%rdi), %rax +; AVX512-NEXT: popcntq 48(%rdi), %rcx +; AVX512-NEXT: addl %eax, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq 40(%rdi), %rax +; AVX512-NEXT: popcntq 32(%rdi), %rdx +; AVX512-NEXT: addl %eax, %edx +; AVX512-NEXT: addl %ecx, %edx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq 24(%rdi), %rax +; AVX512-NEXT: xorl %ecx, %ecx +; AVX512-NEXT: popcntq 16(%rdi), %rcx +; AVX512-NEXT: popcntq 8(%rdi), %rsi +; AVX512-NEXT: addl %eax, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq (%rdi), %rax +; AVX512-NEXT: addl %esi, %eax +; AVX512-NEXT: addl %ecx, %eax +; AVX512-NEXT: addl %edx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i512, ptr %p0 + %cnt = call i512 @llvm.ctpop.i512(i512 %a0) + %res = trunc i512 %cnt to i32 + ret i32 %res +} + +define i32 @test_ctpop_i1024(i1024 %a0) nounwind { +; SSE-LABEL: test_ctpop_i1024: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbx +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: addl %eax, %r10d +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; SSE-NEXT: addl %r11d, %eax +; SSE-NEXT: xorl %r11d, %r11d +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: xorl %ebx, %ebx +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %rbx +; SSE-NEXT: addl %r10d, %eax +; SSE-NEXT: addl %r11d, %ebx +; SSE-NEXT: xorl %r11d, %r11d +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: xorl %r10d, %r10d +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; SSE-NEXT: addl %r11d, %r10d +; SSE-NEXT: addl %ebx, %r10d +; SSE-NEXT: xorl %r11d, %r11d +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: xorl %ebx, %ebx +; SSE-NEXT: popcntq {{[0-9]+}}(%rsp), %rbx +; SSE-NEXT: addl %eax, %r10d +; SSE-NEXT: addl %r11d, %ebx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq %r9, %rax +; SSE-NEXT: popcntq %r8, %r8 +; SSE-NEXT: addl %eax, %r8d +; SSE-NEXT: addl %ebx, %r8d +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq %rcx, %rax +; SSE-NEXT: xorl %ecx, %ecx +; SSE-NEXT: popcntq %rdx, %rcx +; SSE-NEXT: addl %eax, %ecx +; SSE-NEXT: xorl %edx, %edx +; SSE-NEXT: popcntq %rsi, %rdx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq %rdi, %rax +; SSE-NEXT: addl %edx, %eax +; SSE-NEXT: addl %ecx, %eax +; SSE-NEXT: addl %r8d, %eax +; SSE-NEXT: addl %r10d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: retq +; +; AVX2-LABEL: test_ctpop_i1024: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; AVX2-NEXT: addl %eax, %r10d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; AVX2-NEXT: addl %eax, %r11d +; AVX2-NEXT: addl %r10d, %r11d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: xorl %ebx, %ebx +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %rbx +; AVX2-NEXT: xorl %r14d, %r14d +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %r14 +; AVX2-NEXT: addl %eax, %ebx +; AVX2-NEXT: xorl %r10d, %r10d +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; AVX2-NEXT: addl %r14d, %r10d +; AVX2-NEXT: addl %ebx, %r10d +; AVX2-NEXT: addl %r11d, %r10d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: xorl %r11d, %r11d +; AVX2-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; AVX2-NEXT: addl %eax, %r11d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq %r9, %rax +; AVX2-NEXT: popcntq %r8, %r8 +; AVX2-NEXT: addl %eax, %r8d +; AVX2-NEXT: addl %r11d, %r8d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq %rcx, %rax +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: popcntq %rdx, %rcx +; AVX2-NEXT: addl %eax, %ecx +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: popcntq %rsi, %rdx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq %rdi, %rax +; AVX2-NEXT: addl %edx, %eax +; AVX2-NEXT: addl %ecx, %eax +; AVX2-NEXT: addl %r8d, %eax +; AVX2-NEXT: addl %r10d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_ctpop_i1024: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; AVX512-NEXT: addl %eax, %r10d +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; AVX512-NEXT: addl %eax, %r11d +; AVX512-NEXT: addl %r10d, %r11d +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: xorl %ebx, %ebx +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %rbx +; AVX512-NEXT: xorl %r14d, %r14d +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %r14 +; AVX512-NEXT: addl %eax, %ebx +; AVX512-NEXT: xorl %r10d, %r10d +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %r10 +; AVX512-NEXT: addl %r14d, %r10d +; AVX512-NEXT: addl %ebx, %r10d +; AVX512-NEXT: addl %r11d, %r10d +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: xorl %r11d, %r11d +; AVX512-NEXT: popcntq {{[0-9]+}}(%rsp), %r11 +; AVX512-NEXT: addl %eax, %r11d +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq %r9, %rax +; AVX512-NEXT: popcntq %r8, %r8 +; AVX512-NEXT: addl %eax, %r8d +; AVX512-NEXT: addl %r11d, %r8d +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq %rcx, %rax +; AVX512-NEXT: xorl %ecx, %ecx +; AVX512-NEXT: popcntq %rdx, %rcx +; AVX512-NEXT: addl %eax, %ecx +; AVX512-NEXT: xorl %edx, %edx +; AVX512-NEXT: popcntq %rsi, %rdx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq %rdi, %rax +; AVX512-NEXT: addl %edx, %eax +; AVX512-NEXT: addl %ecx, %eax +; AVX512-NEXT: addl %r8d, %eax +; AVX512-NEXT: addl %r10d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: retq + %cnt = call i1024 @llvm.ctpop.i1024(i1024 %a0) + %res = trunc i1024 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctpop_i1024(ptr %p0) nounwind { +; SSE-LABEL: load_ctpop_i1024: +; SSE: # %bb.0: +; SSE-NEXT: popcntq 120(%rdi), %rax +; SSE-NEXT: popcntq 112(%rdi), %rcx +; SSE-NEXT: popcntq 104(%rdi), %rdx +; SSE-NEXT: popcntq 96(%rdi), %rsi +; SSE-NEXT: addl %eax, %ecx +; SSE-NEXT: addl %edx, %esi +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq 88(%rdi), %rax +; SSE-NEXT: addl %ecx, %esi +; SSE-NEXT: xorl %edx, %edx +; SSE-NEXT: popcntq 80(%rdi), %rdx +; SSE-NEXT: addl %eax, %edx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq 72(%rdi), %rax +; SSE-NEXT: xorl %ecx, %ecx +; SSE-NEXT: popcntq 64(%rdi), %rcx +; SSE-NEXT: addl %eax, %ecx +; SSE-NEXT: addl %edx, %ecx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq 56(%rdi), %rax +; SSE-NEXT: addl %esi, %ecx +; SSE-NEXT: xorl %edx, %edx +; SSE-NEXT: popcntq 48(%rdi), %rdx +; SSE-NEXT: addl %eax, %edx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq 40(%rdi), %rax +; SSE-NEXT: xorl %esi, %esi +; SSE-NEXT: popcntq 32(%rdi), %rsi +; SSE-NEXT: addl %eax, %esi +; SSE-NEXT: addl %edx, %esi +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq 24(%rdi), %rax +; SSE-NEXT: xorl %edx, %edx +; SSE-NEXT: popcntq 16(%rdi), %rdx +; SSE-NEXT: popcntq 8(%rdi), %r8 +; SSE-NEXT: addl %eax, %edx +; SSE-NEXT: xorl %eax, %eax +; SSE-NEXT: popcntq (%rdi), %rax +; SSE-NEXT: addl %r8d, %eax +; SSE-NEXT: addl %edx, %eax +; SSE-NEXT: addl %esi, %eax +; SSE-NEXT: addl %ecx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctpop_i1024: +; AVX2: # %bb.0: +; AVX2-NEXT: popcntq 120(%rdi), %rax +; AVX2-NEXT: popcntq 112(%rdi), %rcx +; AVX2-NEXT: addl %eax, %ecx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq 104(%rdi), %rax +; AVX2-NEXT: popcntq 96(%rdi), %rdx +; AVX2-NEXT: addl %eax, %edx +; AVX2-NEXT: addl %ecx, %edx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq 88(%rdi), %rax +; AVX2-NEXT: popcntq 80(%rdi), %rsi +; AVX2-NEXT: popcntq 72(%rdi), %r8 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: popcntq 64(%rdi), %rcx +; AVX2-NEXT: addl %eax, %esi +; AVX2-NEXT: addl %r8d, %ecx +; AVX2-NEXT: addl %esi, %ecx +; AVX2-NEXT: addl %edx, %ecx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq 56(%rdi), %rax +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: popcntq 48(%rdi), %rdx +; AVX2-NEXT: xorl %esi, %esi +; AVX2-NEXT: popcntq 40(%rdi), %rsi +; AVX2-NEXT: xorl %r8d, %r8d +; AVX2-NEXT: popcntq 32(%rdi), %r8 +; AVX2-NEXT: addl %eax, %edx +; AVX2-NEXT: addl %esi, %r8d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq 24(%rdi), %rax +; AVX2-NEXT: addl %edx, %r8d +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: popcntq 16(%rdi), %rdx +; AVX2-NEXT: addl %eax, %edx +; AVX2-NEXT: xorl %esi, %esi +; AVX2-NEXT: popcntq 8(%rdi), %rsi +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: popcntq (%rdi), %rax +; AVX2-NEXT: addl %esi, %eax +; AVX2-NEXT: addl %edx, %eax +; AVX2-NEXT: addl %r8d, %eax +; AVX2-NEXT: addl %ecx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctpop_i1024: +; AVX512: # %bb.0: +; AVX512-NEXT: popcntq 120(%rdi), %rax +; AVX512-NEXT: popcntq 112(%rdi), %rcx +; AVX512-NEXT: addl %eax, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq 104(%rdi), %rax +; AVX512-NEXT: popcntq 96(%rdi), %rdx +; AVX512-NEXT: addl %eax, %edx +; AVX512-NEXT: addl %ecx, %edx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq 88(%rdi), %rax +; AVX512-NEXT: popcntq 80(%rdi), %rsi +; AVX512-NEXT: popcntq 72(%rdi), %r8 +; AVX512-NEXT: addl %eax, %esi +; AVX512-NEXT: xorl %ecx, %ecx +; AVX512-NEXT: popcntq 64(%rdi), %rcx +; AVX512-NEXT: addl %r8d, %ecx +; AVX512-NEXT: addl %esi, %ecx +; AVX512-NEXT: addl %edx, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq 56(%rdi), %rax +; AVX512-NEXT: xorl %edx, %edx +; AVX512-NEXT: popcntq 48(%rdi), %rdx +; AVX512-NEXT: xorl %esi, %esi +; AVX512-NEXT: popcntq 40(%rdi), %rsi +; AVX512-NEXT: addl %eax, %edx +; AVX512-NEXT: xorl %r8d, %r8d +; AVX512-NEXT: popcntq 32(%rdi), %r8 +; AVX512-NEXT: addl %esi, %r8d +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq 24(%rdi), %rax +; AVX512-NEXT: addl %edx, %r8d +; AVX512-NEXT: xorl %edx, %edx +; AVX512-NEXT: popcntq 16(%rdi), %rdx +; AVX512-NEXT: addl %eax, %edx +; AVX512-NEXT: xorl %esi, %esi +; AVX512-NEXT: popcntq 8(%rdi), %rsi +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: popcntq (%rdi), %rax +; AVX512-NEXT: addl %esi, %eax +; AVX512-NEXT: addl %edx, %eax +; AVX512-NEXT: addl %r8d, %eax +; AVX512-NEXT: addl %ecx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i1024, ptr %p0 + %cnt = call i1024 @llvm.ctpop.i1024(i1024 %a0) + %res = trunc i1024 %cnt to i32 + ret i32 %res +} + +; +; CTLZ +; + +define i32 @test_ctlz_i128(i128 %a0) nounwind { +; SSE-LABEL: test_ctlz_i128: +; SSE: # %bb.0: +; SSE-NEXT: bsrq %rsi, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq %rdi, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rsi, %rsi +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: test_ctlz_i128: +; AVX2: # %bb.0: +; AVX2-NEXT: lzcntq %rsi, %rcx +; AVX2-NEXT: lzcntq %rdi, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_ctlz_i128: +; AVX512: # %bb.0: +; AVX512-NEXT: lzcntq %rsi, %rcx +; AVX512-NEXT: lzcntq %rdi, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %cnt = call i128 @llvm.ctlz.i128(i128 %a0, i1 0) + %res = trunc i128 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctlz_i128(ptr %p0) nounwind { +; SSE-LABEL: load_ctlz_i128: +; SSE: # %bb.0: +; SSE-NEXT: movq 8(%rdi), %rcx +; SSE-NEXT: bsrq %rcx, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq (%rdi), %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rcx, %rcx +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctlz_i128: +; AVX2: # %bb.0: +; AVX2-NEXT: movq 8(%rdi), %rcx +; AVX2-NEXT: lzcntq %rcx, %rdx +; AVX2-NEXT: lzcntq (%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %edx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctlz_i128: +; AVX512: # %bb.0: +; AVX512-NEXT: movq 8(%rdi), %rcx +; AVX512-NEXT: lzcntq %rcx, %rdx +; AVX512-NEXT: lzcntq (%rdi), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %edx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i128, ptr %p0 + %cnt = call i128 @llvm.ctlz.i128(i128 %a0, i1 0) + %res = trunc i128 %cnt to i32 + ret i32 %res +} + +define i32 @test_ctlz_i256(i256 %a0) nounwind { +; SSE-LABEL: test_ctlz_i256: +; SSE: # %bb.0: +; SSE-NEXT: bsrq %rcx, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %rdx, %r8 +; SSE-NEXT: xorl $63, %r8d +; SSE-NEXT: orl $64, %r8d +; SSE-NEXT: testq %rcx, %rcx +; SSE-NEXT: cmovnel %eax, %r8d +; SSE-NEXT: bsrq %rsi, %r9 +; SSE-NEXT: xorl $63, %r9d +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq %rdi, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rsi, %rsi +; SSE-NEXT: cmovnel %r9d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rcx, %rdx +; SSE-NEXT: cmovnel %r8d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: test_ctlz_i256: +; AVX2: # %bb.0: +; AVX2-NEXT: lzcntq %rcx, %rax +; AVX2-NEXT: lzcntq %rdx, %r8 +; AVX2-NEXT: addl $64, %r8d +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %eax, %r8d +; AVX2-NEXT: lzcntq %rsi, %r9 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rdi, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %r9d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rcx, %rdx +; AVX2-NEXT: cmovnel %r8d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_ctlz_i256: +; AVX512: # %bb.0: +; AVX512-NEXT: lzcntq %rcx, %rax +; AVX512-NEXT: lzcntq %rdx, %r8 +; AVX512-NEXT: addl $64, %r8d +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %eax, %r8d +; AVX512-NEXT: lzcntq %rsi, %r9 +; AVX512-NEXT: lzcntq %rdi, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %r9d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %rcx, %rdx +; AVX512-NEXT: cmovnel %r8d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %cnt = call i256 @llvm.ctlz.i256(i256 %a0, i1 0) + %res = trunc i256 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctlz_i256(ptr %p0) nounwind { +; SSE-LABEL: load_ctlz_i256: +; SSE: # %bb.0: +; SSE-NEXT: movq 16(%rdi), %rcx +; SSE-NEXT: movq 24(%rdi), %rdx +; SSE-NEXT: bsrq %rdx, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %rcx, %rsi +; SSE-NEXT: xorl $63, %esi +; SSE-NEXT: orl $64, %esi +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %esi +; SSE-NEXT: movq 8(%rdi), %r8 +; SSE-NEXT: bsrq %r8, %r9 +; SSE-NEXT: xorl $63, %r9d +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq (%rdi), %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %r9d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rdx, %rcx +; SSE-NEXT: cmovnel %esi, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctlz_i256: +; AVX2: # %bb.0: +; AVX2-NEXT: movq 16(%rdi), %rcx +; AVX2-NEXT: movq 24(%rdi), %rdx +; AVX2-NEXT: lzcntq %rdx, %rax +; AVX2-NEXT: lzcntq %rcx, %rsi +; AVX2-NEXT: addl $64, %esi +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %esi +; AVX2-NEXT: movq 8(%rdi), %r8 +; AVX2-NEXT: lzcntq %r8, %r9 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq (%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %r9d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rdx, %rcx +; AVX2-NEXT: cmovnel %esi, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctlz_i256: +; AVX512: # %bb.0: +; AVX512-NEXT: movq 8(%rdi), %rcx +; AVX512-NEXT: movq 16(%rdi), %rdx +; AVX512-NEXT: movq 24(%rdi), %rsi +; AVX512-NEXT: lzcntq %rsi, %rax +; AVX512-NEXT: lzcntq %rdx, %r8 +; AVX512-NEXT: addl $64, %r8d +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %eax, %r8d +; AVX512-NEXT: lzcntq %rcx, %r9 +; AVX512-NEXT: lzcntq (%rdi), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %r9d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %rsi, %rdx +; AVX512-NEXT: cmovnel %r8d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i256, ptr %p0 + %cnt = call i256 @llvm.ctlz.i256(i256 %a0, i1 0) + %res = trunc i256 %cnt to i32 + ret i32 %res +} + +define i32 @test_ctlz_i512(i512 %a0) nounwind { +; SSE-LABEL: test_ctlz_i512: +; SSE: # %bb.0: +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: bsrq %r11, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r10, %r14 +; SSE-NEXT: xorl $63, %r14d +; SSE-NEXT: orl $64, %r14d +; SSE-NEXT: testq %r11, %r11 +; SSE-NEXT: cmovnel %eax, %r14d +; SSE-NEXT: bsrq %r9, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r8, %rbx +; SSE-NEXT: xorl $63, %ebx +; SSE-NEXT: orl $64, %ebx +; SSE-NEXT: testq %r9, %r9 +; SSE-NEXT: cmovnel %eax, %ebx +; SSE-NEXT: subl $-128, %ebx +; SSE-NEXT: movq %r10, %rax +; SSE-NEXT: orq %r11, %rax +; SSE-NEXT: cmovnel %r14d, %ebx +; SSE-NEXT: bsrq %rcx, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %rdx, %r14 +; SSE-NEXT: xorl $63, %r14d +; SSE-NEXT: orl $64, %r14d +; SSE-NEXT: testq %rcx, %rcx +; SSE-NEXT: cmovnel %eax, %r14d +; SSE-NEXT: bsrq %rsi, %r15 +; SSE-NEXT: xorl $63, %r15d +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq %rdi, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rsi, %rsi +; SSE-NEXT: cmovnel %r15d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rcx, %rdx +; SSE-NEXT: cmovnel %r14d, %eax +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r11, %r9 +; SSE-NEXT: orq %r10, %r8 +; SSE-NEXT: orq %r9, %r8 +; SSE-NEXT: cmovnel %ebx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: retq +; +; AVX2-LABEL: test_ctlz_i512: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; AVX2-NEXT: lzcntq %r11, %rax +; AVX2-NEXT: xorl %r14d, %r14d +; AVX2-NEXT: lzcntq %r10, %r14 +; AVX2-NEXT: addl $64, %r14d +; AVX2-NEXT: testq %r11, %r11 +; AVX2-NEXT: cmovnel %eax, %r14d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %r9, %rax +; AVX2-NEXT: xorl %ebx, %ebx +; AVX2-NEXT: lzcntq %r8, %rbx +; AVX2-NEXT: addl $64, %ebx +; AVX2-NEXT: testq %r9, %r9 +; AVX2-NEXT: cmovnel %eax, %ebx +; AVX2-NEXT: subl $-128, %ebx +; AVX2-NEXT: movq %r10, %rax +; AVX2-NEXT: orq %r11, %rax +; AVX2-NEXT: cmovnel %r14d, %ebx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rcx, %rax +; AVX2-NEXT: xorl %r14d, %r14d +; AVX2-NEXT: lzcntq %rdx, %r14 +; AVX2-NEXT: addl $64, %r14d +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %eax, %r14d +; AVX2-NEXT: xorl %r15d, %r15d +; AVX2-NEXT: lzcntq %rsi, %r15 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rdi, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %r15d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rcx, %rdx +; AVX2-NEXT: cmovnel %r14d, %eax +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r11, %r9 +; AVX2-NEXT: orq %r10, %r8 +; AVX2-NEXT: orq %r9, %r8 +; AVX2-NEXT: cmovnel %ebx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_ctlz_i512: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %r15 +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; AVX512-NEXT: lzcntq %r11, %rax +; AVX512-NEXT: lzcntq %r10, %r14 +; AVX512-NEXT: addl $64, %r14d +; AVX512-NEXT: testq %r11, %r11 +; AVX512-NEXT: cmovnel %eax, %r14d +; AVX512-NEXT: lzcntq %r9, %rax +; AVX512-NEXT: lzcntq %r8, %rbx +; AVX512-NEXT: addl $64, %ebx +; AVX512-NEXT: testq %r9, %r9 +; AVX512-NEXT: cmovnel %eax, %ebx +; AVX512-NEXT: subl $-128, %ebx +; AVX512-NEXT: movq %r10, %rax +; AVX512-NEXT: orq %r11, %rax +; AVX512-NEXT: cmovnel %r14d, %ebx +; AVX512-NEXT: lzcntq %rcx, %rax +; AVX512-NEXT: lzcntq %rdx, %r14 +; AVX512-NEXT: addl $64, %r14d +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %eax, %r14d +; AVX512-NEXT: lzcntq %rsi, %r15 +; AVX512-NEXT: lzcntq %rdi, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %r15d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %rcx, %rdx +; AVX512-NEXT: cmovnel %r14d, %eax +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r11, %r9 +; AVX512-NEXT: orq %r10, %r8 +; AVX512-NEXT: orq %r9, %r8 +; AVX512-NEXT: cmovnel %ebx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: popq %r15 +; AVX512-NEXT: retq + %cnt = call i512 @llvm.ctlz.i512(i512 %a0, i1 0) + %res = trunc i512 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctlz_i512(ptr %p0) nounwind { +; SSE-LABEL: load_ctlz_i512: +; SSE: # %bb.0: +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq 8(%rdi), %r10 +; SSE-NEXT: movq 16(%rdi), %r9 +; SSE-NEXT: movq 32(%rdi), %rcx +; SSE-NEXT: movq 40(%rdi), %rdx +; SSE-NEXT: movq 48(%rdi), %rsi +; SSE-NEXT: movq 56(%rdi), %r8 +; SSE-NEXT: bsrq %r8, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %rsi, %r14 +; SSE-NEXT: xorl $63, %r14d +; SSE-NEXT: orl $64, %r14d +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %eax, %r14d +; SSE-NEXT: bsrq %rdx, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %rcx, %r11 +; SSE-NEXT: xorl $63, %r11d +; SSE-NEXT: orl $64, %r11d +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %r11d +; SSE-NEXT: movq 24(%rdi), %rbx +; SSE-NEXT: subl $-128, %r11d +; SSE-NEXT: movq %rsi, %rax +; SSE-NEXT: orq %r8, %rax +; SSE-NEXT: cmovnel %r14d, %r11d +; SSE-NEXT: bsrq %rbx, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r9, %r14 +; SSE-NEXT: xorl $63, %r14d +; SSE-NEXT: orl $64, %r14d +; SSE-NEXT: testq %rbx, %rbx +; SSE-NEXT: cmovnel %eax, %r14d +; SSE-NEXT: bsrq %r10, %r15 +; SSE-NEXT: xorl $63, %r15d +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq (%rdi), %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r10, %r10 +; SSE-NEXT: cmovnel %r15d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rbx, %r9 +; SSE-NEXT: cmovnel %r14d, %eax +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r8, %rdx +; SSE-NEXT: orq %rsi, %rcx +; SSE-NEXT: orq %rdx, %rcx +; SSE-NEXT: cmovnel %r11d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctlz_i512: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq 8(%rdi), %r10 +; AVX2-NEXT: movq 16(%rdi), %r9 +; AVX2-NEXT: movq 32(%rdi), %rcx +; AVX2-NEXT: movq 40(%rdi), %rdx +; AVX2-NEXT: movq 48(%rdi), %rsi +; AVX2-NEXT: movq 56(%rdi), %r8 +; AVX2-NEXT: lzcntq %r8, %rax +; AVX2-NEXT: xorl %ebx, %ebx +; AVX2-NEXT: lzcntq %rsi, %rbx +; AVX2-NEXT: addl $64, %ebx +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %eax, %ebx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rdx, %rax +; AVX2-NEXT: lzcntq %rcx, %r11 +; AVX2-NEXT: addl $64, %r11d +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %r11d +; AVX2-NEXT: subl $-128, %r11d +; AVX2-NEXT: movq %rsi, %rax +; AVX2-NEXT: orq %r8, %rax +; AVX2-NEXT: cmovnel %ebx, %r11d +; AVX2-NEXT: movq 24(%rdi), %rbx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rbx, %rax +; AVX2-NEXT: xorl %r14d, %r14d +; AVX2-NEXT: lzcntq %r9, %r14 +; AVX2-NEXT: addl $64, %r14d +; AVX2-NEXT: testq %rbx, %rbx +; AVX2-NEXT: cmovnel %eax, %r14d +; AVX2-NEXT: xorl %r15d, %r15d +; AVX2-NEXT: lzcntq %r10, %r15 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq (%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %r15d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rbx, %r9 +; AVX2-NEXT: cmovnel %r14d, %eax +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r8, %rdx +; AVX2-NEXT: orq %rsi, %rcx +; AVX2-NEXT: orq %rdx, %rcx +; AVX2-NEXT: cmovnel %r11d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctlz_i512: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq 8(%rdi), %r11 +; AVX512-NEXT: movq 16(%rdi), %r9 +; AVX512-NEXT: movq 24(%rdi), %r10 +; AVX512-NEXT: movq 32(%rdi), %rcx +; AVX512-NEXT: movq 40(%rdi), %rdx +; AVX512-NEXT: movq 48(%rdi), %rsi +; AVX512-NEXT: movq 56(%rdi), %r8 +; AVX512-NEXT: lzcntq %r8, %rax +; AVX512-NEXT: lzcntq %rsi, %r14 +; AVX512-NEXT: addl $64, %r14d +; AVX512-NEXT: testq %r8, %r8 +; AVX512-NEXT: cmovnel %eax, %r14d +; AVX512-NEXT: lzcntq %rdx, %rax +; AVX512-NEXT: lzcntq %rcx, %rbx +; AVX512-NEXT: addl $64, %ebx +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %ebx +; AVX512-NEXT: subl $-128, %ebx +; AVX512-NEXT: movq %rsi, %rax +; AVX512-NEXT: orq %r8, %rax +; AVX512-NEXT: cmovnel %r14d, %ebx +; AVX512-NEXT: lzcntq %r10, %rax +; AVX512-NEXT: lzcntq %r9, %r14 +; AVX512-NEXT: addl $64, %r14d +; AVX512-NEXT: testq %r10, %r10 +; AVX512-NEXT: cmovnel %eax, %r14d +; AVX512-NEXT: lzcntq (%rdi), %rax +; AVX512-NEXT: lzcntq %r11, %rdi +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %r11, %r11 +; AVX512-NEXT: cmovnel %edi, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %r10, %r9 +; AVX512-NEXT: cmovnel %r14d, %eax +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r8, %rdx +; AVX512-NEXT: orq %rsi, %rcx +; AVX512-NEXT: orq %rdx, %rcx +; AVX512-NEXT: cmovnel %ebx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: retq + %a0 = load i512, ptr %p0 + %cnt = call i512 @llvm.ctlz.i512(i512 %a0, i1 0) + %res = trunc i512 %cnt to i32 + ret i32 %res +} + +define i32 @test_ctlz_i1024(i1024 %a0) nounwind { +; SSE-LABEL: test_ctlz_i1024: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbp +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %r13 +; SSE-NEXT: pushq %r12 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq %r9, %r11 +; SSE-NEXT: movq %r8, %r9 +; SSE-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: movq %rdx, %r12 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r15 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; SSE-NEXT: bsrq %r8, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r15, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: orl $64, %ecx +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: bsrq %r14, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: bsrq {{[0-9]+}}(%rsp), %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: orl $64, %eax +; SSE-NEXT: testq %r14, %r14 +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r13 +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: movq %r15, %rdx +; SSE-NEXT: orq %r8, %rdx +; SSE-NEXT: movq %r8, %r14 +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: bsrq %r13, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: bsrq %rbx, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: orl $64, %edx +; SSE-NEXT: testq %r13, %r13 +; SSE-NEXT: cmovnel %ecx, %edx +; SSE-NEXT: bsrq %r10, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; SSE-NEXT: bsrq %r8, %rbp +; SSE-NEXT: xorl $63, %ebp +; SSE-NEXT: orl $64, %ebp +; SSE-NEXT: testq %r10, %r10 +; SSE-NEXT: cmovnel %ecx, %ebp +; SSE-NEXT: subl $-128, %ebp +; SSE-NEXT: movq %rbx, %rcx +; SSE-NEXT: orq %r13, %rcx +; SSE-NEXT: cmovnel %edx, %ebp +; SSE-NEXT: addl $256, %ebp # imm = 0x100 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; SSE-NEXT: orq %r14, %rcx +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; SSE-NEXT: orq %r15, %rdx +; SSE-NEXT: orq %rcx, %rdx +; SSE-NEXT: cmovnel %eax, %ebp +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; SSE-NEXT: bsrq %r14, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r15 +; SSE-NEXT: bsrq %r15, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: orl $64, %ecx +; SSE-NEXT: testq %r14, %r14 +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: bsrq %r11, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r9, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: orl $64, %edx +; SSE-NEXT: testq %r11, %r11 +; SSE-NEXT: cmovnel %eax, %edx +; SSE-NEXT: subl $-128, %edx +; SSE-NEXT: movq %r15, %rax +; SSE-NEXT: orq %r14, %rax +; SSE-NEXT: cmovnel %ecx, %edx +; SSE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r15 # 8-byte Reload +; SSE-NEXT: bsrq %r15, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r12, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: orl $64, %ecx +; SSE-NEXT: testq %r15, %r15 +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq %rdi, %rax +; SSE-NEXT: bsrq %rsi, %rdi +; SSE-NEXT: xorl $63, %edi +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rsi, %rsi +; SSE-NEXT: cmovnel %edi, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %r15, %r12 +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: orq %r14, %r11 +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r9 +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r11, %r9 +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r13 +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r10 +; SSE-NEXT: orq %r13, %r10 +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %rbx +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r8 +; SSE-NEXT: orq %rbx, %r8 +; SSE-NEXT: addl $512, %eax # imm = 0x200 +; SSE-NEXT: orq %r10, %r8 +; SSE-NEXT: cmovnel %ebp, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r12 +; SSE-NEXT: popq %r13 +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: popq %rbp +; SSE-NEXT: retq +; +; AVX2-LABEL: test_ctlz_i1024: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %r13 +; AVX2-NEXT: pushq %r12 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq %r9, %r14 +; AVX2-NEXT: movq %r8, %r11 +; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r15 +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r12 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %r12, %rcx +; AVX2-NEXT: xorl %r9d, %r9d +; AVX2-NEXT: lzcntq %r8, %r9 +; AVX2-NEXT: addl $64, %r9d +; AVX2-NEXT: testq %r12, %r12 +; AVX2-NEXT: cmovnel %ecx, %r9d +; AVX2-NEXT: xorl %esi, %esi +; AVX2-NEXT: lzcntq %r10, %rsi +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %rax, %rcx +; AVX2-NEXT: addl $64, %ecx +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %esi, %ecx +; AVX2-NEXT: subl $-128, %ecx +; AVX2-NEXT: movq %r8, %rsi +; AVX2-NEXT: orq %r12, %rsi +; AVX2-NEXT: cmovnel %r9d, %ecx +; AVX2-NEXT: xorl %edi, %edi +; AVX2-NEXT: lzcntq %rbx, %rdi +; AVX2-NEXT: xorl %esi, %esi +; AVX2-NEXT: lzcntq %r15, %rsi +; AVX2-NEXT: addl $64, %esi +; AVX2-NEXT: testq %rbx, %rbx +; AVX2-NEXT: cmovnel %edi, %esi +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r13 +; AVX2-NEXT: xorl %ebp, %ebp +; AVX2-NEXT: lzcntq %r13, %rbp +; AVX2-NEXT: addl $64, %ebp +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r9 +; AVX2-NEXT: xorl %edi, %edi +; AVX2-NEXT: lzcntq %r9, %rdi +; AVX2-NEXT: testq %r9, %r9 +; AVX2-NEXT: cmovnel %edi, %ebp +; AVX2-NEXT: subl $-128, %ebp +; AVX2-NEXT: movq %r15, %rdi +; AVX2-NEXT: orq %rbx, %rdi +; AVX2-NEXT: cmovnel %esi, %ebp +; AVX2-NEXT: addl $256, %ebp # imm = 0x100 +; AVX2-NEXT: movq %r10, %rdi +; AVX2-NEXT: orq %r12, %rdi +; AVX2-NEXT: movq %rax, %rsi +; AVX2-NEXT: orq %r8, %rsi +; AVX2-NEXT: orq %rdi, %rsi +; AVX2-NEXT: cmovnel %ecx, %ebp +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdi +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rdi, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r12 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %r12, %rcx +; AVX2-NEXT: testq %r12, %r12 +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %r11, %rcx +; AVX2-NEXT: addl $64, %ecx +; AVX2-NEXT: xorl %esi, %esi +; AVX2-NEXT: lzcntq %r14, %rsi +; AVX2-NEXT: testq %r14, %r14 +; AVX2-NEXT: cmovnel %esi, %ecx +; AVX2-NEXT: subl $-128, %ecx +; AVX2-NEXT: movq %rdi, %rsi +; AVX2-NEXT: orq %r12, %rsi +; AVX2-NEXT: cmovnel %eax, %ecx +; AVX2-NEXT: movq %rdx, %rdi +; AVX2-NEXT: lzcntq %rdx, %rdx +; AVX2-NEXT: addl $64, %edx +; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %r10, %rax +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %eax, %edx +; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload +; AVX2-NEXT: lzcntq %rax, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload +; AVX2-NEXT: lzcntq %rsi, %r8 +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %r8d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %r10, %rdi +; AVX2-NEXT: cmovnel %edx, %eax +; AVX2-NEXT: orq %r12, %r14 +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r11 +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r14, %r11 +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %rbx +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r9 +; AVX2-NEXT: orq %rbx, %r9 +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r15 +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r13 +; AVX2-NEXT: orq %r15, %r13 +; AVX2-NEXT: addl $512, %eax # imm = 0x200 +; AVX2-NEXT: orq %r9, %r13 +; AVX2-NEXT: cmovnel %ebp, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r12 +; AVX2-NEXT: popq %r13 +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_ctlz_i1024: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %rbp +; AVX512-NEXT: pushq %r15 +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %r13 +; AVX512-NEXT: pushq %r12 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq %r9, %r14 +; AVX512-NEXT: movq %r8, %r11 +; AVX512-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r15 +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r10 +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r12 +; AVX512-NEXT: lzcntq %r12, %rcx +; AVX512-NEXT: lzcntq %r8, %r9 +; AVX512-NEXT: addl $64, %r9d +; AVX512-NEXT: testq %r12, %r12 +; AVX512-NEXT: cmovnel %ecx, %r9d +; AVX512-NEXT: lzcntq %r10, %rsi +; AVX512-NEXT: lzcntq %rax, %rcx +; AVX512-NEXT: addl $64, %ecx +; AVX512-NEXT: testq %r10, %r10 +; AVX512-NEXT: cmovnel %esi, %ecx +; AVX512-NEXT: subl $-128, %ecx +; AVX512-NEXT: movq %r8, %rsi +; AVX512-NEXT: orq %r12, %rsi +; AVX512-NEXT: cmovnel %r9d, %ecx +; AVX512-NEXT: lzcntq %rbx, %rdi +; AVX512-NEXT: lzcntq %r15, %rsi +; AVX512-NEXT: addl $64, %esi +; AVX512-NEXT: testq %rbx, %rbx +; AVX512-NEXT: cmovnel %edi, %esi +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r13 +; AVX512-NEXT: lzcntq %r13, %rbp +; AVX512-NEXT: addl $64, %ebp +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r9 +; AVX512-NEXT: lzcntq %r9, %rdi +; AVX512-NEXT: testq %r9, %r9 +; AVX512-NEXT: cmovnel %edi, %ebp +; AVX512-NEXT: subl $-128, %ebp +; AVX512-NEXT: movq %r15, %rdi +; AVX512-NEXT: orq %rbx, %rdi +; AVX512-NEXT: cmovnel %esi, %ebp +; AVX512-NEXT: addl $256, %ebp # imm = 0x100 +; AVX512-NEXT: movq %r10, %rdi +; AVX512-NEXT: orq %r12, %rdi +; AVX512-NEXT: movq %rax, %rsi +; AVX512-NEXT: orq %r8, %rsi +; AVX512-NEXT: orq %rdi, %rsi +; AVX512-NEXT: cmovnel %ecx, %ebp +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdi +; AVX512-NEXT: lzcntq %rdi, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r12 +; AVX512-NEXT: lzcntq %r12, %rcx +; AVX512-NEXT: testq %r12, %r12 +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: lzcntq %r11, %rcx +; AVX512-NEXT: addl $64, %ecx +; AVX512-NEXT: lzcntq %r14, %rsi +; AVX512-NEXT: testq %r14, %r14 +; AVX512-NEXT: cmovnel %esi, %ecx +; AVX512-NEXT: subl $-128, %ecx +; AVX512-NEXT: movq %rdi, %rsi +; AVX512-NEXT: orq %r12, %rsi +; AVX512-NEXT: cmovnel %eax, %ecx +; AVX512-NEXT: movq %rdx, %rdi +; AVX512-NEXT: lzcntq %rdx, %rdx +; AVX512-NEXT: addl $64, %edx +; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload +; AVX512-NEXT: lzcntq %r10, %rax +; AVX512-NEXT: testq %r10, %r10 +; AVX512-NEXT: cmovnel %eax, %edx +; AVX512-NEXT: lzcntq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload +; AVX512-NEXT: lzcntq %rsi, %r8 +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %r8d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %r10, %rdi +; AVX512-NEXT: cmovnel %edx, %eax +; AVX512-NEXT: orq %r12, %r14 +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r11 +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r14, %r11 +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %rbx +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r9 +; AVX512-NEXT: orq %rbx, %r9 +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r15 +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r13 +; AVX512-NEXT: orq %r15, %r13 +; AVX512-NEXT: addl $512, %eax # imm = 0x200 +; AVX512-NEXT: orq %r9, %r13 +; AVX512-NEXT: cmovnel %ebp, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r12 +; AVX512-NEXT: popq %r13 +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: popq %r15 +; AVX512-NEXT: popq %rbp +; AVX512-NEXT: retq + %cnt = call i1024 @llvm.ctlz.i1024(i1024 %a0, i1 0) + %res = trunc i1024 %cnt to i32 + ret i32 %res +} + +define i32 @load_ctlz_i1024(ptr %p0) nounwind { +; SSE-LABEL: load_ctlz_i1024: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbp +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %r13 +; SSE-NEXT: pushq %r12 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq 40(%rdi), %rbp +; SSE-NEXT: movq 64(%rdi), %rbx +; SSE-NEXT: movq 72(%rdi), %r11 +; SSE-NEXT: movq 80(%rdi), %r12 +; SSE-NEXT: movq 88(%rdi), %r14 +; SSE-NEXT: movq 96(%rdi), %rsi +; SSE-NEXT: movq 104(%rdi), %r9 +; SSE-NEXT: movq 112(%rdi), %r10 +; SSE-NEXT: movq 120(%rdi), %r8 +; SSE-NEXT: bsrq %r8, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r10, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: orl $64, %ecx +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: bsrq %r9, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: bsrq %rsi, %rax +; SSE-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: orl $64, %eax +; SSE-NEXT: testq %r9, %r9 +; SSE-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: movq %r10, %rdx +; SSE-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: orq %r8, %rdx +; SSE-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: bsrq %r14, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: movq %r12, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: bsrq %r12, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: orl $64, %edx +; SSE-NEXT: testq %r14, %r14 +; SSE-NEXT: cmovnel %ecx, %edx +; SSE-NEXT: bsrq %r11, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: bsrq %rbx, %r15 +; SSE-NEXT: xorl $63, %r15d +; SSE-NEXT: orl $64, %r15d +; SSE-NEXT: testq %r11, %r11 +; SSE-NEXT: cmovnel %ecx, %r15d +; SSE-NEXT: subl $-128, %r15d +; SSE-NEXT: movq %r12, %rcx +; SSE-NEXT: orq %r14, %rcx +; SSE-NEXT: cmovnel %edx, %r15d +; SSE-NEXT: movq 48(%rdi), %r12 +; SSE-NEXT: addl $256, %r15d # imm = 0x100 +; SSE-NEXT: movq %r9, %rcx +; SSE-NEXT: orq %r8, %rcx +; SSE-NEXT: movq %rsi, %rdx +; SSE-NEXT: orq %r10, %rdx +; SSE-NEXT: orq %rcx, %rdx +; SSE-NEXT: movq 56(%rdi), %r13 +; SSE-NEXT: cmovnel %eax, %r15d +; SSE-NEXT: bsrq %r13, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: bsrq %r12, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: orl $64, %ecx +; SSE-NEXT: testq %r13, %r13 +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: movq %rbp, %r10 +; SSE-NEXT: bsrq %rbp, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: movq 32(%rdi), %r8 +; SSE-NEXT: bsrq %r8, %rbp +; SSE-NEXT: xorl $63, %ebp +; SSE-NEXT: orl $64, %ebp +; SSE-NEXT: testq %r10, %r10 +; SSE-NEXT: cmovnel %eax, %ebp +; SSE-NEXT: subl $-128, %ebp +; SSE-NEXT: movq %r12, %rax +; SSE-NEXT: orq %r13, %rax +; SSE-NEXT: cmovnel %ecx, %ebp +; SSE-NEXT: movq 24(%rdi), %r9 +; SSE-NEXT: bsrq %r9, %rax +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: movq 16(%rdi), %rsi +; SSE-NEXT: bsrq %rsi, %rcx +; SSE-NEXT: xorl $63, %ecx +; SSE-NEXT: orl $64, %ecx +; SSE-NEXT: testq %r9, %r9 +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: movl $127, %eax +; SSE-NEXT: bsrq (%rdi), %rax +; SSE-NEXT: movq 8(%rdi), %rdi +; SSE-NEXT: bsrq %rdi, %rdx +; SSE-NEXT: xorl $63, %edx +; SSE-NEXT: xorl $63, %eax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rdi, %rdi +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %r9, %rsi +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: orq %r13, %r10 +; SSE-NEXT: orq %r12, %r8 +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r10, %r8 +; SSE-NEXT: cmovnel %ebp, %eax +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Folded Reload +; SSE-NEXT: orq %r14, %r11 +; SSE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Folded Reload +; SSE-NEXT: orq %rcx, %rbx +; SSE-NEXT: addl $512, %eax # imm = 0x200 +; SSE-NEXT: orq %r11, %rbx +; SSE-NEXT: cmovnel %r15d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r12 +; SSE-NEXT: popq %r13 +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: popq %rbp +; SSE-NEXT: retq +; +; AVX2-LABEL: load_ctlz_i1024: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %r13 +; AVX2-NEXT: pushq %r12 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq 48(%rdi), %r9 +; AVX2-NEXT: movq 56(%rdi), %rbp +; AVX2-NEXT: movq 64(%rdi), %r11 +; AVX2-NEXT: movq 72(%rdi), %r10 +; AVX2-NEXT: movq 80(%rdi), %r14 +; AVX2-NEXT: movq 88(%rdi), %rbx +; AVX2-NEXT: movq 96(%rdi), %rdx +; AVX2-NEXT: movq 104(%rdi), %r8 +; AVX2-NEXT: movq 112(%rdi), %rsi +; AVX2-NEXT: movq 120(%rdi), %r15 +; AVX2-NEXT: lzcntq %r15, %rax +; AVX2-NEXT: lzcntq %rsi, %rcx +; AVX2-NEXT: addl $64, %ecx +; AVX2-NEXT: testq %r15, %r15 +; AVX2-NEXT: cmovnel %eax, %ecx +; AVX2-NEXT: xorl %r12d, %r12d +; AVX2-NEXT: lzcntq %r8, %r12 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rdx, %rax +; AVX2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: cmovnel %r12d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: movq %rsi, %r12 +; AVX2-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: orq %r15, %r12 +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %rbx, %rcx +; AVX2-NEXT: movq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: xorl %r13d, %r13d +; AVX2-NEXT: lzcntq %r14, %r13 +; AVX2-NEXT: addl $64, %r13d +; AVX2-NEXT: testq %rbx, %rbx +; AVX2-NEXT: cmovnel %ecx, %r13d +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %r10, %rcx +; AVX2-NEXT: xorl %r12d, %r12d +; AVX2-NEXT: lzcntq %r11, %r12 +; AVX2-NEXT: addl $64, %r12d +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %ecx, %r12d +; AVX2-NEXT: subl $-128, %r12d +; AVX2-NEXT: movq %r14, %rcx +; AVX2-NEXT: orq %rbx, %rcx +; AVX2-NEXT: cmovnel %r13d, %r12d +; AVX2-NEXT: addl $256, %r12d # imm = 0x100 +; AVX2-NEXT: movq %r8, %rcx +; AVX2-NEXT: orq %r15, %rcx +; AVX2-NEXT: orq %rsi, %rdx +; AVX2-NEXT: orq %rcx, %rdx +; AVX2-NEXT: cmovnel %eax, %r12d +; AVX2-NEXT: movq %rbp, %r14 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %rbp, %rcx +; AVX2-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %r9, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rbp, %rbp +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: movq 32(%rdi), %r13 +; AVX2-NEXT: xorl %ebp, %ebp +; AVX2-NEXT: lzcntq %r13, %rbp +; AVX2-NEXT: addl $64, %ebp +; AVX2-NEXT: movq 40(%rdi), %r8 +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: lzcntq %r8, %rdx +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %edx, %ebp +; AVX2-NEXT: subl $-128, %ebp +; AVX2-NEXT: movq %r9, %rdx +; AVX2-NEXT: orq %r14, %rdx +; AVX2-NEXT: cmovnel %eax, %ebp +; AVX2-NEXT: movq 16(%rdi), %r9 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: lzcntq %r9, %rcx +; AVX2-NEXT: addl $64, %ecx +; AVX2-NEXT: movq 24(%rdi), %rdx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq %rdx, %rax +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %ecx +; AVX2-NEXT: movq 8(%rdi), %rsi +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: lzcntq (%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: lzcntq %rsi, %rdi +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %edi, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rdx, %r9 +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: orq %r14, %r8 +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r8, %r13 +; AVX2-NEXT: cmovnel %ebp, %eax +; AVX2-NEXT: orq %r15, %rbx +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Folded Reload +; AVX2-NEXT: orq %rbx, %r10 +; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Folded Reload +; AVX2-NEXT: orq %rcx, %r11 +; AVX2-NEXT: addl $512, %eax # imm = 0x200 +; AVX2-NEXT: orq %r10, %r11 +; AVX2-NEXT: cmovnel %r12d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r12 +; AVX2-NEXT: popq %r13 +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_ctlz_i1024: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %rbp +; AVX512-NEXT: pushq %r15 +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %r13 +; AVX512-NEXT: pushq %r12 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq 32(%rdi), %r14 +; AVX512-NEXT: movq 48(%rdi), %rbp +; AVX512-NEXT: movq 64(%rdi), %r11 +; AVX512-NEXT: movq 72(%rdi), %r10 +; AVX512-NEXT: movq 80(%rdi), %rdx +; AVX512-NEXT: movq 88(%rdi), %rbx +; AVX512-NEXT: movq 96(%rdi), %rsi +; AVX512-NEXT: movq 104(%rdi), %r9 +; AVX512-NEXT: movq 112(%rdi), %r8 +; AVX512-NEXT: movq 120(%rdi), %r15 +; AVX512-NEXT: lzcntq %r15, %rax +; AVX512-NEXT: lzcntq %r8, %rcx +; AVX512-NEXT: addl $64, %ecx +; AVX512-NEXT: testq %r15, %r15 +; AVX512-NEXT: cmovnel %eax, %ecx +; AVX512-NEXT: lzcntq %r9, %r12 +; AVX512-NEXT: lzcntq %rsi, %rax +; AVX512-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %r9, %r9 +; AVX512-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: cmovnel %r12d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: movq %r8, %r12 +; AVX512-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: orq %r15, %r12 +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: lzcntq %rbx, %rcx +; AVX512-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: lzcntq %rdx, %r13 +; AVX512-NEXT: addl $64, %r13d +; AVX512-NEXT: testq %rbx, %rbx +; AVX512-NEXT: cmovnel %ecx, %r13d +; AVX512-NEXT: lzcntq %r10, %rcx +; AVX512-NEXT: lzcntq %r11, %r12 +; AVX512-NEXT: addl $64, %r12d +; AVX512-NEXT: testq %r10, %r10 +; AVX512-NEXT: cmovnel %ecx, %r12d +; AVX512-NEXT: subl $-128, %r12d +; AVX512-NEXT: movq %rdx, %rcx +; AVX512-NEXT: orq %rbx, %rcx +; AVX512-NEXT: cmovnel %r13d, %r12d +; AVX512-NEXT: addl $256, %r12d # imm = 0x100 +; AVX512-NEXT: movq %r9, %rcx +; AVX512-NEXT: orq %r15, %rcx +; AVX512-NEXT: orq %r8, %rsi +; AVX512-NEXT: orq %rcx, %rsi +; AVX512-NEXT: movq 56(%rdi), %r13 +; AVX512-NEXT: cmovnel %eax, %r12d +; AVX512-NEXT: lzcntq %r13, %rcx +; AVX512-NEXT: movq %rbp, %rsi +; AVX512-NEXT: movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: lzcntq %rbp, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %r13, %r13 +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: lzcntq %r14, %rbp +; AVX512-NEXT: addl $64, %ebp +; AVX512-NEXT: movq 40(%rdi), %r8 +; AVX512-NEXT: lzcntq %r8, %rdx +; AVX512-NEXT: testq %r8, %r8 +; AVX512-NEXT: cmovnel %edx, %ebp +; AVX512-NEXT: subl $-128, %ebp +; AVX512-NEXT: movq %rsi, %rdx +; AVX512-NEXT: orq %r13, %rdx +; AVX512-NEXT: cmovnel %eax, %ebp +; AVX512-NEXT: movq 16(%rdi), %r9 +; AVX512-NEXT: lzcntq %r9, %rcx +; AVX512-NEXT: addl $64, %ecx +; AVX512-NEXT: movq 24(%rdi), %rdx +; AVX512-NEXT: lzcntq %rdx, %rax +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %ecx +; AVX512-NEXT: movq 8(%rdi), %rsi +; AVX512-NEXT: lzcntq (%rdi), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: lzcntq %rsi, %rdi +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %edi, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %rdx, %r9 +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: orq %r13, %r8 +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r8, %r14 +; AVX512-NEXT: cmovnel %ebp, %eax +; AVX512-NEXT: orq %r15, %rbx +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Folded Reload +; AVX512-NEXT: orq %rbx, %r10 +; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Folded Reload +; AVX512-NEXT: orq %rcx, %r11 +; AVX512-NEXT: addl $512, %eax # imm = 0x200 +; AVX512-NEXT: orq %r10, %r11 +; AVX512-NEXT: cmovnel %r12d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r12 +; AVX512-NEXT: popq %r13 +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: popq %r15 +; AVX512-NEXT: popq %rbp +; AVX512-NEXT: retq + %a0 = load i1024, ptr %p0 + %cnt = call i1024 @llvm.ctlz.i1024(i1024 %a0, i1 0) + %res = trunc i1024 %cnt to i32 + ret i32 %res +} + +; +; CTTZ +; + +define i32 @test_cttz_i128(i128 %a0) nounwind { +; SSE-LABEL: test_cttz_i128: +; SSE: # %bb.0: +; SSE-NEXT: rep bsfq %rdi, %rcx +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq %rsi, %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rdi, %rdi +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: test_cttz_i128: +; AVX2: # %bb.0: +; AVX2-NEXT: tzcntq %rdi, %rcx +; AVX2-NEXT: tzcntq %rsi, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rdi, %rdi +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_cttz_i128: +; AVX512: # %bb.0: +; AVX512-NEXT: tzcntq %rdi, %rcx +; AVX512-NEXT: tzcntq %rsi, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rdi, %rdi +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %cnt = call i128 @llvm.cttz.i128(i128 %a0, i1 0) + %res = trunc i128 %cnt to i32 + ret i32 %res +} + +define i32 @load_cttz_i128(ptr %p0) nounwind { +; SSE-LABEL: load_cttz_i128: +; SSE: # %bb.0: +; SSE-NEXT: movq (%rdi), %rcx +; SSE-NEXT: rep bsfq %rcx, %rdx +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq 8(%rdi), %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rcx, %rcx +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_cttz_i128: +; AVX2: # %bb.0: +; AVX2-NEXT: movq (%rdi), %rcx +; AVX2-NEXT: tzcntq %rcx, %rdx +; AVX2-NEXT: tzcntq 8(%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %edx, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_cttz_i128: +; AVX512: # %bb.0: +; AVX512-NEXT: movq (%rdi), %rcx +; AVX512-NEXT: tzcntq %rcx, %rdx +; AVX512-NEXT: tzcntq 8(%rdi), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %edx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i128, ptr %p0 + %cnt = call i128 @llvm.cttz.i128(i128 %a0, i1 0) + %res = trunc i128 %cnt to i32 + ret i32 %res +} + +define i32 @test_cttz_i256(i256 %a0) nounwind { +; SSE-LABEL: test_cttz_i256: +; SSE: # %bb.0: +; SSE-NEXT: rep bsfq %rdi, %rax +; SSE-NEXT: rep bsfq %rsi, %r8 +; SSE-NEXT: addl $64, %r8d +; SSE-NEXT: testq %rdi, %rdi +; SSE-NEXT: cmovnel %eax, %r8d +; SSE-NEXT: rep bsfq %rdx, %r9 +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq %rcx, %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %r9d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rsi, %rdi +; SSE-NEXT: cmovnel %r8d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: test_cttz_i256: +; AVX2: # %bb.0: +; AVX2-NEXT: tzcntq %rdi, %rax +; AVX2-NEXT: tzcntq %rsi, %r8 +; AVX2-NEXT: addl $64, %r8d +; AVX2-NEXT: testq %rdi, %rdi +; AVX2-NEXT: cmovnel %eax, %r8d +; AVX2-NEXT: tzcntq %rdx, %r9 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rcx, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %r9d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rsi, %rdi +; AVX2-NEXT: cmovnel %r8d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_cttz_i256: +; AVX512: # %bb.0: +; AVX512-NEXT: tzcntq %rdi, %rax +; AVX512-NEXT: tzcntq %rsi, %r8 +; AVX512-NEXT: addl $64, %r8d +; AVX512-NEXT: testq %rdi, %rdi +; AVX512-NEXT: cmovnel %eax, %r8d +; AVX512-NEXT: tzcntq %rdx, %r9 +; AVX512-NEXT: tzcntq %rcx, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %r9d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %rsi, %rdi +; AVX512-NEXT: cmovnel %r8d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %cnt = call i256 @llvm.cttz.i256(i256 %a0, i1 0) + %res = trunc i256 %cnt to i32 + ret i32 %res +} + +define i32 @load_cttz_i256(ptr %p0) nounwind { +; SSE-LABEL: load_cttz_i256: +; SSE: # %bb.0: +; SSE-NEXT: movq 16(%rdi), %rcx +; SSE-NEXT: movq (%rdi), %rdx +; SSE-NEXT: movq 8(%rdi), %rsi +; SSE-NEXT: rep bsfq %rdx, %rax +; SSE-NEXT: rep bsfq %rsi, %r8 +; SSE-NEXT: addl $64, %r8d +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %r8d +; SSE-NEXT: rep bsfq %rcx, %r9 +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq 24(%rdi), %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rcx, %rcx +; SSE-NEXT: cmovnel %r9d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rsi, %rdx +; SSE-NEXT: cmovnel %r8d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: retq +; +; AVX2-LABEL: load_cttz_i256: +; AVX2: # %bb.0: +; AVX2-NEXT: movq (%rdi), %rcx +; AVX2-NEXT: movq 8(%rdi), %rdx +; AVX2-NEXT: tzcntq %rcx, %rax +; AVX2-NEXT: tzcntq %rdx, %rsi +; AVX2-NEXT: addl $64, %esi +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %eax, %esi +; AVX2-NEXT: movq 16(%rdi), %r8 +; AVX2-NEXT: tzcntq %r8, %r9 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq 24(%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %r9d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rdx, %rcx +; AVX2-NEXT: cmovnel %esi, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_cttz_i256: +; AVX512: # %bb.0: +; AVX512-NEXT: movq 16(%rdi), %rcx +; AVX512-NEXT: movq (%rdi), %rdx +; AVX512-NEXT: movq 8(%rdi), %rsi +; AVX512-NEXT: tzcntq %rdx, %rax +; AVX512-NEXT: tzcntq %rsi, %r8 +; AVX512-NEXT: addl $64, %r8d +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %r8d +; AVX512-NEXT: tzcntq %rcx, %r9 +; AVX512-NEXT: tzcntq 24(%rdi), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %r9d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %rsi, %rdx +; AVX512-NEXT: cmovnel %r8d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: retq + %a0 = load i256, ptr %p0 + %cnt = call i256 @llvm.cttz.i256(i256 %a0, i1 0) + %res = trunc i256 %cnt to i32 + ret i32 %res +} + +define i32 @test_cttz_i512(i512 %a0) nounwind { +; SSE-LABEL: test_cttz_i512: +; SSE: # %bb.0: +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: rep bsfq %rdi, %rax +; SSE-NEXT: rep bsfq %rsi, %r11 +; SSE-NEXT: addl $64, %r11d +; SSE-NEXT: testq %rdi, %rdi +; SSE-NEXT: cmovnel %eax, %r11d +; SSE-NEXT: rep bsfq %rdx, %rax +; SSE-NEXT: rep bsfq %rcx, %r10 +; SSE-NEXT: addl $64, %r10d +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %r10d +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; SSE-NEXT: subl $-128, %r10d +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: orq %rsi, %rax +; SSE-NEXT: cmovnel %r11d, %r10d +; SSE-NEXT: rep bsfq %r8, %rax +; SSE-NEXT: rep bsfq %r9, %r11 +; SSE-NEXT: addl $64, %r11d +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %eax, %r11d +; SSE-NEXT: rep bsfq %rbx, %r14 +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq {{[0-9]+}}(%rsp), %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %rbx, %rbx +; SSE-NEXT: cmovnel %r14d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %r9, %r8 +; SSE-NEXT: cmovnel %r11d, %eax +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %rcx, %rsi +; SSE-NEXT: orq %rdx, %rdi +; SSE-NEXT: orq %rsi, %rdi +; SSE-NEXT: cmovnel %r10d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r14 +; SSE-NEXT: retq +; +; AVX2-LABEL: test_cttz_i512: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: tzcntq %rdi, %rax +; AVX2-NEXT: tzcntq %rsi, %r11 +; AVX2-NEXT: addl $64, %r11d +; AVX2-NEXT: testq %rdi, %rdi +; AVX2-NEXT: cmovnel %eax, %r11d +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rdx, %rax +; AVX2-NEXT: tzcntq %rcx, %r10 +; AVX2-NEXT: addl $64, %r10d +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %r10d +; AVX2-NEXT: subl $-128, %r10d +; AVX2-NEXT: movq %rdi, %rax +; AVX2-NEXT: orq %rsi, %rax +; AVX2-NEXT: cmovnel %r11d, %r10d +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %r8, %rax +; AVX2-NEXT: xorl %ebx, %ebx +; AVX2-NEXT: tzcntq %r9, %rbx +; AVX2-NEXT: addl $64, %ebx +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %eax, %ebx +; AVX2-NEXT: xorl %r14d, %r14d +; AVX2-NEXT: tzcntq %r11, %r14 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r11, %r11 +; AVX2-NEXT: cmovnel %r14d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %r9, %r8 +; AVX2-NEXT: cmovnel %ebx, %eax +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %rcx, %rsi +; AVX2-NEXT: orq %rdx, %rdi +; AVX2-NEXT: orq %rsi, %rdi +; AVX2-NEXT: cmovnel %r10d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_cttz_i512: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; AVX512-NEXT: tzcntq %rdi, %rax +; AVX512-NEXT: tzcntq %rsi, %rbx +; AVX512-NEXT: addl $64, %ebx +; AVX512-NEXT: testq %rdi, %rdi +; AVX512-NEXT: cmovnel %eax, %ebx +; AVX512-NEXT: tzcntq %rdx, %rax +; AVX512-NEXT: tzcntq %rcx, %r10 +; AVX512-NEXT: addl $64, %r10d +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %r10d +; AVX512-NEXT: subl $-128, %r10d +; AVX512-NEXT: movq %rdi, %rax +; AVX512-NEXT: orq %rsi, %rax +; AVX512-NEXT: cmovnel %ebx, %r10d +; AVX512-NEXT: tzcntq %r8, %rax +; AVX512-NEXT: tzcntq %r9, %rbx +; AVX512-NEXT: addl $64, %ebx +; AVX512-NEXT: testq %r8, %r8 +; AVX512-NEXT: cmovnel %eax, %ebx +; AVX512-NEXT: tzcntq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: tzcntq %r11, %r14 +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %r11, %r11 +; AVX512-NEXT: cmovnel %r14d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %r9, %r8 +; AVX512-NEXT: cmovnel %ebx, %eax +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %rcx, %rsi +; AVX512-NEXT: orq %rdx, %rdi +; AVX512-NEXT: orq %rsi, %rdi +; AVX512-NEXT: cmovnel %r10d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: retq + %cnt = call i512 @llvm.cttz.i512(i512 %a0, i1 0) + %res = trunc i512 %cnt to i32 + ret i32 %res +} + +define i32 @load_cttz_i512(ptr %p0) nounwind { +; SSE-LABEL: load_cttz_i512: +; SSE: # %bb.0: +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq 48(%rdi), %r10 +; SSE-NEXT: movq 40(%rdi), %r9 +; SSE-NEXT: movq 24(%rdi), %r8 +; SSE-NEXT: movq 16(%rdi), %rdx +; SSE-NEXT: movq (%rdi), %rcx +; SSE-NEXT: movq 8(%rdi), %rsi +; SSE-NEXT: rep bsfq %rcx, %rax +; SSE-NEXT: rep bsfq %rsi, %rbx +; SSE-NEXT: addl $64, %ebx +; SSE-NEXT: testq %rcx, %rcx +; SSE-NEXT: cmovnel %eax, %ebx +; SSE-NEXT: rep bsfq %rdx, %rax +; SSE-NEXT: rep bsfq %r8, %r11 +; SSE-NEXT: addl $64, %r11d +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %r11d +; SSE-NEXT: movq 32(%rdi), %r14 +; SSE-NEXT: subl $-128, %r11d +; SSE-NEXT: movq %rcx, %rax +; SSE-NEXT: orq %rsi, %rax +; SSE-NEXT: cmovnel %ebx, %r11d +; SSE-NEXT: rep bsfq %r14, %rax +; SSE-NEXT: rep bsfq %r9, %rbx +; SSE-NEXT: addl $64, %ebx +; SSE-NEXT: testq %r14, %r14 +; SSE-NEXT: cmovnel %eax, %ebx +; SSE-NEXT: rep bsfq %r10, %r15 +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq 56(%rdi), %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r10, %r10 +; SSE-NEXT: cmovnel %r15d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %r9, %r14 +; SSE-NEXT: cmovnel %ebx, %eax +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r8, %rsi +; SSE-NEXT: orq %rdx, %rcx +; SSE-NEXT: orq %rsi, %rcx +; SSE-NEXT: cmovnel %r11d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: retq +; +; AVX2-LABEL: load_cttz_i512: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq 48(%rdi), %r10 +; AVX2-NEXT: movq 40(%rdi), %r9 +; AVX2-NEXT: movq 24(%rdi), %r8 +; AVX2-NEXT: movq 16(%rdi), %rdx +; AVX2-NEXT: movq (%rdi), %rcx +; AVX2-NEXT: movq 8(%rdi), %rsi +; AVX2-NEXT: tzcntq %rcx, %rax +; AVX2-NEXT: xorl %ebx, %ebx +; AVX2-NEXT: tzcntq %rsi, %rbx +; AVX2-NEXT: addl $64, %ebx +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %eax, %ebx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rdx, %rax +; AVX2-NEXT: tzcntq %r8, %r11 +; AVX2-NEXT: addl $64, %r11d +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %r11d +; AVX2-NEXT: subl $-128, %r11d +; AVX2-NEXT: movq %rcx, %rax +; AVX2-NEXT: orq %rsi, %rax +; AVX2-NEXT: cmovnel %ebx, %r11d +; AVX2-NEXT: movq 32(%rdi), %rbx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rbx, %rax +; AVX2-NEXT: xorl %r14d, %r14d +; AVX2-NEXT: tzcntq %r9, %r14 +; AVX2-NEXT: addl $64, %r14d +; AVX2-NEXT: testq %rbx, %rbx +; AVX2-NEXT: cmovnel %eax, %r14d +; AVX2-NEXT: xorl %r15d, %r15d +; AVX2-NEXT: tzcntq %r10, %r15 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq 56(%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %r15d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %r9, %rbx +; AVX2-NEXT: cmovnel %r14d, %eax +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r8, %rsi +; AVX2-NEXT: orq %rdx, %rcx +; AVX2-NEXT: orq %rsi, %rcx +; AVX2-NEXT: cmovnel %r11d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_cttz_i512: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq 48(%rdi), %r11 +; AVX512-NEXT: movq 40(%rdi), %r9 +; AVX512-NEXT: movq 32(%rdi), %r10 +; AVX512-NEXT: movq 24(%rdi), %r8 +; AVX512-NEXT: movq 16(%rdi), %rdx +; AVX512-NEXT: movq (%rdi), %rcx +; AVX512-NEXT: movq 8(%rdi), %rsi +; AVX512-NEXT: tzcntq %rcx, %rax +; AVX512-NEXT: tzcntq %rsi, %r14 +; AVX512-NEXT: addl $64, %r14d +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %eax, %r14d +; AVX512-NEXT: tzcntq %rdx, %rax +; AVX512-NEXT: tzcntq %r8, %rbx +; AVX512-NEXT: addl $64, %ebx +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %ebx +; AVX512-NEXT: subl $-128, %ebx +; AVX512-NEXT: movq %rcx, %rax +; AVX512-NEXT: orq %rsi, %rax +; AVX512-NEXT: cmovnel %r14d, %ebx +; AVX512-NEXT: tzcntq %r10, %rax +; AVX512-NEXT: tzcntq %r9, %r14 +; AVX512-NEXT: addl $64, %r14d +; AVX512-NEXT: testq %r10, %r10 +; AVX512-NEXT: cmovnel %eax, %r14d +; AVX512-NEXT: tzcntq 56(%rdi), %rax +; AVX512-NEXT: tzcntq %r11, %rdi +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %r11, %r11 +; AVX512-NEXT: cmovnel %edi, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %r9, %r10 +; AVX512-NEXT: cmovnel %r14d, %eax +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r8, %rsi +; AVX512-NEXT: orq %rdx, %rcx +; AVX512-NEXT: orq %rsi, %rcx +; AVX512-NEXT: cmovnel %ebx, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: retq + %a0 = load i512, ptr %p0 + %cnt = call i512 @llvm.cttz.i512(i512 %a0, i1 0) + %res = trunc i512 %cnt to i32 + ret i32 %res +} + +define i32 @test_cttz_i1024(i1024 %a0) nounwind { +; SSE-LABEL: test_cttz_i1024: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbp +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %r13 +; SSE-NEXT: pushq %r12 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq %r9, %r13 +; SSE-NEXT: movq %r8, %r14 +; SSE-NEXT: movq %rcx, %rbx +; SSE-NEXT: movq %rdx, %r10 +; SSE-NEXT: movq %rsi, %r9 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rsi +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; SSE-NEXT: rep bsfq %rdi, %rax +; SSE-NEXT: rep bsfq %r9, %r15 +; SSE-NEXT: addl $64, %r15d +; SSE-NEXT: testq %rdi, %rdi +; SSE-NEXT: cmovnel %eax, %r15d +; SSE-NEXT: rep bsfq %r10, %r12 +; SSE-NEXT: rep bsfq %rcx, %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r10, %r10 +; SSE-NEXT: cmovnel %r12d, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: movq %rdi, %r12 +; SSE-NEXT: orq %r9, %r12 +; SSE-NEXT: cmovnel %r15d, %eax +; SSE-NEXT: rep bsfq %r8, %r15 +; SSE-NEXT: movq %r13, %rcx +; SSE-NEXT: movq %r13, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: rep bsfq %r13, %r13 +; SSE-NEXT: addl $64, %r13d +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %r15d, %r13d +; SSE-NEXT: rep bsfq %rdx, %r12 +; SSE-NEXT: rep bsfq {{[0-9]+}}(%rsp), %r15 +; SSE-NEXT: addl $64, %r15d +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %r12d, %r15d +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r12 +; SSE-NEXT: subl $-128, %r15d +; SSE-NEXT: movq %r8, %rbp +; SSE-NEXT: orq %rcx, %rbp +; SSE-NEXT: cmovnel %r13d, %r15d +; SSE-NEXT: addl $256, %r15d # imm = 0x100 +; SSE-NEXT: movq %r9, %r13 +; SSE-NEXT: orq %rbx, %r13 +; SSE-NEXT: movq %rdi, %rbp +; SSE-NEXT: orq %r10, %rbp +; SSE-NEXT: orq %r13, %rbp +; SSE-NEXT: cmovnel %eax, %r15d +; SSE-NEXT: rep bsfq %r11, %r13 +; SSE-NEXT: rep bsfq %r12, %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r11, %r11 +; SSE-NEXT: cmovnel %r13d, %eax +; SSE-NEXT: rep bsfq {{[0-9]+}}(%rsp), %r13 +; SSE-NEXT: addl $64, %r13d +; SSE-NEXT: rep bsfq %rsi, %rcx +; SSE-NEXT: testq %rsi, %rsi +; SSE-NEXT: cmovnel %ecx, %r13d +; SSE-NEXT: subl $-128, %r13d +; SSE-NEXT: movq %r11, %rcx +; SSE-NEXT: orq %r12, %rcx +; SSE-NEXT: cmovnel %eax, %r13d +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbp +; SSE-NEXT: rep bsfq %rbp, %rcx +; SSE-NEXT: addl $64, %ecx +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; SSE-NEXT: rep bsfq %rdx, %rax +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq {{[0-9]+}}(%rsp), %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; SSE-NEXT: rep bsfq %r8, %rsi +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %esi, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %rbp, %rdx +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r12 +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r11 +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r12, %r11 +; SSE-NEXT: cmovnel %r13d, %eax +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %rbx +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Folded Reload +; SSE-NEXT: orq %rbx, %r9 +; SSE-NEXT: orq {{[0-9]+}}(%rsp), %r10 +; SSE-NEXT: orq %r14, %rdi +; SSE-NEXT: orq %r10, %rdi +; SSE-NEXT: addl $512, %eax # imm = 0x200 +; SSE-NEXT: orq %r9, %rdi +; SSE-NEXT: cmovnel %r15d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r12 +; SSE-NEXT: popq %r13 +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: popq %rbp +; SSE-NEXT: retq +; +; AVX2-LABEL: test_cttz_i1024: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %r13 +; AVX2-NEXT: pushq %r12 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq %r9, %rbx +; AVX2-NEXT: movq %r8, %r14 +; AVX2-NEXT: movq %rcx, %r11 +; AVX2-NEXT: movq %rdx, %r10 +; AVX2-NEXT: movq %rsi, %r9 +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rsi +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; AVX2-NEXT: tzcntq %rdi, %rax +; AVX2-NEXT: xorl %r15d, %r15d +; AVX2-NEXT: tzcntq %r9, %r15 +; AVX2-NEXT: addl $64, %r15d +; AVX2-NEXT: testq %rdi, %rdi +; AVX2-NEXT: cmovnel %eax, %r15d +; AVX2-NEXT: xorl %r12d, %r12d +; AVX2-NEXT: tzcntq %r10, %r12 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %r11, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %r12d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: movq %rdi, %r12 +; AVX2-NEXT: orq %r9, %r12 +; AVX2-NEXT: cmovnel %r15d, %eax +; AVX2-NEXT: xorl %r15d, %r15d +; AVX2-NEXT: tzcntq %r14, %r15 +; AVX2-NEXT: movq %rbx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: xorl %r12d, %r12d +; AVX2-NEXT: tzcntq %rbx, %r12 +; AVX2-NEXT: addl $64, %r12d +; AVX2-NEXT: testq %r14, %r14 +; AVX2-NEXT: cmovnel %r15d, %r12d +; AVX2-NEXT: xorl %r13d, %r13d +; AVX2-NEXT: tzcntq %rcx, %r13 +; AVX2-NEXT: xorl %r15d, %r15d +; AVX2-NEXT: tzcntq %rdx, %r15 +; AVX2-NEXT: addl $64, %r15d +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %r13d, %r15d +; AVX2-NEXT: subl $-128, %r15d +; AVX2-NEXT: movq %r14, %r13 +; AVX2-NEXT: orq %rbx, %r13 +; AVX2-NEXT: cmovnel %r12d, %r15d +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r12 +; AVX2-NEXT: addl $256, %r15d # imm = 0x100 +; AVX2-NEXT: movq %r9, %r13 +; AVX2-NEXT: orq %r11, %r13 +; AVX2-NEXT: movq %rdi, %rbp +; AVX2-NEXT: orq %r10, %rbp +; AVX2-NEXT: orq %r13, %rbp +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r13 +; AVX2-NEXT: cmovnel %eax, %r15d +; AVX2-NEXT: xorl %ebp, %ebp +; AVX2-NEXT: tzcntq %r12, %rbp +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %r13, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r12, %r12 +; AVX2-NEXT: cmovnel %ebp, %eax +; AVX2-NEXT: xorl %ebp, %ebp +; AVX2-NEXT: tzcntq %r8, %rbp +; AVX2-NEXT: addl $64, %ebp +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: tzcntq %rsi, %rcx +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %ecx, %ebp +; AVX2-NEXT: subl $-128, %ebp +; AVX2-NEXT: movq %r12, %rcx +; AVX2-NEXT: orq %r13, %rcx +; AVX2-NEXT: cmovnel %eax, %ebp +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: tzcntq %rbx, %rcx +; AVX2-NEXT: addl $64, %ecx +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rdx, %rax +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %ecx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq {{[0-9]+}}(%rsp), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; AVX2-NEXT: tzcntq %r8, %rsi +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %esi, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %rbx, %rdx +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r13 +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r12 +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r13, %r12 +; AVX2-NEXT: cmovnel %ebp, %eax +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r11 +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Folded Reload +; AVX2-NEXT: orq %r11, %r9 +; AVX2-NEXT: orq {{[0-9]+}}(%rsp), %r10 +; AVX2-NEXT: orq %r14, %rdi +; AVX2-NEXT: orq %r10, %rdi +; AVX2-NEXT: addl $512, %eax # imm = 0x200 +; AVX2-NEXT: orq %r9, %rdi +; AVX2-NEXT: cmovnel %r15d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r12 +; AVX2-NEXT: popq %r13 +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_cttz_i1024: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %rbp +; AVX512-NEXT: pushq %r15 +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %r13 +; AVX512-NEXT: pushq %r12 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq %r9, %r14 +; AVX512-NEXT: movq %r8, %r15 +; AVX512-NEXT: movq %rcx, %r11 +; AVX512-NEXT: movq %rdx, %r10 +; AVX512-NEXT: movq %rsi, %r9 +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rsi +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rbx +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rcx +; AVX512-NEXT: tzcntq %rdi, %rax +; AVX512-NEXT: tzcntq %r9, %r12 +; AVX512-NEXT: addl $64, %r12d +; AVX512-NEXT: testq %rdi, %rdi +; AVX512-NEXT: cmovnel %eax, %r12d +; AVX512-NEXT: tzcntq %rdx, %r13 +; AVX512-NEXT: tzcntq %r11, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %r13d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: movq %rdi, %r13 +; AVX512-NEXT: orq %r9, %r13 +; AVX512-NEXT: cmovnel %r12d, %eax +; AVX512-NEXT: tzcntq %r8, %r12 +; AVX512-NEXT: movq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: tzcntq %r14, %r13 +; AVX512-NEXT: addl $64, %r13d +; AVX512-NEXT: testq %r8, %r8 +; AVX512-NEXT: cmovnel %r12d, %r13d +; AVX512-NEXT: tzcntq %rcx, %rbp +; AVX512-NEXT: tzcntq {{[0-9]+}}(%rsp), %r12 +; AVX512-NEXT: addl $64, %r12d +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %ebp, %r12d +; AVX512-NEXT: subl $-128, %r12d +; AVX512-NEXT: movq %r8, %rbp +; AVX512-NEXT: orq %r14, %rbp +; AVX512-NEXT: cmovnel %r13d, %r12d +; AVX512-NEXT: addl $256, %r12d # imm = 0x100 +; AVX512-NEXT: movq %r9, %r13 +; AVX512-NEXT: orq %r11, %r13 +; AVX512-NEXT: movq %rdi, %rbp +; AVX512-NEXT: orq %rdx, %rbp +; AVX512-NEXT: orq %r13, %rbp +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r13 +; AVX512-NEXT: cmovnel %eax, %r12d +; AVX512-NEXT: tzcntq %rbx, %rbp +; AVX512-NEXT: tzcntq %r13, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rbx, %rbx +; AVX512-NEXT: cmovnel %ebp, %eax +; AVX512-NEXT: tzcntq {{[0-9]+}}(%rsp), %rbp +; AVX512-NEXT: addl $64, %ebp +; AVX512-NEXT: tzcntq %rsi, %rcx +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %ecx, %ebp +; AVX512-NEXT: subl $-128, %ebp +; AVX512-NEXT: movq %rbx, %rcx +; AVX512-NEXT: orq %r13, %rcx +; AVX512-NEXT: cmovnel %eax, %ebp +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r14 +; AVX512-NEXT: tzcntq %r14, %rcx +; AVX512-NEXT: addl $64, %ecx +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %rdx +; AVX512-NEXT: tzcntq %rdx, %rax +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %ecx +; AVX512-NEXT: tzcntq {{[0-9]+}}(%rsp), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: movq {{[0-9]+}}(%rsp), %r8 +; AVX512-NEXT: tzcntq %r8, %rsi +; AVX512-NEXT: testq %r8, %r8 +; AVX512-NEXT: cmovnel %esi, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %r14, %rdx +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r13 +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %rbx +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r13, %rbx +; AVX512-NEXT: cmovnel %ebp, %eax +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r11 +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Folded Reload +; AVX512-NEXT: orq %r11, %r9 +; AVX512-NEXT: orq {{[0-9]+}}(%rsp), %r10 +; AVX512-NEXT: orq %r15, %rdi +; AVX512-NEXT: orq %r10, %rdi +; AVX512-NEXT: addl $512, %eax # imm = 0x200 +; AVX512-NEXT: orq %r9, %rdi +; AVX512-NEXT: cmovnel %r12d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r12 +; AVX512-NEXT: popq %r13 +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: popq %r15 +; AVX512-NEXT: popq %rbp +; AVX512-NEXT: retq + %cnt = call i1024 @llvm.cttz.i1024(i1024 %a0, i1 0) + %res = trunc i1024 %cnt to i32 + ret i32 %res +} + +define i32 @load_cttz_i1024(ptr %p0) nounwind { +; SSE-LABEL: load_cttz_i1024: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbp +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %r13 +; SSE-NEXT: pushq %r12 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq 88(%rdi), %r10 +; SSE-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: movq 56(%rdi), %rcx +; SSE-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: movq 40(%rdi), %rsi +; SSE-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: movq 24(%rdi), %r9 +; SSE-NEXT: movq 16(%rdi), %r15 +; SSE-NEXT: movq (%rdi), %r8 +; SSE-NEXT: movq 8(%rdi), %r11 +; SSE-NEXT: rep bsfq %r8, %rax +; SSE-NEXT: rep bsfq %r11, %rdx +; SSE-NEXT: addl $64, %edx +; SSE-NEXT: testq %r8, %r8 +; SSE-NEXT: cmovnel %eax, %edx +; SSE-NEXT: rep bsfq %r15, %rbx +; SSE-NEXT: rep bsfq %r9, %rax +; SSE-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r15, %r15 +; SSE-NEXT: cmovnel %ebx, %eax +; SSE-NEXT: movq 32(%rdi), %rbx +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: movq %r8, %r14 +; SSE-NEXT: orq %r11, %r14 +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: rep bsfq %rbx, %rdx +; SSE-NEXT: rep bsfq %rsi, %r12 +; SSE-NEXT: addl $64, %r12d +; SSE-NEXT: testq %rbx, %rbx +; SSE-NEXT: cmovnel %edx, %r12d +; SSE-NEXT: movq 48(%rdi), %r13 +; SSE-NEXT: movq %r13, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; SSE-NEXT: rep bsfq %r13, %rdx +; SSE-NEXT: rep bsfq %rcx, %r14 +; SSE-NEXT: addl $64, %r14d +; SSE-NEXT: testq %r13, %r13 +; SSE-NEXT: cmovnel %edx, %r14d +; SSE-NEXT: subl $-128, %r14d +; SSE-NEXT: movq %rbx, %rdx +; SSE-NEXT: orq %rsi, %rdx +; SSE-NEXT: cmovnel %r12d, %r14d +; SSE-NEXT: movq 72(%rdi), %r12 +; SSE-NEXT: addl $256, %r14d # imm = 0x100 +; SSE-NEXT: movq %r11, %rdx +; SSE-NEXT: orq %r9, %rdx +; SSE-NEXT: movq %r8, %r13 +; SSE-NEXT: orq %r15, %r13 +; SSE-NEXT: orq %rdx, %r13 +; SSE-NEXT: movq 64(%rdi), %r13 +; SSE-NEXT: cmovnel %eax, %r14d +; SSE-NEXT: rep bsfq %r13, %rdx +; SSE-NEXT: rep bsfq %r12, %rax +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: testq %r13, %r13 +; SSE-NEXT: cmovnel %edx, %eax +; SSE-NEXT: rep bsfq %r10, %rbp +; SSE-NEXT: addl $64, %ebp +; SSE-NEXT: movq 80(%rdi), %r10 +; SSE-NEXT: rep bsfq %r10, %rcx +; SSE-NEXT: testq %r10, %r10 +; SSE-NEXT: cmovnel %ecx, %ebp +; SSE-NEXT: subl $-128, %ebp +; SSE-NEXT: movq %r13, %rcx +; SSE-NEXT: orq %r12, %rcx +; SSE-NEXT: cmovnel %eax, %ebp +; SSE-NEXT: movq 104(%rdi), %r9 +; SSE-NEXT: rep bsfq %r9, %rcx +; SSE-NEXT: addl $64, %ecx +; SSE-NEXT: movq 96(%rdi), %rdx +; SSE-NEXT: rep bsfq %rdx, %rax +; SSE-NEXT: testq %rdx, %rdx +; SSE-NEXT: cmovnel %eax, %ecx +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: rep bsfq 120(%rdi), %rax +; SSE-NEXT: movq 112(%rdi), %rdi +; SSE-NEXT: addl $64, %eax +; SSE-NEXT: rep bsfq %rdi, %rsi +; SSE-NEXT: testq %rdi, %rdi +; SSE-NEXT: cmovnel %esi, %eax +; SSE-NEXT: subl $-128, %eax +; SSE-NEXT: orq %r9, %rdx +; SSE-NEXT: cmovnel %ecx, %eax +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload +; SSE-NEXT: orq %r10, %r13 +; SSE-NEXT: addl $256, %eax # imm = 0x100 +; SSE-NEXT: orq %r12, %r13 +; SSE-NEXT: cmovnel %ebp, %eax +; SSE-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Folded Reload +; SSE-NEXT: orq %rcx, %r11 +; SSE-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r15 # 8-byte Folded Reload +; SSE-NEXT: orq %rbx, %r8 +; SSE-NEXT: orq %r15, %r8 +; SSE-NEXT: addl $512, %eax # imm = 0x200 +; SSE-NEXT: orq %r11, %r8 +; SSE-NEXT: cmovnel %r14d, %eax +; SSE-NEXT: # kill: def $eax killed $eax killed $rax +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r12 +; SSE-NEXT: popq %r13 +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: popq %rbp +; SSE-NEXT: retq +; +; AVX2-LABEL: load_cttz_i1024: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: pushq %r15 +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %r13 +; AVX2-NEXT: pushq %r12 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq 72(%rdi), %r14 +; AVX2-NEXT: movq 64(%rdi), %r15 +; AVX2-NEXT: movq 56(%rdi), %r9 +; AVX2-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: movq 48(%rdi), %rcx +; AVX2-NEXT: movq 40(%rdi), %r10 +; AVX2-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: movq 32(%rdi), %rsi +; AVX2-NEXT: movq 24(%rdi), %rbp +; AVX2-NEXT: movq 16(%rdi), %rbx +; AVX2-NEXT: movq (%rdi), %r8 +; AVX2-NEXT: movq 8(%rdi), %r11 +; AVX2-NEXT: tzcntq %r8, %rax +; AVX2-NEXT: tzcntq %r11, %rdx +; AVX2-NEXT: addl $64, %edx +; AVX2-NEXT: testq %r8, %r8 +; AVX2-NEXT: cmovnel %eax, %edx +; AVX2-NEXT: xorl %r12d, %r12d +; AVX2-NEXT: tzcntq %rbx, %r12 +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rbp, %rax +; AVX2-NEXT: movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %rbx, %rbx +; AVX2-NEXT: cmovnel %r12d, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: movq %r8, %r12 +; AVX2-NEXT: orq %r11, %r12 +; AVX2-NEXT: cmovnel %edx, %eax +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: tzcntq %rsi, %rdx +; AVX2-NEXT: xorl %r13d, %r13d +; AVX2-NEXT: tzcntq %r10, %r13 +; AVX2-NEXT: addl $64, %r13d +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: cmovnel %edx, %r13d +; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: tzcntq %rcx, %rdx +; AVX2-NEXT: xorl %r12d, %r12d +; AVX2-NEXT: tzcntq %r9, %r12 +; AVX2-NEXT: addl $64, %r12d +; AVX2-NEXT: testq %rcx, %rcx +; AVX2-NEXT: cmovnel %edx, %r12d +; AVX2-NEXT: subl $-128, %r12d +; AVX2-NEXT: movq %rsi, %rdx +; AVX2-NEXT: orq %r10, %rdx +; AVX2-NEXT: cmovnel %r13d, %r12d +; AVX2-NEXT: addl $256, %r12d # imm = 0x100 +; AVX2-NEXT: movq %r11, %rdx +; AVX2-NEXT: orq %rbp, %rdx +; AVX2-NEXT: movq %r8, %r13 +; AVX2-NEXT: orq %rbx, %r13 +; AVX2-NEXT: orq %rdx, %r13 +; AVX2-NEXT: cmovnel %eax, %r12d +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: tzcntq %r15, %rdx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %r14, %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: testq %r15, %r15 +; AVX2-NEXT: cmovnel %edx, %eax +; AVX2-NEXT: movq 88(%rdi), %rbp +; AVX2-NEXT: xorl %r13d, %r13d +; AVX2-NEXT: tzcntq %rbp, %r13 +; AVX2-NEXT: addl $64, %r13d +; AVX2-NEXT: movq 80(%rdi), %r10 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: tzcntq %r10, %rcx +; AVX2-NEXT: testq %r10, %r10 +; AVX2-NEXT: cmovnel %ecx, %r13d +; AVX2-NEXT: subl $-128, %r13d +; AVX2-NEXT: movq %r15, %rcx +; AVX2-NEXT: orq %r14, %rcx +; AVX2-NEXT: cmovnel %eax, %r13d +; AVX2-NEXT: movq 104(%rdi), %r9 +; AVX2-NEXT: xorl %ecx, %ecx +; AVX2-NEXT: tzcntq %r9, %rcx +; AVX2-NEXT: addl $64, %ecx +; AVX2-NEXT: movq 96(%rdi), %rdx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rdx, %rax +; AVX2-NEXT: testq %rdx, %rdx +; AVX2-NEXT: cmovnel %eax, %ecx +; AVX2-NEXT: movq 112(%rdi), %rsi +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq 120(%rdi), %rax +; AVX2-NEXT: addl $64, %eax +; AVX2-NEXT: tzcntq %rsi, %rdi +; AVX2-NEXT: testq %rsi, %rsi +; AVX2-NEXT: cmovnel %edi, %eax +; AVX2-NEXT: subl $-128, %eax +; AVX2-NEXT: orq %r9, %rdx +; AVX2-NEXT: cmovnel %ecx, %eax +; AVX2-NEXT: orq %rbp, %r14 +; AVX2-NEXT: orq %r10, %r15 +; AVX2-NEXT: addl $256, %eax # imm = 0x100 +; AVX2-NEXT: orq %r14, %r15 +; AVX2-NEXT: cmovnel %r13d, %eax +; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Folded Reload +; AVX2-NEXT: orq %rcx, %r11 +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Folded Reload +; AVX2-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Folded Reload +; AVX2-NEXT: orq %rbx, %r8 +; AVX2-NEXT: addl $512, %eax # imm = 0x200 +; AVX2-NEXT: orq %r11, %r8 +; AVX2-NEXT: cmovnel %r12d, %eax +; AVX2-NEXT: # kill: def $eax killed $eax killed $rax +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r12 +; AVX2-NEXT: popq %r13 +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %r15 +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_cttz_i1024: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %rbp +; AVX512-NEXT: pushq %r15 +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %r13 +; AVX512-NEXT: pushq %r12 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: movq 88(%rdi), %rbp +; AVX512-NEXT: movq 72(%rdi), %r15 +; AVX512-NEXT: movq 56(%rdi), %r9 +; AVX512-NEXT: movq %r9, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: movq 48(%rdi), %rcx +; AVX512-NEXT: movq 40(%rdi), %r10 +; AVX512-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: movq 32(%rdi), %rsi +; AVX512-NEXT: movq 24(%rdi), %r14 +; AVX512-NEXT: movq 16(%rdi), %rbx +; AVX512-NEXT: movq (%rdi), %r8 +; AVX512-NEXT: movq 8(%rdi), %r11 +; AVX512-NEXT: tzcntq %r8, %rax +; AVX512-NEXT: tzcntq %r11, %rdx +; AVX512-NEXT: addl $64, %edx +; AVX512-NEXT: testq %r8, %r8 +; AVX512-NEXT: cmovnel %eax, %edx +; AVX512-NEXT: tzcntq %rbx, %r12 +; AVX512-NEXT: tzcntq %r14, %rax +; AVX512-NEXT: movq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %rbx, %rbx +; AVX512-NEXT: cmovnel %r12d, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: movq %r8, %r12 +; AVX512-NEXT: orq %r11, %r12 +; AVX512-NEXT: cmovnel %edx, %eax +; AVX512-NEXT: tzcntq %rsi, %rdx +; AVX512-NEXT: tzcntq %r10, %r13 +; AVX512-NEXT: addl $64, %r13d +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: cmovnel %edx, %r13d +; AVX512-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill +; AVX512-NEXT: tzcntq %rcx, %rdx +; AVX512-NEXT: tzcntq %r9, %r12 +; AVX512-NEXT: addl $64, %r12d +; AVX512-NEXT: testq %rcx, %rcx +; AVX512-NEXT: cmovnel %edx, %r12d +; AVX512-NEXT: subl $-128, %r12d +; AVX512-NEXT: movq %rsi, %rdx +; AVX512-NEXT: orq %r10, %rdx +; AVX512-NEXT: cmovnel %r13d, %r12d +; AVX512-NEXT: addl $256, %r12d # imm = 0x100 +; AVX512-NEXT: movq %r11, %rdx +; AVX512-NEXT: orq %r14, %rdx +; AVX512-NEXT: movq %r8, %r13 +; AVX512-NEXT: orq %rbx, %r13 +; AVX512-NEXT: orq %rdx, %r13 +; AVX512-NEXT: movq 64(%rdi), %r13 +; AVX512-NEXT: cmovnel %eax, %r12d +; AVX512-NEXT: tzcntq %r13, %rdx +; AVX512-NEXT: tzcntq %r15, %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: testq %r13, %r13 +; AVX512-NEXT: cmovnel %edx, %eax +; AVX512-NEXT: movq %rbp, %r14 +; AVX512-NEXT: tzcntq %rbp, %rbp +; AVX512-NEXT: addl $64, %ebp +; AVX512-NEXT: movq 80(%rdi), %r10 +; AVX512-NEXT: tzcntq %r10, %rcx +; AVX512-NEXT: testq %r10, %r10 +; AVX512-NEXT: cmovnel %ecx, %ebp +; AVX512-NEXT: subl $-128, %ebp +; AVX512-NEXT: movq %r13, %rcx +; AVX512-NEXT: orq %r15, %rcx +; AVX512-NEXT: cmovnel %eax, %ebp +; AVX512-NEXT: movq 104(%rdi), %r9 +; AVX512-NEXT: tzcntq %r9, %rcx +; AVX512-NEXT: addl $64, %ecx +; AVX512-NEXT: movq 96(%rdi), %rdx +; AVX512-NEXT: tzcntq %rdx, %rax +; AVX512-NEXT: testq %rdx, %rdx +; AVX512-NEXT: cmovnel %eax, %ecx +; AVX512-NEXT: movq 112(%rdi), %rsi +; AVX512-NEXT: tzcntq 120(%rdi), %rax +; AVX512-NEXT: addl $64, %eax +; AVX512-NEXT: tzcntq %rsi, %rdi +; AVX512-NEXT: testq %rsi, %rsi +; AVX512-NEXT: cmovnel %edi, %eax +; AVX512-NEXT: subl $-128, %eax +; AVX512-NEXT: orq %r9, %rdx +; AVX512-NEXT: cmovnel %ecx, %eax +; AVX512-NEXT: orq %r14, %r15 +; AVX512-NEXT: orq %r10, %r13 +; AVX512-NEXT: addl $256, %eax # imm = 0x100 +; AVX512-NEXT: orq %r15, %r13 +; AVX512-NEXT: cmovnel %ebp, %eax +; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Folded Reload +; AVX512-NEXT: orq %rcx, %r11 +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Folded Reload +; AVX512-NEXT: orq {{[-0-9]+}}(%r{{[sb]}}p), %r8 # 8-byte Folded Reload +; AVX512-NEXT: orq %rbx, %r8 +; AVX512-NEXT: addl $512, %eax # imm = 0x200 +; AVX512-NEXT: orq %r11, %r8 +; AVX512-NEXT: cmovnel %r12d, %eax +; AVX512-NEXT: # kill: def $eax killed $eax killed $rax +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r12 +; AVX512-NEXT: popq %r13 +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: popq %r15 +; AVX512-NEXT: popq %rbp +; AVX512-NEXT: retq + %a0 = load i1024, ptr %p0 + %cnt = call i1024 @llvm.cttz.i1024(i1024 %a0, i1 0) + %res = trunc i1024 %cnt to i32 + ret i32 %res +} diff --git a/llvm/test/DebugInfo/Generic/compileunit-source-language-name.ll b/llvm/test/DebugInfo/Generic/compileunit-source-language-name.ll index f5dcf01..58b5104 100644 --- a/llvm/test/DebugInfo/Generic/compileunit-source-language-name.ll +++ b/llvm/test/DebugInfo/Generic/compileunit-source-language-name.ll @@ -1,11 +1,11 @@ ; AIX doesn't have support for DWARF 6 DW_AT_language_name ; XFAIL: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}} -; RUN: %llc_dwarf -filetype=obj -O0 < %s | llvm-dwarfdump -debug-info - | FileCheck %s --implicit-check-not "DW_AT_language" +; RUN: %llc_dwarf -filetype=obj -O0 < %s | llvm-dwarfdump -debug-info -v - | FileCheck %s --implicit-check-not "DW_AT_language" -; CHECK: DW_AT_language_name (DW_LNAME_ObjC_plus_plus) -; CHECK: DW_AT_language_name (DW_LNAME_C_plus_plus) -; CHECK: DW_AT_language_version (201100) -; CHECK: DW_AT_language_name (DW_LNAME_Rust) +; CHECK: DW_AT_language_name [DW_FORM_data2] (DW_LNAME_ObjC_plus_plus) +; CHECK: DW_AT_language_name [DW_FORM_data2] (DW_LNAME_C_plus_plus) +; CHECK: DW_AT_language_version [DW_FORM_data4] (201100 C++11) +; CHECK: DW_AT_language_name [DW_FORM_data2] (DW_LNAME_Rust) ; CHECK-NOT: DW_AT_language_version @x = global i32 0, align 4, !dbg !0 diff --git a/llvm/test/DebugInfo/X86/DW_OP_LLVM_extract_bits.ll b/llvm/test/DebugInfo/X86/DW_OP_LLVM_extract_bits.ll index 5928127..b79c84d 100644 --- a/llvm/test/DebugInfo/X86/DW_OP_LLVM_extract_bits.ll +++ b/llvm/test/DebugInfo/X86/DW_OP_LLVM_extract_bits.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: DW_TAG_subprogram ; CHECK: DW_AT_name ("test1") ; CHECK: DW_TAG_variable -; CHECK: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref_size 0x1, DW_OP_constu 0x3d, DW_OP_shl, DW_OP_constu 0x3d, DW_OP_shr, DW_OP_stack_value) +; CHECK: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref_size 0x1, DW_OP_constu 0x7, DW_OP_and, DW_OP_stack_value) ; CHECK: DW_AT_name ("x") ; CHECK: DW_TAG_variable ; CHECK: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref_size 0x1, DW_OP_constu 0x39, DW_OP_shl, DW_OP_constu 0x3c, DW_OP_shra, DW_OP_stack_value) @@ -25,7 +25,7 @@ entry: ; CHECK-LABEL: DW_TAG_subprogram ; CHECK: DW_AT_name ("test2") ; CHECK: DW_TAG_variable -; CHECK: DW_AT_location (DW_OP_breg0 {{R[^+]+}}+0, DW_OP_constu 0xff, DW_OP_and, DW_OP_constu 0x3d, DW_OP_shl, DW_OP_constu 0x3d, DW_OP_shr, DW_OP_stack_value) +; CHECK: DW_AT_location (DW_OP_breg0 {{R[^+]+}}+0, DW_OP_constu 0xff, DW_OP_and, DW_OP_constu 0x7, DW_OP_and, DW_OP_stack_value) ; CHECK: DW_AT_name ("x") ; CHECK: DW_TAG_variable ; CHECK: DW_AT_location (DW_OP_breg0 {{R[^+]+}}+0, DW_OP_constu 0xff, DW_OP_and, DW_OP_constu 0x39, DW_OP_shl, DW_OP_constu 0x3c, DW_OP_shra, DW_OP_stack_value) @@ -67,7 +67,7 @@ entry: ; CHECK: DW_TAG_variable ; CHECK: DW_AT_location (DW_OP_fbreg -4, DW_OP_plus_uconst 0x3, DW_OP_deref_size 0x1, DW_OP_constu 0x38, DW_OP_shl, DW_OP_constu 0x39, DW_OP_shr, DW_OP_stack_value) ; CHECK: DW_AT_name ("z") -; CHECK: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref_size 0x8, DW_OP_stack_value) +; CHECK: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref, DW_OP_stack_value) ; CHECK: DW_AT_name ("q") define i32 @test4() !dbg !28 { diff --git a/llvm/test/ExecutionEngine/JITLink/x86-64/LocalDependencyPropagation.s b/llvm/test/ExecutionEngine/JITLink/x86-64/LocalDependencyPropagation.s index 83d71cd..5293958 100644 --- a/llvm/test/ExecutionEngine/JITLink/x86-64/LocalDependencyPropagation.s +++ b/llvm/test/ExecutionEngine/JITLink/x86-64/LocalDependencyPropagation.s @@ -16,8 +16,7 @@ # CHECK-DAG: Symbols: { _foo }, Dependencies: { (main, { _external_func }) } # CHECK-DAG: Symbols: { _baz }, Dependencies: { (main, { _foo }) } # CHECK: Simplified dependencies: -# CHECK-DAG: Symbols: { _foo }, Dependencies: { (main, { _external_func }) } -# CHECK-DAG: Symbols: { _baz }, Dependencies: { (main, { _external_func }) } +# CHECK-DAG: Defs: { (main, [ _baz _foo ]) }, Deps: { (main, [ _external_func ]) } .section __TEXT,__text,regular,pure_instructions diff --git a/llvm/test/Instrumentation/AllocToken/intrinsic.ll b/llvm/test/Instrumentation/AllocToken/intrinsic.ll new file mode 100644 index 0000000..13aaa90 --- /dev/null +++ b/llvm/test/Instrumentation/AllocToken/intrinsic.ll @@ -0,0 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; Test that the alloc-token pass lowers the intrinsic to a constant token ID. +; +; RUN: opt < %s -passes=alloc-token -alloc-token-mode=typehashpointersplit -alloc-token-max=2 -S | FileCheck %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare i64 @llvm.alloc.token.id.i64(metadata) + +define i64 @test_intrinsic_lowering() { +; CHECK-LABEL: define i64 @test_intrinsic_lowering() { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: ret i64 0 +; +entry: + %token_no_ptr = call i64 @llvm.alloc.token.id.i64(metadata !0) + ret i64 %token_no_ptr +} + +define i64 @test_intrinsic_lowering_ptr() { +; CHECK-LABEL: define i64 @test_intrinsic_lowering_ptr() { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: ret i64 1 +; +entry: + %token_with_ptr = call i64 @llvm.alloc.token.id.i64(metadata !1) + ret i64 %token_with_ptr +} + +!0 = !{!"NoPointerType", i1 false} +!1 = !{!"PointerType", i1 true} diff --git a/llvm/test/Instrumentation/AllocToken/intrinsic32.ll b/llvm/test/Instrumentation/AllocToken/intrinsic32.ll new file mode 100644 index 0000000..eb5dbbe --- /dev/null +++ b/llvm/test/Instrumentation/AllocToken/intrinsic32.ll @@ -0,0 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; Test that the alloc-token pass lowers the intrinsic to a constant token ID. +; +; RUN: opt < %s -passes=alloc-token -alloc-token-mode=typehashpointersplit -alloc-token-max=2 -S | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" +target triple = "i386-pc-linux-gnu" + +declare i32 @llvm.alloc.token.id.i32(metadata) + +define i32 @test_intrinsic_lowering() { +; CHECK-LABEL: define i32 @test_intrinsic_lowering() { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: ret i32 0 +; +entry: + %token_no_ptr = call i32 @llvm.alloc.token.id.i32(metadata !0) + ret i32 %token_no_ptr +} + +define i32 @test_intrinsic_lowering_ptr() { +; CHECK-LABEL: define i32 @test_intrinsic_lowering_ptr() { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: ret i32 1 +; +entry: + %token_with_ptr = call i32 @llvm.alloc.token.id.i32(metadata !1) + ret i32 %token_with_ptr +} + +!0 = !{!"NoPointerType", i1 false} +!1 = !{!"PointerType", i1 true} diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme-aarch64-svcount-mini.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme-aarch64-svcount-mini.ll new file mode 100644 index 0000000..1c869bd --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme-aarch64-svcount-mini.ll @@ -0,0 +1,14 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -passes=msan -mattr=+sme -o - %s + +; XFAIL: * + +; Forked from llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll +; Manually minimized to show MSan leads to a compiler crash + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android9001" + +define target("aarch64.svcount") @test_return_arg1(target("aarch64.svcount") %arg0, target("aarch64.svcount") %arg1) nounwind { + ret target("aarch64.svcount") %arg1 +} diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme-aarch64-svcount.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme-aarch64-svcount.ll new file mode 100644 index 0000000..00cf3204 --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme-aarch64-svcount.ll @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -passes=msan -mattr=+sme -o - %s + +; XFAIL: * + +; Forked from llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android9001" + +; +; Test simple loads, stores and return. +; +define target("aarch64.svcount") @test_load(ptr %ptr) nounwind { + %res = load target("aarch64.svcount"), ptr %ptr + ret target("aarch64.svcount") %res +} + +define void @test_store(ptr %ptr, target("aarch64.svcount") %val) nounwind { + store target("aarch64.svcount") %val, ptr %ptr + ret void +} + +define target("aarch64.svcount") @test_alloca_store_reload(target("aarch64.svcount") %val) nounwind { + %ptr = alloca target("aarch64.svcount"), align 1 + store target("aarch64.svcount") %val, ptr %ptr + %res = load target("aarch64.svcount"), ptr %ptr + ret target("aarch64.svcount") %res +} + +; +; Test passing as arguments (from perspective of callee) +; + +define target("aarch64.svcount") @test_return_arg1(target("aarch64.svcount") %arg0, target("aarch64.svcount") %arg1) nounwind { + ret target("aarch64.svcount") %arg1 +} + +define target("aarch64.svcount") @test_return_arg4(target("aarch64.svcount") %arg0, target("aarch64.svcount") %arg1, target("aarch64.svcount") %arg2, target("aarch64.svcount") %arg3, target("aarch64.svcount") %arg4) nounwind { + ret target("aarch64.svcount") %arg4 +} + +; +; Test passing as arguments (from perspective of caller) +; + +declare void @take_svcount_1(target("aarch64.svcount") %arg) +define void @test_pass_1arg(target("aarch64.svcount") %arg) nounwind { + call void @take_svcount_1(target("aarch64.svcount") %arg) + ret void +} + +declare void @take_svcount_5(target("aarch64.svcount") %arg0, target("aarch64.svcount") %arg1, target("aarch64.svcount") %arg2, target("aarch64.svcount") %arg3, target("aarch64.svcount") %arg4) +define void @test_pass_5args(target("aarch64.svcount") %arg) nounwind { + call void @take_svcount_5(target("aarch64.svcount") %arg, target("aarch64.svcount") %arg, target("aarch64.svcount") %arg, target("aarch64.svcount") %arg, target("aarch64.svcount") %arg) + ret void +} + +define target("aarch64.svcount") @test_sel(target("aarch64.svcount") %x, target("aarch64.svcount") %y, i1 %cmp) sanitize_memory { + %x.y = select i1 %cmp, target("aarch64.svcount") %x, target("aarch64.svcount") %y + ret target("aarch64.svcount") %x.y +} + +define target("aarch64.svcount") @test_sel_cc(target("aarch64.svcount") %x, target("aarch64.svcount") %y, i32 %k) sanitize_memory { + %cmp = icmp sgt i32 %k, 42 + %x.y = select i1 %cmp, target("aarch64.svcount") %x, target("aarch64.svcount") %y + ret target("aarch64.svcount") %x.y +} diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme2-intrinsics-add-mini.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme2-intrinsics-add-mini.ll new file mode 100644 index 0000000..3f43efa --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme2-intrinsics-add-mini.ll @@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -passes=msan -mattr=+sme2 -mattr=+sme-i16i64 -mattr=+sme-f64f64 -o - %s + +; XFAIL: * + +; Forked from llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll +; Manually reduced to show MSan leads to a compiler crash + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android9001" + +define void @multi_vector_add_za_vg1x4_f32_tuple(i64 %stride, ptr %ptr) sanitize_memory { + %1 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() + %2 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %1, ptr %ptr) + ret void +} diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme2-intrinsics-add.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme2-intrinsics-add.ll new file mode 100644 index 0000000..cd04373 --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/sme2-intrinsics-add.ll @@ -0,0 +1,340 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -passes=msan -mattr=+sme2 -mattr=+sme-i16i64 -mattr=+sme-f64f64 -o - %s + +; XFAIL: * + +; Forked from llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android9001" + +define void @multi_vector_add_write_single_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zm) sanitize_memory { + call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %slice, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zm) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %slice.7, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zm) + ret void +} + +define void @multi_vector_add_write_single_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zm) sanitize_memory { + call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %slice, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zm) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %slice.7, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zm) + ret void +} + + +define void @multi_vector_add_write_single_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, + <vscale x 4 x i32> %zm) sanitize_memory { + call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %slice, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, + <vscale x 4 x i32> %zm) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %slice.7, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, + <vscale x 4 x i32> %zm) + ret void +} + +define void @multi_vector_add_write_single_za_vg1x4_i64(i32 %slice, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, + <vscale x 2 x i64> %zm) sanitize_memory { + call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32 %slice, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, + <vscale x 2 x i64> %zm) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32 %slice.7, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, + <vscale x 2 x i64> %zm) + ret void +} + + +define void @multi_vector_add_write_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) sanitize_memory { + call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32 %slice, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32 %slice.7, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) + ret void +} + + +define void @multi_vector_add_write_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) sanitize_memory { + call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32 %slice, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32 %slice.7, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) + ret void +} + + + +define void @multi_vector_add_write_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, + <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1, + <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3) sanitize_memory { + call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32 %slice, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, + <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1, + <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32 %slice.7, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, + <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1, + <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3) + ret void +} + +define void @multi_vector_add_write_za_vg1x4_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, + <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1, + <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3) sanitize_memory { + call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32 %slice, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, + <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1, + <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32 %slice.7, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, + <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1, + <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3) + ret void +} + +define void @multi_vector_add_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) sanitize_memory { + call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32 %slice,<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32 %slice.7, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) + ret void +} + +define void @multi_vector_add_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1) sanitize_memory { + call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32 %slice.7, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1) + ret void +} + +define void @multi_vector_add_za_vg1x2_f32(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) sanitize_memory { + call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32 %slice, + <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32 %slice.7, + <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) + ret void +} + +define void @multi_vector_add_za_vg1x2_f64(i32 %slice, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1) sanitize_memory { + call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 %slice, + <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 %slice.7, + <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1) + ret void +} + +define void @multi_vector_add_za_vg1x2_f64_tuple(i64 %stride, ptr %ptr) sanitize_memory { +entry: + %0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() + %1 = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld1.pn.x2.nxv2f64(target("aarch64.svcount") %0, ptr %ptr) + %2 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %1, 0 + %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %1, 1 + %arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride + %4 = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld1.pn.x2.nxv2f64(target("aarch64.svcount") %0, ptr %arrayidx2) + %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0 + %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1 + call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 0, <vscale x 2 x double> %2, <vscale x 2 x double> %5) + call void @llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32 0, <vscale x 2 x double> %3, <vscale x 2 x double> %6) + ret void +} + + +define void @multi_vector_add_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) sanitize_memory { + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32 %slice, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32 %slice.7, + <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, + <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) + ret void +} + +define void @multi_vector_add_za_vg1x4_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3) sanitize_memory { + call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32 %slice, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32 %slice.7, + <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, + <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3) + ret void +} + +define void @multi_vector_add_za_vg1x4_f32(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) sanitize_memory { + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 %slice, + <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, + <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 %slice.7, + <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, + <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) + ret void +} + +define void @multi_vector_add_za_vg1x4_f32_tuple(i64 %stride, ptr %ptr) sanitize_memory { +entry: + %0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() + %1 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %ptr) + %2 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 0 + %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 1 + %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 2 + %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 3 + %arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride + %6 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx2) + %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 0 + %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 1 + %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 2 + %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 3 + %mul3 = shl i64 %stride, 1 + %arrayidx4 = getelementptr inbounds i8, ptr %ptr, i64 %mul3 + %11 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx4) + %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 0 + %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 1 + %14 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 2 + %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 3 + %mul5 = mul i64 %stride, 3 + %arrayidx6 = getelementptr inbounds i8, ptr %ptr, i64 %mul5 + %16 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx6) + %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 0 + %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 1 + %19 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 2 + %20 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 3 + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %2, <vscale x 4 x float> %7, <vscale x 4 x float> %12, <vscale x 4 x float> %17) + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %3, <vscale x 4 x float> %8, <vscale x 4 x float> %13, <vscale x 4 x float> %18) + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %4, <vscale x 4 x float> %9, <vscale x 4 x float> %14, <vscale x 4 x float> %19) + call void @llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32 0, <vscale x 4 x float> %5, <vscale x 4 x float> %10, <vscale x 4 x float> %15, <vscale x 4 x float> %20) + ret void +} + +define void @multi_vector_add_za_vg1x4_f64(i32 %slice, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3) sanitize_memory { + call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32 %slice, + <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, + <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32 %slice.7, + <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, + <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3) + ret void +} + + +define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_add_single_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) sanitize_memory { + %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } + @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, + <vscale x 16 x i8> %zm) + ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res +} + +define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_add_single_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) sanitize_memory { + %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } + @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, + <vscale x 8 x i16> %zm) + ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res +} + +define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_add_single_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) sanitize_memory { + %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } + @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, + <vscale x 4 x i32> %zm) + ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res +} + +define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_add_single_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) sanitize_memory { + %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } + @llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, + <vscale x 2 x i64> %zm) + ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res +} + + +define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_add_single_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8>%zm) sanitize_memory { + %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } + @llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, + <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, + <vscale x 16 x i8> %zm) + ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res +} + +define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_add_x4_single_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) sanitize_memory { + %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } + @llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, + <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, + <vscale x 8 x i16> %zm) + ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res +} + +define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_add_x4_single_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) sanitize_memory { + %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } + @llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, + <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, + <vscale x 4 x i32> %zm) + ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res +} + +define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_add_x4_single_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) sanitize_memory { + %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } + @llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, + <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, + <vscale x 2 x i64> %zm) + ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res +} +declare void@llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) +declare void@llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) +declare void@llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) +declare void@llvm.aarch64.sme.add.write.single.za.vg1x4.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) +declare void@llvm.aarch64.sme.add.write.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) +declare void@llvm.aarch64.sme.add.write.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) +declare void@llvm.aarch64.sme.add.write.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) +declare void@llvm.aarch64.sme.add.write.za.vg1x4.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) +declare void@llvm.aarch64.sme.add.za32.vg1x2.nxv4i32(i32, <vscale x 4 x i32>,<vscale x 4 x i32>) +declare void@llvm.aarch64.sme.add.za64.vg1x2.nxv2i64(i32, <vscale x 2 x i64>,<vscale x 2 x i64>) +declare void@llvm.aarch64.sme.add.za32.vg1x4.nxv4i32(i32, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>) +declare void@llvm.aarch64.sme.add.za64.vg1x4.nxv2i64(i32, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>) +declare void@llvm.aarch64.sme.add.za32.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>) +declare void@llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>) +declare void@llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>) +declare void@llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>) +declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) +declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) +declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) +declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) +declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) +declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) +declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) +declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s index d3b44eb..8160544 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s @@ -218,64 +218,76 @@ v_mad_nc_i64_i32 v[2:3], s4, v7, v[8:9] clamp // GFX1250: v_mad_nc_i64_i32 v[2:3], s4, v7, v[8:9] clamp ; encoding: [0x02,0x80,0xfb,0xd6,0x04,0x0e,0x22,0x04] v_add_min_i32 v2, s4, v7, v8 -// GFX1250: v_add_min_i32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_min_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04] v_add_min_i32 v2, v4, 0, 1 -// GFX1250: v_add_min_i32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_min_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02] v_add_min_i32 v2, v4, 3, s2 -// GFX1250: v_add_min_i32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_min_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00] v_add_min_i32 v2, s4, 4, v2 -// GFX1250: v_add_min_i32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_min_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04] v_add_min_i32 v2, v4, v7, 12345 -// GFX1250: v_add_min_i32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_min_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_min_i32 v0, v1, v2, v3 clamp +// GFX1250: v_add_min_i32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x60,0xd6,0x01,0x05,0x0e,0x04] v_add_max_i32 v2, s4, v7, v8 -// GFX1250: v_add_max_i32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_max_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04] v_add_max_i32 v2, v4, 0, 1 -// GFX1250: v_add_max_i32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_max_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02] v_add_max_i32 v2, v4, 3, s2 -// GFX1250: v_add_max_i32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_max_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00] v_add_max_i32 v2, s4, 4, v2 -// GFX1250: v_add_max_i32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_max_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04] v_add_max_i32 v2, v4, v7, 12345 -// GFX1250: v_add_max_i32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_max_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_max_i32 v0, v1, v2, v3 clamp +// GFX1250: v_add_max_i32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x5e,0xd6,0x01,0x05,0x0e,0x04] v_add_min_u32 v2, s4, v7, v8 -// GFX1250: v_add_min_u32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_min_u32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04] v_add_min_u32 v2, v4, 0, 1 -// GFX1250: v_add_min_u32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_min_u32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02] v_add_min_u32 v2, v4, 3, s2 -// GFX1250: v_add_min_u32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_min_u32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00] v_add_min_u32 v2, s4, 4, v2 -// GFX1250: v_add_min_u32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_min_u32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04] v_add_min_u32 v2, v4, v7, 12345 -// GFX1250: v_add_min_u32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_min_u32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_min_u32 v0, v1, v2, v3 clamp +// GFX1250: v_add_min_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x61,0xd6,0x01,0x05,0x0e,0x04] v_add_max_u32 v2, s4, v7, v8 -// GFX1250: v_add_max_u32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_max_u32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04] v_add_max_u32 v2, v4, 0, 1 -// GFX1250: v_add_max_u32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_max_u32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02] v_add_max_u32 v2, v4, 3, s2 -// GFX1250: v_add_max_u32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_max_u32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00] v_add_max_u32 v2, s4, 4, v2 -// GFX1250: v_add_max_u32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_max_u32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04] v_add_max_u32 v2, v4, v7, 12345 -// GFX1250: v_add_max_u32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_max_u32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_max_u32 v0, v1, v2, v3 clamp +// GFX1250: v_add_max_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04] v_cvt_pk_bf16_f32 v5, v1, v2 // GFX1250: v_cvt_pk_bf16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s index 98d07ac..d913bd2 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s @@ -218,64 +218,76 @@ v_mad_nc_i64_i32 v[2:3], s4, v7, v[8:9] clamp // GFX1250: v_mad_nc_i64_i32 v[2:3], s4, v7, v[8:9] clamp ; encoding: [0x02,0x80,0xfb,0xd6,0x04,0x0e,0x22,0x04] v_add_min_i32 v2, s4, v7, v8 -// GFX1250: v_add_min_i32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_min_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04] v_add_min_i32 v2, v4, 0, 1 -// GFX1250: v_add_min_i32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_min_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02] v_add_min_i32 v2, v4, 3, s2 -// GFX1250: v_add_min_i32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_min_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00] v_add_min_i32 v2, s4, 4, v2 -// GFX1250: v_add_min_i32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_min_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04] v_add_min_i32 v2, v4, v7, 12345 -// GFX1250: v_add_min_i32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_min_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_min_i32 v0, v1, v2, v3 clamp +// GFX1250: v_add_min_i32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x60,0xd6,0x01,0x05,0x0e,0x04] v_add_max_i32 v2, s4, v7, v8 -// GFX1250: v_add_max_i32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_max_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04] v_add_max_i32 v2, v4, 0, 1 -// GFX1250: v_add_max_i32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_max_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02] v_add_max_i32 v2, v4, 3, s2 -// GFX1250: v_add_max_i32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_max_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00] v_add_max_i32 v2, s4, 4, v2 -// GFX1250: v_add_max_i32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_max_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04] v_add_max_i32 v2, v4, v7, 12345 -// GFX1250: v_add_max_i32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_max_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_max_u32 v0, v1, v2, v3 clamp +// GFX1250: v_add_max_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04] v_add_min_u32 v2, s4, v7, v8 -// GFX1250: v_add_min_u32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_min_u32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04] v_add_min_u32 v2, v4, 0, 1 -// GFX1250: v_add_min_u32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_min_u32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02] v_add_min_u32 v2, v4, 3, s2 -// GFX1250: v_add_min_u32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_min_u32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00] v_add_min_u32 v2, s4, 4, v2 -// GFX1250: v_add_min_u32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_min_u32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04] v_add_min_u32 v2, v4, v7, 12345 -// GFX1250: v_add_min_u32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_min_u32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_min_u32 v0, v1, v2, v3 clamp +// GFX1250: v_add_min_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x61,0xd6,0x01,0x05,0x0e,0x04] v_add_max_u32 v2, s4, v7, v8 -// GFX1250: v_add_max_u32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04] +// GFX1250: v_add_max_u32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04] v_add_max_u32 v2, v4, 0, 1 -// GFX1250: v_add_max_u32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02] +// GFX1250: v_add_max_u32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02] v_add_max_u32 v2, v4, 3, s2 -// GFX1250: v_add_max_u32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00] +// GFX1250: v_add_max_u32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00] v_add_max_u32 v2, s4, 4, v2 -// GFX1250: v_add_max_u32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04] +// GFX1250: v_add_max_u32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04] v_add_max_u32 v2, v4, v7, 12345 -// GFX1250: v_add_max_u32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +// GFX1250: v_add_max_u32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +v_add_max_u32 v0, v1, v2, v3 clamp +// GFX1250: v_add_max_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04] v_cvt_pk_bf16_f32 v5, v1, v2 // GFX1250: v_cvt_pk_bf16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt index 29bfa54..7af0bfe5 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt @@ -237,64 +237,76 @@ # GFX1250: v_mad_nc_i64_i32 v[2:3], s4, v7, v[8:9] clamp ; encoding: [0x02,0x80,0xfb,0xd6,0x04,0x0e,0x22,0x04] 0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04 -# GFX1250: v_add_min_i32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04] +# GFX1250: v_add_min_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x08,0x09,0x04] 0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04 -# GFX1250: v_add_min_i32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04] +# GFX1250: v_add_min_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0e,0x22,0x04] 0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02 -# GFX1250: v_add_min_i32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02] +# GFX1250: v_add_min_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x01,0x05,0x02] 0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00 -# GFX1250: v_add_min_i32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00] +# GFX1250: v_add_min_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x07,0x09,0x00] 0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00 -# GFX1250: v_add_min_i32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +# GFX1250: v_add_min_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x60,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04 +# GFX1250: v_add_max_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04] + +0x00,0x80,0x60,0xd6,0x01,0x05,0x0e,0x04 +# GFX1250: v_add_min_i32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x60,0xd6,0x01,0x05,0x0e,0x04] 0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04 -# GFX1250: v_add_max_i32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04] +# GFX1250: v_add_max_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x08,0x09,0x04] 0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04 -# GFX1250: v_add_max_i32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04] +# GFX1250: v_add_max_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0e,0x22,0x04] 0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02 -# GFX1250: v_add_max_i32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02] +# GFX1250: v_add_max_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x01,0x05,0x02] 0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00 -# GFX1250: v_add_max_i32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00] +# GFX1250: v_add_max_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x07,0x09,0x00] 0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00 -# GFX1250: v_add_max_i32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +# GFX1250: v_add_max_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5e,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] 0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04 -# GFX1250: v_add_min_u32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04] +# GFX1250: v_add_min_u32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x08,0x09,0x04] 0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04 -# GFX1250: v_add_min_u32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04] +# GFX1250: v_add_min_u32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0e,0x22,0x04] 0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02 -# GFX1250: v_add_min_u32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02] +# GFX1250: v_add_min_u32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x01,0x05,0x02] 0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00 -# GFX1250: v_add_min_u32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00] +# GFX1250: v_add_min_u32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x07,0x09,0x00] 0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00 -# GFX1250: v_add_min_u32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +# GFX1250: v_add_min_u32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x61,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +0x00,0x80,0x61,0xd6,0x01,0x05,0x0e,0x04 +# GFX1250: v_add_min_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x61,0xd6,0x01,0x05,0x0e,0x04] 0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04 -# GFX1250: v_add_max_u32_e64 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04] +# GFX1250: v_add_max_u32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x08,0x09,0x04] 0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04 -# GFX1250: v_add_max_u32_e64 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04] +# GFX1250: v_add_max_u32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0e,0x22,0x04] 0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02 -# GFX1250: v_add_max_u32_e64 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02] +# GFX1250: v_add_max_u32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x01,0x05,0x02] 0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00 -# GFX1250: v_add_max_u32_e64 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00] +# GFX1250: v_add_max_u32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x07,0x09,0x00] 0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00 -# GFX1250: v_add_max_u32_e64 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] +# GFX1250: v_add_max_u32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x5f,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00] + +0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04 +# GFX1250: v_add_max_u32 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0x5f,0xd6,0x01,0x05,0x0e,0x04] 0xff,0x81,0x6d,0xd7,0xff,0xd6,0x00,0x38,0x56,0x34,0x12,0xaf # GFX1250: v_cvt_pk_bf16_f32 v255, -|0xaf123456|, vcc_hi clamp div:2 ; encoding: [0xff,0x81,0x6d,0xd7,0xff,0xd6,0x00,0x38,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/RISCV/xsfvfexp.s b/llvm/test/MC/RISCV/xsfvfexp.s new file mode 100644 index 0000000..bd6aecd --- /dev/null +++ b/llvm/test/MC/RISCV/xsfvfexp.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexp32e %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp32e %s \ +# RUN: | llvm-objdump -d --mattr=+xsfvfexp32e - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp32e %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexp16e %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp16e %s \ +# RUN: | llvm-objdump -d --mattr=+xsfvfexp16e - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp16e %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvfbfmin,+xsfvfbfexp16e %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvfbfmin,+xsfvfbfexp16e %s \ +# RUN: | llvm-objdump -d --mattr=+xsfvfbfexp16e - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvfbfmin,+xsfvfbfexp16e %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sf.vfexp.v v2, v5, v0.t +# CHECK-INST: sf.vfexp.v v2, v5, v0.t +# CHECK-ENCODING: [0x57,0x91,0x53,0x4c] +# CHECK-ERROR: instruction requires the following: 'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction){{$}} +# CHECK-UNKNOWN: 4c539157 <unknown> diff --git a/llvm/test/MC/RISCV/xsfvfexpa.s b/llvm/test/MC/RISCV/xsfvfexpa.s new file mode 100644 index 0000000..317a103 --- /dev/null +++ b/llvm/test/MC/RISCV/xsfvfexpa.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexpa %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexpa %s \ +# RUN: | llvm-objdump -d --mattr=+xsfvfexpa - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexpa %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sf.vfexpa.v v2, v5, v0.t +# CHECK-INST: sf.vfexpa.v v2, v5, v0.t +# CHECK-ENCODING: [0x57,0x11,0x53,0x4c] +# CHECK-ERROR: instruction requires the following: 'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction){{$}} +# CHECK-UNKNOWN: 4c531157 <unknown> diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter.td b/llvm/test/TableGen/RuntimeLibcallEmitter.td index 0c23e3b..7aaf3a0 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter.td @@ -73,6 +73,8 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // All entries should be emitted in Libcall enum. // CHECK: #ifdef GET_RUNTIME_LIBCALL_ENUM +// CHECK-NEXT: #undef GET_RUNTIME_LIBCALL_ENUM +// CHECK-EMPTY: // CHECK-NEXT: namespace llvm { // CHECK-NEXT: namespace RTLIB { // CHECK-NEXT: enum Libcall : unsigned short { @@ -101,9 +103,12 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-NEXT: constexpr size_t NumLibcallImpls = 9; // CHECK-NEXT: } // End namespace RTLIB // CHECK-NEXT: } // End namespace llvm -// CHECK-NEXT: #endif +// CHECK-EMPTY: +// CHECK-NEXT: #endif // GET_RUNTIME_LIBCALL_ENUM // CHECK: #ifdef GET_INIT_RUNTIME_LIBCALL_NAMES +// CHECK-NEXT: #undef GET_INIT_RUNTIME_LIBCALL_NAMES +// CHECK-EMPTY: // CHECK-EMPTY: // CHECK-NEXT: #ifdef __GNUC__ // CHECK-NEXT: #pragma GCC diagnostic push @@ -163,13 +168,18 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-NEXT: }; // CHECK: #ifdef GET_LOOKUP_LIBCALL_IMPL_NAME_BODY +// CHECK-NEXT: #undef GET_LOOKUP_LIBCALL_IMPL_NAME_BODY +// CHECK-EMPTY: // CHECK-NEXT: size_t Size = Name.size(); // CHECK-NEXT: if (Size == 0 || Size > 9) // CHECK-NEXT: return enum_seq(RTLIB::Unsupported, RTLIB::Unsupported); // CHECK-NEXT: return lookupLibcallImplNameImpl(Name); -// CHECK-NEXT: #endif +// CHECK-EMPTY: +// CHECK-NEXT: #endif // GET_LOOKUP_LIBCALL_IMPL_NAME_BODY // CHECK: #ifdef DEFINE_GET_LOOKUP_LIBCALL_IMPL_NAME +// CHECK-NEXT: #undef DEFINE_GET_LOOKUP_LIBCALL_IMPL_NAME +// CHECK-EMPTY: // CHECK-NEXT: static inline uint64_t hash(StringRef Str) { // CHECK-NEXT: return static_cast<uint32_t>(xxh3_64bits(Str)); // CHECK-NEXT: } diff --git a/llvm/test/Transforms/InstCombine/fpextend.ll b/llvm/test/Transforms/InstCombine/fpextend.ll index 9125339..a65b73b 100644 --- a/llvm/test/Transforms/InstCombine/fpextend.ll +++ b/llvm/test/Transforms/InstCombine/fpextend.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -passes=instcombine -S | FileCheck %s +; RUN: opt < %s -passes=instcombine -use-constant-fp-for-fixed-length-splat -S | FileCheck %s define float @test(float %x) nounwind { ; CHECK-LABEL: @test( @@ -449,6 +450,28 @@ define bfloat @bf16_frem(bfloat %x) { ret bfloat %t3 } +define <4 x bfloat> @v4bf16_frem_x_const(<4 x bfloat> %x) { +; CHECK-LABEL: @v4bf16_frem_x_const( +; CHECK-NEXT: [[TMP1:%.*]] = frem <4 x bfloat> [[X:%.*]], splat (bfloat 0xR40C9) +; CHECK-NEXT: ret <4 x bfloat> [[TMP1]] +; + %t1 = fpext <4 x bfloat> %x to <4 x float> + %t2 = frem <4 x float> %t1, splat(float 6.281250e+00) + %t3 = fptrunc <4 x float> %t2 to <4 x bfloat> + ret <4 x bfloat> %t3 +} + +define <4 x bfloat> @v4bf16_frem_const_x(<4 x bfloat> %x) { +; CHECK-LABEL: @v4bf16_frem_const_x( +; CHECK-NEXT: [[TMP1:%.*]] = frem <4 x bfloat> splat (bfloat 0xR40C9), [[X:%.*]] +; CHECK-NEXT: ret <4 x bfloat> [[TMP1]] +; + %t1 = fpext <4 x bfloat> %x to <4 x float> + %t2 = frem <4 x float> splat(float 6.281250e+00), %t1 + %t3 = fptrunc <4 x float> %t2 to <4 x bfloat> + ret <4 x bfloat> %t3 +} + define <4 x float> @v4f32_fadd(<4 x float> %a) { ; CHECK-LABEL: @v4f32_fadd( ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[A:%.*]], splat (float -1.000000e+00) @@ -459,3 +482,16 @@ define <4 x float> @v4f32_fadd(<4 x float> %a) { %5 = fptrunc <4 x double> %4 to <4 x float> ret <4 x float> %5 } + +define <4 x float> @v4f32_fadd_const_not_shrinkable(<4 x float> %a) { +; CHECK-LABEL: @v4f32_fadd_const_not_shrinkable( +; CHECK-NEXT: [[TMP1:%.*]] = fpext <4 x float> [[A:%.*]] to <4 x double> +; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x double> [[TMP1]], splat (double -1.000000e+100) +; CHECK-NEXT: [[TMP3:%.*]] = fptrunc <4 x double> [[TMP2]] to <4 x float> +; CHECK-NEXT: ret <4 x float> [[TMP3]] +; + %2 = fpext <4 x float> %a to <4 x double> + %4 = fadd <4 x double> %2, splat (double -1.000000e+100) + %5 = fptrunc <4 x double> %4 to <4 x float> + ret <4 x float> %5 +} diff --git a/llvm/test/Transforms/InstCombine/ptrtoaddr.ll b/llvm/test/Transforms/InstCombine/ptrtoaddr.ll new file mode 100644 index 0000000..410c43c --- /dev/null +++ b/llvm/test/Transforms/InstCombine/ptrtoaddr.ll @@ -0,0 +1,42 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=instcombine < %s | FileCheck %s + +; The ptrtoaddr folds are also valid for pointers that have external state. +target datalayout = "pe1:64:64:64:32" + +; ptrtoaddr result type is fixed, and can't be combined with integer cast. +define i32 @ptrtoaddr_trunc(ptr %p) { +; CHECK-LABEL: define i32 @ptrtoaddr_trunc( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[P_ADDR:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[P_ADDR]] to i32 +; CHECK-NEXT: ret i32 [[TRUNC]] +; + %p.addr = ptrtoaddr ptr %p to i64 + %trunc = trunc i64 %p.addr to i32 + ret i32 %trunc +} + +define i128 @ptrtoaddr_zext(ptr %p) { +; CHECK-LABEL: define i128 @ptrtoaddr_zext( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[P_ADDR:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[EXT:%.*]] = zext i64 [[P_ADDR]] to i128 +; CHECK-NEXT: ret i128 [[EXT]] +; + %p.addr = ptrtoaddr ptr %p to i64 + %ext = zext i64 %p.addr to i128 + ret i128 %ext +} + +define i128 @ptrtoaddr_sext(ptr %p) { +; CHECK-LABEL: define i128 @ptrtoaddr_sext( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[P_ADDR:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[EXT:%.*]] = sext i64 [[P_ADDR]] to i128 +; CHECK-NEXT: ret i128 [[EXT]] +; + %p.addr = ptrtoaddr ptr %p to i64 + %ext = sext i64 %p.addr to i128 + ret i128 %ext +} diff --git a/llvm/test/Transforms/InstCombine/select-and-or.ll b/llvm/test/Transforms/InstCombine/select-and-or.ll index 453ca66..0b8eda4 100644 --- a/llvm/test/Transforms/InstCombine/select-and-or.ll +++ b/llvm/test/Transforms/InstCombine/select-and-or.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals ; RUN: opt -S -passes=instcombine < %s | FileCheck %s declare void @use(i1) @@ -6,6 +6,10 @@ declare i1 @gen_i1() declare <2 x i1> @gen_v2i1() ; Should not be converted to "and", which has different poison semantics. +;. +; CHECK: @g1 = external global i16 +; CHECK: @g2 = external global i16 +;. define i1 @logical_and(i1 %a, i1 %b) { ; CHECK-LABEL: @logical_and( ; CHECK-NEXT: [[RES:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false @@ -225,29 +229,29 @@ define i1 @not_not_true(i1 %x, i1 %y) { ; (!x && !y) --> !(x || y) -define i1 @not_not_false(i1 %x, i1 %y) { +define i1 @not_not_false(i1 %x, i1 %y) !prof !0 { ; CHECK-LABEL: @not_not_false( -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i1 true, i1 [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i1 true, i1 [[Y:%.*]], !prof [[PROF1:![0-9]+]] ; CHECK-NEXT: [[R:%.*]] = xor i1 [[TMP1]], true ; CHECK-NEXT: ret i1 [[R]] ; %notx = xor i1 %x, true %noty = xor i1 %y, true - %r = select i1 %notx, i1 %noty, i1 false + %r = select i1 %notx, i1 %noty, i1 false, !prof !1 ret i1 %r } ; (!x || !y) --> !(x && y) -define i1 @not_true_not(i1 %x, i1 %y) { +define i1 @not_true_not(i1 %x, i1 %y) !prof !0 { ; CHECK-LABEL: @not_true_not( -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false, !prof [[PROF1]] ; CHECK-NEXT: [[R:%.*]] = xor i1 [[TMP1]], true ; CHECK-NEXT: ret i1 [[R]] ; %notx = xor i1 %x, true %noty = xor i1 %y, true - %r = select i1 %notx, i1 true, i1 %noty + %r = select i1 %notx, i1 true, i1 %noty, !prof !1 ret i1 %r } @@ -1348,3 +1352,12 @@ define i8 @test_logical_commuted_and_ne_a_b(i1 %other_cond, i8 %a, i8 %b) { %select = select i1 %or.cond, i8 %a, i8 %b ret i8 %select } + +!0 = !{!"function_entry_count", i64 1000} +!1 = !{!"branch_weights", i32 2, i32 3} +;. +; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;. +; CHECK: [[META0:![0-9]+]] = !{!"function_entry_count", i64 1000} +; CHECK: [[PROF1]] = !{!"branch_weights", i32 3, i32 2} +;. diff --git a/llvm/test/Transforms/InstCombine/select-safe-transforms.ll b/llvm/test/Transforms/InstCombine/select-safe-transforms.ll index d88eaf8..3d97048 100644 --- a/llvm/test/Transforms/InstCombine/select-safe-transforms.ll +++ b/llvm/test/Transforms/InstCombine/select-safe-transforms.ll @@ -58,15 +58,15 @@ define i1 @cond_eq_or_const(i8 %X, i8 %Y) !prof !0 { ret i1 %res } -define i1 @xor_and(i1 %c, i32 %X, i32 %Y) { +define i1 @xor_and(i1 %c, i32 %X, i32 %Y) !prof !0 { ; CHECK-LABEL: @xor_and( ; CHECK-NEXT: [[COMP:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true -; CHECK-NEXT: [[SEL:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[COMP]] +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[COMP]], !prof [[PROF2:![0-9]+]] ; CHECK-NEXT: ret i1 [[SEL]] ; %comp = icmp ult i32 %X, %Y - %sel = select i1 %c, i1 %comp, i1 false + %sel = select i1 %c, i1 %comp, i1 false, !prof !1 %res = xor i1 %sel, true ret i1 %res } @@ -97,15 +97,15 @@ define <2 x i1> @xor_and3(<2 x i1> %c, <2 x i32> %X, <2 x i32> %Y) { ret <2 x i1> %res } -define i1 @xor_or(i1 %c, i32 %X, i32 %Y) { +define i1 @xor_or(i1 %c, i32 %X, i32 %Y) !prof !0 { ; CHECK-LABEL: @xor_or( ; CHECK-NEXT: [[COMP:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true -; CHECK-NEXT: [[SEL:%.*]] = select i1 [[NOT_C]], i1 [[COMP]], i1 false +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[NOT_C]], i1 [[COMP]], i1 false, !prof [[PROF2]] ; CHECK-NEXT: ret i1 [[SEL]] ; %comp = icmp ult i32 %X, %Y - %sel = select i1 %c, i1 true, i1 %comp + %sel = select i1 %c, i1 true, i1 %comp, !prof !1 %res = xor i1 %sel, true ret i1 %res } @@ -802,4 +802,5 @@ define <2 x i1> @not_logical_and2(i1 %b, <2 x i32> %a) { ;. ; CHECK: [[META0:![0-9]+]] = !{!"function_entry_count", i64 1000} ; CHECK: [[PROF1]] = !{!"branch_weights", i32 2, i32 3} +; CHECK: [[PROF2]] = !{!"branch_weights", i32 3, i32 2} ;. diff --git a/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll b/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll new file mode 100644 index 0000000..7816781 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll @@ -0,0 +1,243 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -S -passes=instcombine | FileCheck %s +@A = extern_weak global float, align 4 + +; %same.as.v1 is a select with two phis %v1 and %phi.to.remove as the true +; and false values, while %v1 and %phi.to.remove are actually the same. +; Fold the selection instruction %same.as.v1 to %v1. +define void @select_with_identical_phi(ptr %m, ptr %n, i32 %count) { +; CHECK-LABEL: @select_with_identical_phi( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: [[V0:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q:%.*]] = phi ptr [ [[M:%.*]], [[ENTRY]] ], [ [[Q_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[C:%.*]] = phi ptr [ [[N:%.*]], [[ENTRY]] ], [ [[C_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q_LOAD:%.*]] = load float, ptr [[Q]], align 4 +; CHECK-NEXT: [[C_LOAD:%.*]] = load float, ptr [[C]], align 4 +; CHECK-NEXT: [[SUB:%.*]] = fsub float [[Q_LOAD]], [[C_LOAD]] +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[SUB]], [[V0]] +; CHECK-NEXT: [[V0_1]] = select i1 [[CMP1]], float [[SUB]], float [[V0]] +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[SUB]], [[V1]] +; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2]], float [[SUB]], float [[V1]] +; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1 +; CHECK-NEXT: [[Q_NEXT]] = getelementptr inbounds nuw i8, ptr [[Q]], i64 4 +; CHECK-NEXT: [[C_NEXT]] = getelementptr inbounds nuw i8, ptr [[C]], i64 4 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC_I]], [[COUNT:%.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[FOR_BODY]] +; CHECK: exit: +; CHECK-NEXT: store float [[V1_1]], ptr @A, align 4 +; CHECK-NEXT: ret void +; +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %v0 = phi float [ 0x4415AF1D80000000, %entry ], [ %v0.1, %for.body ] + %v1 = phi float [ 0xC415AF1D80000000, %entry ], [ %v1.1, %for.body ] + %phi.to.remove = phi float [ 0xC415AF1D80000000, %entry ], [ %phi.to.remove.next, %for.body ] + %i = phi i32 [ 0, %entry ], [ %inc.i, %for.body ] + %q = phi ptr [ %m, %entry ], [ %q.next, %for.body ] + %c = phi ptr [ %n, %entry ], [ %c.next, %for.body ] + %q.load = load float, ptr %q + %c.load = load float, ptr %c + %sub = fsub float %q.load, %c.load + %cmp1 = fcmp olt float %sub, %v0 + %v0.1 = select i1 %cmp1, float %sub, float %v0 + %same.as.v1 = select i1 %cmp1, float %v1, float %phi.to.remove + %cmp2 = fcmp ogt float %sub, %same.as.v1 + %v1.1 = select i1 %cmp2, float %sub, float %v1 + %phi.to.remove.next = select i1 %cmp2, float %sub, float %same.as.v1 + %inc.i = add nuw nsw i32 %i, 1 + %q.next = getelementptr inbounds i8, ptr %q, i64 4 + %c.next = getelementptr inbounds i8, ptr %c, i64 4 + %exitcond = icmp eq i32 %inc.i, %count + br i1 %exitcond, label %exit, label %for.body + +exit: + %vl.1.lcssa = phi float [ %v1.1, %for.body ] + store float %vl.1.lcssa, ptr @A + ret void +} + +; The difference from select_with_identical_phi() is that the true and false values in +; %phi.to.remove.next and %v1.1 are swapped. +; Check that %same.as.v1 can be folded. +define void @select_with_identical_phi_2(ptr %m, ptr %n, i32 %count) { +; CHECK-LABEL: @select_with_identical_phi_2( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: [[V0:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q:%.*]] = phi ptr [ [[M:%.*]], [[ENTRY]] ], [ [[Q_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[C:%.*]] = phi ptr [ [[N:%.*]], [[ENTRY]] ], [ [[C_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q_LOAD:%.*]] = load float, ptr [[Q]], align 4 +; CHECK-NEXT: [[C_LOAD:%.*]] = load float, ptr [[C]], align 4 +; CHECK-NEXT: [[SUB:%.*]] = fsub float [[Q_LOAD]], [[C_LOAD]] +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[SUB]], [[V0]] +; CHECK-NEXT: [[V0_1]] = select i1 [[CMP1]], float [[SUB]], float [[V0]] +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[SUB]], [[V1]] +; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2]], float [[V1]], float [[SUB]] +; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1 +; CHECK-NEXT: [[Q_NEXT]] = getelementptr inbounds nuw i8, ptr [[Q]], i64 4 +; CHECK-NEXT: [[C_NEXT]] = getelementptr inbounds nuw i8, ptr [[C]], i64 4 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC_I]], [[COUNT:%.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[FOR_BODY]] +; CHECK: exit: +; CHECK-NEXT: store float [[V1_1]], ptr @A, align 4 +; CHECK-NEXT: ret void +; +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %v0 = phi float [ 0x4415AF1D80000000, %entry ], [ %v0.1, %for.body ] + %v1 = phi float [ 0xC415AF1D80000000, %entry ], [ %v1.1, %for.body ] + %phi.to.remove = phi float [ 0xC415AF1D80000000, %entry ], [ %phi.to.remove.next, %for.body ] + %i = phi i32 [ 0, %entry ], [ %inc.i, %for.body ] + %q = phi ptr [ %m, %entry ], [ %q.next, %for.body ] + %c = phi ptr [ %n, %entry ], [ %c.next, %for.body ] + %q.load = load float, ptr %q + %c.load = load float, ptr %c + %sub = fsub float %q.load, %c.load + %cmp1 = fcmp olt float %sub, %v0 + %v0.1 = select i1 %cmp1, float %sub, float %v0 + %same.as.v1 = select i1 %cmp1, float %v1, float %phi.to.remove + %cmp2 = fcmp ogt float %sub, %same.as.v1 + %v1.1 = select i1 %cmp2, float %v1, float %sub + %phi.to.remove.next = select i1 %cmp2, float %same.as.v1, float %sub + %inc.i = add nuw nsw i32 %i, 1 + %q.next = getelementptr inbounds i8, ptr %q, i64 4 + %c.next = getelementptr inbounds i8, ptr %c, i64 4 + %exitcond = icmp eq i32 %inc.i, %count + br i1 %exitcond, label %exit, label %for.body + +exit: + %vl.1.lcssa = phi float [ %v1.1, %for.body ] + store float %vl.1.lcssa, ptr @A + ret void +} + +; The difference from select_with_identical_phi() is that the true and false values in +; same.as.v1 are swapped. +; Check that %same.as.v1 can be folded. +define void @select_with_identical_phi_3(ptr %m, ptr %n, i32 %count) { +; CHECK-LABEL: @select_with_identical_phi_3( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: [[V0:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q:%.*]] = phi ptr [ [[M:%.*]], [[ENTRY]] ], [ [[Q_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[C:%.*]] = phi ptr [ [[N:%.*]], [[ENTRY]] ], [ [[C_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q_LOAD:%.*]] = load float, ptr [[Q]], align 4 +; CHECK-NEXT: [[C_LOAD:%.*]] = load float, ptr [[C]], align 4 +; CHECK-NEXT: [[SUB:%.*]] = fsub float [[Q_LOAD]], [[C_LOAD]] +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[SUB]], [[V0]] +; CHECK-NEXT: [[V0_1]] = select i1 [[CMP1]], float [[SUB]], float [[V0]] +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[SUB]], [[V1]] +; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2]], float [[SUB]], float [[V1]] +; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1 +; CHECK-NEXT: [[Q_NEXT]] = getelementptr inbounds nuw i8, ptr [[Q]], i64 4 +; CHECK-NEXT: [[C_NEXT]] = getelementptr inbounds nuw i8, ptr [[C]], i64 4 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC_I]], [[COUNT:%.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[FOR_BODY]] +; CHECK: exit: +; CHECK-NEXT: store float [[V1_1]], ptr @A, align 4 +; CHECK-NEXT: ret void +; +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %v0 = phi float [ 0x4415AF1D80000000, %entry ], [ %v0.1, %for.body ] + %v1 = phi float [ 0xC415AF1D80000000, %entry ], [ %v1.1, %for.body ] + %phi.to.remove = phi float [ 0xC415AF1D80000000, %entry ], [ %phi.to.remove.next, %for.body ] + %i = phi i32 [ 0, %entry ], [ %inc.i, %for.body ] + %q = phi ptr [ %m, %entry ], [ %q.next, %for.body ] + %c = phi ptr [ %n, %entry ], [ %c.next, %for.body ] + %q.load = load float, ptr %q + %c.load = load float, ptr %c + %sub = fsub float %q.load, %c.load + %cmp1 = fcmp olt float %sub, %v0 + %v0.1 = select i1 %cmp1, float %sub, float %v0 + %same.as.v1 = select i1 %cmp1, float %phi.to.remove, float %v1 + %cmp2 = fcmp ogt float %sub, %same.as.v1 + %v1.1 = select i1 %cmp2, float %sub, float %v1 + %phi.to.remove.next = select i1 %cmp2, float %sub, float %same.as.v1 + %inc.i = add nuw nsw i32 %i, 1 + %q.next = getelementptr inbounds i8, ptr %q, i64 4 + %c.next = getelementptr inbounds i8, ptr %c, i64 4 + %exitcond = icmp eq i32 %inc.i, %count + br i1 %exitcond, label %exit, label %for.body + +exit: + %vl.1.lcssa = phi float [ %v1.1, %for.body ] + store float %vl.1.lcssa, ptr @A + ret void +} + +; The difference from select_with_identical_phi() is that the true and false values in +; %same.as.v1, %phi.to.remove.next and %v1.1 are swapped. +; Check that %same.as.v1 can be folded. +define void @select_with_identical_phi_4(ptr %m, ptr %n, i32 %count) { +; CHECK-LABEL: @select_with_identical_phi_4( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: [[V0:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q:%.*]] = phi ptr [ [[M:%.*]], [[ENTRY]] ], [ [[Q_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[C:%.*]] = phi ptr [ [[N:%.*]], [[ENTRY]] ], [ [[C_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[Q_LOAD:%.*]] = load float, ptr [[Q]], align 4 +; CHECK-NEXT: [[C_LOAD:%.*]] = load float, ptr [[C]], align 4 +; CHECK-NEXT: [[SUB:%.*]] = fsub float [[Q_LOAD]], [[C_LOAD]] +; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[SUB]], [[V0]] +; CHECK-NEXT: [[V0_1]] = select i1 [[CMP1]], float [[SUB]], float [[V0]] +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[SUB]], [[V1]] +; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2]], float [[V1]], float [[SUB]] +; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1 +; CHECK-NEXT: [[Q_NEXT]] = getelementptr inbounds nuw i8, ptr [[Q]], i64 4 +; CHECK-NEXT: [[C_NEXT]] = getelementptr inbounds nuw i8, ptr [[C]], i64 4 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC_I]], [[COUNT:%.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[FOR_BODY]] +; CHECK: exit: +; CHECK-NEXT: store float [[V1_1]], ptr @A, align 4 +; CHECK-NEXT: ret void +; +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %v0 = phi float [ 0x4415AF1D80000000, %entry ], [ %v0.1, %for.body ] + %v1 = phi float [ 0xC415AF1D80000000, %entry ], [ %v1.1, %for.body ] + %phi.to.remove = phi float [ 0xC415AF1D80000000, %entry ], [ %phi.to.remove.next, %for.body ] + %i = phi i32 [ 0, %entry ], [ %inc.i, %for.body ] + %q = phi ptr [ %m, %entry ], [ %q.next, %for.body ] + %c = phi ptr [ %n, %entry ], [ %c.next, %for.body ] + %q.load = load float, ptr %q + %c.load = load float, ptr %c + %sub = fsub float %q.load, %c.load + %cmp1 = fcmp olt float %sub, %v0 + %v0.1 = select i1 %cmp1, float %sub, float %v0 + %same.as.v1 = select i1 %cmp1, float %phi.to.remove, float %v1 + %cmp2 = fcmp ogt float %sub, %same.as.v1 + %v1.1 = select i1 %cmp2, float %v1, float %sub + %phi.to.remove.next = select i1 %cmp2, float %same.as.v1, float %sub + %inc.i = add nuw nsw i32 %i, 1 + %q.next = getelementptr inbounds i8, ptr %q, i64 4 + %c.next = getelementptr inbounds i8, ptr %c, i64 4 + %exitcond = icmp eq i32 %inc.i, %count + br i1 %exitcond, label %exit, label %for.body + +exit: + %vl.1.lcssa = phi float [ %v1.1, %for.body ] + store float %vl.1.lcssa, ptr @A + ret void +} diff --git a/llvm/test/Transforms/InstSimplify/ptrtoaddr.ll b/llvm/test/Transforms/InstSimplify/ptrtoaddr.ll index 03a2d4b..d06b520 100644 --- a/llvm/test/Transforms/InstSimplify/ptrtoaddr.ll +++ b/llvm/test/Transforms/InstSimplify/ptrtoaddr.ll @@ -207,3 +207,112 @@ define i32 @ptrtoaddr_of_ptradd_of_sub_addrsize(i32 %x, ptr addrspace(1) %p) { %ptradd.addr = ptrtoaddr ptr addrspace(1) %ptradd to i32 ret i32 %ptradd.addr } + +define ptr @gep_of_sub_ptrtoaddr_unrelated_pointers(ptr %p, ptr %p2, i64 %x) { +; CHECK-LABEL: define ptr @gep_of_sub_ptrtoaddr_unrelated_pointers( +; CHECK-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[P2_ADDR:%.*]] = ptrtoaddr ptr [[P2]] to i64 +; CHECK-NEXT: [[P_ADDR:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[P2_ADDR]], [[P_ADDR]] +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr [[P]], i64 [[SUB]] +; CHECK-NEXT: ret ptr [[GEP2]] +; + %p2.addr = ptrtoaddr ptr %p2 to i64 + %p.addr = ptrtoaddr ptr %p to i64 + %sub = sub i64 %p2.addr, %p.addr + %gep2 = getelementptr i8, ptr %p, i64 %sub + ret ptr %gep2 +} + +define ptr @gep_of_sub_ptrtoaddr(ptr %p, i64 %x) { +; CHECK-LABEL: define ptr @gep_of_sub_ptrtoaddr( +; CHECK-SAME: ptr [[P:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr [[P]], i64 [[X]] +; CHECK-NEXT: ret ptr [[GEP1]] +; + %gep1 = getelementptr i8, ptr %p, i64 %x + %gep1.addr = ptrtoaddr ptr %gep1 to i64 + %p.addr = ptrtoaddr ptr %p to i64 + %sub = sub i64 %gep1.addr, %p.addr + %gep2 = getelementptr i8, ptr %p, i64 %sub + ret ptr %gep2 +} + +define ptr addrspace(1) @gep_of_sub_ptrtoaddr_addrsize(ptr addrspace(1) %p, i32 %x) { +; CHECK-LABEL: define ptr addrspace(1) @gep_of_sub_ptrtoaddr_addrsize( +; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[X:%.*]]) { +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[P]], i32 [[X]] +; CHECK-NEXT: ret ptr addrspace(1) [[GEP1]] +; + %gep1 = getelementptr i8, ptr addrspace(1) %p, i32 %x + %gep1.addr = ptrtoaddr ptr addrspace(1) %gep1 to i32 + %p.addr = ptrtoaddr ptr addrspace(1) %p to i32 + %sub = sub i32 %gep1.addr, %p.addr + %gep2 = getelementptr i8, ptr addrspace(1) %p, i32 %sub + ret ptr addrspace(1) %gep2 +} + +define ptr @gep_of_sub_ptrtoaddr_ashr(ptr %p, i64 %x) { +; CHECK-LABEL: define ptr @gep_of_sub_ptrtoaddr_ashr( +; CHECK-SAME: ptr [[P:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr [[P]], i64 [[X]] +; CHECK-NEXT: ret ptr [[GEP1]] +; + %gep1 = getelementptr i8, ptr %p, i64 %x + %gep1.addr = ptrtoaddr ptr %gep1 to i64 + %p.addr = ptrtoaddr ptr %p to i64 + %sub = sub i64 %gep1.addr, %p.addr + %ashr = ashr i64 %sub, 1 + %gep2 = getelementptr i16, ptr %p, i64 %ashr + ret ptr %gep2 +} + +define ptr addrspace(1) @gep_of_sub_ptrtoaddr_ashr_addrsize(ptr addrspace(1) %p, i32 %x) { +; CHECK-LABEL: define ptr addrspace(1) @gep_of_sub_ptrtoaddr_ashr_addrsize( +; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[X:%.*]]) { +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[P]], i32 [[X]] +; CHECK-NEXT: ret ptr addrspace(1) [[GEP1]] +; + %gep1 = getelementptr i8, ptr addrspace(1) %p, i32 %x + %gep1.addr = ptrtoaddr ptr addrspace(1) %gep1 to i32 + %p.addr = ptrtoaddr ptr addrspace(1) %p to i32 + %sub = sub i32 %gep1.addr, %p.addr + %sdiv = sdiv i32 %sub, 3 + %gep2 = getelementptr [3 x i8], ptr addrspace(1) %p, i32 %sdiv + ret ptr addrspace(1) %gep2 +} + +; Not folding this to inttoptr(123), as this may have different provenance from +; %p, and the use of ptrtoaddr implies that the provenance of %p may not be +; exposed, such that inttoptr cannot recover it. +define ptr @gep_gep_neg_ptrtoaddr(ptr %p) { +; CHECK-LABEL: define ptr @gep_gep_neg_ptrtoaddr( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 123 +; CHECK-NEXT: [[P_ADDR:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[P_ADDR_NEG:%.*]] = sub i64 0, [[P_ADDR]] +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr [[GEP1]], i64 [[P_ADDR_NEG]] +; CHECK-NEXT: ret ptr [[GEP2]] +; + %gep1 = getelementptr inbounds i8, ptr %p, i64 123 + %p.addr = ptrtoaddr ptr %p to i64 + %p.addr.neg = sub i64 0, %p.addr + %gep2 = getelementptr i8, ptr %gep1, i64 %p.addr.neg + ret ptr %gep2 +} + +define ptr @gep_gep_inv_ptrtoaddr(ptr %p) { +; CHECK-LABEL: define ptr @gep_gep_inv_ptrtoaddr( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 123 +; CHECK-NEXT: [[P_ADDR:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[P_ADDR_INV:%.*]] = xor i64 [[P_ADDR]], -1 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr [[GEP1]], i64 [[P_ADDR_INV]] +; CHECK-NEXT: ret ptr [[GEP2]] +; + %gep1 = getelementptr inbounds i8, ptr %p, i64 123 + %p.addr = ptrtoaddr ptr %p to i64 + %p.addr.inv = xor i64 %p.addr, -1 + %gep2 = getelementptr i8, ptr %gep1, i64 %p.addr.inv + ret ptr %gep2 +} diff --git a/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll b/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll index 2b5960e..90d0db2 100644 --- a/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll +++ b/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll @@ -56,7 +56,7 @@ if.then46: ; preds = %for.body40 br label %for.inc50 for.inc50: ; preds = %if.then46, %for.body40 - %k.1 = phi i32 [ undef, %for.body40 ], [ %inc47, %if.then46 ] + %k.1 = phi i32 [ 0, %for.body40 ], [ %inc47, %if.then46 ] %step.1 = phi i32 [ %step.0121, %for.body40 ], [ %inc47, %if.then46 ] %indvars.iv.next124 = add i64 %indvars.iv123, 1 %lftr.wideiv = trunc i64 %indvars.iv.next124 to i32 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll index 1c2840f..70532ad 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll @@ -1117,24 +1117,24 @@ define i64 @sext_reduction_i32_to_i64(ptr %arr, i64 %n) #1 { ; CHECK-INTERLEAVE1-SAME: ptr [[ARR:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { ; CHECK-INTERLEAVE1-NEXT: entry: ; CHECK-INTERLEAVE1-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) -; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 2 +; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4 ; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK-INTERLEAVE1: vector.ph: -; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 2 +; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4 ; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]] ; CHECK-INTERLEAVE1-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-INTERLEAVE1: vector.body: ; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] +; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ] ; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[INDEX]] -; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4 -; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = sext <2 x i32> [[WIDE_LOAD]] to <2 x i64> -; CHECK-INTERLEAVE1-NEXT: [[TMP2]] = add <2 x i64> [[VEC_PHI]], [[TMP1]] -; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64> +; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <2 x i64> @llvm.vector.partial.reduce.add.v2i64.v4i64(<2 x i64> [[VEC_PHI]], <4 x i64> [[TMP1]]) +; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: -; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[TMP2]]) +; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[PARTIAL_REDUCE]]) ; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; CHECK-INTERLEAVE1: scalar.ph: @@ -1143,42 +1143,42 @@ define i64 @sext_reduction_i32_to_i64(ptr %arr, i64 %n) #1 { ; CHECK-INTERLEAVED-SAME: ptr [[ARR:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { ; CHECK-INTERLEAVED-NEXT: entry: ; CHECK-INTERLEAVED-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) -; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 8 +; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 16 ; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK-INTERLEAVED: vector.ph: -; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 8 +; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 16 ; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]] ; CHECK-INTERLEAVED-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-INTERLEAVED: vector.body: ; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI2:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE7:%.*]], [[VECTOR_BODY]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI2:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE8:%.*]], [[VECTOR_BODY]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE9:%.*]], [[VECTOR_BODY]] ] ; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[INDEX]] -; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 2 ; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 4 -; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 6 -; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4 -; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4 -; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i32>, ptr [[TMP2]], align 4 -; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4 -; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = sext <2 x i32> [[WIDE_LOAD]] to <2 x i64> -; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = sext <2 x i32> [[WIDE_LOAD4]] to <2 x i64> -; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = sext <2 x i32> [[WIDE_LOAD5]] to <2 x i64> -; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = sext <2 x i32> [[WIDE_LOAD6]] to <2 x i64> -; CHECK-INTERLEAVED-NEXT: [[TMP8]] = add <2 x i64> [[VEC_PHI]], [[TMP14]] -; CHECK-INTERLEAVED-NEXT: [[TMP9]] = add <2 x i64> [[VEC_PHI1]], [[TMP5]] -; CHECK-INTERLEAVED-NEXT: [[TMP10]] = add <2 x i64> [[VEC_PHI2]], [[TMP6]] -; CHECK-INTERLEAVED-NEXT: [[TMP11]] = add <2 x i64> [[VEC_PHI3]], [[TMP7]] -; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 8 +; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 12 +; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 +; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4 +; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 +; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64> +; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = sext <4 x i32> [[WIDE_LOAD4]] to <4 x i64> +; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = sext <4 x i32> [[WIDE_LOAD5]] to <4 x i64> +; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = sext <4 x i32> [[WIDE_LOAD6]] to <4 x i64> +; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <2 x i64> @llvm.vector.partial.reduce.add.v2i64.v4i64(<2 x i64> [[VEC_PHI]], <4 x i64> [[TMP15]]) +; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE7]] = call <2 x i64> @llvm.vector.partial.reduce.add.v2i64.v4i64(<2 x i64> [[VEC_PHI1]], <4 x i64> [[TMP5]]) +; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE8]] = call <2 x i64> @llvm.vector.partial.reduce.add.v2i64.v4i64(<2 x i64> [[VEC_PHI2]], <4 x i64> [[TMP6]]) +; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE9]] = call <2 x i64> @llvm.vector.partial.reduce.add.v2i64.v4i64(<2 x i64> [[VEC_PHI3]], <4 x i64> [[TMP7]]) +; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: -; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[TMP9]], [[TMP8]] -; CHECK-INTERLEAVED-NEXT: [[BIN_RDX7:%.*]] = add <2 x i64> [[TMP10]], [[BIN_RDX]] -; CHECK-INTERLEAVED-NEXT: [[BIN_RDX8:%.*]] = add <2 x i64> [[TMP11]], [[BIN_RDX7]] -; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX8]]) +; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[PARTIAL_REDUCE7]], [[PARTIAL_REDUCE]] +; CHECK-INTERLEAVED-NEXT: [[BIN_RDX10:%.*]] = add <2 x i64> [[PARTIAL_REDUCE8]], [[BIN_RDX]] +; CHECK-INTERLEAVED-NEXT: [[BIN_RDX11:%.*]] = add <2 x i64> [[PARTIAL_REDUCE9]], [[BIN_RDX10]] +; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX11]]) ; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; CHECK-INTERLEAVED: scalar.ph: @@ -1187,24 +1187,24 @@ define i64 @sext_reduction_i32_to_i64(ptr %arr, i64 %n) #1 { ; CHECK-MAXBW-SAME: ptr [[ARR:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { ; CHECK-MAXBW-NEXT: entry: ; CHECK-MAXBW-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) -; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 2 +; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4 ; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK-MAXBW: vector.ph: -; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 2 +; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4 ; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]] ; CHECK-MAXBW-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-MAXBW: vector.body: ; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] +; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], [[VECTOR_BODY]] ] ; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[INDEX]] -; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4 -; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = sext <2 x i32> [[WIDE_LOAD]] to <2 x i64> -; CHECK-MAXBW-NEXT: [[TMP2]] = add <2 x i64> [[VEC_PHI]], [[TMP1]] -; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 +; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64> +; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <2 x i64> @llvm.vector.partial.reduce.add.v2i64.v4i64(<2 x i64> [[VEC_PHI]], <4 x i64> [[TMP1]]) +; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]] ; CHECK-MAXBW: middle.block: -; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[TMP2]]) +; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[PARTIAL_REDUCE]]) ; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; CHECK-MAXBW: scalar.ph: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll b/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll index 20b5364..ebf4a4f 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll @@ -9,9 +9,7 @@ define i32 @fn1() local_unnamed_addr #0 { ; We expect the backend to expand all reductions. ; CHECK: @llvm.vector.reduce entry: - %0 = load i32, ptr @b, align 4, !tbaa !1 - %cmp40 = icmp sgt i32 %0, 0 - br i1 %cmp40, label %for.body.lr.ph, label %for.end + br label %for.body.lr.ph for.body.lr.ph: ; preds = %entry %1 = load ptr, ptr @a, align 8, !tbaa !5 @@ -21,8 +19,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] - %d.043 = phi i16 [ undef, %for.body.lr.ph ], [ %.sink28, %for.body ] - %c.042 = phi i16 [ undef, %for.body.lr.ph ], [ %c.0., %for.body ] + %d.043 = phi i16 [ 0, %for.body.lr.ph ], [ %.sink28, %for.body ] + %c.042 = phi i16 [ 0, %for.body.lr.ph ], [ %c.0., %for.body ] %arrayidx = getelementptr inbounds i16, ptr %1, i64 %indvars.iv %4 = load i16, ptr %arrayidx, align 2, !tbaa !7 %cmp2 = icmp sgt i16 %c.042, %4 @@ -33,10 +31,8 @@ for.body: ; preds = %for.body.lr.ph, %fo %cmp = icmp slt i64 %indvars.iv.next, %3 br i1 %cmp, label %for.body, label %for.end -for.end: ; preds = %for.body, %entry - %c.0.lcssa = phi i16 [ undef, %entry ], [ %c.0., %for.body ] - %d.0.lcssa = phi i16 [ undef, %entry ], [ %.sink28, %for.body ] - %cmp26 = icmp sgt i16 %c.0.lcssa, %d.0.lcssa +for.end: ; preds = %for.body + %cmp26 = icmp sgt i16 %c.0., %.sink28 %conv27 = zext i1 %cmp26 to i32 ret i32 %conv27 } diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll b/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll index 44820e0..33ce300 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll @@ -18,7 +18,7 @@ define void @_Z1dv() local_unnamed_addr #0 { ; CHECK-NEXT: br label [[FOR_COND:%.*]] ; CHECK: for.cond: ; CHECK-NEXT: [[F_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD5:%.*]], [[FOR_COND_CLEANUP:%.*]] ] -; CHECK-NEXT: [[G_0:%.*]] = phi i32 [ undef, [[ENTRY]] ], [ [[G_1_LCSSA:%.*]], [[FOR_COND_CLEANUP]] ] +; CHECK-NEXT: [[G_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[G_1_LCSSA:%.*]], [[FOR_COND_CLEANUP]] ] ; CHECK-NEXT: [[CMP12:%.*]] = icmp ult i32 [[G_0]], 4 ; CHECK-NEXT: [[CONV:%.*]] = and i32 [[F_0]], 65535 ; CHECK-NEXT: br i1 [[CMP12]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_COND_CLEANUP]] @@ -50,7 +50,7 @@ entry: for.cond: ; preds = %for.cond.cleanup, %entry %f.0 = phi i32 [ 0, %entry ], [ %add5, %for.cond.cleanup ] - %g.0 = phi i32 [ undef, %entry ], [ %g.1.lcssa, %for.cond.cleanup ] + %g.0 = phi i32 [ 0, %entry ], [ %g.1.lcssa, %for.cond.cleanup ] %cmp12 = icmp ult i32 %g.0, 4 %conv = and i32 %f.0, 65535 br i1 %cmp12, label %for.body.lr.ph, label %for.cond.cleanup diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll index de804600..786a2aa 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll @@ -728,8 +728,8 @@ define void @int_float_struct(ptr nocapture readonly %p) #0 { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> zeroinitializer, float undef, i32 0), [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ insertelement (<vscale x 4 x i32> zeroinitializer, i32 undef, i32 0), [[VECTOR_PH]] ], [ [[TMP6:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP6:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_INTFLOAT:%.*]], ptr [[P:%.*]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 8 x i32>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC]]) @@ -755,8 +755,8 @@ for.cond.cleanup: ; preds = %for.body for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] - %SumB.014 = phi float [ undef, %entry ], [ %add3, %for.body ] - %SumA.013 = phi i32 [ undef, %entry ], [ %add, %for.body ] + %SumB.014 = phi float [ 0.0e+00, %entry ], [ %add3, %for.body ] + %SumA.013 = phi i32 [ 0, %entry ], [ %add, %for.body ] %a = getelementptr inbounds %struct.IntFloat, ptr %p, i64 %indvars.iv, i32 0 %load1 = load i32, ptr %a, align 4 %add = add nsw i32 %load1, %SumA.013 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll index 005ca8c..ae8dc2d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll @@ -175,28 +175,18 @@ define void @test_add_double_same_var_args_1(ptr %res, ptr noalias %A, ptr noali ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[A]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[A]], i64 [[TMP0]] -; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP1]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3> -; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <4 x double>, ptr [[TMP2]], align 4 -; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 1, i32 3> -; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[STRIDED_VEC]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[STRIDED_VEC3]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = load <2 x double>, ptr [[TMP1]], align 4 +; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = load <2 x double>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[STRIDED_VEC1]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[STRIDED_VEC4]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[RES]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[RES]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP7]], align 4 -; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC5:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC5]], ptr [[TMP8]], align 4 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[TMP7]], align 4 +; CHECK-NEXT: store <2 x double> [[TMP6]], ptr [[TMP8]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 ; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: @@ -237,28 +227,18 @@ define void @test_add_double_same_var_args_2(ptr %res, ptr noalias %A, ptr noali ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[A]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[A]], i64 [[TMP0]] -; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP1]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3> -; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <4 x double>, ptr [[TMP2]], align 4 -; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 1, i32 3> -; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[BROADCAST_SPLAT]], [[STRIDED_VEC]] -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[BROADCAST_SPLAT]], [[STRIDED_VEC3]] +; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = load <2 x double>, ptr [[TMP1]], align 4 +; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = load <2 x double>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[BROADCAST_SPLAT]], [[STRIDED_VEC1]] ; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[BROADCAST_SPLAT]], [[STRIDED_VEC4]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[RES]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[RES]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP7]], align 4 -; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC5:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC5]], ptr [[TMP8]], align 4 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[TMP7]], align 4 +; CHECK-NEXT: store <2 x double> [[TMP6]], ptr [[TMP8]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 ; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll index 2a19402..b23702d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll @@ -319,46 +319,46 @@ define void @single_fmul_used_by_each_member(ptr noalias %A, ptr noalias %B, ptr ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 2 -; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[INDEX]], 6 +; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[INDEX]], 3 ; CHECK-NEXT: [[TMP23:%.*]] = getelementptr double, ptr [[A]], i64 [[INDEX]] -; CHECK-NEXT: [[TMP25:%.*]] = getelementptr double, ptr [[TMP23]], i32 2 -; CHECK-NEXT: [[TMP26:%.*]] = getelementptr double, ptr [[TMP23]], i32 4 -; CHECK-NEXT: [[TMP27:%.*]] = getelementptr double, ptr [[TMP23]], i32 6 -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP23]], align 8 -; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <2 x double>, ptr [[TMP25]], align 8 -; CHECK-NEXT: [[WIDE_LOAD13:%.*]] = load <2 x double>, ptr [[TMP26]], align 8 -; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <2 x double>, ptr [[TMP27]], align 8 +; CHECK-NEXT: [[TMP33:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP21]] +; CHECK-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP20]] +; CHECK-NEXT: [[TMP39:%.*]] = getelementptr double, ptr [[A]], i64 [[TMP22]] +; CHECK-NEXT: [[TMP24:%.*]] = load double, ptr [[TMP23]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x double> poison, double [[TMP24]], i64 0 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT1]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP25:%.*]] = load double, ptr [[TMP33]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT12:%.*]] = insertelement <2 x double> poison, double [[TMP25]], i64 0 +; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT12]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP26:%.*]] = load double, ptr [[TMP37]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT14:%.*]] = insertelement <2 x double> poison, double [[TMP26]], i64 0 +; CHECK-NEXT: [[WIDE_LOAD13:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT14]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP27:%.*]] = load double, ptr [[TMP39]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT16:%.*]] = insertelement <2 x double> poison, double [[TMP27]], i64 0 +; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT16]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP28:%.*]] = fmul <2 x double> [[WIDE_LOAD]], splat (double 5.000000e+00) ; CHECK-NEXT: [[TMP29:%.*]] = fmul <2 x double> [[WIDE_LOAD12]], splat (double 5.000000e+00) ; CHECK-NEXT: [[TMP30:%.*]] = fmul <2 x double> [[WIDE_LOAD13]], splat (double 5.000000e+00) ; CHECK-NEXT: [[TMP31:%.*]] = fmul <2 x double> [[WIDE_LOAD14]], splat (double 5.000000e+00) ; CHECK-NEXT: [[TMP32:%.*]] = getelementptr { double, double }, ptr [[B]], i64 [[INDEX]] -; CHECK-NEXT: [[TMP33:%.*]] = getelementptr { double, double }, ptr [[B]], i64 [[TMP20]] ; CHECK-NEXT: [[TMP34:%.*]] = getelementptr { double, double }, ptr [[B]], i64 [[TMP21]] +; CHECK-NEXT: [[TMP38:%.*]] = getelementptr { double, double }, ptr [[B]], i64 [[TMP20]] ; CHECK-NEXT: [[TMP35:%.*]] = getelementptr { double, double }, ptr [[B]], i64 [[TMP22]] -; CHECK-NEXT: [[TMP36:%.*]] = shufflevector <2 x double> [[TMP28]], <2 x double> [[TMP28]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP36]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP32]], align 8 -; CHECK-NEXT: [[TMP37:%.*]] = shufflevector <2 x double> [[TMP29]], <2 x double> [[TMP29]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC15:%.*]] = shufflevector <4 x double> [[TMP37]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC15]], ptr [[TMP33]], align 8 -; CHECK-NEXT: [[TMP38:%.*]] = shufflevector <2 x double> [[TMP30]], <2 x double> [[TMP30]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC16:%.*]] = shufflevector <4 x double> [[TMP38]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC16]], ptr [[TMP34]], align 8 -; CHECK-NEXT: [[TMP39:%.*]] = shufflevector <2 x double> [[TMP31]], <2 x double> [[TMP31]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC17:%.*]] = shufflevector <4 x double> [[TMP39]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC17]], ptr [[TMP35]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP28]], ptr [[TMP32]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP29]], ptr [[TMP34]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP30]], ptr [[TMP38]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP31]], ptr [[TMP35]], align 8 ; CHECK-NEXT: [[TMP40:%.*]] = getelementptr { double, double }, ptr [[C]], i64 [[INDEX]] -; CHECK-NEXT: [[TMP41:%.*]] = getelementptr { double, double }, ptr [[C]], i64 [[TMP20]] ; CHECK-NEXT: [[TMP42:%.*]] = getelementptr { double, double }, ptr [[C]], i64 [[TMP21]] +; CHECK-NEXT: [[TMP41:%.*]] = getelementptr { double, double }, ptr [[C]], i64 [[TMP20]] ; CHECK-NEXT: [[TMP43:%.*]] = getelementptr { double, double }, ptr [[C]], i64 [[TMP22]] -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP40]], align 8 -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC15]], ptr [[TMP41]], align 8 -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC16]], ptr [[TMP42]], align 8 -; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC17]], ptr [[TMP43]], align 8 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; CHECK-NEXT: store <2 x double> [[TMP28]], ptr [[TMP40]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP29]], ptr [[TMP42]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP30]], ptr [[TMP41]], align 8 +; CHECK-NEXT: store <2 x double> [[TMP31]], ptr [[TMP43]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP44]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: @@ -435,7 +435,7 @@ exit: ret void } -; FIXME: We should interleave by 2 after narrowing interleave groups to saturate +; We should interleave by 2 after narrowing interleave groups to saturate ; load/store units. define void @test_interleave_after_narrowing(i32 %n, ptr %x, ptr noalias %y) { ; CHECK-LABEL: define void @test_interleave_after_narrowing( @@ -447,12 +447,18 @@ define void @test_interleave_after_narrowing(i32 %n, ptr %x, ptr noalias %y) { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 4 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[X]], i64 [[OFFSET_IDX]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw float, ptr [[X]], i64 [[TMP5]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4 +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP7]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = fneg <4 x float> [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP4:%.*]] = fneg <4 x float> [[WIDE_LOAD1]] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[Y]], i64 [[OFFSET_IDX]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw float, ptr [[Y]], i64 [[TMP5]] ; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[TMP2]], align 4 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1 +; CHECK-NEXT: store <4 x float> [[TMP4]], ptr [[TMP6]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 ; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll index c261760..2865495 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll @@ -13,12 +13,8 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) { ; VF2: [[VECTOR_PH]]: ; VF2-NEXT: br label %[[VECTOR_BODY:.*]] ; VF2: [[VECTOR_BODY]]: -; VF2-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[DATA]], align 8 -; VF2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> -; VF2-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> -; VF2-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[STRIDED_VEC]], <2 x i64> [[STRIDED_VEC1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[DATA]], align 8 +; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[DATA]], align 8 +; VF2-NEXT: store <2 x i64> [[WIDE_LOAD]], ptr [[DATA]], align 8 ; VF2-NEXT: br label %[[MIDDLE_BLOCK:.*]] ; VF2: [[MIDDLE_BLOCK]]: ; VF2-NEXT: br label %[[EXIT:.*]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll index 6c36dfb..829acbbf 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll @@ -1,29 +1,81 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph:" --version 5 -; RUN: opt -p loop-vectorize -force-vector-interleave=1 -S -mcpu=neoverse-512tvb %s | FileCheck --check-prefixes=CHECK %s +; RUN: opt -p loop-vectorize -force-vector-interleave=1 -S -mcpu=neoverse-512tvb %s | FileCheck --check-prefixes=IC1 %s +; RUN: opt -p loop-vectorize -S -mcpu=neoverse-512tvb %s | FileCheck --check-prefixes=CHECK %s target triple = "aarch64-unknown-linux" define void @load_store_interleave_group(ptr noalias %data) { +; IC1-LABEL: define void @load_store_interleave_group( +; IC1-SAME: ptr noalias [[DATA:%.*]]) #[[ATTR0:[0-9]+]] { +; IC1-NEXT: [[ENTRY:.*:]] +; IC1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; IC1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1 +; IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 100, [[TMP1]] +; IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; IC1: [[VECTOR_PH]]: +; IC1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; IC1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2 +; IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 100, [[TMP3]] +; IC1-NEXT: [[N_VEC:%.*]] = sub i64 100, [[N_MOD_VF]] +; IC1-NEXT: br label %[[VECTOR_BODY:.*]] +; IC1: [[VECTOR_BODY]]: +; IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IC1-NEXT: [[TMP4:%.*]] = shl nsw i64 [[INDEX]], 1 +; IC1-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP4]] +; IC1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP5]], align 8 +; IC1-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD]], ptr [[TMP5]], align 8 +; IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]] +; IC1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; IC1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; IC1: [[MIDDLE_BLOCK]]: +; IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 100, [[N_VEC]] +; IC1-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] +; IC1: [[SCALAR_PH]]: +; ; CHECK-LABEL: define void @load_store_interleave_group( ; CHECK-SAME: ptr noalias [[DATA:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP4]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP4]], 3 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 100, [[TMP5]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2 +; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 100, [[TMP3]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 100, [[N_MOD_VF]] +; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP2]], 4 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP2]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP20]], 1 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], [[TMP6]] +; CHECK-NEXT: [[TMP24:%.*]] = mul i64 [[TMP2]], 2 +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP24]], 0 +; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 1 +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP2]], 3 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 0 +; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 1 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], [[TMP14]] ; CHECK-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP17:%.*]] = shl nsw i64 [[TMP7]], 1 +; CHECK-NEXT: [[TMP18:%.*]] = shl nsw i64 [[TMP11]], 1 +; CHECK-NEXT: [[TMP19:%.*]] = shl nsw i64 [[TMP15]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP17]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP19]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP1]], align 8 +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x i64>, ptr [[TMP21]], align 8 +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x i64>, ptr [[TMP22]], align 8 +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 2 x i64>, ptr [[TMP23]], align 8 ; CHECK-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD]], ptr [[TMP1]], align 8 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]] +; CHECK-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD1]], ptr [[TMP21]], align 8 +; CHECK-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD2]], ptr [[TMP22]], align 8 +; CHECK-NEXT: store <vscale x 2 x i64> [[WIDE_LOAD3]], ptr [[TMP23]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP16]] ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: @@ -53,27 +105,82 @@ exit: } define void @test_2xi64_unary_op_load_interleave_group(ptr noalias %data, ptr noalias %factor) { +; IC1-LABEL: define void @test_2xi64_unary_op_load_interleave_group( +; IC1-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[FACTOR:%.*]]) #[[ATTR0]] { +; IC1-NEXT: [[ENTRY:.*:]] +; IC1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; IC1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1 +; IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1111, [[TMP1]] +; IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; IC1: [[VECTOR_PH]]: +; IC1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; IC1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2 +; IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1111, [[TMP3]] +; IC1-NEXT: [[N_VEC:%.*]] = sub i64 1111, [[N_MOD_VF]] +; IC1-NEXT: br label %[[VECTOR_BODY:.*]] +; IC1: [[VECTOR_BODY]]: +; IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IC1-NEXT: [[TMP4:%.*]] = shl nsw i64 [[INDEX]], 1 +; IC1-NEXT: [[TMP5:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP4]] +; IC1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 8 +; IC1-NEXT: [[TMP6:%.*]] = fneg <vscale x 2 x double> [[WIDE_LOAD]] +; IC1-NEXT: store <vscale x 2 x double> [[TMP6]], ptr [[TMP5]], align 8 +; IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]] +; IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; IC1: [[MIDDLE_BLOCK]]: +; IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1111, [[N_VEC]] +; IC1-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] +; IC1: [[SCALAR_PH]]: +; ; CHECK-LABEL: define void @test_2xi64_unary_op_load_interleave_group( ; CHECK-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[FACTOR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP4]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP4]], 3 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1111, [[TMP5]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2 +; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 1111, [[TMP3]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 1111, [[N_MOD_VF]] +; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP2]], 4 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP2]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP20]], 1 +; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[INDEX]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[TMP2]], 2 +; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP8]], 0 +; CHECK-NEXT: [[TMP29:%.*]] = mul i64 [[TMP28]], 1 +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], [[TMP29]] +; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP2]], 3 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 0 +; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 1 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], [[TMP14]] ; CHECK-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP17:%.*]] = shl nsw i64 [[TMP24]], 1 +; CHECK-NEXT: [[TMP18:%.*]] = shl nsw i64 [[TMP11]], 1 +; CHECK-NEXT: [[TMP19:%.*]] = shl nsw i64 [[TMP15]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP17]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP19]] ; CHECK-NEXT: [[TMP7:%.*]] = load <vscale x 2 x double>, ptr [[TMP1]], align 8 +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP21]], align 8 +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x double>, ptr [[TMP22]], align 8 +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 2 x double>, ptr [[TMP23]], align 8 ; CHECK-NEXT: [[TMP9:%.*]] = fneg <vscale x 2 x double> [[TMP7]] +; CHECK-NEXT: [[TMP25:%.*]] = fneg <vscale x 2 x double> [[WIDE_LOAD1]] +; CHECK-NEXT: [[TMP26:%.*]] = fneg <vscale x 2 x double> [[WIDE_LOAD2]] +; CHECK-NEXT: [[TMP27:%.*]] = fneg <vscale x 2 x double> [[WIDE_LOAD3]] ; CHECK-NEXT: store <vscale x 2 x double> [[TMP9]], ptr [[TMP1]], align 8 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]] +; CHECK-NEXT: store <vscale x 2 x double> [[TMP25]], ptr [[TMP21]], align 8 +; CHECK-NEXT: store <vscale x 2 x double> [[TMP26]], ptr [[TMP22]], align 8 +; CHECK-NEXT: store <vscale x 2 x double> [[TMP27]], ptr [[TMP23]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP16]] ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll index d290f2d..abfb44d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll @@ -60,32 +60,26 @@ define void @test_2xi64_with_wide_load(ptr noalias %data, ptr noalias %factor) { ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[INDEX]] -; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2 -; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = load <2 x i64>, ptr [[TMP1]], align 8 -; CHECK-NEXT: [[BROADCAST_SPLAT3:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP4]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <2 x i64> poison, i64 [[TMP3]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT2]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = shl nsw i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP7:%.*]] = shl nsw i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP7]] -; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP8]], align 8 -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> -; CHECK-NEXT: [[WIDE_VEC3:%.*]] = load <4 x i64>, ptr [[TMP9]], align 8 -; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC3]], <4 x i64> poison, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <4 x i64> [[WIDE_VEC3]], <4 x i64> poison, <2 x i32> <i32 1, i32 3> -; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT]], [[WIDE_LOAD]] -; CHECK-NEXT: [[TMP11:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT3]], [[WIDE_LOAD1]] +; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = load <2 x i64>, ptr [[TMP8]], align 8 +; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = load <2 x i64>, ptr [[TMP9]], align 8 ; CHECK-NEXT: [[TMP15:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT]], [[STRIDED_VEC2]] ; CHECK-NEXT: [[TMP16:%.*]] = mul <2 x i64> [[BROADCAST_SPLAT3]], [[STRIDED_VEC5]] -; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> [[TMP15]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP17]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP8]], align 8 -; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i64> [[TMP11]], <2 x i64> [[TMP16]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; CHECK-NEXT: [[INTERLEAVED_VEC6:%.*]] = shufflevector <4 x i64> [[TMP18]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC6]], ptr [[TMP9]], align 8 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: store <2 x i64> [[TMP15]], ptr [[TMP8]], align 8 +; CHECK-NEXT: store <2 x i64> [[TMP16]], ptr [[TMP9]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 ; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory.ll index 75980ba..f2e689c 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory.ll @@ -328,10 +328,8 @@ define void @same_live_in_store_interleave_group(i64 %x, ptr noalias %dst) { ; VF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; VF2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 ; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]] -; VF2-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLAT]], <2 x i64> [[BROADCAST_SPLAT]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> -; VF2-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> -; VF2-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8 -; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; VF2-NEXT: store <2 x i64> [[BROADCAST_SPLAT]], ptr [[TMP1]], align 8 +; VF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1 ; VF2-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 ; VF2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; VF2: [[MIDDLE_BLOCK]]: diff --git a/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll b/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll index 44a48a9..0f398a6 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll @@ -84,15 +84,14 @@ for.end: ; preds = %for.end.loopexit, % ; CHECK: We can vectorize this loop! define i32 @redi(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %N) { entry: - %cmp5 = icmp eq i32 %N, 0 - br i1 %cmp5, label %for.end, label %for.body.preheader + br label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body for.body: ; preds = %for.body.preheader, %for.body %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] - %Red.06 = phi i32 [ %add, %for.body ], [ undef, %for.body.preheader ] + %Red.06 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] %arrayidx = getelementptr inbounds i32, ptr %a, i32 %i.07 %0 = load i32, ptr %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32, ptr %b, i32 %i.07 @@ -107,9 +106,8 @@ for.end.loopexit: ; preds = %for.body %add.lcssa = phi i32 [ %add, %for.body ] br label %for.end -for.end: ; preds = %for.end.loopexit, %entry - %Red.0.lcssa = phi i32 [ undef, %entry ], [ %add.lcssa, %for.end.loopexit ] - ret i32 %Red.0.lcssa +for.end: ; preds = %for.end.loopexit + ret i32 %add.lcssa } ; Floating-point loops need fast-math to be vectorizeable @@ -121,15 +119,14 @@ for.end: ; preds = %for.end.loopexit, % ; DARWIN: We can vectorize this loop! define float @redf(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %N) { entry: - %cmp5 = icmp eq i32 %N, 0 - br i1 %cmp5, label %for.end, label %for.body.preheader + br label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body for.body: ; preds = %for.body.preheader, %for.body %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] - %Red.06 = phi float [ %add, %for.body ], [ undef, %for.body.preheader ] + %Red.06 = phi float [ %add, %for.body ], [ 0.0e+00, %for.body.preheader ] %arrayidx = getelementptr inbounds float, ptr %a, i32 %i.07 %0 = load float, ptr %arrayidx, align 4 %arrayidx1 = getelementptr inbounds float, ptr %b, i32 %i.07 @@ -144,9 +141,8 @@ for.end.loopexit: ; preds = %for.body %add.lcssa = phi float [ %add, %for.body ] br label %for.end -for.end: ; preds = %for.end.loopexit, %entry - %Red.0.lcssa = phi float [ undef, %entry ], [ %add.lcssa, %for.end.loopexit ] - ret float %Red.0.lcssa +for.end: ; preds = %for.end.loopexit + ret float %add.lcssa } ; Make sure calls that turn into builtins are also covered @@ -252,7 +248,7 @@ for.body.preheader: ; preds = %entry for.body: ; preds = %for.body.preheader, %for.body %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] - %Red.06 = phi i32 [ %add, %for.body ], [ undef, %for.body.preheader ] + %Red.06 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] %arrayidx = getelementptr inbounds i32, ptr %a, i32 %i.07 %0 = load i32, ptr %arrayidx, align 4 %arrayidx1 = getelementptr inbounds i32, ptr %b, i32 %i.07 @@ -268,7 +264,7 @@ for.end.loopexit: ; preds = %for.body br label %for.end for.end: ; preds = %for.end.loopexit, %entry - %Red.0.lcssa = phi i32 [ undef, %entry ], [ %add.lcssa, %for.end.loopexit ] + %Red.0.lcssa = phi i32 [ 0, %entry ], [ %add.lcssa, %for.end.loopexit ] ret i32 %Red.0.lcssa } @@ -277,15 +273,14 @@ for.end: ; preds = %for.end.loopexit, % ; CHECK: We can vectorize this loop! define float @redf_fast(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %N) { entry: - %cmp5 = icmp eq i32 %N, 0 - br i1 %cmp5, label %for.end, label %for.body.preheader + br label %for.body.preheader for.body.preheader: ; preds = %entry br label %for.body for.body: ; preds = %for.body.preheader, %for.body %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] - %Red.06 = phi float [ %add, %for.body ], [ undef, %for.body.preheader ] + %Red.06 = phi float [ %add, %for.body ], [ 0.0e+00, %for.body.preheader ] %arrayidx = getelementptr inbounds float, ptr %a, i32 %i.07 %0 = load float, ptr %arrayidx, align 4 %arrayidx1 = getelementptr inbounds float, ptr %b, i32 %i.07 @@ -300,9 +295,8 @@ for.end.loopexit: ; preds = %for.body %add.lcssa = phi float [ %add, %for.body ] br label %for.end -for.end: ; preds = %for.end.loopexit, %entry - %Red.0.lcssa = phi float [ undef, %entry ], [ %add.lcssa, %for.end.loopexit ] - ret float %Red.0.lcssa +for.end: ; preds = %for.end.loopexit + ret float %add.lcssa } ; Make sure calls that turn into builtins are also covered diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll index fe3504b..23609b1 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll @@ -249,7 +249,7 @@ define dso_local i32 @predicated_test(i32 noundef %0, ptr %glob) #0 { br label %7 7: ; preds = %5, %155 - %8 = phi i32 [ %10, %155 ], [ undef, %5 ] + %8 = phi i32 [ %10, %155 ], [ 0, %5 ] %9 = phi i32 [ %156, %155 ], [ 0, %5 ] %10 = shl i32 %8, 4 store i32 %10, ptr %6, align 4 diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll index c5319c6..f4c7c6f 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll @@ -246,6 +246,57 @@ exit: ret void } +; Test for https://github.com/llvm/llvm-project/issues/162688. +define void @test_minbws_for_trunc(i32 %n, ptr noalias %p1, ptr noalias %p2) { +; CHECK-LABEL: define void @test_minbws_for_trunc( +; CHECK-SAME: i32 [[N:%.*]], ptr noalias [[P1:%.*]], ptr noalias [[P2:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i16 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[IV_EXT:%.*]] = sext i16 [[IV]] to i64 +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i32, ptr [[P1]], i64 [[IV_EXT]] +; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[GEP1]], align 4 +; CHECK-NEXT: [[V1_TRUNC:%.*]] = trunc i32 [[V1]] to i16 +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr [1 x [1 x i16]], ptr [[P2]], i64 [[IV_EXT]] +; CHECK-NEXT: store i16 [[V1_TRUNC]], ptr [[GEP2]], align 2 +; CHECK-NEXT: [[V1_TRUNC_I8:%.*]] = trunc i32 [[V1]] to i8 +; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr [[P2]], i64 [[IV_EXT]] +; CHECK-NEXT: store i8 [[V1_TRUNC_I8]], ptr [[GEP3]], align 1 +; CHECK-NEXT: [[GEP4:%.*]] = getelementptr [1 x i64], ptr [[P2]], i64 [[IV_EXT]] +; CHECK-NEXT: store i64 0, ptr [[GEP4]], align 8 +; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 4 +; CHECK-NEXT: [[IV_NEXT_EXT:%.*]] = sext i16 [[IV_NEXT]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[IV_NEXT_EXT]], 1024 +; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i16 [ 0, %entry ], [ %iv.next, %loop ] + %iv.ext = sext i16 %iv to i64 + %gep1 = getelementptr i32, ptr %p1, i64 %iv.ext + %v1 = load i32, ptr %gep1, align 4 + %v1.trunc = trunc i32 %v1 to i16 + %gep2 = getelementptr [1 x [1 x i16]], ptr %p2, i64 %iv.ext + store i16 %v1.trunc, ptr %gep2, align 2 + %v1.trunc.i8 = trunc i32 %v1 to i8 + %gep3 = getelementptr i8, ptr %p2, i64 %iv.ext + store i8 %v1.trunc.i8, ptr %gep3, align 1 + %gep4 = getelementptr [1 x i64], ptr %p2, i64 %iv.ext + store i64 0, ptr %gep4, align 8 + %iv.next = add i16 %iv, 4 + %iv.next.ext = sext i16 %iv.next to i32 + %cmp = icmp ne i32 %iv.next.ext, 1024 + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + attributes #0 = { "target-features"="+64bit,+v,+zvl256b" } attributes #1 = { "target-features"="+64bit,+v" } diff --git a/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll b/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll index 2ef9d4b..3718ad2 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll @@ -14,7 +14,7 @@ define x86_fp80 @test() { ; CHECK-NEXT: br label [[FOR_BODY3_I_3:%.*]] ; CHECK: for.body3.i.3: ; CHECK-NEXT: [[N_ADDR_112_I_3:%.*]] = phi i64 [ [[DEC_I_3:%.*]], [[FOR_BODY3_I_3]] ], [ 24, [[FOO_EXIT:%.*]] ] -; CHECK-NEXT: [[X_ADDR_111_I_3:%.*]] = phi x86_fp80 [ [[MUL_I_3:%.*]], [[FOR_BODY3_I_3]] ], [ undef, [[FOO_EXIT]] ] +; CHECK-NEXT: [[X_ADDR_111_I_3:%.*]] = phi x86_fp80 [ [[MUL_I_3:%.*]], [[FOR_BODY3_I_3]] ], [ 0xK00000000000000000000, [[FOO_EXIT]] ] ; CHECK-NEXT: [[MUL_I_3]] = fmul x86_fp80 [[X_ADDR_111_I_3]], 0xK40008000000000000000 ; CHECK-NEXT: [[DEC_I_3]] = add nsw i64 [[N_ADDR_112_I_3]], -1 ; CHECK-NEXT: [[CMP2_I_3:%.*]] = icmp sgt i64 [[N_ADDR_112_I_3]], 1 @@ -28,7 +28,7 @@ foo.exit: for.body3.i.3: ; preds = %for.body3.i.3, %foo.exit %n.addr.112.i.3 = phi i64 [ %dec.i.3, %for.body3.i.3 ], [ 24, %foo.exit ] - %x.addr.111.i.3 = phi x86_fp80 [ %mul.i.3, %for.body3.i.3 ], [ undef, %foo.exit ] + %x.addr.111.i.3 = phi x86_fp80 [ %mul.i.3, %for.body3.i.3 ], [ zeroinitializer, %foo.exit ] %mul.i.3 = fmul x86_fp80 %x.addr.111.i.3, 0xK40008000000000000000 %dec.i.3 = add nsw i64 %n.addr.112.i.3, -1 %cmp2.i.3 = icmp sgt i64 %n.addr.112.i.3, 1 diff --git a/llvm/test/Transforms/LoopVectorize/X86/rauw-bug.ll b/llvm/test/Transforms/LoopVectorize/X86/rauw-bug.ll index df1c4f9..5321d69 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/rauw-bug.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/rauw-bug.ll @@ -21,10 +21,10 @@ while.cond63.preheader.while.end76_crit_edge: ret void while.body: - %d2_fx.015 = phi double [ %sub52, %while.body ], [ undef, %entry ] - %d2_fy.014 = phi double [ %sub58, %while.body ], [ undef, %entry ] - %d3_fy.013 = phi double [ %div56, %while.body ], [ undef, %entry ] - %d3_fx.012 = phi double [ %div50, %while.body ], [ undef, %entry ] + %d2_fx.015 = phi double [ %sub52, %while.body ], [ 0.0e+00, %entry ] + %d2_fy.014 = phi double [ %sub58, %while.body ], [ 0.0e+00, %entry ] + %d3_fy.013 = phi double [ %div56, %while.body ], [ 0.0e+00, %entry ] + %d3_fx.012 = phi double [ %div50, %while.body ], [ 0.0e+00, %entry ] %div50 = fmul double %d3_fx.012, 1.250000e-01 %sub52 = fsub double 0.000000e+00, %div50 %div56 = fmul double %d3_fy.013, 1.250000e-01 diff --git a/llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll b/llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll index 2a3ce03..f4d80af 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll @@ -8,15 +8,69 @@ target triple = "x86_64-unknown-linux" define void @test_4xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) { ; CHECK-LABEL: define void @test_4xi64( ; CHECK-SAME: ptr noalias [[DATA:%.*]], ptr noalias [[FACTOR:%.*]], i64 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: [[ITER_CHECK:.*]]: ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] +; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: +; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 16 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: -; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 -; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECK-NEXT: [[N_MOD_VF1:%.*]] = urem i64 [[N]], 16 +; CHECK-NEXT: [[N_VEC1:%.*]] = sub i64 [[N]], [[N_MOD_VF1]] ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: -; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 3 +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[INDEX]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP20]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[TMP7]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT1:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP21]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i64> poison, i64 [[TMP8]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT5]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP22]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <4 x i64> poison, i64 [[TMP9]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT7]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <4 x i64> poison, i64 [[TMP10]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT10:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT9]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds { i64, i64, i64, i64 }, ptr [[DATA]], i64 [[INDEX]], i32 0 +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds { i64, i64, i64, i64 }, ptr [[DATA]], i64 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds { i64, i64, i64, i64 }, ptr [[DATA]], i64 [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds { i64, i64, i64, i64 }, ptr [[DATA]], i64 [[TMP2]], i32 0 +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP11]], align 8 +; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i64>, ptr [[TMP12]], align 8 +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i64>, ptr [[TMP13]], align 8 +; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP23]], align 8 +; CHECK-NEXT: [[TMP15:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT1]], [[WIDE_LOAD1]] +; CHECK-NEXT: [[TMP16:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT6]], [[WIDE_LOAD2]] +; CHECK-NEXT: [[TMP17:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT8]], [[WIDE_LOAD3]] +; CHECK-NEXT: [[TMP18:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT10]], [[WIDE_LOAD4]] +; CHECK-NEXT: store <4 x i64> [[TMP15]], ptr [[TMP11]], align 8 +; CHECK-NEXT: store <4 x i64> [[TMP16]], ptr [[TMP12]], align 8 +; CHECK-NEXT: store <4 x i64> [[TMP17]], ptr [[TMP13]], align 8 +; CHECK-NEXT: store <4 x i64> [[TMP18]], ptr [[TMP23]], align 8 +; CHECK-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC1]] +; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N1:%.*]] = icmp eq i64 [[N]], [[N_VEC1]] +; CHECK-NEXT: br i1 [[CMP_N1]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] +; CHECK: [[VEC_EPILOG_ITER_CHECK]]: +; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF1]], 4 +; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]] +; CHECK: [[VEC_EPILOG_PH]]: +; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] +; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[IV]] ; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP5]], i64 0 @@ -27,15 +81,15 @@ define void @test_4xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP3]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 1 ; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] -; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br i1 [[TMP14]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] -; CHECK: [[SCALAR_PH]]: -; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] +; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] +; CHECK: [[VEC_EPILOG_SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] ; CHECK-NEXT: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] ; CHECK-NEXT: [[DATA_2:%.*]] = getelementptr inbounds i64, ptr [[FACTOR]], i64 [[IV1]] ; CHECK-NEXT: [[L_2:%.*]] = load i64, ptr [[DATA_2]], align 8 ; CHECK-NEXT: [[DATA_0:%.*]] = getelementptr inbounds { i64, i64, i64, i64 }, ptr [[DATA]], i64 [[IV1]], i32 0 @@ -56,7 +110,7 @@ define void @test_4xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store i64 [[MUL_3]], ptr [[DATA_3]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -117,7 +171,7 @@ define void @test_2xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] @@ -140,7 +194,7 @@ define void @test_2xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store i64 [[MUL_1]], ptr [[DATA_1]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -195,7 +249,7 @@ define void @test_2xi64_interleave_loads_order_flipped(ptr noalias %data, ptr no ; CHECK-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] @@ -218,7 +272,7 @@ define void @test_2xi64_interleave_loads_order_flipped(ptr noalias %data, ptr no ; CHECK-NEXT: store i64 [[MUL_1]], ptr [[DATA_1]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -273,7 +327,7 @@ define void @test_2xi64_store_order_flipped_1(ptr noalias %data, ptr noalias %fa ; CHECK-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] @@ -296,7 +350,7 @@ define void @test_2xi64_store_order_flipped_1(ptr noalias %data, ptr noalias %fa ; CHECK-NEXT: store i64 [[MUL_0]], ptr [[DATA_1]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -351,7 +405,7 @@ define void @test_2xi64_store_order_flipped_2(ptr noalias %data, ptr noalias %fa ; CHECK-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP4]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] @@ -374,7 +428,7 @@ define void @test_2xi64_store_order_flipped_2(ptr noalias %data, ptr noalias %fa ; CHECK-NEXT: store i64 [[MUL_1]], ptr [[DATA_0]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -435,7 +489,7 @@ define void @test_2xi64_different_loads_feeding_fmul(ptr noalias %data, ptr noal ; CHECK-NEXT: store <8 x i64> [[INTERLEAVED_VEC]], ptr [[TMP16]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: br label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: @@ -459,7 +513,7 @@ define void @test_2xi64_different_loads_feeding_fmul(ptr noalias %data, ptr noal ; CHECK-NEXT: store i64 [[MUL_1]], ptr [[DATA_1]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -519,7 +573,7 @@ define void @test_3xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store <12 x i64> [[INTERLEAVED_VEC]], ptr [[TMP3]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 ; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] @@ -544,7 +598,7 @@ define void @test_3xi64(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store i64 [[MUL_2]], ptr [[DATA_2]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP16:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -653,7 +707,7 @@ define void @test_3xi32(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store <24 x i32> [[INTERLEAVED_VEC]], ptr [[TMP5]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8 ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: br label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: @@ -677,7 +731,7 @@ define void @test_3xi32(ptr noalias %data, ptr noalias %factor, i64 noundef %n) ; CHECK-NEXT: store i32 [[MUL_2]], ptr [[DATA_2]], align 8 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -711,19 +765,20 @@ exit: ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} -; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} -; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} -; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} -; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} -; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} -; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} -; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]} -; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} -; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]} -; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]} -; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]} -; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]} -; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META2]], [[META1]]} -; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} -; CHECK: [[LOOP17]] = distinct !{[[LOOP17]], [[META2]], [[META1]]} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]} +; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META2]], [[META1]]} +; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]} +; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META2]], [[META1]]} +; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]} +; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META2]], [[META1]]} +; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} +; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META2]], [[META1]]} +; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]} +; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META2]], [[META1]]} +; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]], [[META2]]} +; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META2]], [[META1]]} +; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]], [[META2]]} +; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META2]], [[META1]]} +; CHECK: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]], [[META2]]} +; CHECK: [[LOOP18]] = distinct !{[[LOOP18]], [[META2]], [[META1]]} ;. diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-interleaved-access.ll b/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-interleaved-access.ll index 368361f..0f55d79 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-interleaved-access.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-interleaved-access.ll @@ -15,7 +15,7 @@ for.cond.cleanup: for.body: %i.09 = phi i16 [ 0, %entry ], [ %add3, %for.body ] - %res.08 = phi x86_fp80 [ undef, %entry ], [ %3, %for.body ] + %res.08 = phi x86_fp80 [ zeroinitializer, %entry ], [ %3, %for.body ] %arrayidx = getelementptr inbounds x86_fp80, ptr %a, i16 %i.09 %0 = load x86_fp80, ptr %arrayidx, align 1 %add = or i16 %i.09, 1 diff --git a/llvm/test/Transforms/LoopVectorize/i8-induction.ll b/llvm/test/Transforms/LoopVectorize/i8-induction.ll index 220fd64..712c75d 100644 --- a/llvm/test/Transforms/LoopVectorize/i8-induction.ll +++ b/llvm/test/Transforms/LoopVectorize/i8-induction.ll @@ -20,7 +20,7 @@ scalar.ph: for.body: %mul16 = phi i8 [ 0, %scalar.ph ], [ %mul, %for.body ] ; <------- i8 induction var. - %c.015 = phi i8 [ undef, %scalar.ph ], [ %conv8, %for.body ] + %c.015 = phi i8 [ 0, %scalar.ph ], [ %conv8, %for.body ] %conv2 = sext i8 %c.015 to i32 %tobool = icmp ne i8 %c.015, 0 %.sink = select i1 %tobool, i8 %c.015, i8 %0 diff --git a/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll b/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll index f7376a0..c164c4a 100644 --- a/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll +++ b/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll @@ -277,7 +277,7 @@ define void @bug18724(i1 %cond, ptr %ptr, i1 %cond.2, i64 %v.1, i32 %v.2) { ; UNROLL-NOSIMPLIFY-NEXT: [[INEWCHUNKS_2_LCSSA:%.*]] = phi i32 [ [[INEWCHUNKS_2]], [[FOR_INC23]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ] ; UNROLL-NOSIMPLIFY-NEXT: br label [[FOR_INC26]] ; UNROLL-NOSIMPLIFY: for.inc26: -; UNROLL-NOSIMPLIFY-NEXT: [[INEWCHUNKS_1_LCSSA:%.*]] = phi i32 [ undef, [[FOR_BODY9]] ], [ [[INEWCHUNKS_2_LCSSA]], [[FOR_INC26_LOOPEXIT]] ] +; UNROLL-NOSIMPLIFY-NEXT: [[INEWCHUNKS_1_LCSSA:%.*]] = phi i32 [ 0, [[FOR_BODY9]] ], [ [[INEWCHUNKS_2_LCSSA]], [[FOR_INC26_LOOPEXIT]] ] ; UNROLL-NOSIMPLIFY-NEXT: unreachable ; ; VEC-LABEL: @bug18724( @@ -376,7 +376,7 @@ for.inc23: br i1 %cmp13, label %for.body14, label %for.inc26 for.inc26: - %iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ] + %iNewChunks.1.lcssa = phi i32 [ 0, %for.body9 ], [ %iNewChunks.2, %for.inc23 ] unreachable } diff --git a/llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll b/llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll index 9e75002..5cf99b8 100644 --- a/llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll +++ b/llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll @@ -53,8 +53,8 @@ thread-pre-split.loopexit: ; preds = %11, %.thread-pre-sp br i1 false, label %thread-pre-split._crit_edge, label %.lr.ph21 .lr.ph21: ; preds = %26, %thread-pre-split.loopexit, %thread-pre-split.preheader - %d.020 = phi ptr [ undef, %26 ], [ %d.1.lcssa, %thread-pre-split.loopexit ], [ undef, %thread-pre-split.preheader ] - %10 = phi i64 [ %28, %26 ], [ undef, %thread-pre-split.loopexit ], [ undef, %thread-pre-split.preheader ] + %d.020 = phi ptr [ zeroinitializer, %26 ], [ %d.1.lcssa, %thread-pre-split.loopexit ], [ zeroinitializer, %thread-pre-split.preheader ] + %10 = phi i64 [ %28, %26 ], [ zeroinitializer, %thread-pre-split.loopexit ], [ zeroinitializer, %thread-pre-split.preheader ] br i1 %arg, label %11, label %22 ; <label>:11 ; preds = %.lr.ph21 diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll index 16357b3..8efe29a 100644 --- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll @@ -791,8 +791,8 @@ define void @int_float_struct(ptr nocapture readonly %A) #0 { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ <i32 undef, i32 0, i32 0, i32 0>, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_INTFLOAT:%.*]], ptr [[A:%.*]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, ptr [[TMP0]], align 4 ; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -822,8 +822,8 @@ for.cond.cleanup: ; preds = %for.body for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] - %SumB.014 = phi float [ undef, %entry ], [ %add3, %for.body ] - %SumA.013 = phi i32 [ undef, %entry ], [ %add, %for.body ] + %SumB.014 = phi float [ 0.0e+00, %entry ], [ %add3, %for.body ] + %SumA.013 = phi i32 [ 0, %entry ], [ %add, %for.body ] %a = getelementptr inbounds %struct.IntFloat, ptr %A, i64 %indvars.iv, i32 0 %tmp = load i32, ptr %a, align 4 %add = add nsw i32 %tmp, %SumA.013 diff --git a/llvm/test/Transforms/LoopVectorize/middle-block-dbg.ll b/llvm/test/Transforms/LoopVectorize/middle-block-dbg.ll index 741ca55..1675a59 100644 --- a/llvm/test/Transforms/LoopVectorize/middle-block-dbg.ll +++ b/llvm/test/Transforms/LoopVectorize/middle-block-dbg.ll @@ -48,7 +48,7 @@ for.cond.cleanup.loopexit: br label %for.cond.cleanup, !dbg !33 for.cond.cleanup: - %2 = phi i32 [ %.pre, %for.cond.cleanup.loopexit ], [ undef, %entry ], !dbg !33 + %2 = phi i32 [ %.pre, %for.cond.cleanup.loopexit ], [ 0, %entry ], !dbg !33 %sub = add nsw i32 %0, -5, !dbg !33 %idxprom3 = sext i32 %sub to i64, !dbg !33 %arrayidx4 = getelementptr inbounds i32, ptr %vla, i64 %idxprom3, !dbg !33 diff --git a/llvm/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll b/llvm/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll index 659dc62..2038633 100644 --- a/llvm/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll +++ b/llvm/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll @@ -22,8 +22,8 @@ entry: br label %for.body for.body: - %inc107 = phi i32 [ undef, %entry ], [ %inc10, %for.body ] - %inc6 = phi i32 [ %nf.promoted, %entry ], [ undef, %for.body ] + %inc107 = phi i32 [ 0, %entry ], [ %inc10, %for.body ] + %inc6 = phi i32 [ %nf.promoted, %entry ], [ 3, %for.body ] %add55 = phi i32 [ %n.promoted, %entry ], [ %add5, %for.body ] %.neg2 = sub i32 0, %inc6 %add.neg = add i32 0, %add55 diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll index ec7fde8..964a257 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll @@ -1207,11 +1207,11 @@ for.end: define i32 @reduction_sum_multiuse(ptr noalias nocapture %A, ptr noalias nocapture %B) { ; CHECK-LABEL: define i32 @reduction_sum_multiuse( ; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) { -; CHECK-NEXT: [[_LR_PH1:.*]]: +; CHECK-NEXT: [[_LR_PH:.*]]: ; CHECK-NEXT: br label %[[DOTLR_PH:.*]] -; CHECK: [[_LR_PH:.*:]] -; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ] -; CHECK-NEXT: [[SUM_02:%.*]] = phi i32 [ [[L10:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ] +; CHECK: [[_LR_PH1:.*:]] +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH]] ] +; CHECK-NEXT: [[SUM_02:%.*]] = phi i32 [ [[L10:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH]] ] ; CHECK-NEXT: [[L2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[L3:%.*]] = load i32, ptr [[L2]], align 4 ; CHECK-NEXT: [[L4:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]] @@ -1231,11 +1231,11 @@ define i32 @reduction_sum_multiuse(ptr noalias nocapture %A, ptr noalias nocaptu ; ; CHECK-INTERLEAVED-LABEL: define i32 @reduction_sum_multiuse( ; CHECK-INTERLEAVED-SAME: ptr noalias captures(none) [[A:%.*]], ptr noalias captures(none) [[B:%.*]]) { -; CHECK-INTERLEAVED-NEXT: [[_LR_PH1:.*]]: +; CHECK-INTERLEAVED-NEXT: [[_LR_PH:.*]]: ; CHECK-INTERLEAVED-NEXT: br label %[[DOTLR_PH:.*]] -; CHECK-INTERLEAVED: [[_LR_PH:.*:]] -; CHECK-INTERLEAVED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ] -; CHECK-INTERLEAVED-NEXT: [[SUM_02:%.*]] = phi i32 [ [[L10:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH1]] ] +; CHECK-INTERLEAVED: [[_LR_PH1:.*:]] +; CHECK-INTERLEAVED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH]] ] +; CHECK-INTERLEAVED-NEXT: [[SUM_02:%.*]] = phi i32 [ [[L10:%.*]], %[[DOTLR_PH]] ], [ 0, %[[_LR_PH]] ] ; CHECK-INTERLEAVED-NEXT: [[L2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]] ; CHECK-INTERLEAVED-NEXT: [[L3:%.*]] = load i32, ptr [[L2]], align 4 ; CHECK-INTERLEAVED-NEXT: [[L4:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]] @@ -1947,7 +1947,7 @@ define i32 @predicated_not_dominates_reduction(ptr nocapture noundef readonly %h ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], zeroinitializer @@ -1966,7 +1966,7 @@ define i32 @predicated_not_dominates_reduction(ptr nocapture noundef readonly %h ; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ undef, %[[ENTRY]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-NEXT: br label %[[FOR_BODY2:.*]] ; CHECK: [[FOR_BODY2]]: ; CHECK-NEXT: [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] @@ -2002,7 +2002,7 @@ define i32 @predicated_not_dominates_reduction(ptr nocapture noundef readonly %h ; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK-INTERLEAVED: [[VECTOR_BODY]]: ; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] ; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] ; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]] ; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 4 @@ -2033,7 +2033,7 @@ define i32 @predicated_not_dominates_reduction(ptr nocapture noundef readonly %h ; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]] ; CHECK-INTERLEAVED: [[SCALAR_PH]]: ; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] -; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ undef, %[[ENTRY]] ] +; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY2:.*]] ; CHECK-INTERLEAVED: [[FOR_BODY2]]: ; CHECK-INTERLEAVED-NEXT: [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] @@ -2063,7 +2063,7 @@ entry: for.body2: ; preds = %entry, %for.inc5 %a.117 = phi i32 [ %inc6, %for.inc5 ], [ 0, %entry ] - %g.016 = phi i32 [ %g.1, %for.inc5 ], [ undef, %entry ] + %g.016 = phi i32 [ %g.1, %for.inc5 ], [ 0, %entry ] %arrayidx = getelementptr inbounds i8, ptr %h, i32 %a.117 %0 = load i8, ptr %arrayidx, align 1 %tobool3.not = icmp eq i8 %0, 0 @@ -2100,7 +2100,7 @@ define i32 @predicated_not_dominates_reduction_twoadd(ptr nocapture noundef read ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], zeroinitializer @@ -2122,7 +2122,7 @@ define i32 @predicated_not_dominates_reduction_twoadd(ptr nocapture noundef read ; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ undef, %[[ENTRY]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-NEXT: br label %[[FOR_BODY2:.*]] ; CHECK: [[FOR_BODY2]]: ; CHECK-NEXT: [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] @@ -2159,7 +2159,7 @@ define i32 @predicated_not_dominates_reduction_twoadd(ptr nocapture noundef read ; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK-INTERLEAVED: [[VECTOR_BODY]]: ; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] ; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] ; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[H]], i32 [[INDEX]] ; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 4 @@ -2196,7 +2196,7 @@ define i32 @predicated_not_dominates_reduction_twoadd(ptr nocapture noundef read ; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_END7:.*]], label %[[SCALAR_PH]] ; CHECK-INTERLEAVED: [[SCALAR_PH]]: ; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] -; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ undef, %[[ENTRY]] ] +; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY2:.*]] ; CHECK-INTERLEAVED: [[FOR_BODY2]]: ; CHECK-INTERLEAVED-NEXT: [[A_117:%.*]] = phi i32 [ [[INC6:%.*]], %[[FOR_INC5:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] @@ -2227,7 +2227,7 @@ entry: for.body2: ; preds = %entry, %for.inc5 %a.117 = phi i32 [ %inc6, %for.inc5 ], [ 0, %entry ] - %g.016 = phi i32 [ %g.1, %for.inc5 ], [ undef, %entry ] + %g.016 = phi i32 [ %g.1, %for.inc5 ], [ 0, %entry ] %arrayidx = getelementptr inbounds i8, ptr %h, i32 %a.117 %0 = load i8, ptr %arrayidx, align 1 %tobool3.not = icmp eq i8 %0, 0 @@ -2263,7 +2263,7 @@ define i32 @predicated_or_dominates_reduction(ptr %b) { ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, %[[VECTOR_PH]] ], [ [[TMP48:%.*]], %[[PRED_LOAD_CONTINUE6]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP48:%.*]], %[[PRED_LOAD_CONTINUE6]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 2 @@ -2340,7 +2340,7 @@ define i32 @predicated_or_dominates_reduction(ptr %b) { ; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK-INTERLEAVED: [[VECTOR_BODY]]: ; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE15:.*]] ] -; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, %[[VECTOR_PH]] ], [ [[TMP94:%.*]], %[[PRED_LOAD_CONTINUE15]] ] +; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP94:%.*]], %[[PRED_LOAD_CONTINUE15]] ] ; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP98:%.*]], %[[PRED_LOAD_CONTINUE15]] ] ; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 ; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1 @@ -2480,7 +2480,7 @@ for.cond.cleanup: ; preds = %for.inc for.body: ; preds = %entry, %for.inc %g.09 = phi i32 [ 0, %entry ], [ %inc3, %for.inc ] - %a.08 = phi i32 [ undef, %entry ], [ %a.1, %for.inc ] + %a.08 = phi i32 [ 0, %entry ], [ %a.1, %for.inc ] %d = getelementptr inbounds [0 x %struct.e], ptr %b, i32 0, i32 %g.09, i32 1 %0 = load i32, ptr %d, align 4 %tobool.not = icmp eq i32 %0, 0 diff --git a/llvm/test/Transforms/LoopVectorize/reverse_iter.ll b/llvm/test/Transforms/LoopVectorize/reverse_iter.ll index 43e916b..6576675 100644 --- a/llvm/test/Transforms/LoopVectorize/reverse_iter.ll +++ b/llvm/test/Transforms/LoopVectorize/reverse_iter.ll @@ -17,8 +17,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ;CHECK: <i32 0, i32 -1, i32 -2, i32 -3> ;CHECK: ret define i32 @foo(i32 %n, ptr nocapture %A) { - %1 = icmp sgt i32 %n, 0 - br i1 %1, label %.lr.ph, label %._crit_edge + br label %.lr.ph .lr.ph: ; preds = %0 %2 = sext i32 %n to i64 @@ -26,7 +25,7 @@ define i32 @foo(i32 %n, ptr nocapture %A) { ; <label>:3 ; preds = %.lr.ph, %3 %indvars.iv = phi i64 [ %2, %.lr.ph ], [ %indvars.iv.next, %3 ] - %sum.01 = phi i32 [ undef, %.lr.ph ], [ %9, %3 ] + %sum.01 = phi i32 [ 0, %.lr.ph ], [ %9, %3 ] %4 = trunc i64 %indvars.iv to i32 %5 = shl nsw i32 %4, 1 %6 = sext i32 %5 to i64 @@ -38,8 +37,7 @@ define i32 @foo(i32 %n, ptr nocapture %A) { %11 = icmp sgt i32 %10, 0 br i1 %11, label %3, label %._crit_edge -._crit_edge: ; preds = %3, %0 - %sum.0.lcssa = phi i32 [ undef, %0 ], [ %9, %3 ] - ret i32 %sum.0.lcssa +._crit_edge: ; preds = %3 + ret i32 %9 } diff --git a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll index 60da336..1216bc1 100644 --- a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll +++ b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll @@ -178,13 +178,14 @@ for.exit: define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) { ; CHECK-VF4UF1-LABEL: define i32 @recurrence_2( ; CHECK-VF4UF1-SAME: ptr readonly captures(none) [[A:%.*]], i32 [[N:%.*]]) { -; CHECK-VF4UF1-NEXT: [[ENTRY:.*]]: -; CHECK-VF4UF1-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[N]], 0 -; CHECK-VF4UF1-NEXT: br i1 [[CMP27]], label %[[FOR_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]] +; CHECK-VF4UF1-NEXT: [[ENTRY:.*:]] +; CHECK-VF4UF1-NEXT: br label %[[FOR_PREHEADER:.*]] ; CHECK-VF4UF1: [[FOR_PREHEADER]]: ; CHECK-VF4UF1-NEXT: [[ARRAYIDX2_PHI_TRANS_INSERT:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 -1 ; CHECK-VF4UF1-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ARRAYIDX2_PHI_TRANS_INSERT]], align 4 -; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-VF4UF1-NEXT: [[TMP5:%.*]] = add i32 [[N]], -1 +; CHECK-VF4UF1-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64 +; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[TMP6]], 1 ; CHECK-VF4UF1-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-VF4UF1-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 2 ; CHECK-VF4UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] @@ -202,7 +203,7 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) { ; CHECK-VF4UF1: [[VECTOR_BODY]]: ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF1-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 4 x i32> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ] -; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ undef, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] +; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] ; CHECK-VF4UF1-NEXT: [[WIDE_LOAD]] = load <vscale x 4 x i32>, ptr [[TMP10]], align 4 ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> [[VECTOR_RECUR]], <vscale x 4 x i32> [[WIDE_LOAD]], i32 -1) @@ -225,25 +226,25 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) { ; CHECK-VF4UF1: [[SCALAR_PH]]: ; CHECK-VF4UF1-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ [[DOTPRE]], %[[FOR_PREHEADER]] ] ; CHECK-VF4UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ] -; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP19]], %[[MIDDLE_BLOCK]] ], [ undef, %[[FOR_PREHEADER]] ] +; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP19]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ] ; CHECK-VF4UF1-NEXT: br label %[[SCALAR_BODY:.*]] ; CHECK-VF4UF1: [[FOR_COND_CLEANUP_LOOPEXIT]]: -; CHECK-VF4UF1-NEXT: [[MINMAX_0_COND_LCSSA:%.*]] = phi i32 [ [[MINMAX_0_COND:%.*]], %[[SCALAR_BODY]] ], [ [[TMP19]], %[[MIDDLE_BLOCK]] ] -; CHECK-VF4UF1-NEXT: br label %[[FOR_COND_CLEANUP]] +; CHECK-VF4UF1-NEXT: [[MINMAX_0_LCSSA:%.*]] = phi i32 [ [[MINMAX_0_COND:%.*]], %[[SCALAR_BODY]] ], [ [[TMP19]], %[[MIDDLE_BLOCK]] ] +; CHECK-VF4UF1-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; CHECK-VF4UF1: [[FOR_COND_CLEANUP]]: -; CHECK-VF4UF1-NEXT: [[MINMAX_0_LCSSA:%.*]] = phi i32 [ undef, %[[ENTRY]] ], [ [[MINMAX_0_COND_LCSSA]], %[[FOR_COND_CLEANUP_LOOPEXIT]] ] ; CHECK-VF4UF1-NEXT: ret i32 [[MINMAX_0_LCSSA]] ; CHECK-VF4UF1: [[SCALAR_BODY]]: ; ; CHECK-VF4UF2-LABEL: define i32 @recurrence_2( ; CHECK-VF4UF2-SAME: ptr readonly captures(none) [[A:%.*]], i32 [[N:%.*]]) { -; CHECK-VF4UF2-NEXT: [[ENTRY:.*]]: -; CHECK-VF4UF2-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[N]], 0 -; CHECK-VF4UF2-NEXT: br i1 [[CMP27]], label %[[FOR_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]] +; CHECK-VF4UF2-NEXT: [[ENTRY:.*:]] +; CHECK-VF4UF2-NEXT: br label %[[FOR_PREHEADER:.*]] ; CHECK-VF4UF2: [[FOR_PREHEADER]]: ; CHECK-VF4UF2-NEXT: [[ARRAYIDX2_PHI_TRANS_INSERT:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 -1 ; CHECK-VF4UF2-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ARRAYIDX2_PHI_TRANS_INSERT]], align 4 -; CHECK-VF4UF2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-VF4UF2-NEXT: [[TMP5:%.*]] = add i32 [[N]], -1 +; CHECK-VF4UF2-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64 +; CHECK-VF4UF2-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[TMP6]], 1 ; CHECK-VF4UF2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-VF4UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 3 ; CHECK-VF4UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] @@ -261,8 +262,8 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) { ; CHECK-VF4UF2: [[VECTOR_BODY]]: ; CHECK-VF4UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF2-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 4 x i32> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD2:%.*]], %[[VECTOR_BODY]] ] -; CHECK-VF4UF2-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ undef, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] -; CHECK-VF4UF2-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ undef, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] +; CHECK-VF4UF2-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] +; CHECK-VF4UF2-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] ; CHECK-VF4UF2-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-VF4UF2-NEXT: [[TMP13:%.*]] = shl nuw i64 [[TMP12]], 2 @@ -296,19 +297,17 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) { ; CHECK-VF4UF2: [[SCALAR_PH]]: ; CHECK-VF4UF2-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ [[DOTPRE]], %[[FOR_PREHEADER]] ] ; CHECK-VF4UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ] -; CHECK-VF4UF2-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP28]], %[[MIDDLE_BLOCK]] ], [ undef, %[[FOR_PREHEADER]] ] +; CHECK-VF4UF2-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP28]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ] ; CHECK-VF4UF2-NEXT: br label %[[SCALAR_BODY:.*]] ; CHECK-VF4UF2: [[FOR_COND_CLEANUP_LOOPEXIT]]: -; CHECK-VF4UF2-NEXT: [[MINMAX_0_COND_LCSSA:%.*]] = phi i32 [ [[MINMAX_0_COND:%.*]], %[[SCALAR_BODY]] ], [ [[TMP28]], %[[MIDDLE_BLOCK]] ] -; CHECK-VF4UF2-NEXT: br label %[[FOR_COND_CLEANUP]] +; CHECK-VF4UF2-NEXT: [[MINMAX_0_LCSSA:%.*]] = phi i32 [ [[MINMAX_0_COND:%.*]], %[[SCALAR_BODY]] ], [ [[TMP28]], %[[MIDDLE_BLOCK]] ] +; CHECK-VF4UF2-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; CHECK-VF4UF2: [[FOR_COND_CLEANUP]]: -; CHECK-VF4UF2-NEXT: [[MINMAX_0_LCSSA:%.*]] = phi i32 [ undef, %[[ENTRY]] ], [ [[MINMAX_0_COND_LCSSA]], %[[FOR_COND_CLEANUP_LOOPEXIT]] ] ; CHECK-VF4UF2-NEXT: ret i32 [[MINMAX_0_LCSSA]] ; CHECK-VF4UF2: [[SCALAR_BODY]]: ; entry: - %cmp27 = icmp sgt i32 %n, 0 - br i1 %cmp27, label %for.preheader, label %for.cond.cleanup + br label %for.preheader for.preheader: %arrayidx2.phi.trans.insert = getelementptr inbounds i32, ptr %a, i64 -1 @@ -320,13 +319,12 @@ for.cond.cleanup.loopexit: br label %for.cond.cleanup for.cond.cleanup: - %minmax.0.lcssa = phi i32 [ undef, %entry ], [ %minmax.0.cond.lcssa, %for.cond.cleanup.loopexit ] - ret i32 %minmax.0.lcssa + ret i32 %minmax.0.cond.lcssa scalar.body: %0 = phi i32 [ %.pre, %for.preheader ], [ %1, %scalar.body ] %indvars.iv = phi i64 [ 0, %for.preheader ], [ %indvars.iv.next, %scalar.body ] - %minmax.028 = phi i32 [ undef, %for.preheader ], [ %minmax.0.cond, %scalar.body ] + %minmax.028 = phi i32 [ 0, %for.preheader ], [ %minmax.0.cond, %scalar.body ] %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv %1 = load i32, ptr %arrayidx, align 4 %sub3 = sub nsw i32 %1, %0 diff --git a/llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll b/llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll index 58ad64d..8224d6b 100644 --- a/llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll +++ b/llvm/test/Transforms/LoopVectorize/scev-exitlim-crash.ll @@ -16,7 +16,7 @@ entry: br label %for.cond for.cond: ; preds = %for.cond, %entry - %i.0 = phi i32 [ undef, %entry ], [ %inc, %for.cond ] + %i.0 = phi i32 [ poison, %entry ], [ %inc, %for.cond ] %cmp = icmp slt i32 %i.0, 0 %fsub = fsub double undef, undef %fadd = fadd double %fsub, 1.000000e+00 @@ -36,7 +36,7 @@ for.cond7.preheader.lr.ph: ; preds = %for.cond4.preheader for.cond7.preheader: ; preds = %for.cond7.preheader.lr.ph, %for.inc23 %y.017 = phi i32 [ 0, %for.cond7.preheader.lr.ph ], [ %inc24, %for.inc23 ] %i.116 = phi i32 [ 0, %for.cond7.preheader.lr.ph ], [ %i.2.lcssa, %for.inc23 ] - %n.015 = phi i32 [ undef, %for.cond7.preheader.lr.ph ], [ %inc25, %for.inc23 ] + %n.015 = phi i32 [ poison, %for.cond7.preheader.lr.ph ], [ %inc25, %for.inc23 ] %1 = load i32, ptr @b, align 4, !tbaa !5 %tobool11 = icmp eq i32 %1, 0 br i1 %tobool11, label %for.inc23, label %for.body8.lr.ph diff --git a/llvm/test/Transforms/LoopVectorize/select-reduction-start-value-may-be-undef-or-poison.ll b/llvm/test/Transforms/LoopVectorize/select-reduction-start-value-may-be-undef-or-poison.ll index f4d5a84..cd9eb72 100644 --- a/llvm/test/Transforms/LoopVectorize/select-reduction-start-value-may-be-undef-or-poison.ll +++ b/llvm/test/Transforms/LoopVectorize/select-reduction-start-value-may-be-undef-or-poison.ll @@ -23,7 +23,7 @@ define i64 @pr62565_incoming_value_known_undef(i64 %a, ptr %src) { ; CHECK: middle.block: ; CHECK-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> [[TMP2]]) ; CHECK-NEXT: [[TMP5:%.*]] = freeze i1 [[TMP4]] -; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP5]], i64 [[A]], i64 undef +; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP5]], i64 [[A]], i64 poison ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: ; CHECK-NEXT: ret i64 [[RDX_SELECT]] @@ -33,7 +33,7 @@ entry: loop: %iv = phi i32 [ 1, %entry ], [ %add, %loop ] - %red = phi i64 [ undef, %entry ], [ %select, %loop ] + %red = phi i64 [ poison, %entry ], [ %select, %loop ] %gep = getelementptr inbounds i32, ptr %src, i32 %iv %l = load i32, ptr %gep %c = icmp eq i32 %l, 1 diff --git a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll index 358f1b0..71311db 100644 --- a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll +++ b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll @@ -102,7 +102,7 @@ define void @blend_chain_iv(i1 %c) { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[PREDPHI1:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i64> [[PREDPHI1]], <4 x i64> undef +; CHECK-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i64> [[PREDPHI1]], <4 x i64> poison ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 1 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 2 @@ -139,11 +139,11 @@ loop.next.2: br label %loop.next.3 loop.next.3: - %blend.1 = phi i64 [ undef, %loop.next ], [ %iv, %loop.next.2 ] + %blend.1 = phi i64 [ poison, %loop.next ], [ %iv, %loop.next.2 ] br label %loop.latch loop.latch: ; preds = %loop.next, %loop.header - %blend = phi i64 [ undef, %loop.header ], [ %blend.1, %loop.next.3 ] + %blend = phi i64 [ poison, %loop.header ], [ %blend.1, %loop.next.3 ] %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 %blend store i16 0, ptr %dst.ptr %iv.next = add nuw nsw i64 %iv, 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll new file mode 100644 index 0000000..7accca3 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll @@ -0,0 +1,37 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s -slp-threshold=-99999 | FileCheck %s + +define void @test() { +; CHECK-LABEL: define void @test() { +; CHECK-NEXT: [[BB:.*]]: +; CHECK-NEXT: br i1 false, label %[[BB1:.*]], label %[[BB6:.*]] +; CHECK: [[BB1]]: +; CHECK-NEXT: br label %[[BB6]] +; CHECK: [[BB6]]: +; CHECK-NEXT: [[TMP0:%.*]] = phi <4 x i32> [ <i32 0, i32 0, i32 poison, i32 0>, %[[BB]] ], [ <i32 0, i32 0, i32 -1, i32 -1>, %[[BB1]] ] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 0 +; CHECK-NEXT: ret void +; +bb: + br i1 false, label %bb1, label %bb6 + +bb1: + %add = add i32 0, 0 + %shl = shl i32 %add, 0 + %sub = sub i32 0, 1 + %add2 = add i32 %sub, %shl + %add3 = add i32 0, 0 + %shl4 = shl i32 %add3, 0 + %ashr = ashr i32 %shl4, 1 + %add5 = add i32 0, 0 + br label %bb6 + +bb6: + %phi = phi i32 [ poison, %bb ], [ %add2, %bb1 ] + %phi7 = phi i32 [ 0, %bb ], [ %ashr, %bb1 ] + %phi8 = phi i32 [ 0, %bb ], [ %add2, %bb1 ] + %phi9 = phi i32 [ 0, %bb ], [ %add5, %bb1 ] + %or = or i32 %phi8, 0 + ret void +} diff --git a/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version-pretty.s b/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version-pretty.s new file mode 100644 index 0000000..b889ce5 --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version-pretty.s @@ -0,0 +1,44 @@ +# Demonstrate dumping DW_AT_language_version in human-readable form. +# RUN: llvm-mc -triple=x86_64--linux -filetype=obj -o %t.o < %s +# RUN: llvm-dwarfdump %t.o -v | FileCheck %s --check-prefix=VERBOSE +# RUN: llvm-dwarfdump %t.o | FileCheck %s --check-prefix=NO-VERBOSE + +# VERBOSE: .debug_info contents: +# VERBOSE: DW_AT_language_name [DW_FORM_data2] (DW_LNAME_C) +# VERBOSE: DW_AT_language_version [DW_FORM_data4] (201112 C11) +# VERBOSE: DW_AT_language_name [DW_FORM_data2] (0x0000) +# VERBOSE: DW_AT_language_version [DW_FORM_data4] (12 Unknown) + +# NO-VERBOSE: .debug_info contents: +# NO-VERBOSE: DW_AT_language_name (DW_LNAME_C) +# NO-VERBOSE: DW_AT_language_version (C11) +# NO-VERBOSE: DW_AT_language_name (0x0000) +# NO-VERBOSE: DW_AT_language_version (Unknown) + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 1 # DW_CHILDREN_no + .ascii "\220\001" # DW_AT_language_name + .byte 5 # DW_FORM_data2 + .ascii "\221\001" # DW_AT_language_version + .byte 6 # DW_FORM_data4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + + .section .debug_info,"",@progbits + .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit +.Ldebug_info_start0: + .short 5 # DWARF version number + .byte 1 # Unit type + .byte 8 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + .byte 1 # Abbrev [1] DW_TAG_compile_unit + .short 3 # DW_AT_language_name + .long 201112 # DW_AT_language_version + .byte 1 # Abbrev [1] DW_TAG_compile_unit + .short 0 # DW_AT_language_name + .long 12 # DW_AT_language_version + .byte 0 +.Ldebug_info_end0: diff --git a/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version.s b/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version.s index f1be8fd..985836f 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/DW_AT_language_version.s @@ -1,13 +1,19 @@ -# Demonstrate dumping DW_AT_language_version. -# RUN: llvm-mc -triple=x86_64--linux -filetype=obj < %s | \ -# RUN: llvm-dwarfdump -v - | FileCheck %s +# Demonstrate dumping DW_AT_language_version without an +# accompanying DW_AT_language_name. +# RUN: llvm-mc -triple=x86_64--linux -filetype=obj -o %t.o < %s +# RUN: llvm-dwarfdump -v %t.o | FileCheck %s --check-prefix=VERBOSE +# RUN: llvm-dwarfdump %t.o | FileCheck %s --check-prefix=NO-VERBOSE -# CHECK: .debug_abbrev contents: -# CHECK: DW_AT_language_version DW_FORM_data4 -# CHECK: DW_AT_language_version DW_FORM_data2 -# CHECK: .debug_info contents: -# CHECK: DW_AT_language_version [DW_FORM_data4] (201402) -# CHECK: DW_AT_language_version [DW_FORM_data2] (0) +# VERBOSE: .debug_abbrev contents: +# VERBOSE: DW_AT_language_version DW_FORM_data4 +# VERBOSE: DW_AT_language_version DW_FORM_data2 +# VERBOSE: .debug_info contents: +# VERBOSE: DW_AT_language_version [DW_FORM_data4] (201402) +# VERBOSE: DW_AT_language_version [DW_FORM_data2] (0) + +# NO-VERBOSE: .debug_info contents: +# NO-VERBOSE: DW_AT_language_version (201402) +# NO-VERBOSE: DW_AT_language_version (0) .section .debug_abbrev,"",@progbits .byte 1 # Abbreviation Code |