diff options
Diffstat (limited to 'llvm/test')
112 files changed, 30396 insertions, 7264 deletions
diff --git a/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll b/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll index b1fe7b1..7ba422d 100644 --- a/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll @@ -615,22 +615,14 @@ define void @test_ptrs_aligned_by_4_via_assumption(ptr %start, ptr %end) { ; CHECK-LABEL: 'test_ptrs_aligned_by_4_via_assumption' ; CHECK-NEXT: Classifying expressions for: @test_ptrs_aligned_by_4_via_assumption ; CHECK-NEXT: %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] -; CHECK-NEXT: --> {%start,+,4}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {%start,+,4}<%loop> U: full-set S: full-set Exits: ((4 * ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4))<nuw> + %start) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: %iv.next = getelementptr i8, ptr %iv, i64 4 -; CHECK-NEXT: --> {(4 + %start),+,4}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {(4 + %start),+,4}<%loop> U: full-set S: full-set Exits: (4 + (4 * ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4))<nuw> + %start) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_ptrs_aligned_by_4_via_assumption -; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. -; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) -; CHECK-NEXT: Predicates: -; CHECK-NEXT: Equal predicate: (zext i2 ((trunc i64 (ptrtoint ptr %end to i64) to i2) + (-1 * (trunc i64 (ptrtoint ptr %start to i64) to i2))) to i64) == 0 -; CHECK-NEXT: Loop %loop: Predicated constant max backedge-taken count is i64 4611686018427387903 -; CHECK-NEXT: Predicates: -; CHECK-NEXT: Equal predicate: (zext i2 ((trunc i64 (ptrtoint ptr %end to i64) to i2) + (-1 * (trunc i64 (ptrtoint ptr %start to i64) to i2))) to i64) == 0 -; CHECK-NEXT: Loop %loop: Predicated symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) -; CHECK-NEXT: Predicates: -; CHECK-NEXT: Equal predicate: (zext i2 ((trunc i64 (ptrtoint ptr %end to i64) to i2) + (-1 * (trunc i64 (ptrtoint ptr %start to i64) to i2))) to i64) == 0 +; CHECK-NEXT: Loop %loop: backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i64 4611686018427387903 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) +; CHECK-NEXT: Loop %loop: Trip multiple is 1 ; entry: call void @llvm.assume(i1 true) [ "align"(ptr %start, i64 4) ] @@ -652,22 +644,14 @@ define void @test_ptrs_aligned_by_8_via_assumption(ptr %start, ptr %end) { ; CHECK-LABEL: 'test_ptrs_aligned_by_8_via_assumption' ; CHECK-NEXT: Classifying expressions for: @test_ptrs_aligned_by_8_via_assumption ; CHECK-NEXT: %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] -; CHECK-NEXT: --> {%start,+,4}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {%start,+,4}<%loop> U: full-set S: full-set Exits: ((4 * ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4))<nuw> + %start) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: %iv.next = getelementptr i8, ptr %iv, i64 4 -; CHECK-NEXT: --> {(4 + %start),+,4}<%loop> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {(4 + %start),+,4}<%loop> U: full-set S: full-set Exits: (4 + (4 * ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4))<nuw> + %start) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_ptrs_aligned_by_8_via_assumption -; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. -; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) -; CHECK-NEXT: Predicates: -; CHECK-NEXT: Equal predicate: (zext i2 ((trunc i64 (ptrtoint ptr %end to i64) to i2) + (-1 * (trunc i64 (ptrtoint ptr %start to i64) to i2))) to i64) == 0 -; CHECK-NEXT: Loop %loop: Predicated constant max backedge-taken count is i64 4611686018427387903 -; CHECK-NEXT: Predicates: -; CHECK-NEXT: Equal predicate: (zext i2 ((trunc i64 (ptrtoint ptr %end to i64) to i2) + (-1 * (trunc i64 (ptrtoint ptr %start to i64) to i2))) to i64) == 0 -; CHECK-NEXT: Loop %loop: Predicated symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) -; CHECK-NEXT: Predicates: -; CHECK-NEXT: Equal predicate: (zext i2 ((trunc i64 (ptrtoint ptr %end to i64) to i2) + (-1 * (trunc i64 (ptrtoint ptr %start to i64) to i2))) to i64) == 0 +; CHECK-NEXT: Loop %loop: backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i64 4611686018427387903 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) /u 4) +; CHECK-NEXT: Loop %loop: Trip multiple is 1 ; entry: call void @llvm.assume(i1 true) [ "align"(ptr %start, i64 8) ] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir index 6362ed6..9381f0f4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir @@ -1,11 +1,12 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s -# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s +# RUN: llc -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s +# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s ... --- name: fconstant_to_constant_s32 alignment: 4 tracksRegLiveness: true +legalized: true frameInfo: maxAlignment: 1 machineFunctionInfo: {} @@ -24,16 +25,17 @@ body: | ; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD]](p0) :: (store (s32)) ; CHECK-NEXT: RET_ReallyLR %0:_(p0) = COPY $x0 - %3:_(s32) = G_FCONSTANT float 0x3FA99999A0000000 - %1:_(s64) = G_CONSTANT i64 524 - %2:_(p0) = G_PTR_ADD %0, %1(s64) - G_STORE %3(s32), %2(p0) :: (store (s32)) + %1:_(s32) = G_FCONSTANT float 0x3FA99999A0000000 + %2:_(s64) = G_CONSTANT i64 524 + %3:_(p0) = G_PTR_ADD %0, %2(s64) + G_STORE %1(s32), %3(p0) :: (store (s32)) RET_ReallyLR ... --- name: fconstant_to_constant_s64 alignment: 4 tracksRegLiveness: true +legalized: true frameInfo: maxAlignment: 1 machineFunctionInfo: {} @@ -48,7 +50,7 @@ body: | ; CHECK-NEXT: G_STORE %c(s64), %ptr(p0) :: (store (s64)) ; CHECK-NEXT: RET_ReallyLR %ptr:_(p0) = COPY $x0 - %c:_(s64) = G_FCONSTANT double 0.0 + %c:_(s64) = G_FCONSTANT double 0.000000e+00 G_STORE %c(s64), %ptr(p0) :: (store (s64)) RET_ReallyLR ... @@ -56,6 +58,7 @@ body: | name: no_store_means_no_combine alignment: 4 tracksRegLiveness: true +legalized: true frameInfo: maxAlignment: 1 machineFunctionInfo: {} @@ -71,7 +74,7 @@ body: | ; CHECK-NEXT: %add:_(s64) = G_FADD %v, %c ; CHECK-NEXT: RET_ReallyLR implicit %add(s64) %v:_(s64) = COPY $x0 - %c:_(s64) = G_FCONSTANT double 0.0 + %c:_(s64) = G_FCONSTANT double 0.000000e+00 %add:_(s64) = G_FADD %v, %c - RET_ReallyLR implicit %add + RET_ReallyLR implicit %add(s64) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir index c301e76..c00ce22 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir @@ -48,8 +48,9 @@ body: | ; CHECK-NEXT: $w0 = COPY [[C]](s32) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00 ; CHECK-NEXT: $x0 = COPY [[C1]](s64) - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: $w0 = COPY [[C2]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C2]](s16) + ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32) %0:_(s32) = G_FCONSTANT float 1.0 $w0 = COPY %0 %1:_(s64) = G_FCONSTANT double 2.0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir index ddf219d..c6df345 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir @@ -8,7 +8,7 @@ tracksRegLiveness: true body: | bb.0: ; NO-FP16-LABEL: name: fp16 - ; NO-FP16: %cst:_(s16) = G_CONSTANT i16 0 + ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH0000 ; NO-FP16-NEXT: $h0 = COPY %cst(s16) ; NO-FP16-NEXT: RET_ReallyLR implicit $h0 ; @@ -26,7 +26,7 @@ tracksRegLiveness: true body: | bb.0: ; NO-FP16-LABEL: name: fp16_non_zero - ; NO-FP16: %cst:_(s16) = G_CONSTANT i16 16384 + ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH4000 ; NO-FP16-NEXT: $h0 = COPY %cst(s16) ; NO-FP16-NEXT: RET_ReallyLR implicit $h0 ; @@ -44,7 +44,7 @@ tracksRegLiveness: true body: | bb.1.entry: ; NO-FP16-LABEL: name: nan - ; NO-FP16: %cst:_(s16) = G_CONSTANT i16 31745 + ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH7C01 ; NO-FP16-NEXT: %ext:_(s32) = G_FPEXT %cst(s16) ; NO-FP16-NEXT: $w0 = COPY %ext(s32) ; NO-FP16-NEXT: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll index cb5df07..322a96a 100644 --- a/llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll +++ b/llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll @@ -739,15 +739,14 @@ define ptr @postidx32_shalf(ptr %src, ptr %out, half %a) { ; ; GISEL-LABEL: postidx32_shalf: ; GISEL: ; %bb.0: -; GISEL-NEXT: mov w8, #0 ; =0x0 -; GISEL-NEXT: ldr h1, [x0], #4 -; GISEL-NEXT: fmov s2, w8 +; GISEL-NEXT: movi d1, #0000000000000000 +; GISEL-NEXT: ldr h2, [x0], #4 ; GISEL-NEXT: ; kill: def $h0 killed $h0 def $s0 ; GISEL-NEXT: fmov w9, s0 -; GISEL-NEXT: fcvt s3, h1 -; GISEL-NEXT: fmov w8, s1 -; GISEL-NEXT: fcvt s2, h2 -; GISEL-NEXT: fcmp s3, s2 +; GISEL-NEXT: fcvt s3, h2 +; GISEL-NEXT: fmov w8, s2 +; GISEL-NEXT: fcvt s1, h1 +; GISEL-NEXT: fcmp s3, s1 ; GISEL-NEXT: csel w8, w8, w9, mi ; GISEL-NEXT: strh w8, [x1] ; GISEL-NEXT: ret diff --git a/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir b/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir new file mode 100644 index 0000000..074f75a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: saddlp1d +legalized: true +regBankSelected: false +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x0 + + ; CHECK-LABEL: name: saddlp1d + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>)) + ; CHECK-NEXT: [[SADDLP:%[0-9]+]]:fpr(s64) = G_SADDLP [[LOAD]] + ; CHECK-NEXT: $d0 = COPY [[SADDLP]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 + %0:_(p0) = COPY $x0 + %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>)) + %2:_(s64) = G_SADDLP %1 + $d0 = COPY %2(s64) + RET_ReallyLR implicit $d0 +... +--- +name: uaddlp1d +legalized: true +regBankSelected: false +failedISel: false +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x0 + + ; CHECK-LABEL: name: uaddlp1d + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>)) + ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:fpr(s64) = G_UADDLP [[LOAD]] + ; CHECK-NEXT: $d0 = COPY [[UADDLP]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 + %0:_(p0) = COPY $x0 + %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>)) + %2:_(s64) = G_UADDLP %1 + $d0 = COPY %2(s64) + RET_ReallyLR implicit $d0 +... diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll index 938712a..3cf0115 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll @@ -1,9 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI - -; CHECK-GI: warning: Instruction selection used fallback path for saddlp1d -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uaddlp1d +; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI define <8 x i8> @addhn8b(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: addhn8b: diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll index adc536d..b234ef7 100644 --- a/llvm/test/CodeGen/AArch64/f16-instructions.ll +++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll @@ -782,18 +782,19 @@ define void @test_fccmp(half %in, ptr %out) { ; ; CHECK-CVT-GI-LABEL: test_fccmp: ; CHECK-CVT-GI: // %bb.0: -; CHECK-CVT-GI-NEXT: mov w8, #17664 // =0x4500 -; CHECK-CVT-GI-NEXT: mov w9, #18432 // =0x4800 +; CHECK-CVT-GI-NEXT: adrp x8, .LCPI29_0 ; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $s0 ; CHECK-CVT-GI-NEXT: fcvt s2, h0 -; CHECK-CVT-GI-NEXT: fmov s1, w8 -; CHECK-CVT-GI-NEXT: fmov s3, w9 -; CHECK-CVT-GI-NEXT: fmov w9, s0 -; CHECK-CVT-GI-NEXT: fcvt s1, h1 -; CHECK-CVT-GI-NEXT: fcvt s3, h3 -; CHECK-CVT-GI-NEXT: fcmp s2, s1 -; CHECK-CVT-GI-NEXT: fccmp s2, s3, #4, mi -; CHECK-CVT-GI-NEXT: csel w8, w9, w8, gt +; CHECK-CVT-GI-NEXT: ldr h1, [x8, :lo12:.LCPI29_0] +; CHECK-CVT-GI-NEXT: adrp x8, .LCPI29_1 +; CHECK-CVT-GI-NEXT: ldr h4, [x8, :lo12:.LCPI29_1] +; CHECK-CVT-GI-NEXT: fmov w8, s0 +; CHECK-CVT-GI-NEXT: fcvt s3, h1 +; CHECK-CVT-GI-NEXT: fmov w9, s1 +; CHECK-CVT-GI-NEXT: fcvt s4, h4 +; CHECK-CVT-GI-NEXT: fcmp s2, s3 +; CHECK-CVT-GI-NEXT: fccmp s2, s4, #4, mi +; CHECK-CVT-GI-NEXT: csel w8, w8, w9, gt ; CHECK-CVT-GI-NEXT: strh w8, [x0] ; CHECK-CVT-GI-NEXT: ret ; diff --git a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll index 51aad4fe..7409bfb 100644 --- a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll +++ b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll @@ -166,9 +166,9 @@ define i32 @fcvtzs_f16_i32_7(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_f16_i32_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI8_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI8_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -206,9 +206,9 @@ define i32 @fcvtzs_f16_i32_15(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_f16_i32_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI9_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI9_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -246,9 +246,9 @@ define i64 @fcvtzs_f16_i64_7(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_f16_i64_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI10_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI10_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -286,9 +286,9 @@ define i64 @fcvtzs_f16_i64_15(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_f16_i64_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI11_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI11_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -470,9 +470,9 @@ define i32 @fcvtzu_f16_i32_7(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_f16_i32_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI20_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI20_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -510,9 +510,9 @@ define i32 @fcvtzu_f16_i32_15(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_f16_i32_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI21_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI21_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -550,9 +550,9 @@ define i64 @fcvtzu_f16_i64_7(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_f16_i64_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI22_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI22_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -590,9 +590,9 @@ define i64 @fcvtzu_f16_i64_15(half %flt) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_f16_i64_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI23_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI23_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -775,10 +775,10 @@ define half @scvtf_f16_i32_7(i32 %int) { ; CHECK-GI-NO16-LABEL: scvtf_f16_i32_7: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: scvtf s0, w0 -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI32_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI32_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -815,10 +815,10 @@ define half @scvtf_f16_i32_15(i32 %int) { ; CHECK-GI-NO16-LABEL: scvtf_f16_i32_15: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: scvtf s0, w0 -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI33_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI33_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -855,10 +855,10 @@ define half @scvtf_f16_i64_7(i64 %long) { ; CHECK-GI-NO16-LABEL: scvtf_f16_i64_7: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: scvtf s0, x0 -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI34_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI34_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -895,10 +895,10 @@ define half @scvtf_f16_i64_15(i64 %long) { ; CHECK-GI-NO16-LABEL: scvtf_f16_i64_15: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: scvtf s0, x0 -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI35_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI35_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1079,10 +1079,10 @@ define half @ucvtf_f16_i32_7(i32 %int) { ; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_7: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: ucvtf s0, w0 -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI44_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI44_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1119,10 +1119,10 @@ define half @ucvtf_f16_i32_15(i32 %int) { ; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_15: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: ucvtf s0, w0 -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI45_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI45_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1159,10 +1159,10 @@ define half @ucvtf_f16_i64_7(i64 %long) { ; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_7: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: ucvtf s0, x0 -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI46_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI46_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1199,10 +1199,10 @@ define half @ucvtf_f16_i64_15(i64 %long) { ; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_15: ; CHECK-GI-NO16: // %bb.0: ; CHECK-GI-NO16-NEXT: ucvtf s0, x0 -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 -; CHECK-GI-NO16-NEXT: fmov s1, w8 -; CHECK-GI-NO16-NEXT: fcvt h0, s0 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI47_0 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI47_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 +; CHECK-GI-NO16-NEXT: fcvt h0, s0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 ; CHECK-GI-NO16-NEXT: fdiv s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1373,9 +1373,9 @@ define i32 @fcvtzs_sat_f16_i32_7(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_sat_f16_i32_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI55_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI55_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1413,9 +1413,9 @@ define i32 @fcvtzs_sat_f16_i32_15(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_sat_f16_i32_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI56_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI56_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1453,9 +1453,9 @@ define i64 @fcvtzs_sat_f16_i64_7(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_sat_f16_i64_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI57_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI57_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1493,9 +1493,9 @@ define i64 @fcvtzs_sat_f16_i64_15(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzs_sat_f16_i64_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI58_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI58_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1667,9 +1667,9 @@ define i32 @fcvtzu_sat_f16_i32_7(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_sat_f16_i32_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI66_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI66_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1707,9 +1707,9 @@ define i32 @fcvtzu_sat_f16_i32_15(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_sat_f16_i32_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI67_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI67_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1747,9 +1747,9 @@ define i64 @fcvtzu_sat_f16_i64_7(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_sat_f16_i64_7: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #22528 // =0x5800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI68_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI68_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 @@ -1787,9 +1787,9 @@ define i64 @fcvtzu_sat_f16_i64_15(half %dbl) { ; ; CHECK-GI-NO16-LABEL: fcvtzu_sat_f16_i64_15: ; CHECK-GI-NO16: // %bb.0: -; CHECK-GI-NO16-NEXT: mov w8, #30720 // =0x7800 +; CHECK-GI-NO16-NEXT: adrp x8, .LCPI69_0 ; CHECK-GI-NO16-NEXT: fcvt s0, h0 -; CHECK-GI-NO16-NEXT: fmov s1, w8 +; CHECK-GI-NO16-NEXT: ldr h1, [x8, :lo12:.LCPI69_0] ; CHECK-GI-NO16-NEXT: fcvt s1, h1 ; CHECK-GI-NO16-NEXT: fmul s0, s0, s1 ; CHECK-GI-NO16-NEXT: fcvt h0, s0 diff --git a/llvm/test/CodeGen/AArch64/fdiv-combine.ll b/llvm/test/CodeGen/AArch64/fdiv-combine.ll index 91bb8ac..9eacb61 100644 --- a/llvm/test/CodeGen/AArch64/fdiv-combine.ll +++ b/llvm/test/CodeGen/AArch64/fdiv-combine.ll @@ -12,22 +12,14 @@ ; => ; recip = 1.0 / D; a * recip; b * recip; c * recip; define void @three_fdiv_float(float %D, float %a, float %b, float %c) { -; CHECK-SD-LABEL: three_fdiv_float: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: fmov s4, #1.00000000 -; CHECK-SD-NEXT: fdiv s4, s4, s0 -; CHECK-SD-NEXT: fmul s0, s1, s4 -; CHECK-SD-NEXT: fmul s1, s2, s4 -; CHECK-SD-NEXT: fmul s2, s3, s4 -; CHECK-SD-NEXT: b foo_3f -; -; CHECK-GI-LABEL: three_fdiv_float: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: fdiv s4, s1, s0 -; CHECK-GI-NEXT: fdiv s1, s2, s0 -; CHECK-GI-NEXT: fdiv s2, s3, s0 -; CHECK-GI-NEXT: fmov s0, s4 -; CHECK-GI-NEXT: b foo_3f +; CHECK-LABEL: three_fdiv_float: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s4, #1.00000000 +; CHECK-NEXT: fdiv s4, s4, s0 +; CHECK-NEXT: fmul s0, s1, s4 +; CHECK-NEXT: fmul s1, s2, s4 +; CHECK-NEXT: fmul s2, s3, s4 +; CHECK-NEXT: b foo_3f %div = fdiv arcp float %a, %D %div1 = fdiv arcp float %b, %D %div2 = fdiv arcp float %c, %D @@ -36,22 +28,14 @@ define void @three_fdiv_float(float %D, float %a, float %b, float %c) { } define void @three_fdiv_double(double %D, double %a, double %b, double %c) { -; CHECK-SD-LABEL: three_fdiv_double: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: fmov d4, #1.00000000 -; CHECK-SD-NEXT: fdiv d4, d4, d0 -; CHECK-SD-NEXT: fmul d0, d1, d4 -; CHECK-SD-NEXT: fmul d1, d2, d4 -; CHECK-SD-NEXT: fmul d2, d3, d4 -; CHECK-SD-NEXT: b foo_3d -; -; CHECK-GI-LABEL: three_fdiv_double: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: fdiv d4, d1, d0 -; CHECK-GI-NEXT: fdiv d1, d2, d0 -; CHECK-GI-NEXT: fdiv d2, d3, d0 -; CHECK-GI-NEXT: fmov d0, d4 -; CHECK-GI-NEXT: b foo_3d +; CHECK-LABEL: three_fdiv_double: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d4, #1.00000000 +; CHECK-NEXT: fdiv d4, d4, d0 +; CHECK-NEXT: fmul d0, d1, d4 +; CHECK-NEXT: fmul d1, d2, d4 +; CHECK-NEXT: fmul d2, d3, d4 +; CHECK-NEXT: b foo_3d %div = fdiv arcp double %a, %D %div1 = fdiv arcp double %b, %D %div2 = fdiv arcp double %c, %D @@ -60,22 +44,14 @@ define void @three_fdiv_double(double %D, double %a, double %b, double %c) { } define void @three_fdiv_4xfloat(<4 x float> %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) { -; CHECK-SD-LABEL: three_fdiv_4xfloat: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: fmov v4.4s, #1.00000000 -; CHECK-SD-NEXT: fdiv v4.4s, v4.4s, v0.4s -; CHECK-SD-NEXT: fmul v0.4s, v1.4s, v4.4s -; CHECK-SD-NEXT: fmul v1.4s, v2.4s, v4.4s -; CHECK-SD-NEXT: fmul v2.4s, v3.4s, v4.4s -; CHECK-SD-NEXT: b foo_3_4xf -; -; CHECK-GI-LABEL: three_fdiv_4xfloat: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: fdiv v4.4s, v1.4s, v0.4s -; CHECK-GI-NEXT: fdiv v1.4s, v2.4s, v0.4s -; CHECK-GI-NEXT: fdiv v2.4s, v3.4s, v0.4s -; CHECK-GI-NEXT: mov v0.16b, v4.16b -; CHECK-GI-NEXT: b foo_3_4xf +; CHECK-LABEL: three_fdiv_4xfloat: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov v4.4s, #1.00000000 +; CHECK-NEXT: fdiv v4.4s, v4.4s, v0.4s +; CHECK-NEXT: fmul v0.4s, v1.4s, v4.4s +; CHECK-NEXT: fmul v1.4s, v2.4s, v4.4s +; CHECK-NEXT: fmul v2.4s, v3.4s, v4.4s +; CHECK-NEXT: b foo_3_4xf %div = fdiv arcp <4 x float> %a, %D %div1 = fdiv arcp <4 x float> %b, %D %div2 = fdiv arcp <4 x float> %c, %D @@ -84,22 +60,14 @@ define void @three_fdiv_4xfloat(<4 x float> %D, <4 x float> %a, <4 x float> %b, } define void @three_fdiv_2xdouble(<2 x double> %D, <2 x double> %a, <2 x double> %b, <2 x double> %c) { -; CHECK-SD-LABEL: three_fdiv_2xdouble: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: fmov v4.2d, #1.00000000 -; CHECK-SD-NEXT: fdiv v4.2d, v4.2d, v0.2d -; CHECK-SD-NEXT: fmul v0.2d, v1.2d, v4.2d -; CHECK-SD-NEXT: fmul v1.2d, v2.2d, v4.2d -; CHECK-SD-NEXT: fmul v2.2d, v3.2d, v4.2d -; CHECK-SD-NEXT: b foo_3_2xd -; -; CHECK-GI-LABEL: three_fdiv_2xdouble: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: fdiv v4.2d, v1.2d, v0.2d -; CHECK-GI-NEXT: fdiv v1.2d, v2.2d, v0.2d -; CHECK-GI-NEXT: fdiv v2.2d, v3.2d, v0.2d -; CHECK-GI-NEXT: mov v0.16b, v4.16b -; CHECK-GI-NEXT: b foo_3_2xd +; CHECK-LABEL: three_fdiv_2xdouble: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov v4.2d, #1.00000000 +; CHECK-NEXT: fdiv v4.2d, v4.2d, v0.2d +; CHECK-NEXT: fmul v0.2d, v1.2d, v4.2d +; CHECK-NEXT: fmul v1.2d, v2.2d, v4.2d +; CHECK-NEXT: fmul v2.2d, v3.2d, v4.2d +; CHECK-NEXT: b foo_3_2xd %div = fdiv arcp <2 x double> %a, %D %div1 = fdiv arcp <2 x double> %b, %D %div2 = fdiv arcp <2 x double> %c, %D @@ -135,26 +103,47 @@ define void @two_fdiv_double(double %D, double %a, double %b) { ret void } -define void @splat_three_fdiv_4xfloat(float %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) { -; CHECK-SD-LABEL: splat_three_fdiv_4xfloat: +define void @four_fdiv_multi_float(float %D, float %a, float %b, float %c) #0 { +; CHECK-SD-LABEL: four_fdiv_multi_float: ; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: fmov v4.4s, #1.00000000 -; CHECK-SD-NEXT: dup v0.4s, v0.s[0] -; CHECK-SD-NEXT: fdiv v4.4s, v4.4s, v0.4s -; CHECK-SD-NEXT: fmul v0.4s, v1.4s, v4.4s -; CHECK-SD-NEXT: fmul v1.4s, v2.4s, v4.4s -; CHECK-SD-NEXT: fmul v2.4s, v3.4s, v4.4s -; CHECK-SD-NEXT: b foo_3_4xf +; CHECK-SD-NEXT: fmov s4, #1.00000000 +; CHECK-SD-NEXT: fdiv s5, s4, s0 +; CHECK-SD-NEXT: fmul s4, s1, s5 +; CHECK-SD-NEXT: fmul s1, s2, s5 +; CHECK-SD-NEXT: fmul s2, s3, s5 +; CHECK-SD-NEXT: fmul s3, s0, s5 +; CHECK-SD-NEXT: fmov s0, s4 +; CHECK-SD-NEXT: b foo_4f ; -; CHECK-GI-LABEL: splat_three_fdiv_4xfloat: +; CHECK-GI-LABEL: four_fdiv_multi_float: ; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-GI-NEXT: dup v4.4s, v0.s[0] -; CHECK-GI-NEXT: fdiv v0.4s, v1.4s, v4.4s -; CHECK-GI-NEXT: fdiv v1.4s, v2.4s, v4.4s -; CHECK-GI-NEXT: fdiv v2.4s, v3.4s, v4.4s -; CHECK-GI-NEXT: b foo_3_4xf +; CHECK-GI-NEXT: fmov s4, #1.00000000 +; CHECK-GI-NEXT: fdiv s5, s4, s0 +; CHECK-GI-NEXT: fdiv s4, s0, s0 +; CHECK-GI-NEXT: fmul s0, s1, s5 +; CHECK-GI-NEXT: fmul s1, s2, s5 +; CHECK-GI-NEXT: fmul s2, s3, s5 +; CHECK-GI-NEXT: fmov s3, s4 +; CHECK-GI-NEXT: b foo_4f + %div = fdiv arcp float %a, %D + %div1 = fdiv arcp float %b, %D + %div2 = fdiv arcp float %c, %D + %div3 = fdiv arcp float %D, %D + tail call void @foo_4f(float %div, float %div1, float %div2, float %div3) + ret void +} + +define void @splat_three_fdiv_4xfloat(float %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) { +; CHECK-LABEL: splat_three_fdiv_4xfloat: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-NEXT: fmov v4.4s, #1.00000000 +; CHECK-NEXT: dup v0.4s, v0.s[0] +; CHECK-NEXT: fdiv v4.4s, v4.4s, v0.4s +; CHECK-NEXT: fmul v0.4s, v1.4s, v4.4s +; CHECK-NEXT: fmul v1.4s, v2.4s, v4.4s +; CHECK-NEXT: fmul v2.4s, v3.4s, v4.4s +; CHECK-NEXT: b foo_3_4xf %D.ins = insertelement <4 x float> poison, float %D, i64 0 %splat = shufflevector <4 x float> %D.ins, <4 x float> poison, <4 x i32> zeroinitializer %div = fdiv arcp <4 x float> %a, %splat @@ -256,6 +245,7 @@ entry: } declare void @foo_3f(float, float, float) +declare void @foo_4f(float, float, float, float) declare void @foo_3d(double, double, double) declare void @foo_3_4xf(<4 x float>, <4 x float>, <4 x float>) declare void @foo_3_2xd(<2 x double>, <2 x double>, <2 x double>) diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll b/llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll index 594a3ab..be07978 100644 --- a/llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll @@ -38,10 +38,10 @@ define half @add_v2HalfH(<2 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: add_v2HalfH: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #32768 // =0x8000 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI1_0 ; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-GI-NOFP16-NEXT: fcvt s2, h0 -; CHECK-GI-NOFP16-NEXT: fmov s1, w8 +; CHECK-GI-NOFP16-NEXT: ldr h1, [x8, :lo12:.LCPI1_0] ; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[1] ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 ; CHECK-GI-NOFP16-NEXT: fcvt s0, h0 @@ -88,10 +88,10 @@ define half @add_v3HalfH(<3 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: add_v3HalfH: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #32768 // =0x8000 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI2_0 ; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-GI-NOFP16-NEXT: fcvt s2, h0 -; CHECK-GI-NOFP16-NEXT: fmov s1, w8 +; CHECK-GI-NOFP16-NEXT: ldr h1, [x8, :lo12:.LCPI2_0] ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 ; CHECK-GI-NOFP16-NEXT: fadd s1, s1, s2 ; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1] @@ -152,10 +152,10 @@ define half @add_HalfH(<4 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: add_HalfH: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #32768 // =0x8000 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI3_0 ; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-GI-NOFP16-NEXT: fcvt s2, h0 -; CHECK-GI-NOFP16-NEXT: fmov s1, w8 +; CHECK-GI-NOFP16-NEXT: ldr h1, [x8, :lo12:.LCPI3_0] ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 ; CHECK-GI-NOFP16-NEXT: fadd s1, s1, s2 ; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1] @@ -250,9 +250,9 @@ define half @add_H(<8 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: add_H: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #32768 // =0x8000 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI4_0 ; CHECK-GI-NOFP16-NEXT: fcvt s2, h0 -; CHECK-GI-NOFP16-NEXT: fmov s1, w8 +; CHECK-GI-NOFP16-NEXT: ldr h1, [x8, :lo12:.LCPI4_0] ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 ; CHECK-GI-NOFP16-NEXT: fadd s1, s1, s2 ; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1] @@ -448,9 +448,9 @@ define half @add_2H(<16 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: add_2H: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #32768 // =0x8000 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI7_0 ; CHECK-GI-NOFP16-NEXT: fcvt s3, h0 -; CHECK-GI-NOFP16-NEXT: fmov s2, w8 +; CHECK-GI-NOFP16-NEXT: ldr h2, [x8, :lo12:.LCPI7_0] ; CHECK-GI-NOFP16-NEXT: fcvt s2, h2 ; CHECK-GI-NOFP16-NEXT: fadd s2, s2, s3 ; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[1] diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll b/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll index 18f463c..40925da 100644 --- a/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll @@ -405,26 +405,23 @@ define half @fadd_reduction_v4f16_in_loop(ptr %ptr.start) { ; ; CHECK-GI-NOFP16-LABEL: fadd_reduction_v4f16_in_loop: ; CHECK-GI-NOFP16: // %bb.0: // %entry +; CHECK-GI-NOFP16-NEXT: movi d0, #0000000000000000 ; CHECK-GI-NOFP16-NEXT: mov x8, xzr -; CHECK-GI-NOFP16-NEXT: mov w9, #0 // =0x0 ; CHECK-GI-NOFP16-NEXT: .LBB13_1: // %loop ; CHECK-GI-NOFP16-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-GI-NOFP16-NEXT: ldr d0, [x0, x8] -; CHECK-GI-NOFP16-NEXT: fmov s1, w9 +; CHECK-GI-NOFP16-NEXT: ldr d1, [x0, x8] +; CHECK-GI-NOFP16-NEXT: fcvt s0, h0 ; CHECK-GI-NOFP16-NEXT: add x8, x8, #8 ; CHECK-GI-NOFP16-NEXT: cmp w8, #56 -; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h +; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h +; CHECK-GI-NOFP16-NEXT: faddp v1.4s, v1.4s, v1.4s +; CHECK-GI-NOFP16-NEXT: faddp s1, v1.2s +; CHECK-GI-NOFP16-NEXT: fcvt h1, s1 ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 -; CHECK-GI-NOFP16-NEXT: faddp v0.4s, v0.4s, v0.4s -; CHECK-GI-NOFP16-NEXT: faddp s0, v0.2s -; CHECK-GI-NOFP16-NEXT: fcvt h0, s0 -; CHECK-GI-NOFP16-NEXT: fcvt s0, h0 -; CHECK-GI-NOFP16-NEXT: fadd s0, s0, s1 +; CHECK-GI-NOFP16-NEXT: fadd s0, s1, s0 ; CHECK-GI-NOFP16-NEXT: fcvt h0, s0 -; CHECK-GI-NOFP16-NEXT: fmov w9, s0 ; CHECK-GI-NOFP16-NEXT: b.ne .LBB13_1 ; CHECK-GI-NOFP16-NEXT: // %bb.2: // %exit -; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0 ; CHECK-GI-NOFP16-NEXT: ret ; ; CHECK-GI-FP16-LABEL: fadd_reduction_v4f16_in_loop: @@ -521,28 +518,25 @@ define half @fadd_reduction_v8f16_in_loop(ptr %ptr.start) { ; ; CHECK-GI-NOFP16-LABEL: fadd_reduction_v8f16_in_loop: ; CHECK-GI-NOFP16: // %bb.0: // %entry +; CHECK-GI-NOFP16-NEXT: movi d0, #0000000000000000 ; CHECK-GI-NOFP16-NEXT: mov x8, xzr -; CHECK-GI-NOFP16-NEXT: mov w9, #0 // =0x0 ; CHECK-GI-NOFP16-NEXT: .LBB14_1: // %loop ; CHECK-GI-NOFP16-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-GI-NOFP16-NEXT: ldr q0, [x0, x8] +; CHECK-GI-NOFP16-NEXT: ldr q1, [x0, x8] +; CHECK-GI-NOFP16-NEXT: fcvt s0, h0 ; CHECK-GI-NOFP16-NEXT: add x8, x8, #8 ; CHECK-GI-NOFP16-NEXT: cmp w8, #56 -; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h -; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h -; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v1.4s, v0.4s -; CHECK-GI-NOFP16-NEXT: fmov s1, w9 +; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v1.4h +; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h +; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s +; CHECK-GI-NOFP16-NEXT: faddp v1.4s, v1.4s, v1.4s +; CHECK-GI-NOFP16-NEXT: faddp s1, v1.2s +; CHECK-GI-NOFP16-NEXT: fcvt h1, s1 ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 -; CHECK-GI-NOFP16-NEXT: faddp v0.4s, v0.4s, v0.4s -; CHECK-GI-NOFP16-NEXT: faddp s0, v0.2s -; CHECK-GI-NOFP16-NEXT: fcvt h0, s0 -; CHECK-GI-NOFP16-NEXT: fcvt s0, h0 -; CHECK-GI-NOFP16-NEXT: fadd s0, s0, s1 +; CHECK-GI-NOFP16-NEXT: fadd s0, s1, s0 ; CHECK-GI-NOFP16-NEXT: fcvt h0, s0 -; CHECK-GI-NOFP16-NEXT: fmov w9, s0 ; CHECK-GI-NOFP16-NEXT: b.ne .LBB14_1 ; CHECK-GI-NOFP16-NEXT: // %bb.2: // %exit -; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0 ; CHECK-GI-NOFP16-NEXT: ret ; ; CHECK-GI-FP16-LABEL: fadd_reduction_v8f16_in_loop: diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll index e1b2170..c10d6e9 100644 --- a/llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll @@ -52,10 +52,10 @@ define half @mul_HalfH(<4 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: mul_HalfH: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #15360 // =0x3c00 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI1_0 ; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-GI-NOFP16-NEXT: fcvt s2, h0 -; CHECK-GI-NOFP16-NEXT: fmov s1, w8 +; CHECK-GI-NOFP16-NEXT: ldr h1, [x8, :lo12:.LCPI1_0] ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 ; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2 ; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1] @@ -144,9 +144,9 @@ define half @mul_H(<8 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: mul_H: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #15360 // =0x3c00 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI2_0 ; CHECK-GI-NOFP16-NEXT: fcvt s2, h0 -; CHECK-GI-NOFP16-NEXT: fmov s1, w8 +; CHECK-GI-NOFP16-NEXT: ldr h1, [x8, :lo12:.LCPI2_0] ; CHECK-GI-NOFP16-NEXT: fcvt s1, h1 ; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2 ; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1] @@ -321,9 +321,9 @@ define half @mul_2H(<16 x half> %bin.rdx) { ; ; CHECK-GI-NOFP16-LABEL: mul_2H: ; CHECK-GI-NOFP16: // %bb.0: -; CHECK-GI-NOFP16-NEXT: mov w8, #15360 // =0x3c00 +; CHECK-GI-NOFP16-NEXT: adrp x8, .LCPI5_0 ; CHECK-GI-NOFP16-NEXT: fcvt s3, h0 -; CHECK-GI-NOFP16-NEXT: fmov s2, w8 +; CHECK-GI-NOFP16-NEXT: ldr h2, [x8, :lo12:.LCPI5_0] ; CHECK-GI-NOFP16-NEXT: fcvt s2, h2 ; CHECK-GI-NOFP16-NEXT: fmul s2, s2, s3 ; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[1] diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll index 664dfa2..2ad6e68 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll @@ -1,103 +1,166 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals all --version 4 ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -passes=amdgpu-attributor %s | FileCheck %s +; Shrink result attribute list by preventing use of most attributes. +define internal void @use_most() { +; CHECK-LABEL: define internal void @use_most( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [256 x i8], align 1, addrspace(5) +; CHECK-NEXT: [[ALLOCA_CAST:%.*]] = addrspacecast ptr addrspace(5) [[ALLOCA]] to ptr +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() +; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() +; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() +; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.cluster.id.x() +; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.cluster.id.y() +; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.amdgcn.cluster.id.z() +; CHECK-NEXT: [[TMP7:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() +; CHECK-NEXT: [[TMP8:%.*]] = call ptr addrspace(4) @llvm.amdgcn.queue.ptr() +; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.dispatch.id() +; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; CHECK-NEXT: [[IMPLICIT_ARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() +; CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr [[ALLOCA_CAST]], ptr addrspace(4) [[IMPLICIT_ARG_PTR]], i64 256, i1 false) +; CHECK-NEXT: ret void +; + %alloca = alloca [256 x i8], addrspace(5) + %alloca.cast = addrspacecast ptr addrspace(5) %alloca to ptr + call i32 @llvm.amdgcn.workitem.id.x() + call i32 @llvm.amdgcn.workitem.id.y() + call i32 @llvm.amdgcn.workitem.id.z() + call i32 @llvm.amdgcn.workgroup.id.x() + call i32 @llvm.amdgcn.workgroup.id.y() + call i32 @llvm.amdgcn.workgroup.id.z() + call i32 @llvm.amdgcn.cluster.id.x() + call i32 @llvm.amdgcn.cluster.id.y() + call i32 @llvm.amdgcn.cluster.id.z() + call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() + call ptr addrspace(4) @llvm.amdgcn.queue.ptr() + call i64 @llvm.amdgcn.dispatch.id() + call i32 @llvm.amdgcn.lds.kernel.id() + %implicit.arg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() + call void @llvm.memcpy.p0.p4(ptr %alloca.cast, ptr addrspace(4) %implicit.arg.ptr, i64 256, i1 false) + ret void +} + define amdgpu_kernel void @kernel_uses_asm_virtreg() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg( -; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "a"(i32 poison) + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_asm_virtreg_def() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: [[DEF:%.*]] = call i32 asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %def = call i32 asm sideeffect "; def $0", "=a"() + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: [[DEF:%.*]] = call i64 asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %def = call i64 asm sideeffect "; def $0", "={a[0:1]}"() + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_asm_virtreg_second_arg() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_second_arg( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "v,a"(i32 poison, i32 poison) + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_non_agpr_asm() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_non_agpr_asm( -; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "v"(i32 poison) + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_asm_physreg() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "{a0}"(i32 poison) + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_asm_physreg_tuple() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_tuple( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "{a[0:1]}"(i64 poison) + call void @use_most() ret void } define void @func_uses_asm_virtreg_agpr() { ; CHECK-LABEL: define void @func_uses_asm_virtreg_agpr( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "a"(i32 poison) + call void @use_most() ret void } define void @func_uses_asm_physreg_agpr() { ; CHECK-LABEL: define void @func_uses_asm_physreg_agpr( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "{a0}"(i32 poison) + call void @use_most() ret void } define void @func_uses_asm_physreg_agpr_tuple() { ; CHECK-LABEL: define void @func_uses_asm_physreg_agpr_tuple( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void asm sideeffect "; use $0", "{a[0:1]}"(i64 poison) + call void @use_most() ret void } @@ -105,99 +168,119 @@ declare void @unknown() define amdgpu_kernel void @kernel_calls_extern() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern( -; CHECK-SAME: ) #[[ATTR2:[0-9]+]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void @unknown() +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @unknown() + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_extern_marked_callsite() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern_marked_callsite( -; CHECK-SAME: ) #[[ATTR2]] { -; CHECK-NEXT: call void @unknown() #[[ATTR6:[0-9]+]] +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void @unknown() #[[ATTR10:[0-9]+]] +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @unknown() #0 + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect( -; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] { +; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR1]] { ; CHECK-NEXT: call void [[INDIRECT]]() +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void %indirect() + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(ptr %indirect) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect_marked_callsite( -; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] { -; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR6]] +; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR10]] +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void %indirect() #0 + call void @use_most() ret void } define amdgpu_kernel void @kernel_transitively_uses_agpr_asm() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_transitively_uses_agpr_asm( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void @func_uses_asm_physreg_agpr() +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @func_uses_asm_physreg_agpr() + call void @use_most() ret void } define void @empty() { ; CHECK-LABEL: define void @empty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; + call void @use_most() ret void } define void @also_empty() { ; CHECK-LABEL: define void @also_empty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_empty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_empty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: call void @empty() +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @empty() + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_non_agpr_and_agpr() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_non_agpr_and_agpr( -; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-SAME: ) #[[ATTR1]] { ; CHECK-NEXT: call void @empty() ; CHECK-NEXT: call void @func_uses_asm_physreg_agpr() +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @empty() call void @func_uses_asm_physreg_agpr() + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_generic_intrinsic(ptr %ptr0, ptr %ptr1, i64 %size) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_generic_intrinsic( -; CHECK-SAME: ptr [[PTR0:%.*]], ptr [[PTR1:%.*]], i64 [[SIZE:%.*]]) #[[ATTR1]] { +; CHECK-SAME: ptr [[PTR0:%.*]], ptr [[PTR1:%.*]], i64 [[SIZE:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr [[PTR0]], ptr [[PTR1]], i64 [[SIZE]], i1 false) +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @llvm.memcpy.p0.p0.i64(ptr %ptr0, ptr %ptr1, i64 %size, i1 false) + call void @use_most() ret void } @@ -205,31 +288,35 @@ declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float> define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %out, float %a, float %b, <32 x float> %c) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32( -; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]], <32 x float> [[C:%.*]]) #[[ATTR1]] { +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]], <32 x float> [[C:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[RESULT:%.*]] = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float [[A]], float [[B]], <32 x float> [[C]], i32 0, i32 0, i32 0) ; CHECK-NEXT: store <32 x float> [[RESULT]], ptr addrspace(1) [[OUT]], align 128 +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %result = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %a, float %b, <32 x float> %c, i32 0, i32 0, i32 0) store <32 x float> %result, ptr addrspace(1) %out + call void @use_most() ret void } define amdgpu_kernel void @kernel_calls_workitem_id_x(ptr addrspace(1) %out) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_workitem_id_x( -; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]]) #[[ATTR1]] { +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() ; CHECK-NEXT: store i32 [[RESULT]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %result = call i32 @llvm.amdgcn.workitem.id.x() store i32 %result, ptr addrspace(1) %out + call void @use_most() ret void } define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) { ; CHECK-LABEL: define amdgpu_kernel void @indirect_calls_none_agpr( -; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR1]] { ; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty ; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] @@ -244,21 +331,476 @@ define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) { ; CHECK: 5: ; CHECK-NEXT: unreachable ; CHECK: 6: +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %fptr = select i1 %cond, ptr @empty, ptr @also_empty call void %fptr() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_def_struct_0() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_struct_0( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call { i32, i32 } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call {i32, i32} asm sideeffect "; def $0", "=a,=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_1() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_1( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call { i32, <2 x i32> } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call {i32, <2 x i32>} asm sideeffect "; def $0", "=a,=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_2() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_2( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call { i32, <2 x i32> } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call {i32, <2 x i32>} asm sideeffect "; def $0", "=a,=v"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_ptr_ty() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_ptr_ty( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(ptr poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_def_ptr_ty() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_ptr_ty( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call ptr asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call ptr asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_def_vector_ptr_ty() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_vector_ptr_ty( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call <2 x ptr> asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call <2 x ptr> asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_physreg_def_struct_0() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_def_struct_0( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call { i32, i32 } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call {i32, i32} asm sideeffect "; def $0", "={a0},={a[4:5]}"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_clobber() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; clobber $0", "~{a4}"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_clobber_tuple() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber_tuple( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; clobber $0", "~{a[10:13]}"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_clobber_oob() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber_oob( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; clobber $0", "~{a256}"() + call void @use_most() ret void } +define amdgpu_kernel void @kernel_uses_asm_clobber_max() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber_max( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; clobber $0", "~{a255}"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_physreg_oob() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_oob( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "{a256}"(i32 poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_def_max_ty() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_max_ty( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call <32 x i32> asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call <32 x i32> asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_use_max_ty() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_max_ty( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(<32 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_asm_virtreg_use_def_max_ty() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_def_max_ty( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call <32 x i32> asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call <32 x i32> asm sideeffect "; use $0", "=a,a"(<32 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @vreg_use_exceeds_register_file() { +; CHECK-LABEL: define amdgpu_kernel void @vreg_use_exceeds_register_file( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(<257 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @vreg_def_exceeds_register_file() { +; CHECK-LABEL: define amdgpu_kernel void @vreg_def_exceeds_register_file( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call <257 x i32> asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call <257 x i32> asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @multiple() { +; CHECK-LABEL: define amdgpu_kernel void @multiple( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call { <16 x i32>, <8 x i32>, <8 x i32> } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call {<16 x i32>, <8 x i32>, <8 x i32>} asm sideeffect "; def $0", "=a,=a,=a,a,a,a"(<4 x i32> splat (i32 0), <8 x i32> splat (i32 1), i64 999) + call void @use_most() + ret void +} + +define amdgpu_kernel void @earlyclobber_0() { +; CHECK-LABEL: define amdgpu_kernel void @earlyclobber_0( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call <8 x i32> asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call <8 x i32> asm sideeffect "; def $0", "=&a,a"(i32 0) + call void @use_most() + ret void +} + +define amdgpu_kernel void @earlyclobber_1() { +; CHECK-LABEL: define amdgpu_kernel void @earlyclobber_1( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[DEF:%.*]] = call { <8 x i32>, <16 x i32> } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %def = call { <8 x i32>, <16 x i32 > } asm sideeffect "; def $0, $1", "=&a,=&a,a,a"(i32 0, <16 x i32> splat (i32 1)) + call void @use_most() + ret void +} + +define amdgpu_kernel void @physreg_a32__vreg_a256__vreg_a512() { +; CHECK-LABEL: define amdgpu_kernel void @physreg_a32__vreg_a256__vreg_a512( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1, $2", "{a16},a,a"(i32 poison, <8 x i32> poison, <16 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @physreg_def_a32__def_vreg_a256__def_vreg_a512() { +; CHECK-LABEL: define amdgpu_kernel void @physreg_def_a32__def_vreg_a256__def_vreg_a512( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[TMP1:%.*]] = call { i32, <8 x i32>, <16 x i32> } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call {i32, <8 x i32>, <16 x i32>} asm sideeffect "; def $0, $1, $2", "={a16},=a,=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @physreg_def_a32___def_vreg_a512_use_vreg_a256() { +; CHECK-LABEL: define amdgpu_kernel void @physreg_def_a32___def_vreg_a512_use_vreg_a256( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: [[TMP1:%.*]] = call { i32, <16 x i32> } asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call {i32, <16 x i32>} asm sideeffect "; def $0, $1, $2", "={a16},=a,a"(<8 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @mixed_physreg_vreg_tuples_0() { +; CHECK-LABEL: define amdgpu_kernel void @mixed_physreg_vreg_tuples_0( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "{a[1:4]},a"(<4 x i32> poison, <4 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @mixed_physreg_vreg_tuples_1() { +; CHECK-LABEL: define amdgpu_kernel void @mixed_physreg_vreg_tuples_1( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "a,{a[0:3]}"(<4 x i32> poison, <4 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @physreg_raises_limit() { +; CHECK-LABEL: define amdgpu_kernel void @physreg_raises_limit( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "a,{a[5:8]}"(<4 x i32> poison, <4 x i32> poison) + call void @use_most() + ret void +} + +; FIXME: This should require 9. We cannot allocate an a128 at a0. +define amdgpu_kernel void @physreg_tuple_alignment_raises_limit() { +; CHECK-LABEL: define amdgpu_kernel void @physreg_tuple_alignment_raises_limit( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "a,{a[1:4]}"(<4 x i32> poison, <4 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @align3_virtreg() { +; CHECK-LABEL: define amdgpu_kernel void @align3_virtreg( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "a,a"(<3 x i32> poison, <3 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @align3_align4_virtreg() { +; CHECK-LABEL: define amdgpu_kernel void @align3_align4_virtreg( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "a,a"(<3 x i32> poison, <4 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @align2_align4_virtreg() { +; CHECK-LABEL: define amdgpu_kernel void @align2_align4_virtreg( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0, $1", "a,a"(<2 x i32> poison, <4 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_write_register_a55() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_a55( +; CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +; CHECK-NEXT: call void @llvm.write_register.i32(metadata [[META0:![0-9]+]], i32 0) +; CHECK-NEXT: ret void +; + call void @llvm.write_register.i64(metadata !0, i32 0) + ret void +} + +define amdgpu_kernel void @kernel_uses_write_register_v55() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_v55( +; CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +; CHECK-NEXT: call void @llvm.write_register.i32(metadata [[META1:![0-9]+]], i32 0) +; CHECK-NEXT: ret void +; + call void @llvm.write_register.i64(metadata !1, i32 0) + ret void +} + +define amdgpu_kernel void @kernel_uses_write_register_a55_57() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_a55_57( +; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-NEXT: call void @llvm.write_register.i96(metadata [[META2:![0-9]+]], i96 0) +; CHECK-NEXT: ret void +; + call void @llvm.write_register.i64(metadata !2, i96 0) + ret void +} + +define amdgpu_kernel void @kernel_uses_read_register_a55(ptr addrspace(1) %ptr) { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_read_register_a55( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: [[REG:%.*]] = call i32 @llvm.read_register.i32(metadata [[META0]]) +; CHECK-NEXT: store i32 [[REG]], ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: ret void +; + %reg = call i32 @llvm.read_register.i64(metadata !0) + store i32 %reg, ptr addrspace(1) %ptr + ret void +} + +define amdgpu_kernel void @kernel_uses_read_volatile_register_a55(ptr addrspace(1) %ptr) { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_read_volatile_register_a55( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: [[REG:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META0]]) +; CHECK-NEXT: store i32 [[REG]], ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: ret void +; + %reg = call i32 @llvm.read_volatile_register.i64(metadata !0) + store i32 %reg, ptr addrspace(1) %ptr + ret void +} + +define amdgpu_kernel void @kernel_uses_read_register_a56_59(ptr addrspace(1) %ptr) { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_read_register_a56_59( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: [[REG:%.*]] = call i128 @llvm.read_register.i128(metadata [[META3:![0-9]+]]) +; CHECK-NEXT: store i128 [[REG]], ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: ret void +; + %reg = call i128 @llvm.read_register.i64(metadata !3) + store i128 %reg, ptr addrspace(1) %ptr + ret void +} + +define amdgpu_kernel void @kernel_uses_write_register_out_of_bounds_a256() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_out_of_bounds_a256( +; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-NEXT: call void @llvm.write_register.i32(metadata [[META4:![0-9]+]], i32 0) +; CHECK-NEXT: ret void +; + call void @llvm.write_register.i64(metadata !4, i32 0) + ret void +} attributes #0 = { "amdgpu-agpr-alloc"="0" } + +!0 = !{!"a55"} +!1 = !{!"v55"} +!2 = !{!"a[55:57]"} +!3 = !{!"a[56:59]"} +!4 = !{!"a256"} + +;. +; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(read) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR8:[0-9]+]] = { nounwind "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR9:[0-9]+]] = { nocallback nounwind "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR10]] = { "amdgpu-agpr-alloc"="0" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR2:[0-9]+]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="0" } +; CHECK: [[META0]] = !{!"a55"} +; CHECK: [[META1]] = !{!"v55"} +; CHECK: [[META2]] = !{!"a[55:57]"} +; CHECK: [[META3]] = !{!"a[56:59]"} +; CHECK: [[META4]] = !{!"a256"} ;. diff --git a/llvm/test/CodeGen/AMDGPU/fsub.ll b/llvm/test/CodeGen/AMDGPU/fsub.ll index 743431c..d6a9cb1 100644 --- a/llvm/test/CodeGen/AMDGPU/fsub.ll +++ b/llvm/test/CodeGen/AMDGPU/fsub.ll @@ -92,43 +92,11 @@ define amdgpu_kernel void @v_fneg_fsub_nsz_f32(ptr addrspace(1) %out, ptr addrsp ret void } -; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_attribute_f32: -; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} -; SI-NOT: xor -define amdgpu_kernel void @v_fneg_fsub_nsz_attribute_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { - %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 1 - %a = load float, ptr addrspace(1) %in, align 4 - %b = load float, ptr addrspace(1) %b_ptr, align 4 - %result = fsub float %a, %b - %neg.result = fsub float -0.0, %result - store float %neg.result, ptr addrspace(1) %out, align 4 - ret void -} - -; For some reason the attribute has a string "true" or "false", so -; make sure it is disabled and the fneg is not folded if it is not -; "true". -; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_false_attribute_f32: -; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} -; SI: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]] -define amdgpu_kernel void @v_fneg_fsub_nsz_false_attribute_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #1 { - %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 1 - %a = load float, ptr addrspace(1) %in, align 4 - %b = load float, ptr addrspace(1) %b_ptr, align 4 - %result = fsub float %a, %b - %neg.result = fsub float -0.0, %result - store float %neg.result, ptr addrspace(1) %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}v_fsub_0_nsz_attribute_f32: +; FUNC-LABEL: {{^}}v_fsub_0_nsz_flag_f32: ; SI-NOT: v_sub -define amdgpu_kernel void @v_fsub_0_nsz_attribute_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { +define amdgpu_kernel void @v_fsub_0_nsz_flag_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) { %a = load float, ptr addrspace(1) %in, align 4 - %result = fsub float %a, 0.0 + %result = fsub nsz float %a, 0.0 store float %result, ptr addrspace(1) %out, align 4 ret void } - -attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" } -attributes #1 = { nounwind "no-signed-zeros-fp-math"="false" } diff --git a/llvm/test/CodeGen/AMDGPU/mad_int24.ll b/llvm/test/CodeGen/AMDGPU/mad_int24.ll index 93fda94..dd88310 100644 --- a/llvm/test/CodeGen/AMDGPU/mad_int24.ll +++ b/llvm/test/CodeGen/AMDGPU/mad_int24.ll @@ -1,17 +1,79 @@ -; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefix=GCN --check-prefix=FUNC -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefix=GCN --check-prefix=FUNC -; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=amdgcn| FileCheck %s --check-prefixes=GCN +; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=VI +; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG,R600,RW +; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=EG,R600,CM -; FUNC-LABEL: {{^}}i32_mad24: ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. -; EG: MULLO_INT -; CM: MULLO_INT -; GCN: s_bfe_i32 -; GCN: s_bfe_i32 -; GCN: s_mul_i32 -; GCN: s_add_i32 define amdgpu_kernel void @i32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) { +; GCN-LABEL: i32_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000 +; GCN-NEXT: s_bfe_i32 s1, s1, 0x180000 +; GCN-NEXT: s_mul_i32 s0, s0, s1 +; GCN-NEXT: s_add_i32 s0, s0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: i32_mad24: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_bfe_i32 s0, s0, 0x180000 +; VI-NEXT: s_bfe_i32 s1, s1, 0x180000 +; VI-NEXT: s_mul_i32 s0, s0, s1 +; VI-NEXT: s_add_i32 s0, s0, s2 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; VI-NEXT: s_endpgm +; +; RW-LABEL: i32_mad24: +; RW: ; %bb.0: ; %entry +; RW-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] +; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; RW-NEXT: CF_END +; RW-NEXT: PAD +; RW-NEXT: ALU clause starting at 4: +; RW-NEXT: LSHL T0.W, KC0[2].Z, literal.x, +; RW-NEXT: LSHL * T1.W, KC0[2].W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR T1.W, PS, literal.x, +; RW-NEXT: ASHR * T0.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PS, PV.W, +; RW-NEXT: ADD_INT T0.X, PS, KC0[3].X, +; RW-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: i32_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHL T0.Z, KC0[2].Z, literal.x, +; CM-NEXT: LSHL * T0.W, KC0[2].W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR T1.Z, PV.W, literal.x, +; CM-NEXT: ASHR * T0.W, PV.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z, +; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) entry: %0 = shl i32 %a, 8 %a_24 = ashr i32 %0, 8 @@ -23,13 +85,25 @@ entry: ret void } -; GCN-LABEL: {{^}}mad24_known_bits_destroyed: -; GCN: s_waitcnt -; GCN-NEXT: v_mad_i32_i24 -; GCN-NEXT: v_mul_i32_i24 -; GCN-NEXT: s_setpc_b64 define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { - +; GCN-LABEL: mad24_known_bits_destroyed: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mad24_known_bits_destroyed: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: mad24_known_bits_destroyed: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD %shl.0 = shl i32 %a, 8 %sra.0 = ashr i32 %shl.0, 8 %shl.1 = shl i32 %b, 8 @@ -48,12 +122,25 @@ define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { ret i32 %mul1 } -; GCN-LABEL: {{^}}mad24_intrin_known_bits_destroyed: -; GCN: s_waitcnt -; GCN-NEXT: v_mad_i32_i24 -; GCN-NEXT: v_mul_i32_i24 -; GCN-NEXT: s_setpc_b64 define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { +; GCN-LABEL: mad24_intrin_known_bits_destroyed: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mad24_intrin_known_bits_destroyed: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: mad24_intrin_known_bits_destroyed: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD %shl.0 = shl i32 %a, 8 %sra.0 = ashr i32 %shl.0, 8 %shl.1 = shl i32 %b, 8 @@ -73,17 +160,177 @@ define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { } ; Make sure no unnecessary BFEs are emitted in the loop. -; GCN-LABEL: {{^}}mad24_destroyed_knownbits_2: -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe define void @mad24_destroyed_knownbits_2(i32 %arg, i32 %arg1, i32 %arg2, ptr addrspace(1) %arg3) { +; GCN-LABEL: mad24_destroyed_knownbits_2: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, 1 +; GCN-NEXT: s_mov_b64 s[4:5], 0 +; GCN-NEXT: .LBB3_1: ; %bb6 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v5 +; GCN-NEXT: v_add_i32_e32 v1, vcc, -1, v1 +; GCN-NEXT: v_mad_i32_i24 v5, v0, v5, v0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GCN-NEXT: v_mad_i32_i24 v0, v5, v0, v5 +; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v0 +; GCN-NEXT: v_mov_b32_e32 v5, v2 +; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GCN-NEXT: s_cbranch_execnz .LBB3_1 +; GCN-NEXT: ; %bb.2: ; %bb5 +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mad24_destroyed_knownbits_2: +; VI: ; %bb.0: ; %bb +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 1 +; VI-NEXT: s_mov_b64 s[4:5], 0 +; VI-NEXT: .LBB3_1: ; %bb6 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v5 +; VI-NEXT: v_mad_i32_i24 v5, v0, v5, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v1 +; VI-NEXT: v_mad_i32_i24 v0, v5, v0, v5 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v0 +; VI-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; VI-NEXT: v_mov_b32_e32 v5, v2 +; VI-NEXT: s_andn2_b64 exec, exec, s[4:5] +; VI-NEXT: s_cbranch_execnz .LBB3_1 +; VI-NEXT: ; %bb.2: ; %bb5 +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[3:4], v0 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; RW-LABEL: mad24_destroyed_knownbits_2: +; RW: ; %bb.0: ; %bb +; RW-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; RW-NEXT: LOOP_START_DX10 @7 +; RW-NEXT: ALU_PUSH_BEFORE 30, @16, KC0[], KC1[] +; RW-NEXT: JUMP @6 POP:1 +; RW-NEXT: LOOP_BREAK @6 +; RW-NEXT: POP @6 POP:1 +; RW-NEXT: END_LOOP @2 +; RW-NEXT: ALU 1, @47, KC0[], KC1[] +; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; RW-NEXT: CF_END +; RW-NEXT: ALU clause starting at 10: +; RW-NEXT: MOV T0.X, KC0[2].Y, +; RW-NEXT: MOV T0.Y, KC0[2].Z, +; RW-NEXT: MOV * T0.Z, KC0[2].W, +; RW-NEXT: MOV T0.W, KC0[3].X, +; RW-NEXT: MOV * T1.W, literal.x, +; RW-NEXT: 1(1.401298e-45), 0(0.000000e+00) +; RW-NEXT: ALU clause starting at 16: +; RW-NEXT: LSHL T2.W, T1.W, literal.x, +; RW-NEXT: LSHL * T3.W, T0.X, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR T3.W, PS, literal.x, +; RW-NEXT: ASHR * T2.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PV.W, PS, +; RW-NEXT: ADD_INT * T1.W, PS, T1.W, +; RW-NEXT: LSHL * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W, +; RW-NEXT: ADD_INT * T1.W, PS, T1.W, +; RW-NEXT: LSHL * T2.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR * T2.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PV.W, T3.W, +; RW-NEXT: ADD_INT * T1.W, PS, T1.W, +; RW-NEXT: LSHL * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ADD_INT T0.Y, T0.Y, literal.x, +; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W, +; RW-NEXT: -1(nan), 0(0.000000e+00) +; RW-NEXT: ADD_INT T0.X, PS, T1.W, +; RW-NEXT: SETE_INT T2.W, PV.Y, 0.0, +; RW-NEXT: MOV * T1.W, T0.Z, +; RW-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; RW-NEXT: ALU clause starting at 47: +; RW-NEXT: LSHR * T1.X, T0.W, literal.x, +; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: mad24_destroyed_knownbits_2: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @7 +; CM-NEXT: ALU_PUSH_BEFORE 41, @16, KC0[], KC1[] +; CM-NEXT: JUMP @6 POP:1 +; CM-NEXT: LOOP_BREAK @6 +; CM-NEXT: POP @6 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: ALU 1, @58, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T1.X, KC0[2].Y, +; CM-NEXT: MOV T0.X, KC0[2].Z, +; CM-NEXT: MOV T0.Y, KC0[2].W, +; CM-NEXT: MOV T0.Z, KC0[3].X, +; CM-NEXT: MOV * T0.W, literal.x, +; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: LSHL T1.Z, T0.W, literal.x, +; CM-NEXT: LSHL * T1.W, T1.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR T2.Z, PV.W, literal.x, +; CM-NEXT: ASHR * T1.W, PV.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T1.X, T2.Z, T1.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.Z, T1.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.Z, T1.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.Z, T1.W, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W, +; CM-NEXT: LSHL * T2.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR * T2.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W, +; CM-NEXT: LSHL * T1.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR * T1.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T1.X, T1.W, T2.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T1.W, T2.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T1.W, T2.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T1.W, T2.W, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W, +; CM-NEXT: LSHL * T2.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ADD_INT T0.X, T0.X, literal.x, +; CM-NEXT: ASHR * T2.W, PV.W, literal.y, +; CM-NEXT: -1(nan), 8(1.121039e-44) +; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W, +; CM-NEXT: ADD_INT T1.X, PV.X, T0.W, +; CM-NEXT: SETE_INT T1.Z, T0.X, 0.0, +; CM-NEXT: MOV * T0.W, T0.Y, +; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.Z, 0.0, +; CM-NEXT: ALU clause starting at 58: +; CM-NEXT: LSHR * T0.X, T0.Z, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) bb: br label %bb6 @@ -119,3 +366,5 @@ bb6: ; preds = %bb6, %bb } declare i32 @llvm.amdgcn.mul.i24(i32, i32) +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; R600: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/mad_uint24.ll b/llvm/test/CodeGen/AMDGPU/mad_uint24.ll index a6d458e..46b8df4 100644 --- a/llvm/test/CodeGen/AMDGPU/mad_uint24.ll +++ b/llvm/test/CodeGen/AMDGPU/mad_uint24.ll @@ -1,19 +1,75 @@ -; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2 -; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG +; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=CM +; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefixes=GCN +; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX8,SI +; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX8,VI declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone -; FUNC-LABEL: {{^}}u32_mad24: -; EG: MULLO_INT -; SI: s_mul_i32 -; SI: s_add_i32 -; VI: s_mul_{{[iu]}}32 -; VI: s_add_{{[iu]}}32 - define amdgpu_kernel void @u32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) { +; EG-LABEL: u32_mad24: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x, +; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.X, PS, PV.W, +; EG-NEXT: ADD_INT T0.X, PS, KC0[3].X, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: u32_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: AND_INT T0.Z, KC0[2].W, literal.x, +; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z, +; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: u32_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s0, s0, 0xffffff +; GCN-NEXT: s_and_b32 s1, s1, 0xffffff +; GCN-NEXT: s_mul_i32 s0, s0, s1 +; GCN-NEXT: s_add_i32 s0, s0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: u32_mad24: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s0, s0, 0xffffff +; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX8-NEXT: s_mul_i32 s0, s0, s1 +; GFX8-NEXT: s_add_i32 s0, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm entry: %0 = shl i32 %a, 8 %a_24 = lshr i32 %0, 8 @@ -25,18 +81,88 @@ entry: ret void } -; FUNC-LABEL: {{^}}i16_mad24: ; The order of A and B does not matter. -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] ; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 16 -; GCN: s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}} -; GCN: s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}} -; GCN: s_sext_i32_i16 [[EXT:s[0-9]]], [[MAD]] -; GCN: v_mov_b32_e32 v0, [[EXT]] define amdgpu_kernel void @i16_mad24(ptr addrspace(1) %out, i16 %a, i16 %b, i16 %c) { +; EG-LABEL: i16_mad24: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @12, KC0[], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 4, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_16 T1.X, T0.X, 40, #3 +; EG-NEXT: VTX_READ_16 T2.X, T0.X, 42, #3 +; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: MULLO_INT * T0.Y, T1.X, T2.X, +; EG-NEXT: ADD_INT * T0.W, PS, T0.X, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) +; +; CM-LABEL: i16_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 0, @12, KC0[], KC1[] +; CM-NEXT: TEX 2 @6 +; CM-NEXT: ALU 8, @13, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_16 T1.X, T0.X, 40, #3 +; CM-NEXT: VTX_READ_16 T2.X, T0.X, 42, #3 +; CM-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 13: +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Y, T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T1.X, T2.X, +; CM-NEXT: ADD_INT * T0.W, PV.Y, T0.X, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i16_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_load_dword s4, s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s2, 16 +; GCN-NEXT: s_mul_i32 s2, s4, s2 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_sext_i32_i16 s2, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: i16_mad24: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX8-NEXT: s_load_dword s8, s[4:5], 0x2c +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_mov_b32 s4, s0 +; GFX8-NEXT: s_lshr_b32 s0, s2, 16 +; GFX8-NEXT: s_mul_i32 s0, s8, s0 +; GFX8-NEXT: s_add_i32 s0, s0, s3 +; GFX8-NEXT: s_sext_i32_i16 s0, s0 +; GFX8-NEXT: s_mov_b32 s5, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm entry: %0 = mul i16 %a, %b %1 = add i16 %0, %c @@ -46,17 +172,85 @@ entry: } ; FIXME: Need to handle non-uniform case for function below (load without gep). -; FUNC-LABEL: {{^}}i8_mad24: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] ; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; GCN: s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}} -; GCN: s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}} -; GCN: s_sext_i32_i8 [[EXT:s[0-9]]], [[MAD]] -; GCN: v_mov_b32_e32 v0, [[EXT]] define amdgpu_kernel void @i8_mad24(ptr addrspace(1) %out, i8 %a, i8 %b, i8 %c) { +; EG-LABEL: i8_mad24: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @12, KC0[], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 4, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3 +; EG-NEXT: VTX_READ_8 T2.X, T0.X, 41, #3 +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 42, #3 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: MULLO_INT * T0.Y, T1.X, T2.X, +; EG-NEXT: ADD_INT * T0.W, PS, T0.X, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) +; +; CM-LABEL: i8_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 0, @12, KC0[], KC1[] +; CM-NEXT: TEX 2 @6 +; CM-NEXT: ALU 8, @13, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3 +; CM-NEXT: VTX_READ_8 T2.X, T0.X, 41, #3 +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 42, #3 +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 13: +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Y, T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T1.X, T2.X, +; CM-NEXT: ADD_INT * T0.W, PV.Y, T0.X, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i8_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s2, s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s4, s2, 8 +; GCN-NEXT: s_lshr_b32 s5, s2, 16 +; GCN-NEXT: s_mul_i32 s2, s2, s4 +; GCN-NEXT: s_add_i32 s2, s2, s5 +; GCN-NEXT: s_sext_i32_i8 s4, s2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: i8_mad24: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dword s6, s[4:5], 0x2c +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s4, s6, 8 +; GFX8-NEXT: s_lshr_b32 s5, s6, 16 +; GFX8-NEXT: s_mul_i32 s4, s6, s4 +; GFX8-NEXT: s_add_i32 s4, s4, s5 +; GFX8-NEXT: s_sext_i32_i8 s4, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm entry: %0 = mul i8 %a, %b %1 = add i8 %0, %c @@ -72,11 +266,75 @@ entry: ; 24-bit mad pattern wasn't being matched. ; Check that the select instruction is not deleted. -; FUNC-LABEL: {{^}}i24_i32_i32_mad: -; EG: CNDE_INT -; SI: s_cselect -; GCN2: s_cselect define amdgpu_kernel void @i24_i32_i32_mad(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) { +; EG-LABEL: i24_i32_i32_mad: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: ASHR * T0.W, KC0[2].Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W, +; EG-NEXT: 34(4.764415e-44), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.X, PV.W, KC0[3].X, +; EG-NEXT: ADD_INT T0.X, PS, KC0[3].Y, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: i24_i32_i32_mad: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: ASHR * T0.W, KC0[2].Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W, +; CM-NEXT: 34(4.764415e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, KC0[3].X, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, KC0[3].X, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, KC0[3].X, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, KC0[3].X, +; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].Y, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i24_i32_i32_mad: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s2, s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s2, 8 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_cselect_b32 s2, s2, 34 +; GCN-NEXT: s_mul_i32 s2, s2, s6 +; GCN-NEXT: s_add_i32 s4, s2, s7 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: i24_i32_i32_mad: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dword s8, s[4:5], 0x2c +; GFX8-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_ashr_i32 s4, s8, 8 +; GFX8-NEXT: s_cmp_lg_u32 s6, 0 +; GFX8-NEXT: s_cselect_b32 s4, s4, 34 +; GFX8-NEXT: s_mul_i32 s4, s4, s6 +; GFX8-NEXT: s_add_i32 s4, s4, s7 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm entry: %0 = ashr i32 %a, 8 %1 = icmp ne i32 %c, 0 @@ -87,13 +345,139 @@ entry: ret void } -; FUNC-LABEL: {{^}}extra_and: -; SI-NOT: v_and -; SI: s_mul_i32 -; SI: s_mul_i32 -; SI: s_add_i32 -; SI: s_add_i32 define amdgpu_kernel void @extra_and(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) { +; EG-LABEL: extra_and: +; EG: ; %bb.0: ; %bb +; EG-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: LOOP_START_DX10 @7 +; EG-NEXT: ALU_PUSH_BEFORE 12, @16, KC0[], KC1[] +; EG-NEXT: JUMP @6 POP:1 +; EG-NEXT: LOOP_BREAK @6 +; EG-NEXT: POP @6 POP:1 +; EG-NEXT: END_LOOP @2 +; EG-NEXT: ALU 1, @29, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T1.W, literal.x, +; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; EG-NEXT: MOV * T3.W, PV.W, +; EG-NEXT: MOV T0.Z, KC0[2].Y, +; EG-NEXT: MOV T0.W, KC0[2].Z, +; EG-NEXT: MOV * T2.W, KC0[2].W, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: AND_INT T1.W, T1.W, literal.x, +; EG-NEXT: AND_INT * T4.W, T3.W, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: AND_INT T3.W, T3.W, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PS, PV.W, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W, +; EG-NEXT: ADD_INT T3.W, T2.W, PS, +; EG-NEXT: ADD_INT * T1.W, T0.W, T0.X, +; EG-NEXT: ADD_INT * T0.X, PS, PV.W, +; EG-NEXT: SETNE_INT * T4.W, PV.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; EG-NEXT: ALU clause starting at 29: +; EG-NEXT: LSHR * T1.X, T0.Z, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: extra_and: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @7 +; CM-NEXT: ALU_PUSH_BEFORE 17, @16, KC0[], KC1[] +; CM-NEXT: JUMP @6 POP:1 +; CM-NEXT: LOOP_BREAK @6 +; CM-NEXT: POP @6 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: ALU 1, @34, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T0.W, literal.x, +; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; CM-NEXT: MOV * T1.Z, PV.W, +; CM-NEXT: MOV T0.Y, KC0[2].Y, +; CM-NEXT: MOV T0.Z, KC0[2].Z, +; CM-NEXT: MOV * T1.W, KC0[2].W, +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: AND_INT T1.Y, T1.Z, literal.x, +; CM-NEXT: AND_INT T2.Z, T0.W, literal.x, +; CM-NEXT: AND_INT * T0.W, T1.Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT * T0.W, T1.Y, T2.Z, +; CM-NEXT: ADD_INT T1.Z, T1.W, PV.W, +; CM-NEXT: ADD_INT * T0.W, T0.Z, T0.X, +; CM-NEXT: ADD_INT * T0.X, PV.W, PV.Z, +; CM-NEXT: SETNE_INT * T2.W, PV.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; CM-NEXT: ALU clause starting at 34: +; CM-NEXT: LSHR * T1.X, T0.Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: extra_and: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s2, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: .LBB4_1: ; %bb4 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: s_and_b32 s3, s6, 0xffffff +; GCN-NEXT: s_and_b32 s6, s6, 0xffffff +; GCN-NEXT: s_and_b32 s2, s2, 0xffffff +; GCN-NEXT: s_mul_i32 s3, s3, s2 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s2, s0, s3 +; GCN-NEXT: s_add_i32 s6, s1, s6 +; GCN-NEXT: s_add_i32 s3, s2, s6 +; GCN-NEXT: s_cmp_lg_u32 s3, 8 +; GCN-NEXT: s_cbranch_scc1 .LBB4_1 +; GCN-NEXT: ; %bb.2: ; %bb18 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: extra_and: +; GFX8: ; %bb.0: ; %bb +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c +; GFX8-NEXT: s_mov_b32 s2, 0 +; GFX8-NEXT: s_mov_b32 s6, 0 +; GFX8-NEXT: .LBB4_1: ; %bb4 +; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX8-NEXT: s_and_b32 s3, s6, 0xffffff +; GFX8-NEXT: s_and_b32 s6, s6, 0xffffff +; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff +; GFX8-NEXT: s_mul_i32 s3, s3, s2 +; GFX8-NEXT: s_mul_i32 s6, s6, s2 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_add_i32 s2, s0, s3 +; GFX8-NEXT: s_add_i32 s6, s1, s6 +; GFX8-NEXT: s_add_i32 s3, s2, s6 +; GFX8-NEXT: s_cmp_lg_u32 s3, 8 +; GFX8-NEXT: s_cbranch_scc1 .LBB4_1 +; GFX8-NEXT: ; %bb.2: ; %bb18 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm bb: br label %bb4 @@ -119,13 +503,139 @@ bb18: ; preds = %bb4 ret void } -; FUNC-LABEL: {{^}}dont_remove_shift -; SI: s_lshr -; SI: s_mul_i32 -; SI: s_mul_i32 -; SI: s_add_i32 -; SI: s_add_i32 define amdgpu_kernel void @dont_remove_shift(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) { +; EG-LABEL: dont_remove_shift: +; EG: ; %bb.0: ; %bb +; EG-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: LOOP_START_DX10 @7 +; EG-NEXT: ALU_PUSH_BEFORE 12, @16, KC0[], KC1[] +; EG-NEXT: JUMP @6 POP:1 +; EG-NEXT: LOOP_BREAK @6 +; EG-NEXT: POP @6 POP:1 +; EG-NEXT: END_LOOP @2 +; EG-NEXT: ALU 1, @29, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T1.W, literal.x, +; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; EG-NEXT: MOV * T3.W, PV.W, +; EG-NEXT: MOV T0.Z, KC0[2].Y, +; EG-NEXT: MOV T0.W, KC0[2].Z, +; EG-NEXT: MOV * T2.W, KC0[2].W, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: LSHR T1.W, T1.W, literal.x, +; EG-NEXT: LSHR * T4.W, T3.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T3.W, T3.W, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PS, PV.W, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W, +; EG-NEXT: ADD_INT T3.W, T2.W, PS, +; EG-NEXT: ADD_INT * T1.W, T0.W, T0.X, +; EG-NEXT: ADD_INT * T0.X, PS, PV.W, +; EG-NEXT: SETNE_INT * T4.W, PV.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; EG-NEXT: ALU clause starting at 29: +; EG-NEXT: LSHR * T1.X, T0.Z, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: dont_remove_shift: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @7 +; CM-NEXT: ALU_PUSH_BEFORE 17, @16, KC0[], KC1[] +; CM-NEXT: JUMP @6 POP:1 +; CM-NEXT: LOOP_BREAK @6 +; CM-NEXT: POP @6 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: ALU 1, @34, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T0.W, literal.x, +; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; CM-NEXT: MOV * T1.Z, PV.W, +; CM-NEXT: MOV T0.Y, KC0[2].Y, +; CM-NEXT: MOV T0.Z, KC0[2].Z, +; CM-NEXT: MOV * T1.W, KC0[2].W, +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: LSHR T1.Y, T1.Z, literal.x, +; CM-NEXT: LSHR T2.Z, T0.W, literal.x, +; CM-NEXT: LSHR * T0.W, T1.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT * T0.W, T1.Y, T2.Z, +; CM-NEXT: ADD_INT T1.Z, T1.W, PV.W, +; CM-NEXT: ADD_INT * T0.W, T0.Z, T0.X, +; CM-NEXT: ADD_INT * T0.X, PV.W, PV.Z, +; CM-NEXT: SETNE_INT * T2.W, PV.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; CM-NEXT: ALU clause starting at 34: +; CM-NEXT: LSHR * T1.X, T0.Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: dont_remove_shift: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s2, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: .LBB5_1: ; %bb4 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: s_lshr_b32 s3, s6, 8 +; GCN-NEXT: s_lshr_b32 s6, s6, 8 +; GCN-NEXT: s_lshr_b32 s2, s2, 8 +; GCN-NEXT: s_mul_i32 s3, s3, s2 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s2, s0, s3 +; GCN-NEXT: s_add_i32 s6, s1, s6 +; GCN-NEXT: s_add_i32 s3, s2, s6 +; GCN-NEXT: s_cmp_lg_u32 s3, 8 +; GCN-NEXT: s_cbranch_scc1 .LBB5_1 +; GCN-NEXT: ; %bb.2: ; %bb18 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: dont_remove_shift: +; GFX8: ; %bb.0: ; %bb +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c +; GFX8-NEXT: s_mov_b32 s2, 0 +; GFX8-NEXT: s_mov_b32 s6, 0 +; GFX8-NEXT: .LBB5_1: ; %bb4 +; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX8-NEXT: s_lshr_b32 s3, s6, 8 +; GFX8-NEXT: s_lshr_b32 s6, s6, 8 +; GFX8-NEXT: s_lshr_b32 s2, s2, 8 +; GFX8-NEXT: s_mul_i32 s3, s3, s2 +; GFX8-NEXT: s_mul_i32 s6, s6, s2 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_add_i32 s2, s0, s3 +; GFX8-NEXT: s_add_i32 s6, s1, s6 +; GFX8-NEXT: s_add_i32 s3, s2, s6 +; GFX8-NEXT: s_cmp_lg_u32 s3, 8 +; GFX8-NEXT: s_cbranch_scc1 .LBB5_1 +; GFX8-NEXT: ; %bb.2: ; %bb18 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm bb: br label %bb4 @@ -151,19 +661,234 @@ bb18: ; preds = %bb4 ret void } -; FUNC-LABEL: {{^}}i8_mad_sat_16: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16 -; SI: v_med3_i32 v{{[0-9]}}, [[EXT]], -; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; VI: v_max_i16_e32 [[MAX:v[0-9]]], 0xff80, [[MAD]] -; VI: v_min_i16_e32 {{v[0-9]}}, 0x7f, [[MAX]] define amdgpu_kernel void @i8_mad_sat_16(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(5) %idx) { +; EG-LABEL: i8_mad_sat_16: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 24, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_8 T3.X, T3.X, 0, #1 +; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X, +; EG-NEXT: ALU clause starting at 19: +; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X, +; EG-NEXT: ADD_INT * T3.X, KC0[3].X, T0.X, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T1.W, T3.X, 0.0, literal.x, +; EG-NEXT: MULLO_INT * T0.Y, PV.Z, PV.W, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PS, PV.W, +; EG-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: MAX_INT T0.W, PV.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, T0.X, +; EG-NEXT: -128(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PS, literal.x, +; EG-NEXT: MIN_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 3(4.203895e-45), 127(1.779649e-43) +; EG-NEXT: AND_INT T0.W, PS, literal.x, +; EG-NEXT: LSHL * T2.W, PV.W, literal.y, +; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45) +; EG-NEXT: LSHL T0.X, PV.W, PS, +; EG-NEXT: LSHL * T0.W, literal.x, PS, +; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; EG-NEXT: MOV T0.Y, 0.0, +; EG-NEXT: MOV * T0.Z, 0.0, +; EG-NEXT: LSHR * T1.X, T1.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: i8_mad_sat_16: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 26, @21, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT MSKOR T1.XW, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_8 T3.X, T3.X, 0, #1 +; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X, +; CM-NEXT: ALU clause starting at 19: +; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X, +; CM-NEXT: ADD_INT * T3.X, KC0[2].Z, T0.X, +; CM-NEXT: ALU clause starting at 21: +; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x, +; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: BFE_INT * T0.W, T3.X, 0.0, literal.x, BS:VEC_201 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Z, T0.W, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.Z, T0.W, +; CM-NEXT: MULLO_INT T0.Z, T0.Z, T0.W, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Z, T0.W, +; CM-NEXT: ADD_INT * T0.W, PV.Z, T0.Y, +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: MAX_INT T0.Z, PV.W, literal.x, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.X, +; CM-NEXT: -128(nan), 0(0.000000e+00) +; CM-NEXT: AND_INT T1.Z, PV.W, literal.x, +; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.y, +; CM-NEXT: 3(4.203895e-45), 127(1.779649e-43) +; CM-NEXT: AND_INT T0.Z, PV.W, literal.x, +; CM-NEXT: LSHL * T1.W, PV.Z, literal.y, +; CM-NEXT: 255(3.573311e-43), 3(4.203895e-45) +; CM-NEXT: LSHL T1.X, PV.Z, PV.W, +; CM-NEXT: LSHL * T1.W, literal.x, PV.W, +; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; CM-NEXT: MOV T1.Y, 0.0, +; CM-NEXT: MOV * T1.Z, 0.0, +; CM-NEXT: LSHR * T0.X, T0.W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i8_mad_sat_16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0 +; GCN-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1 +; GCN-NEXT: s_mov_b32 s22, -1 +; GCN-NEXT: s_mov_b32 s23, 0xe8f000 +; GCN-NEXT: s_add_u32 s20, s20, s11 +; GCN-NEXT: s_addc_u32 s21, s21, 0 +; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s9, s8, 4 +; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: buffer_load_dword v1, v1, s[20:23], 0 offen +; GCN-NEXT: buffer_load_dword v0, v0, s[20:23], 0 offen +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, 0 +; GCN-NEXT: s_mov_b64 s[14:15], s[10:11] +; GCN-NEXT: s_mov_b64 s[18:19], s[10:11] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[8:9], s[2:3] +; GCN-NEXT: s_mov_b64 s[12:13], s[4:5] +; GCN-NEXT: s_mov_b64 s[16:17], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[8:11], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v4, v[0:1], s[16:19], 0 addr64 +; GCN-NEXT: s_movk_i32 s2, 0xff80 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mad_u32_u24 v2, v2, v3, v4 +; GCN-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GCN-NEXT: v_mov_b32_e32 v3, 0x7f +; GCN-NEXT: v_med3_i32 v2, v2, s2, v3 +; GCN-NEXT: s_mov_b64 s[2:3], s[10:11] +; GCN-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 +; GCN-NEXT: s_endpgm +; +; SI-LABEL: i8_mad_sat_16: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0 +; SI-NEXT: s_load_dword s0, s[4:5], 0x44 +; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1 +; SI-NEXT: s_mov_b32 s90, -1 +; SI-NEXT: s_mov_b32 s91, 0xe80000 +; SI-NEXT: s_add_u32 s88, s88, s11 +; SI-NEXT: s_addc_u32 s89, s89, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_add_i32 s1, s0, 4 +; SI-NEXT: v_mov_b32_e32 v0, s0 +; SI-NEXT: buffer_load_dword v6, v0, s[88:91], 0 offen +; SI-NEXT: v_mov_b32_e32 v0, s1 +; SI-NEXT: buffer_load_dword v7, v0, s[88:91], 0 offen +; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s3 +; SI-NEXT: v_mov_b32_e32 v3, s5 +; SI-NEXT: v_mov_b32_e32 v5, s7 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v6 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc +; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v6 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc +; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v6 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; SI-NEXT: flat_load_sbyte v0, v[0:1] +; SI-NEXT: flat_load_sbyte v1, v[2:3] +; SI-NEXT: flat_load_sbyte v2, v[4:5] +; SI-NEXT: v_mov_b32_e32 v3, s1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_u16 v0, v1, v0, v2 +; SI-NEXT: v_max_i16_e32 v0, 0xff80, v0 +; SI-NEXT: v_min_i16_e32 v2, 0x7f, v0 +; SI-NEXT: v_add_u32_e32 v0, vcc, s0, v6 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v7, vcc +; SI-NEXT: flat_store_byte v[0:1], v2 +; SI-NEXT: s_endpgm +; +; VI-LABEL: i8_mad_sat_16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; VI-NEXT: s_load_dword s0, s[4:5], 0x44 +; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; VI-NEXT: s_mov_b32 s14, -1 +; VI-NEXT: s_mov_b32 s15, 0xe80000 +; VI-NEXT: s_add_u32 s12, s12, s11 +; VI-NEXT: s_addc_u32 s13, s13, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s0, 4 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_load_dword v6, v0, s[12:15], 0 offen +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: buffer_load_dword v7, v0, s[12:15], 0 offen +; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6 +; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; VI-NEXT: flat_load_sbyte v0, v[0:1] +; VI-NEXT: flat_load_sbyte v1, v[2:3] +; VI-NEXT: flat_load_sbyte v2, v[4:5] +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u16 v0, v1, v0, v2 +; VI-NEXT: v_max_i16_e32 v0, 0xff80, v0 +; VI-NEXT: v_min_i16_e32 v2, 0x7f, v0 +; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6 +; VI-NEXT: v_addc_u32_e32 v1, vcc, v3, v7, vcc +; VI-NEXT: flat_store_byte v[0:1], v2 +; VI-NEXT: s_endpgm entry: %retval.0.i = load i64, ptr addrspace(5) %idx %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 %retval.0.i @@ -187,16 +912,201 @@ entry: ret void } -; FUNC-LABEL: {{^}}i8_mad_32: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16 define amdgpu_kernel void @i8_mad_32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) { +; EG-LABEL: i8_mad_32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 9, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X, +; EG-NEXT: ALU clause starting at 19: +; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X, +; EG-NEXT: ADD_INT * T0.X, KC0[3].X, T0.X, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T1.W, T0.X, 0.0, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PV.W, PV.Z, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PS, PV.W, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) +; +; CM-LABEL: i8_mad_32: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 12, @21, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X, +; CM-NEXT: ALU clause starting at 19: +; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X, +; CM-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, +; CM-NEXT: ALU clause starting at 21: +; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x, +; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_201 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.Y, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i8_mad_32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0 +; GCN-NEXT: s_mov_b32 s25, SCRATCH_RSRC_DWORD1 +; GCN-NEXT: s_mov_b32 s26, -1 +; GCN-NEXT: s_mov_b32 s27, 0xe8f000 +; GCN-NEXT: s_add_u32 s24, s24, s11 +; GCN-NEXT: s_addc_u32 s25, s25, 0 +; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s9, s8, 4 +; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: buffer_load_dword v1, v1, s[24:27], 0 offen +; GCN-NEXT: buffer_load_dword v0, v0, s[24:27], 0 offen +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s14, 0 +; GCN-NEXT: s_mov_b32 s15, s11 +; GCN-NEXT: s_mov_b64 s[18:19], s[14:15] +; GCN-NEXT: s_mov_b64 s[22:23], s[14:15] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[12:13], s[2:3] +; GCN-NEXT: s_mov_b64 s[16:17], s[4:5] +; GCN-NEXT: s_mov_b64 s[20:21], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[16:19], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v0, v[0:1], s[20:23], 0 addr64 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_mov_b32 s8, s0 +; GCN-NEXT: s_mov_b32 s9, s1 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v2 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mad_u32_u24 v0, v1, v2, v0 +; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GCN-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; GCN-NEXT: s_endpgm +; +; SI-LABEL: i8_mad_32: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0 +; SI-NEXT: s_load_dword s0, s[4:5], 0x44 +; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1 +; SI-NEXT: s_mov_b32 s90, -1 +; SI-NEXT: s_mov_b32 s91, 0xe80000 +; SI-NEXT: s_add_u32 s88, s88, s11 +; SI-NEXT: s_addc_u32 s89, s89, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_add_i32 s1, s0, 4 +; SI-NEXT: v_mov_b32_e32 v0, s0 +; SI-NEXT: buffer_load_dword v4, v0, s[88:91], 0 offen +; SI-NEXT: v_mov_b32_e32 v0, s1 +; SI-NEXT: buffer_load_dword v5, v0, s[88:91], 0 offen +; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s3 +; SI-NEXT: v_mov_b32_e32 v3, s5 +; SI-NEXT: v_mov_b32_e32 v6, s7 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; SI-NEXT: flat_load_sbyte v0, v[0:1] +; SI-NEXT: flat_load_sbyte v1, v[2:3] +; SI-NEXT: flat_load_sbyte v2, v[4:5] +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_u16 v0, v0, v1, v2 +; SI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: i8_mad_32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; VI-NEXT: s_load_dword s0, s[4:5], 0x44 +; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; VI-NEXT: s_mov_b32 s14, -1 +; VI-NEXT: s_mov_b32 s15, 0xe80000 +; VI-NEXT: s_add_u32 s12, s12, s11 +; VI-NEXT: s_addc_u32 s13, s13, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s0, 4 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_load_dword v4, v0, s[12:15], 0 offen +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: buffer_load_dword v5, v0, s[12:15], 0 offen +; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_mov_b32_e32 v6, s7 +; VI-NEXT: s_mov_b32 s3, 0xf000 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; VI-NEXT: flat_load_sbyte v0, v[0:1] +; VI-NEXT: flat_load_sbyte v1, v[2:3] +; VI-NEXT: flat_load_sbyte v2, v[4:5] +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u16 v0, v0, v1, v2 +; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; VI-NEXT: s_endpgm entry: %retval.0.i = load i64, ptr addrspace(5) %idx %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i @@ -215,16 +1125,207 @@ entry: ret void } -; FUNC-LABEL: {{^}}i8_mad_64: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16 define amdgpu_kernel void @i8_mad_64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) { +; EG-LABEL: i8_mad_64: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 11, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X, +; EG-NEXT: ALU clause starting at 19: +; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X, +; EG-NEXT: ADD_INT * T0.X, KC0[3].X, T0.X, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T1.W, T0.X, 0.0, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PV.W, PV.Z, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PS, PV.W, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) +; EG-NEXT: ASHR * T0.Y, PV.X, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; +; CM-LABEL: i8_mad_64: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 13, @21, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X, +; CM-NEXT: ALU clause starting at 19: +; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X, +; CM-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, +; CM-NEXT: ALU clause starting at 21: +; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x, +; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_201 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.Y, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; CM-NEXT: ASHR * T0.Y, PV.X, literal.y, +; CM-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; +; GCN-LABEL: i8_mad_64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0 +; GCN-NEXT: s_mov_b32 s25, SCRATCH_RSRC_DWORD1 +; GCN-NEXT: s_mov_b32 s26, -1 +; GCN-NEXT: s_mov_b32 s27, 0xe8f000 +; GCN-NEXT: s_add_u32 s24, s24, s11 +; GCN-NEXT: s_addc_u32 s25, s25, 0 +; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s9, s8, 4 +; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: buffer_load_dword v1, v1, s[24:27], 0 offen +; GCN-NEXT: buffer_load_dword v0, v0, s[24:27], 0 offen +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s14, 0 +; GCN-NEXT: s_mov_b32 s15, s11 +; GCN-NEXT: s_mov_b64 s[18:19], s[14:15] +; GCN-NEXT: s_mov_b64 s[22:23], s[14:15] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[12:13], s[2:3] +; GCN-NEXT: s_mov_b64 s[16:17], s[4:5] +; GCN-NEXT: s_mov_b64 s[20:21], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[16:19], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v0, v[0:1], s[20:23], 0 addr64 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_mov_b32 s8, s0 +; GCN-NEXT: s_mov_b32 s9, s1 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v2 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mad_u32_u24 v0, v1, v2, v0 +; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: s_endpgm +; +; SI-LABEL: i8_mad_64: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0 +; SI-NEXT: s_load_dword s0, s[4:5], 0x44 +; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1 +; SI-NEXT: s_mov_b32 s90, -1 +; SI-NEXT: s_mov_b32 s91, 0xe80000 +; SI-NEXT: s_add_u32 s88, s88, s11 +; SI-NEXT: s_addc_u32 s89, s89, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_add_i32 s1, s0, 4 +; SI-NEXT: v_mov_b32_e32 v0, s0 +; SI-NEXT: buffer_load_dword v4, v0, s[88:91], 0 offen +; SI-NEXT: v_mov_b32_e32 v0, s1 +; SI-NEXT: buffer_load_dword v5, v0, s[88:91], 0 offen +; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s3 +; SI-NEXT: v_mov_b32_e32 v3, s5 +; SI-NEXT: v_mov_b32_e32 v6, s7 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; SI-NEXT: flat_load_sbyte v0, v[0:1] +; SI-NEXT: flat_load_sbyte v1, v[2:3] +; SI-NEXT: flat_load_sbyte v2, v[4:5] +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_u16 v0, v0, v1, v2 +; SI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: i8_mad_64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; VI-NEXT: s_load_dword s0, s[4:5], 0x44 +; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; VI-NEXT: s_mov_b32 s14, -1 +; VI-NEXT: s_mov_b32 s15, 0xe80000 +; VI-NEXT: s_add_u32 s12, s12, s11 +; VI-NEXT: s_addc_u32 s13, s13, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s0, 4 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_load_dword v4, v0, s[12:15], 0 offen +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: buffer_load_dword v5, v0, s[12:15], 0 offen +; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_mov_b32_e32 v6, s7 +; VI-NEXT: s_mov_b32 s3, 0xf000 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; VI-NEXT: flat_load_sbyte v0, v[0:1] +; VI-NEXT: flat_load_sbyte v1, v[2:3] +; VI-NEXT: flat_load_sbyte v2, v[4:5] +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u16 v0, v0, v1, v2 +; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; VI-NEXT: s_endpgm entry: %retval.0.i = load i64, ptr addrspace(5) %idx %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i @@ -248,17 +1349,236 @@ entry: ; had a chance to form mul24. The mul combine would then see ; extractelement with no known bits and fail. All of the mul/add ; combos in this loop should form v_mad_u32_u24. - -; FUNC-LABEL: {{^}}mad24_known_bits_destroyed: -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 define void @mad24_known_bits_destroyed(i32 %arg, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, i32 %arg4, i32 %arg5, i32 %arg6, ptr addrspace(1) %arg7, ptr addrspace(1) %arg8) #0 { +; EG-LABEL: mad24_known_bits_destroyed: +; EG: ; %bb.0: ; %bb +; EG-NEXT: ALU 21, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: LOOP_START_DX10 @11 +; EG-NEXT: ALU 8, @34, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 0 +; EG-NEXT: ALU 14, @43, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 0 +; EG-NEXT: ALU_PUSH_BEFORE 3, @58, KC0[], KC1[] +; EG-NEXT: JUMP @10 POP:1 +; EG-NEXT: LOOP_BREAK @10 +; EG-NEXT: POP @10 POP:1 +; EG-NEXT: END_LOOP @2 +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.W, KC0[5].X, +; EG-NEXT: MOV * T0.Z, KC0[4].W, +; EG-NEXT: MOV * T0.Y, KC0[4].Z, +; EG-NEXT: MOV T0.X, KC0[2].Y, +; EG-NEXT: AND_INT * T1.Y, KC0[4].X, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.Z, KC0[3].W, literal.x, +; EG-NEXT: AND_INT T1.W, KC0[3].Z, literal.x, +; EG-NEXT: MOV * T2.W, KC0[7].Y, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: LSHR T1.X, PS, literal.x, +; EG-NEXT: AND_INT T2.Y, KC0[6].Y, literal.y, +; EG-NEXT: MOV T2.Z, KC0[6].X, +; EG-NEXT: MOV * T2.W, KC0[5].W, +; EG-NEXT: 2(2.802597e-45), 16777215(2.350989e-38) +; EG-NEXT: MOV * T3.W, KC0[7].X, +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: MOV T3.Y, KC0[5].Z, +; EG-NEXT: MOV T3.Z, KC0[6].Z, +; EG-NEXT: MOV * T3.W, KC0[6].W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV * T4.W, KC0[4].Y, +; EG-NEXT: ALU clause starting at 34: +; EG-NEXT: MULLO_INT * T0.X, T0.X, T2.Y, +; EG-NEXT: ADD_INT * T4.W, PS, T3.Z, +; EG-NEXT: AND_INT * T4.W, PV.W, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.X, PV.W, T2.Y, +; EG-NEXT: MULLO_INT * T0.W, T0.W, T1.Y, +; EG-NEXT: MULLO_INT * T0.Z, T0.Z, T1.Z, +; EG-NEXT: MULLO_INT * T0.Y, T0.Y, T1.W, +; EG-NEXT: ADD_INT * T0.X, T0.X, T3.Z, +; EG-NEXT: ALU clause starting at 43: +; EG-NEXT: ADD_INT * T4.W, T0.Y, T3.Y, +; EG-NEXT: AND_INT T4.W, PV.W, literal.x, +; EG-NEXT: ADD_INT * T5.W, T0.Z, T2.W, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: AND_INT T0.Z, PS, literal.x, +; EG-NEXT: ADD_INT T0.W, T0.W, T2.Z, +; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: ADD_INT T0.Y, PS, T3.Y, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: MULLO_INT * T0.Z, PV.Z, T1.Z, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: ADD_INT T0.Z, PS, T2.W, +; EG-NEXT: MULLO_INT * T0.W, PV.W, T1.Y, +; EG-NEXT: ADD_INT * T0.W, PS, T2.Z, +; EG-NEXT: ALU clause starting at 58: +; EG-NEXT: ADD_INT * T3.W, T3.W, literal.x, +; EG-NEXT: -1(nan), 0(0.000000e+00) +; EG-NEXT: SETE_INT * T4.W, PV.W, 0.0, +; EG-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; +; CM-LABEL: mad24_known_bits_destroyed: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 22, @12, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @11 +; CM-NEXT: ALU 23, @35, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T2.X +; CM-NEXT: ALU 23, @59, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X +; CM-NEXT: ALU_PUSH_BEFORE 3, @83, KC0[], KC1[] +; CM-NEXT: JUMP @10 POP:1 +; CM-NEXT: LOOP_BREAK @10 +; CM-NEXT: POP @10 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T0.W, KC0[5].X, +; CM-NEXT: MOV * T0.Z, KC0[4].W, +; CM-NEXT: MOV * T0.Y, KC0[4].Z, +; CM-NEXT: MOV T0.X, KC0[2].Y, +; CM-NEXT: AND_INT * T1.Y, KC0[4].X, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: AND_INT T1.Z, KC0[3].W, literal.x, +; CM-NEXT: AND_INT * T1.W, KC0[3].Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: AND_INT T2.Y, KC0[6].Y, literal.x, +; CM-NEXT: MOV T2.Z, KC0[6].X, +; CM-NEXT: MOV * T2.W, KC0[7].Y, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: LSHR T1.X, PV.W, literal.x, +; CM-NEXT: MOV T3.Y, KC0[5].W, +; CM-NEXT: MOV T3.Z, KC0[5].Z, +; CM-NEXT: MOV * T2.W, KC0[7].X, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: LSHR T2.X, PV.W, literal.x, +; CM-NEXT: MOV T4.Y, KC0[6].Z, +; CM-NEXT: MOV T4.Z, KC0[6].W, +; CM-NEXT: MOV * T2.W, KC0[4].Y, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 35: +; CM-NEXT: MULLO_INT T0.X, T0.X, T2.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.X, T2.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.X, T2.Y, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.X, T2.Y, +; CM-NEXT: ADD_INT * T2.W, PV.X, T4.Y, +; CM-NEXT: AND_INT * T2.W, PV.W, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T2.W, T2.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T2.W, T2.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T2.W, T2.Y, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T2.W, T2.Y, +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT * T0.W, T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Z, T1.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.Z, T1.Z, +; CM-NEXT: MULLO_INT T0.Z, T0.Z, T1.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Z, T1.Z, +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Y, T1.W, +; CM-NEXT: MULLO_INT T0.Y, T0.Y, T1.W, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.Y, T1.W, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Y, T1.W, +; CM-NEXT: ADD_INT * T0.X, T0.X, T4.Y, +; CM-NEXT: ALU clause starting at 59: +; CM-NEXT: ADD_INT * T2.W, T0.Y, T3.Z, +; CM-NEXT: ADD_INT T0.Z, T0.Z, T3.Y, +; CM-NEXT: AND_INT * T2.W, PV.W, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT T0.Y, T2.W, T1.W, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T2.W, T1.W, +; CM-NEXT: ADD_INT T0.Y, PV.Y, T3.Z, +; CM-NEXT: ADD_INT T5.Z, T0.W, T2.Z, BS:VEC_021/SCL_122 +; CM-NEXT: AND_INT * T0.W, T0.Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Z, T0.W, T1.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z, +; CM-NEXT: ADD_INT T0.Z, PV.Z, T3.Y, +; CM-NEXT: AND_INT * T0.W, T5.Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT * T0.W, T0.W, T1.Y, +; CM-NEXT: ADD_INT * T0.W, PV.W, T2.Z, +; CM-NEXT: ALU clause starting at 83: +; CM-NEXT: ADD_INT * T4.Z, T4.Z, literal.x, +; CM-NEXT: -1(nan), 0(0.000000e+00) +; CM-NEXT: SETE_INT * T2.W, PV.Z, 0.0, +; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; +; GCN-LABEL: mad24_known_bits_destroyed: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, v0 +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v13 +; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v2 +; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v3 +; GCN-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; GCN-NEXT: s_mov_b64 s[8:9], 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: .LBB9_1: ; %bb19 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: v_mad_u32_u24 v4, v5, v0, v14 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GCN-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GCN-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GCN-NEXT: v_add_i32_e32 v15, vcc, -1, v15 +; GCN-NEXT: v_mad_u32_u24 v5, v4, v0, v14 +; GCN-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GCN-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GCN-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 +; GCN-NEXT: buffer_store_dword v5, v[16:17], s[4:7], 0 addr64 +; GCN-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GCN-NEXT: buffer_store_dwordx4 v[5:8], v[18:19], s[4:7], 0 addr64 +; GCN-NEXT: s_andn2_b64 exec, exec, s[8:9] +; GCN-NEXT: s_cbranch_execnz .LBB9_1 +; GCN-NEXT: ; %bb.2: ; %bb18 +; GCN-NEXT: s_or_b64 exec, exec, s[8:9] +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: mad24_known_bits_destroyed: +; GFX8: ; %bb.0: ; %bb +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v5, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v13 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v2 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; GFX8-NEXT: s_mov_b64 s[4:5], 0 +; GFX8-NEXT: .LBB9_1: ; %bb19 +; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX8-NEXT: v_add_u32_e32 v15, vcc, -1, v15 +; GFX8-NEXT: v_mad_u32_u24 v4, v5, v0, v14 +; GFX8-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GFX8-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GFX8-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 +; GFX8-NEXT: v_mad_u32_u24 v5, v4, v0, v14 +; GFX8-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GFX8-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GFX8-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GFX8-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX8-NEXT: flat_store_dword v[16:17], v5 +; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[5:8] +; GFX8-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX8-NEXT: s_cbranch_execnz .LBB9_1 +; GFX8-NEXT: ; %bb.2: ; %bb18 +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] bb: %tmp = and i32 %arg4, 16777215 %tmp9 = extractelement <4 x i32> %arg1, i64 1 diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll index bb22144..9814ed8 100644 --- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll +++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll @@ -1,15 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-SAFE %s -; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,VI-SAFE %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9,GFX9-SAFE %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-FAKE16 %s - -; RUN: llc -mtriple=amdgcn -mcpu=hawaii -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=CI,CI-NSZ %s -; RUN: llc -mtriple=amdgcn -mcpu=fiji -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=VI,VI-NSZ %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=GFX9,GFX9-NSZ %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI %s +; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s define <2 x half> @add_select_fabs_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x half> %y, <2 x half> %z) { ; CI-LABEL: add_select_fabs_fabs_v2f16: @@ -63,69 +57,37 @@ define <2 x half> @add_select_fabs_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -198,73 +160,39 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_lhs_fabs_fabs_v2f16(<2 x ; GFX9-NEXT: v_pk_add_f16 v1, v1, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v1, v2, v4 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v5 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v1, v2, v4 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v5 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v1, v2, v4 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v5 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v1, v2, v4 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v5 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v2, v4 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v5 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, v2, v4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v5 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -328,73 +256,39 @@ define { <2 x half>, <2 x half> } @add_select_multi_store_use_lhs_fabs_fabs_v2f1 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-SAFE-TRUE16-NEXT: v_mov_b32_e32 v1, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v1, v2 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NSZ-TRUE16-NEXT: v_mov_b32_e32 v1, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v1, v2 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -469,73 +363,39 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_rhs_fabs_fabs_v2f16(<2 x ; GFX9-NEXT: v_pk_add_f16 v1, v2, v5 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v1, v2, v5 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v1, v3, v5 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v1, v2, v5 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v1, v3, v5 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v2, v5 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, v3, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -597,63 +457,34 @@ define <2 x half> @add_select_fabs_var_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_var_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_var_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_var_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_var_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_var_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_var_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %select = select <2 x i1> %cmp, <2 x half> %fabs.x, <2 x half> %y @@ -709,61 +540,33 @@ define <2 x half> @add_select_fabs_negk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_negk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_negk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_negk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_negk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_negk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_negk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %select = select <2 x i1> %cmp, <2 x half> %fabs, <2 x half> <half -1.0, half -1.0> @@ -815,61 +618,33 @@ define <2 x half> @add_select_fabs_negk_negk_v2f16(<2 x i32> %c, <2 x half> %x) ; GFX9-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_negk_negk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_negk_negk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_negk_negk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_negk_negk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_negk_negk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_negk_negk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %select = select <2 x i1> %cmp, <2 x half> <half -2.0, half -2.0>, <2 x half> <half -1.0, half -1.0> %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %select) @@ -920,61 +695,33 @@ define <2 x half> @add_select_posk_posk_v2f16(<2 x i32> %c, <2 x half> %x) { ; GFX9-NEXT: v_pk_add_f16 v0, v0, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_posk_posk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x3c00 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0x4000, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0x4000, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_posk_posk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4000 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_posk_posk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x3c00 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0x4000, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0x4000, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_posk_posk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4000 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_posk_posk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x3c00 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0x4000, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0x4000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_posk_posk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4000 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %select = select <2 x i1> %cmp, <2 x half> <half 2.0, half 2.0>, <2 x half> <half 1.0, half 1.0> %add = fadd <2 x half> %select, %x @@ -1029,61 +776,33 @@ define <2 x half> @add_select_negk_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negk_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negk_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negk_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negk_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negk_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negk_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %select = select <2 x i1> %cmp, <2 x half> <half -1.0, half -1.0>, <2 x half> %fabs @@ -1140,61 +859,33 @@ define <2 x half> @add_select_negliteralk_fabs_v2f16(<2 x i32> %c, <2 x half> %x ; GFX9-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negliteralk_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xe400, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xe400, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negliteralk_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xe400, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xe400, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negliteralk_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xe400, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xe400, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negliteralk_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xe400, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xe400, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negliteralk_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xe400, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xe400, v2.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negliteralk_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xe400, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xe400, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %select = select <2 x i1> %cmp, <2 x half> <half -1024.0, half -1024.0>, <2 x half> %fabs @@ -1250,61 +941,33 @@ define <2 x half> @add_select_fabs_posk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_posk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_posk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_posk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_posk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_posk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_posk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %select = select <2 x i1> %cmp, <2 x half> %fabs, <2 x half> <half 1.0, half 1.0> @@ -1360,61 +1023,33 @@ define <2 x half> @add_select_posk_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_posk_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_posk_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_posk_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_posk_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_posk_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_posk_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %select = select <2 x i1> %cmp, <2 x half> <half 1.0, half 1.0>, <2 x half> %fabs @@ -1470,57 +1105,31 @@ define <2 x half> @add_select_fneg_fneg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_fneg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_fneg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_fneg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_fneg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_fneg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_fneg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %fneg.y = fneg <2 x half> %y @@ -1587,61 +1196,33 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_lhs_fneg_fneg_v2f16(<2 x ; GFX9-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_multi_use_lhs_fneg_fneg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_multi_use_lhs_fneg_fneg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_lhs_fneg_fneg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_lhs_fneg_fneg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_multi_use_lhs_fneg_fneg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_multi_use_lhs_fneg_fneg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %fneg.y = fneg <2 x half> %y @@ -1705,61 +1286,33 @@ define { <2 x half>, <2 x half> } @add_select_multi_store_use_lhs_fneg_fneg_v2f1 ; GFX9-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %fneg.y = fneg <2 x half> %y @@ -1828,61 +1381,33 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_rhs_fneg_fneg_v2f16(<2 x ; GFX9-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_multi_use_rhs_fneg_fneg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_multi_use_rhs_fneg_fneg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_rhs_fneg_fneg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_rhs_fneg_fneg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_multi_use_rhs_fneg_fneg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_multi_use_rhs_fneg_fneg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %fneg.y = fneg <2 x half> %y @@ -1948,63 +1473,34 @@ define <2 x half> @add_select_fneg_var_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_var_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_var_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_var_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_var_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_var_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_var_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> %fneg.x, <2 x half> %y @@ -2058,55 +1554,30 @@ define <2 x half> @add_select_fneg_negk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_negk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_negk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_negk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_negk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_negk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_negk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> %fneg.x, <2 x half> <half -1.0, half -1.0> @@ -2161,55 +1632,30 @@ define <2 x half> @add_select_fneg_inv2pi_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_inv2pi_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xb118, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xb118, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_inv2pi_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xb118, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xb118, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_inv2pi_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xb118, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xb118, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_inv2pi_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xb118, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xb118, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_inv2pi_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xb118, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xb118, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_inv2pi_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xb118, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xb118, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> %fneg.x, <2 x half> <half 0xH3118, half 0xH3118> @@ -2264,55 +1710,30 @@ define <2 x half> @add_select_fneg_neginv2pi_v2f16(<2 x i32> %c, <2 x half> %x, ; GFX9-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_neginv2pi_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3118, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3118, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_neginv2pi_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3118, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3118, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_neginv2pi_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3118, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3118, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_neginv2pi_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3118, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3118, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_neginv2pi_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3118, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3118, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_neginv2pi_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3118, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3118, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> %fneg.x, <2 x half> <half 0xHB118, half 0xHB118> @@ -2363,61 +1784,33 @@ define <2 x half> @add_select_negk_negk_v2f16(<2 x i32> %c, <2 x half> %x) { ; GFX9-NEXT: v_pk_add_f16 v0, v0, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negk_negk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negk_negk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negk_negk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negk_negk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negk_negk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negk_negk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %select = select <2 x i1> %cmp, <2 x half> <half -2.0, half -2.0>, <2 x half> <half -1.0, half -1.0> %add = fadd <2 x half> %select, %x @@ -2469,61 +1862,33 @@ define <2 x half> @add_select_negliteralk_negliteralk_v2f16(<2 x i32> %c, <2 x h ; GFX9-NEXT: v_pk_add_f16 v0, v0, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negliteralk_negliteralk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xec00 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xe800, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xe800, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negliteralk_negliteralk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v3, 0xe800 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xec00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xec00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negliteralk_negliteralk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xec00 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xe800, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xe800, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negliteralk_negliteralk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v3, 0xe800 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xec00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xec00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negliteralk_negliteralk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xec00 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xe800, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xe800, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negliteralk_negliteralk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xe800 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xec00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xec00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %select = select <2 x i1> %cmp, <2 x half> <half -2048.0, half -2048.0>, <2 x half> <half -4096.0, half -4096.0> %add = fadd <2 x half> %select, %x @@ -2573,61 +1938,33 @@ define <2 x half> @add_select_fneg_negk_negk_v2f16(<2 x i32> %c, <2 x half> %x) ; GFX9-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_negk_negk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_negk_negk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_negk_negk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_negk_negk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_negk_negk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xbc00 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xc000, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xc000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_negk_negk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc000 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v2, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %select = select <2 x i1> %cmp, <2 x half> <half -2.0, half -2.0>, <2 x half> <half -1.0, half -1.0> %fneg.x = fneg <2 x half> %select @@ -2681,55 +2018,30 @@ define <2 x half> @add_select_negk_fneg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negk_fneg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negk_fneg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negk_fneg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negk_fneg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negk_fneg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negk_fneg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> <half -1.0, half -1.0>, <2 x half> %fneg.x @@ -2783,55 +2095,30 @@ define <2 x half> @add_select_fneg_posk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fneg_posk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fneg_posk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_posk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_posk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fneg_posk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fneg_posk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> %fneg.x, <2 x half> <half 1.0, half 1.0> @@ -2885,55 +2172,30 @@ define <2 x half> @add_select_posk_fneg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x ; GFX9-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_posk_fneg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_posk_fneg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_posk_fneg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_posk_fneg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_posk_fneg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_posk_fneg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %select = select <2 x i1> %cmp, <2 x half> <half 1.0, half 1.0>, <2 x half> %fneg.x @@ -2997,69 +2259,37 @@ define <2 x half> @add_select_negfabs_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negfabs_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negfabs_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negfabs_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negfabs_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negfabs_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negfabs_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.fabs.x = fneg <2 x half> %fabs.x @@ -3125,69 +2355,37 @@ define <2 x half> @add_select_fabs_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_negfabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_negfabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_or_b32_e32 v3, 0x80008000, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_negfabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_negfabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v3, 0x80008000, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_negfabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_negfabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x80008000, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -3253,69 +2451,37 @@ define <2 x half> @add_select_neg_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_neg_fabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_neg_fabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_neg_fabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_neg_fabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_neg_fabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_neg_fabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -3380,69 +2546,37 @@ define <2 x half> @add_select_fabs_neg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h ; GFX9-NEXT: v_pk_add_f16 v0, v0, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_fabs_neg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_fabs_neg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v3, 0x80008000, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_neg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_neg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v3, 0x80008000, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_fabs_neg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_fabs_neg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v3, 0x80008000, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v0, v4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.y = fneg <2 x half> %y @@ -3501,63 +2635,34 @@ define <2 x half> @add_select_neg_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_neg_negfabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v3 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_neg_negfabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_neg_negfabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v3 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_neg_negfabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_neg_negfabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v3 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_neg_negfabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fneg.x = fneg <2 x half> %x %fabs.y = call <2 x half> @llvm.fabs.v2f16(<2 x half> %y) @@ -3617,63 +2722,34 @@ define <2 x half> @add_select_negfabs_neg_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: add_select_negfabs_neg_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v3.h, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.l, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: add_select_negfabs_neg_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: add_select_negfabs_neg_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v3.h, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.l, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: add_select_negfabs_neg_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: add_select_negfabs_neg_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v3.h, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.l, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: add_select_negfabs_neg_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.fabs.x = fneg <2 x half> %fabs.x @@ -3735,61 +2811,33 @@ define <2 x half> @mul_select_negfabs_posk_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: mul_select_negfabs_posk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: mul_select_negfabs_posk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: mul_select_negfabs_posk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: mul_select_negfabs_posk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: mul_select_negfabs_posk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: mul_select_negfabs_posk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.fabs.x = fneg <2 x half> %fabs.x @@ -3850,61 +2898,33 @@ define <2 x half> @mul_select_posk_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: mul_select_posk_negfabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: mul_select_posk_negfabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: mul_select_posk_negfabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: mul_select_posk_negfabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: mul_select_posk_negfabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v2.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: mul_select_posk_negfabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.fabs.x = fneg <2 x half> %fabs.x @@ -3965,61 +2985,33 @@ define <2 x half> @mul_select_negfabs_negk_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: mul_select_negfabs_negk_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: mul_select_negfabs_negk_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: mul_select_negfabs_negk_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: mul_select_negfabs_negk_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: mul_select_negfabs_negk_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v0.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: mul_select_negfabs_negk_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.fabs.x = fneg <2 x half> %fabs.x @@ -4080,61 +3072,33 @@ define <2 x half> @mul_select_negk_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: mul_select_negk_negfabs_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v2.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v2.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: mul_select_negk_negfabs_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v4, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: mul_select_negk_negfabs_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v2.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v2.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: mul_select_negk_negfabs_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v4, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: mul_select_negk_negfabs_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v2.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v2.h, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: mul_select_negk_negfabs_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xc400, v4, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v3 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fneg.fabs.x = fneg <2 x half> %fabs.x @@ -4171,115 +3135,63 @@ define <2 x half> @select_fneg_posk_src_add_v2f16(<2 x i32> %c, <2 x half> %x, < ; CI-NEXT: v_cndmask_b32_e32 v1, 2.0, v2, vcc ; CI-NEXT: s_setpc_b64 s[30:31] ; -; VI-SAFE-LABEL: select_fneg_posk_src_add_v2f16: -; VI-SAFE: ; %bb.0: -; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-SAFE-NEXT: v_mov_b32_e32 v1, 0x4400 -; VI-SAFE-NEXT: v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; VI-SAFE-NEXT: v_add_f16_e32 v2, 4.0, v2 -; VI-SAFE-NEXT: v_or_b32_e32 v1, v2, v1 -; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; VI-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; VI-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-SAFE-LABEL: select_fneg_posk_src_add_v2f16: -; GFX9-SAFE: ; %bb.0: -; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-SAFE-NEXT: v_pk_add_f16 v1, v2, 4.0 op_sel_hi:[1,0] -; GFX9-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-SAFE-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_add_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_add_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; VI-NSZ-LABEL: select_fneg_posk_src_add_v2f16: -; VI-NSZ: ; %bb.0: -; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-NSZ-NEXT: v_mov_b32_e32 v1, 0xc400 -; VI-NSZ-NEXT: v_sub_f16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; VI-NSZ-NEXT: v_sub_f16_e32 v2, -4.0, v2 -; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x4000 -; VI-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-NSZ-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5] -; VI-NSZ-NEXT: v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; VI-NSZ-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-NSZ-LABEL: select_fneg_posk_src_add_v2f16: -; GFX9-NSZ: ; %bb.0: -; GFX9-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-NSZ-NEXT: v_pk_add_f16 v1, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX9-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-NSZ-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-NSZ-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NSZ-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NSZ-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_add_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_add_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; VI-LABEL: select_fneg_posk_src_add_v2f16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_mov_b32_e32 v1, 0x4400 +; VI-NEXT: v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v2, 4.0, v2 +; VI-NEXT: v_or_b32_e32 v1, v2, v1 +; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; VI-NEXT: v_mov_b32_e32 v2, 0x4000 +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; VI-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: select_fneg_posk_src_add_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX9-NEXT: v_pk_add_f16 v1, v2, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4000 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: select_fneg_posk_src_add_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_add_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %add = fadd <2 x half> %x, <half 4.0, half 4.0> %fneg = fneg <2 x half> %add @@ -4330,55 +3242,30 @@ define <2 x half> @select_fneg_posk_src_add_v2f16_nsz(<2 x i32> %c, <2 x half> % ; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_add_v2f16_nsz: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v0, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_add_v2f16_nsz: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_add_v2f16_nsz: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_add_v2f16_nsz: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: select_fneg_posk_src_add_v2f16_nsz: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_add_v2f16_nsz: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %add = fadd nsz <2 x half> %x, <half 4.0, half 4.0> %fneg = fneg <2 x half> %add @@ -4387,153 +3274,86 @@ define <2 x half> @select_fneg_posk_src_add_v2f16_nsz(<2 x i32> %c, <2 x half> % } define <2 x half> @select_fneg_posk_src_sub_v2f16(<2 x i32> %c, <2 x half> %x) { -; CI-SAFE-LABEL: select_fneg_posk_src_sub_v2f16: -; CI-SAFE: ; %bb.0: -; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3 -; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2 -; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3 -; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2 -; CI-SAFE-NEXT: v_add_f32_e32 v3, -4.0, v3 -; CI-SAFE-NEXT: v_add_f32_e32 v2, -4.0, v2 -; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3 -; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2 -; CI-SAFE-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; CI-SAFE-NEXT: v_or_b32_e32 v2, v2, v3 -; CI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v2 -; CI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2 -; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, 2.0, v3, vcc -; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CI-SAFE-NEXT: v_cndmask_b32_e32 v1, 2.0, v2, vcc -; CI-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; VI-SAFE-LABEL: select_fneg_posk_src_sub_v2f16: -; VI-SAFE: ; %bb.0: -; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-SAFE-NEXT: v_mov_b32_e32 v1, 0xc400 -; VI-SAFE-NEXT: v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; VI-SAFE-NEXT: v_add_f16_e32 v2, -4.0, v2 -; VI-SAFE-NEXT: v_or_b32_e32 v1, v2, v1 -; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; VI-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; VI-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-SAFE-LABEL: select_fneg_posk_src_sub_v2f16: -; GFX9-SAFE: ; %bb.0: -; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-SAFE-NEXT: v_pk_add_f16 v1, v2, -4.0 op_sel_hi:[1,0] -; GFX9-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-SAFE-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_sub_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_sub_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; CI-NSZ-LABEL: select_fneg_posk_src_sub_v2f16: -; CI-NSZ: ; %bb.0: -; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v2, v2 -; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v3, v3 -; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2 -; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v3 -; CI-NSZ-NEXT: v_sub_f32_e32 v2, 4.0, v2 -; CI-NSZ-NEXT: v_sub_f32_e32 v3, 4.0, v3 -; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, 2.0, v2, vcc -; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; CI-NSZ-NEXT: v_cndmask_b32_e32 v1, 2.0, v3, vcc -; CI-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; VI-NSZ-LABEL: select_fneg_posk_src_sub_v2f16: -; VI-NSZ: ; %bb.0: -; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-NSZ-NEXT: v_mov_b32_e32 v1, 0x4400 -; VI-NSZ-NEXT: v_sub_f16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; VI-NSZ-NEXT: v_sub_f16_e32 v2, 4.0, v2 -; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x4000 -; VI-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-NSZ-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5] -; VI-NSZ-NEXT: v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; VI-NSZ-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-NSZ-LABEL: select_fneg_posk_src_sub_v2f16: -; GFX9-NSZ: ; %bb.0: -; GFX9-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-NSZ-NEXT: v_pk_add_f16 v1, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX9-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-NSZ-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-NSZ-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NSZ-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NSZ-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_sub_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_add_f16 v0, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_sub_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; CI-LABEL: select_fneg_posk_src_sub_v2f16: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; CI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; CI-NEXT: v_add_f32_e32 v3, -4.0, v3 +; CI-NEXT: v_add_f32_e32 v2, -4.0, v2 +; CI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; CI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; CI-NEXT: v_or_b32_e32 v2, v2, v3 +; CI-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; CI-NEXT: v_cvt_f32_f16_e32 v3, v2 +; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v3, vcc +; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, 2.0, v2, vcc +; CI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: select_fneg_posk_src_sub_v2f16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_mov_b32_e32 v1, 0xc400 +; VI-NEXT: v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v2, -4.0, v2 +; VI-NEXT: v_or_b32_e32 v1, v2, v1 +; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; VI-NEXT: v_mov_b32_e32 v2, 0x4000 +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; VI-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: select_fneg_posk_src_sub_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX9-NEXT: v_pk_add_f16 v1, v2, -4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4000 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: select_fneg_posk_src_sub_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_sub_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %add = fsub <2 x half> %x, <half 4.0, half 4.0> %fneg = fneg <2 x half> %add @@ -4541,6 +3361,80 @@ define <2 x half> @select_fneg_posk_src_sub_v2f16(<2 x i32> %c, <2 x half> %x) { ret <2 x half> %select } +define <2 x half> @select_fneg_posk_src_sub_v2f16_nsz(<2 x i32> %c, <2 x half> %x) { +; CI-LABEL: select_fneg_posk_src_sub_v2f16_nsz: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; CI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; CI-NEXT: v_sub_f32_e32 v2, 4.0, v2 +; CI-NEXT: v_sub_f32_e32 v3, 4.0, v3 +; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v2, vcc +; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, 2.0, v3, vcc +; CI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: select_fneg_posk_src_sub_v2f16_nsz: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_mov_b32_e32 v1, 0x4400 +; VI-NEXT: v_sub_f16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-NEXT: v_sub_f16_e32 v2, 4.0, v2 +; VI-NEXT: v_mov_b32_e32 v3, 0x4000 +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; VI-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5] +; VI-NEXT: v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: select_fneg_posk_src_sub_v2f16_nsz: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX9-NEXT: v_pk_add_f16 v1, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4000 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: select_fneg_posk_src_sub_v2f16_nsz: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_sub_v2f16_nsz: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq <2 x i32> %c, zeroinitializer + %add = fsub <2 x half> %x, <half 4.0, half 4.0> + %fneg = fneg nsz <2 x half> %add + %select = select <2 x i1> %cmp, <2 x half> %fneg, <2 x half> <half 2.0, half 2.0> + ret <2 x half> %select +} + define <2 x half> @select_fneg_posk_src_mul_v2f16(<2 x i32> %c, <2 x half> %x) { ; CI-LABEL: select_fneg_posk_src_mul_v2f16: ; CI: ; %bb.0: @@ -4584,55 +3478,30 @@ define <2 x half> @select_fneg_posk_src_mul_v2f16(<2 x i32> %c, <2 x half> %x) { ; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_mul_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_mul_f16 v0, v2, -4.0 op_sel_hi:[1,0] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_mul_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_mul_f16 v2, v2, -4.0 op_sel_hi:[1,0] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_mul_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_mul_f16 v0, v2, -4.0 op_sel_hi:[1,0] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_mul_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_mul_f16 v2, v2, -4.0 op_sel_hi:[1,0] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: select_fneg_posk_src_mul_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v2, -4.0 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_mul_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_mul_f16 v2, v2, -4.0 op_sel_hi:[1,0] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %mul = fmul <2 x half> %x, <half 4.0, half 4.0> %fneg = fneg <2 x half> %mul @@ -4668,118 +3537,65 @@ define <2 x half> @select_fneg_posk_src_fma_v2f16(<2 x i32> %c, <2 x half> %x, < ; CI-NEXT: v_cndmask_b32_e32 v1, 2.0, v2, vcc ; CI-NEXT: s_setpc_b64 s[30:31] ; -; VI-SAFE-LABEL: select_fneg_posk_src_fma_v2f16: -; VI-SAFE: ; %bb.0: -; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v3 -; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; VI-SAFE-NEXT: v_fma_f16 v1, v4, 4.0, v1 -; VI-SAFE-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; VI-SAFE-NEXT: v_fma_f16 v2, v2, 4.0, v3 -; VI-SAFE-NEXT: v_or_b32_e32 v1, v2, v1 -; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; VI-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; VI-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-SAFE-LABEL: select_fneg_posk_src_fma_v2f16: -; GFX9-SAFE: ; %bb.0: -; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-SAFE-NEXT: v_pk_fma_f16 v1, v2, 4.0, v3 op_sel_hi:[1,0,1] -; GFX9-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-SAFE-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fma_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_fma_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; VI-NSZ-LABEL: select_fneg_posk_src_fma_v2f16: -; VI-NSZ: ; %bb.0: -; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v3 -; VI-NSZ-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; VI-NSZ-NEXT: v_fma_f16 v1, v4, -4.0, -v1 -; VI-NSZ-NEXT: v_fma_f16 v2, v2, -4.0, -v3 -; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x4000 -; VI-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-NSZ-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5] -; VI-NSZ-NEXT: v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; VI-NSZ-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-NSZ-LABEL: select_fneg_posk_src_fma_v2f16: -; GFX9-NSZ: ; %bb.0: -; GFX9-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-NSZ-NEXT: v_pk_fma_f16 v1, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX9-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-NSZ-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-NSZ-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NSZ-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NSZ-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_fma_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_fma_f16 v0, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_fma_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_fma_f16 v2, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; VI-LABEL: select_fneg_posk_src_fma_v2f16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3 +; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; VI-NEXT: v_fma_f16 v1, v4, 4.0, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_fma_f16 v2, v2, 4.0, v3 +; VI-NEXT: v_or_b32_e32 v1, v2, v1 +; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; VI-NEXT: v_mov_b32_e32 v2, 0x4000 +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; VI-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: select_fneg_posk_src_fma_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX9-NEXT: v_pk_fma_f16 v1, v2, 4.0, v3 op_sel_hi:[1,0,1] +; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4000 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: select_fneg_posk_src_fma_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_fma_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> <half 4.0, half 4.0>, <2 x half> %z) %fneg = fneg <2 x half> %fma @@ -4817,118 +3633,65 @@ define <2 x half> @select_fneg_posk_src_fmad_v2f16(<2 x i32> %c, <2 x half> %x, ; CI-NEXT: v_cndmask_b32_e32 v1, 2.0, v2, vcc ; CI-NEXT: s_setpc_b64 s[30:31] ; -; VI-SAFE-LABEL: select_fneg_posk_src_fmad_v2f16: -; VI-SAFE: ; %bb.0: -; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v3 -; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; VI-SAFE-NEXT: v_fma_f16 v1, v4, 4.0, v1 -; VI-SAFE-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; VI-SAFE-NEXT: v_fma_f16 v2, v2, 4.0, v3 -; VI-SAFE-NEXT: v_or_b32_e32 v1, v2, v1 -; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; VI-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; VI-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-SAFE-LABEL: select_fneg_posk_src_fmad_v2f16: -; GFX9-SAFE: ; %bb.0: -; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-SAFE-NEXT: v_pk_fma_f16 v1, v2, 4.0, v3 op_sel_hi:[1,0,1] -; GFX9-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-SAFE-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-SAFE-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-SAFE-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-SAFE-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; VI-NSZ-LABEL: select_fneg_posk_src_fmad_v2f16: -; VI-NSZ: ; %bb.0: -; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; VI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v3 -; VI-NSZ-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; VI-NSZ-NEXT: v_fma_f16 v1, v4, -4.0, -v1 -; VI-NSZ-NEXT: v_fma_f16 v2, v2, -4.0, -v3 -; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x4000 -; VI-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; VI-NSZ-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[4:5] -; VI-NSZ-NEXT: v_cndmask_b32_sdwa v1, v3, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; VI-NSZ-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-NSZ-LABEL: select_fneg_posk_src_fmad_v2f16: -; GFX9-NSZ: ; %bb.0: -; GFX9-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-NSZ-NEXT: v_pk_fma_f16 v1, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX9-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000 -; GFX9-NSZ-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GFX9-NSZ-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GFX9-NSZ-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NSZ-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NSZ-NEXT: v_perm_b32 v0, v1, v0, s4 -; GFX9-NSZ-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_fma_f16 v0, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_fma_f16 v2, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; VI-LABEL: select_fneg_posk_src_fmad_v2f16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3 +; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; VI-NEXT: v_fma_f16 v1, v4, 4.0, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_fma_f16 v2, v2, 4.0, v3 +; VI-NEXT: v_or_b32_e32 v1, v2, v1 +; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; VI-NEXT: v_mov_b32_e32 v2, 0x4000 +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; VI-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: select_fneg_posk_src_fmad_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX9-NEXT: v_pk_fma_f16 v1, v2, 4.0, v3 op_sel_hi:[1,0,1] +; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4000 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] +; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_fma_f16 v2, v2, 4.0, v3 op_sel_hi:[1,0,1] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fmad = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> %x, <2 x half> <half 4.0, half 4.0>, <2 x half> %z) %fneg = fneg <2 x half> %fmad @@ -4986,55 +3749,30 @@ define <2 x half> @select_fneg_posk_src_fmad_v2f16_nsz(<2 x i32> %c, <2 x half> ; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz: -; GFX11-SAFE-TRUE16: ; %bb.0: -; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-TRUE16-NEXT: v_pk_fma_f16 v0, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz: -; GFX11-SAFE-FAKE16: ; %bb.0: -; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SAFE-FAKE16-NEXT: v_pk_fma_f16 v2, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-SAFE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SAFE-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz: -; GFX11-NSZ-TRUE16: ; %bb.0: -; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-TRUE16-NEXT: v_pk_fma_f16 v0, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 -; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo -; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 -; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz: -; GFX11-NSZ-FAKE16: ; %bb.0: -; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NSZ-FAKE16-NEXT: v_pk_fma_f16 v2, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NSZ-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo -; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NSZ-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_pk_fma_f16 v0, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v0.h, s0 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_pk_fma_f16 v2, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v2, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v3, vcc_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq <2 x i32> %c, zeroinitializer %fmad = call nsz <2 x half> @llvm.fmuladd.v2f16(<2 x half> %x, <2 x half> <half 4.0, half 4.0>, <2 x half> %z) %fneg = fneg <2 x half> %fmad @@ -5049,5 +3787,3 @@ declare <2 x half> @llvm.fmuladd.v2f16(<2 x half>, <2 x half>, <2 x half>) #0 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX11: {{.*}} -; GFX11-NSZ: {{.*}} -; GFX11-SAFE: {{.*}} diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index 77eeb34..4dd8af0 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -447,7 +447,7 @@ body: | ; CHECK-LABEL: name: test_vnmuls ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VNMULS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -477,7 +477,7 @@ body: | ; CHECK-LABEL: name: test_vnmuls_reassociate ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VNMULS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -507,7 +507,7 @@ body: | ; CHECK-LABEL: name: test_vnmuld ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VNMULD:%[0-9]+]]:dpr = nofpexcept VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VNMULD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 @@ -539,7 +539,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 - ; CHECK: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMAS:%[0-9]+]]:spr = nofpexcept VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VFNMAS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -573,7 +573,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = nofpexcept VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VFNMAD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 @@ -607,7 +607,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 - ; CHECK: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFMSS:%[0-9]+]]:spr = nofpexcept VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VFMSS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -640,7 +640,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg + ; CHECK: [[VFMSD:%[0-9]+]]:dpr = nofpexcept VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VFMSD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 @@ -673,7 +673,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 - ; CHECK: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMSS:%[0-9]+]]:spr = nofpexcept VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VFNMSS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir index 45a846b..4cded13 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir @@ -19,7 +19,7 @@ body: | bb.1: ; CHECK-LABEL: name: test_fptosi ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 - ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]] ; CHECK: $r0 = COPY [[COPY1]] ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir index ec834f1..4517fe6 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -O0 -mtriple arm-- -mattr=+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | @@ -76,11 +77,9 @@ body: | ... --- name: test_fadd_s32 -# CHECK-LABEL: name: test_fadd_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -89,28 +88,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fadd_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VADDS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fadd_s64 -# CHECK-LABEL: name: test_fadd_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -119,28 +119,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fadd_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VADDD:%[0-9]+]]:dpr = nofpexcept VADDD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VADDD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fsub_s32 -# CHECK-LABEL: name: test_fsub_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -149,28 +150,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fsub_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VSUBS:%[0-9]+]]:spr = nofpexcept VSUBS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VSUBS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fsub_s64 -# CHECK-LABEL: name: test_fsub_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -179,28 +181,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fsub_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VSUBD:%[0-9]+]]:dpr = nofpexcept VSUBD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VSUBD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fmul_s32 -# CHECK-LABEL: name: test_fmul_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -209,28 +212,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fmul_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nofpexcept VMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VMULS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fmul_s64 -# CHECK-LABEL: name: test_fmul_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -239,28 +243,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fmul_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VMULD:%[0-9]+]]:dpr = nofpexcept VMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VMULD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fdiv_s32 -# CHECK-LABEL: name: test_fdiv_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -269,28 +274,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fdiv_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VDIVS:%[0-9]+]]:spr = nofpexcept VDIVS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VDIVS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fdiv_s64 -# CHECK-LABEL: name: test_fdiv_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -299,28 +305,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fdiv_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VDIVD:%[0-9]+]]:dpr = nofpexcept VDIVD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VDIVD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fneg_s32 -# CHECK-LABEL: name: test_fneg_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -328,25 +335,26 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fneg_s32 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VNEGS:%[0-9]+]]:spr = VNEGS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $s0 = COPY [[VNEGS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FNEG %0 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fneg_s64 -# CHECK-LABEL: name: test_fneg_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -355,25 +363,26 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fneg_s64 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VNEGD:%[0-9]+]]:dpr = VNEGD [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $d0 = COPY [[VNEGD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = G_FNEG %0 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fma_s32 -# CHECK-LABEL: name: test_fma_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -383,31 +392,32 @@ body: | bb.0: liveins: $s0, $s1, $s2 + ; CHECK-LABEL: name: test_fma_s32 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:spr = COPY $s2 + ; CHECK-NEXT: [[VFMAS:%[0-9]+]]:spr = nofpexcept VFMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VFMAS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = COPY $s2 - ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2 %3(s32) = G_FMA %0, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %3(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fma_s64 -# CHECK-LABEL: name: test_fma_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -417,31 +427,32 @@ body: | bb.0: liveins: $d0, $d1, $d2 + ; CHECK-LABEL: name: test_fma_s64 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK-NEXT: [[VFMAD:%[0-9]+]]:dpr = nofpexcept VFMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VFMAD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = COPY $d2 - ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 %3(s64) = G_FMA %0, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %3(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fpext_s32_to_s64 -# CHECK-LABEL: name: test_fpext_s32_to_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -449,25 +460,26 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fpext_s32_to_s64 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VCVTDS:%[0-9]+]]:dpr = nofpexcept VCVTDS [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VCVTDS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s64) = G_FPEXT %0(s32) - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fptrunc_s64_to_s32 -# CHECK-LABEL: name: test_fptrunc_s64_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -475,25 +487,26 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fptrunc_s64_to_s32 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VCVTSD:%[0-9]+]]:spr = nofpexcept VCVTSD [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VCVTSD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTRUNC %0(s64) - ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fptosi_s32 -# CHECK-LABEL: name: test_fptosi_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -501,26 +514,27 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fptosi_s32 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FPTOSI %0(s32) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_fptosi_s64 -# CHECK-LABEL: name: test_fptosi_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -528,26 +542,27 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fptosi_s64 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VTOSIZD:%[0-9]+]]:spr = nofpexcept VTOSIZD [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZD]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTOSI %0(s64) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_fptoui_s32 -# CHECK-LABEL: name: test_fptoui_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -555,26 +570,27 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fptoui_s32 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VTOUIZS:%[0-9]+]]:spr = nofpexcept VTOUIZS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZS]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FPTOUI %0(s32) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_fptoui_s64 -# CHECK-LABEL: name: test_fptoui_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -582,26 +598,27 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fptoui_s64 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VTOUIZD:%[0-9]+]]:spr = nofpexcept VTOUIZD [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZD]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTOUI %0(s64) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_sitofp_s32 -# CHECK-LABEL: name: test_sitofp_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -609,26 +626,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_sitofp_s32 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VSITOS:%[0-9]+]]:spr = nofpexcept VSITOS [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $s0 = COPY [[VSITOS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_SITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_sitofp_s64 -# CHECK-LABEL: name: test_sitofp_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -636,26 +654,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_sitofp_s64 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VSITOD:%[0-9]+]]:dpr = nofpexcept VSITOD [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $d0 = COPY [[VSITOD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s64) = G_SITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_uitofp_s32 -# CHECK-LABEL: name: test_uitofp_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -663,26 +682,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_uitofp_s32 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VUITOS:%[0-9]+]]:spr = nofpexcept VUITOS [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $s0 = COPY [[VUITOS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_UITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_uitofp_s64 -# CHECK-LABEL: name: test_uitofp_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -690,26 +710,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_uitofp_s64 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VUITOD:%[0-9]+]]:dpr = nofpexcept VUITOD [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $d0 = COPY [[VUITOD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s64) = G_UITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_load_f32 -# CHECK-LABEL: name: test_load_f32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -717,25 +738,26 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_load_f32 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) + ; CHECK-NEXT: $s0 = COPY [[VLDRS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s32) = G_LOAD %0(p0) :: (load (s32)) - ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14 /* CC::al */, $noreg $s0 = COPY %1 - ; CHECK: $s0 = COPY %[[V]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_load_f64 -# CHECK-LABEL: name: test_load_f64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -743,45 +765,50 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_load_f64 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[VLDRD:%[0-9]+]]:dpr = VLDRD [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s64)) + ; CHECK-NEXT: $d0 = COPY [[VLDRD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s64) = G_LOAD %0(p0) :: (load (s64)) - ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14 /* CC::al */, $noreg $d0 = COPY %1 - ; CHECK: $d0 = COPY %[[V]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_stores -# CHECK-LABEL: name: test_stores legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } - { id: 2, class: fprb } -# CHECK: id: [[P:[0-9]+]], class: gpr -# CHECK: id: [[F32:[0-9]+]], class: spr -# CHECK: id: [[F64:[0-9]+]], class: dpr body: | bb.0: liveins: $r0, $s0, $d0 + ; CHECK-LABEL: name: test_stores + ; CHECK: liveins: $r0, $s0, $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK-NEXT: VSTRS [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) + ; CHECK-NEXT: VSTRD [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s64)) + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg %0(p0) = COPY $r0 %1(s32) = COPY $s0 %2(s64) = COPY $d2 G_STORE %1(s32), %0(p0) :: (store (s32)) - ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14 /* CC::al */, $noreg G_STORE %2(s64), %0(p0) :: (store (s64)) - ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14 /* CC::al */, $noreg BX_RET 14, $noreg ... @@ -833,11 +860,9 @@ body: | ... --- name: test_soft_fp_double -# CHECK-LABEL: name: test_soft_fp_double legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -848,24 +873,27 @@ body: | bb.0: liveins: $r0, $r1, $r2, $r3 + ; CHECK-LABEL: name: test_soft_fp_double + ; CHECK: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r3 + ; CHECK-NEXT: [[VMOVDRR:%[0-9]+]]:dpr = VMOVDRR [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[VMOVDRR]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = COPY [[VMOVRRD]] + ; CHECK-NEXT: $r1 = COPY [[VMOVRRD1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1 %0(s32) = COPY $r2 - ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2 %1(s32) = COPY $r3 - ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3 %2(s64) = G_MERGE_VALUES %0(s32), %1(s32) - ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]] %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) - ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]] $r0 = COPY %3 - ; CHECK: $r0 = COPY [[OUT1]] $r1 = COPY %4 - ; CHECK: $r1 = COPY [[OUT2]] BX_RET 14, $noreg, implicit $r0, implicit $r1 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1 ... diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir index a6fc4da..fa982d8 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir @@ -31,7 +31,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = nofpexcept VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VFNMSD]] ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0 %0:fprb(s64) = COPY $d0 diff --git a/llvm/test/CodeGen/ARM/bf16_fast_math.ll b/llvm/test/CodeGen/ARM/bf16_fast_math.ll index 1b18ea6..5f7e1e6 100644 --- a/llvm/test/CodeGen/ARM/bf16_fast_math.ll +++ b/llvm/test/CodeGen/ARM/bf16_fast_math.ll @@ -17,7 +17,7 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -44,7 +44,7 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -71,7 +71,7 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -102,7 +102,7 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY2]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -113,7 +113,7 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR2:%[0-9]+]]:spr = VMOVSR killed [[MOVsi2]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi3:%[0-9]+]]:gpr = MOVsi [[COPY3]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR3:%[0-9]+]]:spr = VMOVSR killed [[MOVsi3]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = nofpexcept VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS killed [[VADDS1]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS1]] @@ -142,10 +142,10 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY2]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[MOVsi2:%[0-9]+]]:gpr = MOVsi [[COPY]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR2:%[0-9]+]]:spr = VMOVSR killed [[MOVsi2]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VADDS]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS1]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -174,7 +174,7 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY2]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -185,7 +185,7 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR2:%[0-9]+]]:spr = VMOVSR killed [[MOVsi2]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi3:%[0-9]+]]:gpr = MOVsi [[COPY3]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR3:%[0-9]+]]:spr = VMOVSR killed [[MOVsi3]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS killed [[VADDS1]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS1]] diff --git a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir index 1bee32f..fe23e85 100644 --- a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir +++ b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir @@ -22,15 +22,16 @@ body: | ; CHECK-LABEL: name: test_groups ; CHECK: liveins: $d0, $r0, $r1, $r2, $r3, $r4 - ; CHECK: renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg - ; CHECK: VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg - ; CHECK: t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = t2ADDrr killed renamable $r4, renamable $r4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: renamable $r4 = t2ADDrr killed renamable $r4, renamable $r4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $d0 renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg - renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg + renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg, implicit $fpscr_rm VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir index 8e671c9..f5b2e98 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir @@ -81,7 +81,7 @@ body: | STRi12 killed renamable $r1, killed renamable $r0, 0, 14, $noreg :: (volatile store (s32) into %ir.LL, align 8) dead renamable $r0 = SPACE 8920, undef renamable $r0 renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S) - renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg + renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg, implicit $fpscr_rm VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S) renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg dead renamable $r1 = SPACE 1350, undef renamable $r0 diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir index 03ddd80..4b66476 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir @@ -72,7 +72,7 @@ body: | renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S) renamable $s0 = VLDRH %const.1, 0, 14, $noreg :: (load (s16) from constant-pool) dead renamable $r0 = SPACE 1230, undef renamable $r0 - renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg + renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg, implicit $fpscr_rm VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S) renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg dead renamable $r1 = SPACE 1330, undef renamable $r0 diff --git a/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir index 46f028b..c16a62a 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir @@ -89,7 +89,7 @@ body: | $sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg frame-setup CFI_INSTRUCTION def_cfa_offset 4 renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load (s16) from constant-pool) - VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv + VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (store (s16) into %ir.res) FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv Bcc %bb.2, 0, killed $cpsr diff --git a/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir index 5a03fcd..049b7d9 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir @@ -95,7 +95,7 @@ body: | $sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg frame-setup CFI_INSTRUCTION def_cfa_offset 4 renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load (s16) from constant-pool) - VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv + VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (store (s16) into %ir.res) FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv Bcc %bb.2, 0, killed $cpsr diff --git a/llvm/test/CodeGen/ARM/fp16_fast_math.ll b/llvm/test/CodeGen/ARM/fp16_fast_math.ll index 165eb4b..47e1f84f 100644 --- a/llvm/test/CodeGen/ARM/fp16_fast_math.ll +++ b/llvm/test/CodeGen/ARM/fp16_fast_math.ll @@ -16,11 +16,11 @@ define half @normal_fadd(half %x, half %y) { ; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]] ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -33,7 +33,7 @@ define half @normal_fadd(half %x, half %y) { ; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -50,11 +50,11 @@ define half @fast_fadd(half %x, half %y) { ; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]] ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -67,7 +67,7 @@ define half @fast_fadd(half %x, half %y) { ; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf nsz arcp contract afn reassoc VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf nsz arcp contract afn reassoc nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -84,11 +84,11 @@ define half @ninf_fadd(half %x, half %y) { ; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]] ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -101,7 +101,7 @@ define half @ninf_fadd(half %x, half %y) { ; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -122,19 +122,19 @@ define half @normal_fadd_sequence(half %x, half %y, half %z) { ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]] ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]] - ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nofpexcept VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -148,9 +148,9 @@ define half @normal_fadd_sequence(half %x, half %y, half %z) { ; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nofpexcept VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -169,14 +169,14 @@ define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) { ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]] ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf contract nofpexcept VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf contract nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nnan ninf contract nofpexcept VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY6]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -190,9 +190,9 @@ define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) { ; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf contract VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf contract nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nnan ninf contract VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nnan ninf contract nofpexcept VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -211,19 +211,19 @@ define half @ninf_fadd_sequence(half %x, half %y, half %z) { ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]] ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]] - ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -237,9 +237,9 @@ define half @ninf_fadd_sequence(half %x, half %y, half %z) { ; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = ninf VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = ninf nofpexcept VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: diff --git a/llvm/test/CodeGen/ARM/ipra-reg-usage.ll b/llvm/test/CodeGen/ARM/ipra-reg-usage.ll index c928390..90142cb 100644 --- a/llvm/test/CodeGen/ARM/ipra-reg-usage.ll +++ b/llvm/test/CodeGen/ARM/ipra-reg-usage.ll @@ -6,7 +6,7 @@ target triple = "armv7-eabi" declare void @bar1() define void @foo()#0 { -; CHECK: foo Clobbered Registers: $apsr $apsr_nzcv $cpsr $fpcxtns $fpcxts $fpexc $fpinst $fpscr $fpscr_nzcv $fpscr_nzcvqc $fpsid $itstate $pc $ra_auth_code $sp $spsr $vpr $zr $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $fpinst2 $mvfr0 $mvfr1 $mvfr2 $p0 $q0 $q1 $q2 $q3 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $r0 $r1 $r2 $r3 $r12 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s8 $s9 $s10 $s11 $s12 $s13 $s14 $s15 $d0_d2 $d1_d3 $d2_d4 $d3_d5 $d4_d6 $d5_d7 $d6_d8 $d7_d9 $d14_d16 $d15_d17 $d16_d18 $d17_d19 $d18_d20 $d19_d21 $d20_d22 $d21_d23 $d22_d24 $d23_d25 $d24_d26 $d25_d27 $d26_d28 $d27_d29 $d28_d30 $d29_d31 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $r0_r1 $r2_r3 $r12_sp $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d0_d2_d4 $d1_d3_d5 $d2_d4_d6 $d3_d5_d7 $d4_d6_d8 $d5_d7_d9 $d6_d8_d10 $d7_d9_d11 $d12_d14_d16 $d13_d15_d17 $d14_d16_d18 $d15_d17_d19 $d16_d18_d20 $d17_d19_d21 $d18_d20_d22 $d19_d21_d23 $d20_d22_d24 $d21_d23_d25 $d22_d24_d26 $d23_d25_d27 $d24_d26_d28 $d25_d27_d29 $d26_d28_d30 $d27_d29_d31 $d0_d2_d4_d6 $d1_d3_d5_d7 $d2_d4_d6_d8 $d3_d5_d7_d9 $d4_d6_d8_d10 $d5_d7_d9_d11 $d6_d8_d10_d12 $d7_d9_d11_d13 $d10_d12_d14_d16 $d11_d13_d15_d17 $d12_d14_d16_d18 $d13_d15_d17_d19 $d14_d16_d18_d20 $d15_d17_d19_d21 $d16_d18_d20_d22 $d17_d19_d21_d23 $d18_d20_d22_d24 $d19_d21_d23_d25 $d20_d22_d24_d26 $d21_d23_d25_d27 $d22_d24_d26_d28 $d23_d25_d27_d29 $d24_d26_d28_d30 $d25_d27_d29_d31 $d1_d2 $d3_d4 $d5_d6 $d7_d8 $d15_d16 $d17_d18 $d19_d20 $d21_d22 $d23_d24 $d25_d26 $d27_d28 $d29_d30 $d1_d2_d3_d4 $d3_d4_d5_d6 $d5_d6_d7_d8 $d7_d8_d9_d10 $d13_d14_d15_d16 $d15_d16_d17_d18 $d17_d18_d19_d20 $d19_d20_d21_d22 $d21_d22_d23_d24 $d23_d24_d25_d26 $d25_d26_d27_d28 $d27_d28_d29_d30 +; CHECK: foo Clobbered Registers: $apsr $apsr_nzcv $cpsr $fpcxtns $fpcxts $fpexc $fpinst $fpscr $fpscr_nzcv $fpscr_nzcvqc $fpscr_rm $fpsid $itstate $pc $ra_auth_code $sp $spsr $vpr $zr $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $fpinst2 $mvfr0 $mvfr1 $mvfr2 $p0 $q0 $q1 $q2 $q3 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $r0 $r1 $r2 $r3 $r12 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s8 $s9 $s10 $s11 $s12 $s13 $s14 $s15 $d0_d2 $d1_d3 $d2_d4 $d3_d5 $d4_d6 $d5_d7 $d6_d8 $d7_d9 $d14_d16 $d15_d17 $d16_d18 $d17_d19 $d18_d20 $d19_d21 $d20_d22 $d21_d23 $d22_d24 $d23_d25 $d24_d26 $d25_d27 $d26_d28 $d27_d29 $d28_d30 $d29_d31 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $r0_r1 $r2_r3 $r12_sp $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d0_d2_d4 $d1_d3_d5 $d2_d4_d6 $d3_d5_d7 $d4_d6_d8 $d5_d7_d9 $d6_d8_d10 $d7_d9_d11 $d12_d14_d16 $d13_d15_d17 $d14_d16_d18 $d15_d17_d19 $d16_d18_d20 $d17_d19_d21 $d18_d20_d22 $d19_d21_d23 $d20_d22_d24 $d21_d23_d25 $d22_d24_d26 $d23_d25_d27 $d24_d26_d28 $d25_d27_d29 $d26_d28_d30 $d27_d29_d31 $d0_d2_d4_d6 $d1_d3_d5_d7 $d2_d4_d6_d8 $d3_d5_d7_d9 $d4_d6_d8_d10 $d5_d7_d9_d11 $d6_d8_d10_d12 $d7_d9_d11_d13 $d10_d12_d14_d16 $d11_d13_d15_d17 $d12_d14_d16_d18 $d13_d15_d17_d19 $d14_d16_d18_d20 $d15_d17_d19_d21 $d16_d18_d20_d22 $d17_d19_d21_d23 $d18_d20_d22_d24 $d19_d21_d23_d25 $d20_d22_d24_d26 $d21_d23_d25_d27 $d22_d24_d26_d28 $d23_d25_d27_d29 $d24_d26_d28_d30 $d25_d27_d29_d31 $d1_d2 $d3_d4 $d5_d6 $d7_d8 $d15_d16 $d17_d18 $d19_d20 $d21_d22 $d23_d24 $d25_d26 $d27_d28 $d29_d30 $d1_d2_d3_d4 $d3_d4_d5_d6 $d5_d6_d7_d8 $d7_d8_d9_d10 $d13_d14_d15_d16 $d15_d16_d17_d18 $d17_d18_d19_d20 $d19_d20_d21_d22 $d21_d22_d23_d24 $d23_d24_d25_d26 $d25_d26_d27_d28 $d27_d28_d29_d30 call void @bar1() call void @bar2() ret void diff --git a/llvm/test/CodeGen/ARM/llrint-conv.ll b/llvm/test/CodeGen/ARM/llrint-conv.ll index a1a04db..7274a8b 100644 --- a/llvm/test/CodeGen/ARM/llrint-conv.ll +++ b/llvm/test/CodeGen/ARM/llrint-conv.ll @@ -1,7 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT ; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16 -; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 define i64 @testmsxh_builtin(half %x) { ; CHECK-SOFT-LABEL: testmsxh_builtin: @@ -22,6 +23,14 @@ define i64 @testmsxh_builtin(half %x) { ; CHECK-NOFP16-NEXT: bl llrintf ; CHECK-NOFP16-NEXT: pop {r11, pc} ; +; CHECK-FPv8-LABEL: testmsxh_builtin: +; CHECK-FPv8: @ %bb.0: @ %entry +; CHECK-FPv8-NEXT: .save {r11, lr} +; CHECK-FPv8-NEXT: push {r11, lr} +; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0 +; CHECK-FPv8-NEXT: bl llrintf +; CHECK-FPv8-NEXT: pop {r11, pc} +; ; CHECK-FP16-LABEL: testmsxh_builtin: ; CHECK-FP16: @ %bb.0: @ %entry ; CHECK-FP16-NEXT: .save {r11, lr} diff --git a/llvm/test/CodeGen/ARM/lrint-conv.ll b/llvm/test/CodeGen/ARM/lrint-conv.ll index 23a2685..2de2349 100644 --- a/llvm/test/CodeGen/ARM/lrint-conv.ll +++ b/llvm/test/CodeGen/ARM/lrint-conv.ll @@ -1,14 +1,43 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT ; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16 -; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 -; FIXME: crash -; define i32 @testmswh_builtin(half %x) { -; entry: -; %0 = tail call i32 @llvm.lrint.i32.f16(half %x) -; ret i32 %0 -; } +define i32 @testmswh_builtin(half %x) { +; CHECK-SOFT-LABEL: testmswh_builtin: +; CHECK-SOFT: @ %bb.0: @ %entry +; CHECK-SOFT-NEXT: .save {r11, lr} +; CHECK-SOFT-NEXT: push {r11, lr} +; CHECK-SOFT-NEXT: bl __aeabi_h2f +; CHECK-SOFT-NEXT: pop {r11, lr} +; CHECK-SOFT-NEXT: b lrintf +; +; CHECK-NOFP16-LABEL: testmswh_builtin: +; CHECK-NOFP16: @ %bb.0: @ %entry +; CHECK-NOFP16-NEXT: .save {r11, lr} +; CHECK-NOFP16-NEXT: push {r11, lr} +; CHECK-NOFP16-NEXT: vmov r0, s0 +; CHECK-NOFP16-NEXT: bl __aeabi_h2f +; CHECK-NOFP16-NEXT: vmov s0, r0 +; CHECK-NOFP16-NEXT: pop {r11, lr} +; CHECK-NOFP16-NEXT: b lrintf +; +; CHECK-FPv8-LABEL: testmswh_builtin: +; CHECK-FPv8: @ %bb.0: @ %entry +; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0 +; CHECK-FPv8-NEXT: b lrintf +; +; CHECK-FP16-LABEL: testmswh_builtin: +; CHECK-FP16: @ %bb.0: @ %entry +; CHECK-FP16-NEXT: vrintx.f16 s0, s0 +; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s0 +; CHECK-FP16-NEXT: vmov r0, s0 +; CHECK-FP16-NEXT: bx lr +entry: + %0 = tail call i32 @llvm.lrint.i32.f16(half %x) + ret i32 %0 +} define i32 @testmsws_builtin(float %x) { ; CHECK-LABEL: testmsws_builtin: @@ -39,8 +68,3 @@ entry: %0 = tail call i32 @llvm.lrint.i32.f128(fp128 %x) ret i32 %0 } - -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK-FP16: {{.*}} -; CHECK-NOFP16: {{.*}} -; CHECK-SOFT: {{.*}} diff --git a/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir b/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir index 46f3e4b..17d6619 100644 --- a/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir +++ b/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir @@ -14,7 +14,7 @@ # CHECK: SU(1): %1:dpr = VABSD %0:dpr, 14, $noreg # CHECK: SU(2): %2:dpr = VLDRD %const.0, 0, 14, $noreg :: (load (s64) from constant-pool) # CHECK: SU(4): %3:rgpr = t2MOVi 0, 14, $noreg, $noreg -# CHECK: SU(3): VCMPD %1:dpr, %2:dpr, 14, $noreg, implicit-def $fpscr_nzcv +# CHECK: SU(3): VCMPD %1:dpr, %2:dpr, 14, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm # CHECK: SU(5): $r0 = COPY %3:rgpr --- name: test @@ -29,7 +29,7 @@ body: | %0:dpr = COPY $d0 %1:dpr = VABSD %0, 14 /* CC::al */, $noreg %2:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load (s64) from constant-pool) - VCMPD %1, %2, 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv + VCMPD %1, %2, 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm %4:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg $r0 = COPY %4 tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 diff --git a/llvm/test/CodeGen/ARM/vector-lrint.ll b/llvm/test/CodeGen/ARM/vector-lrint.ll index c1159da..c3c8884 100644 --- a/llvm/test/CodeGen/ARM/vector-lrint.ll +++ b/llvm/test/CodeGen/ARM/vector-lrint.ll @@ -9,31 +9,1290 @@ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon | FileCheck %s --check-prefixes=BE-I32 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon | FileCheck %s --check-prefixes=BE-I64 -; FIXME: crash "Do not know how to soft promote this operator's operand!" -; define <1 x iXLen> @lrint_v1f16(<1 x half> %x) { -; %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x) -; ret <1 x iXLen> %a -; } +define <1 x iXLen> @lrint_v1f16(<1 x half> %x) { +; LE-I32-LABEL: lrint_v1f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r11, lr} +; LE-I32-NEXT: push {r11, lr} +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: bl __aeabi_f2h +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: pop {r11, pc} +; +; LE-I64-LABEL: lrint_v1f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r11, lr} +; LE-I64-NEXT: push {r11, lr} +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_f2h +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d0[0], r0 +; LE-I64-NEXT: vmov.32 d0[1], r1 +; LE-I64-NEXT: pop {r11, pc} +; +; BE-I32-LABEL: lrint_v1f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r11, lr} +; BE-I32-NEXT: push {r11, lr} +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_f2h +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: pop {r11, pc} +; +; BE-I64-LABEL: lrint_v1f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r11, lr} +; BE-I64-NEXT: push {r11, lr} +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: bl __aeabi_f2h +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d0, d16 +; BE-I64-NEXT: pop {r11, pc} + %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x) + ret <1 x iXLen> %a +} -; define <2 x iXLen> @lrint_v2f16(<2 x half> %x) { -; %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x) -; ret <2 x iXLen> %a -; } +define <2 x iXLen> @lrint_v2f16(<2 x half> %x) { +; LE-I32-LABEL: lrint_v2f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r11, lr} +; LE-I32-NEXT: push {r11, lr} +; LE-I32-NEXT: .vsave {d8} +; LE-I32-NEXT: vpush {d8} +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: vmov.f32 s16, s1 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov r1, s16 +; LE-I32-NEXT: vmov.32 d8[0], r0 +; LE-I32-NEXT: mov r0, r1 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d8[1], r0 +; LE-I32-NEXT: vorr d0, d8, d8 +; LE-I32-NEXT: vpop {d8} +; LE-I32-NEXT: pop {r11, pc} +; +; LE-I64-LABEL: lrint_v2f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r11, lr} +; LE-I64-NEXT: push {r4, r5, r11, lr} +; LE-I64-NEXT: .vsave {d8, d9} +; LE-I64-NEXT: vpush {d8, d9} +; LE-I64-NEXT: vmov r0, s1 +; LE-I64-NEXT: vmov.f32 s16, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r4, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d9[0], r4 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: vmov.32 d9[1], r5 +; LE-I64-NEXT: vmov.32 d8[1], r1 +; LE-I64-NEXT: vorr q0, q4, q4 +; LE-I64-NEXT: vpop {d8, d9} +; LE-I64-NEXT: pop {r4, r5, r11, pc} +; +; BE-I32-LABEL: lrint_v2f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r11, lr} +; BE-I32-NEXT: push {r11, lr} +; BE-I32-NEXT: .vsave {d8} +; BE-I32-NEXT: vpush {d8} +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: vmov.f32 s16, s1 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov r1, s16 +; BE-I32-NEXT: vmov.32 d8[0], r0 +; BE-I32-NEXT: mov r0, r1 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d8[1], r0 +; BE-I32-NEXT: vrev64.32 d0, d8 +; BE-I32-NEXT: vpop {d8} +; BE-I32-NEXT: pop {r11, pc} +; +; BE-I64-LABEL: lrint_v2f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r11, lr} +; BE-I64-NEXT: push {r4, r5, r11, lr} +; BE-I64-NEXT: .vsave {d8} +; BE-I64-NEXT: vpush {d8} +; BE-I64-NEXT: vmov r0, s1 +; BE-I64-NEXT: vmov.f32 s16, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d8[0], r4 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov.32 d8[1], r5 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d8 +; BE-I64-NEXT: vrev64.32 d0, d16 +; BE-I64-NEXT: vpop {d8} +; BE-I64-NEXT: pop {r4, r5, r11, pc} + %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x) + ret <2 x iXLen> %a +} -; define <4 x iXLen> @lrint_v4f16(<4 x half> %x) { -; %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x) -; ret <4 x iXLen> %a -; } +define <4 x iXLen> @lrint_v4f16(<4 x half> %x) { +; LE-I32-LABEL: lrint_v4f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r4, r5, r11, lr} +; LE-I32-NEXT: push {r4, r5, r11, lr} +; LE-I32-NEXT: .vsave {d8, d9, d10, d11} +; LE-I32-NEXT: vpush {d8, d9, d10, d11} +; LE-I32-NEXT: vmov r0, s3 +; LE-I32-NEXT: vmov.f32 s16, s2 +; LE-I32-NEXT: vmov.f32 s18, s1 +; LE-I32-NEXT: vmov.f32 s20, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: mov r4, r0 +; LE-I32-NEXT: vmov r0, s16 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r5, r0 +; LE-I32-NEXT: vmov r0, s20 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r5 +; LE-I32-NEXT: vmov.32 d10[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d11[0], r0 +; LE-I32-NEXT: vmov r0, s18 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: vmov.32 d11[1], r4 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[1], r0 +; LE-I32-NEXT: vorr q0, q5, q5 +; LE-I32-NEXT: vpop {d8, d9, d10, d11} +; LE-I32-NEXT: pop {r4, r5, r11, pc} +; +; LE-I64-LABEL: lrint_v4f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r6, r7, r11, lr} +; LE-I64-NEXT: push {r4, r5, r6, r7, r11, lr} +; LE-I64-NEXT: .vsave {d12, d13} +; LE-I64-NEXT: vpush {d12, d13} +; LE-I64-NEXT: .vsave {d8, d9, d10} +; LE-I64-NEXT: vpush {d8, d9, d10} +; LE-I64-NEXT: vmov r0, s1 +; LE-I64-NEXT: vmov.f32 s16, s3 +; LE-I64-NEXT: vmov.f32 s20, s2 +; LE-I64-NEXT: vmov.f32 s18, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s18 +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r7 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: vmov.32 d9[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d12[0], r0 +; LE-I64-NEXT: vmov r0, s20 +; LE-I64-NEXT: mov r7, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d13[0], r5 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: vmov.32 d13[1], r4 +; LE-I64-NEXT: vmov.32 d9[1], r6 +; LE-I64-NEXT: vmov.32 d12[1], r7 +; LE-I64-NEXT: vmov.32 d8[1], r1 +; LE-I64-NEXT: vorr q0, q6, q6 +; LE-I64-NEXT: vorr q1, q4, q4 +; LE-I64-NEXT: vpop {d8, d9, d10} +; LE-I64-NEXT: vpop {d12, d13} +; LE-I64-NEXT: pop {r4, r5, r6, r7, r11, pc} +; +; BE-I32-LABEL: lrint_v4f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r4, r5, r11, lr} +; BE-I32-NEXT: push {r4, r5, r11, lr} +; BE-I32-NEXT: .vsave {d8, d9, d10, d11} +; BE-I32-NEXT: vpush {d8, d9, d10, d11} +; BE-I32-NEXT: vmov r0, s3 +; BE-I32-NEXT: vmov.f32 s16, s2 +; BE-I32-NEXT: vmov.f32 s18, s1 +; BE-I32-NEXT: vmov.f32 s20, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: mov r4, r0 +; BE-I32-NEXT: vmov r0, s16 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r5, r0 +; BE-I32-NEXT: vmov r0, s20 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r5 +; BE-I32-NEXT: vmov.32 d10[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d11[0], r0 +; BE-I32-NEXT: vmov r0, s18 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: vmov.32 d11[1], r4 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d10[1], r0 +; BE-I32-NEXT: vrev64.32 q0, q5 +; BE-I32-NEXT: vpop {d8, d9, d10, d11} +; BE-I32-NEXT: pop {r4, r5, r11, pc} +; +; BE-I64-LABEL: lrint_v4f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r6, r7, r11, lr} +; BE-I64-NEXT: push {r4, r5, r6, r7, r11, lr} +; BE-I64-NEXT: .vsave {d8, d9, d10} +; BE-I64-NEXT: vpush {d8, d9, d10} +; BE-I64-NEXT: vmov r0, s1 +; BE-I64-NEXT: vmov.f32 s16, s3 +; BE-I64-NEXT: vmov.f32 s18, s2 +; BE-I64-NEXT: vmov.f32 s20, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r5, r0 +; BE-I64-NEXT: vmov r0, s20 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r7, r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r7 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: vmov.32 d8[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d10[0], r0 +; BE-I64-NEXT: vmov r0, s18 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d9[0], r5 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov.32 d9[1], r4 +; BE-I64-NEXT: vmov.32 d8[1], r6 +; BE-I64-NEXT: vmov.32 d10[1], r7 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d9 +; BE-I64-NEXT: vrev64.32 d3, d8 +; BE-I64-NEXT: vrev64.32 d0, d10 +; BE-I64-NEXT: vrev64.32 d2, d16 +; BE-I64-NEXT: vpop {d8, d9, d10} +; BE-I64-NEXT: pop {r4, r5, r6, r7, r11, pc} + %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x) + ret <4 x iXLen> %a +} -; define <8 x iXLen> @lrint_v8f16(<8 x half> %x) { -; %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x) -; ret <8 x iXLen> %a -; } +define <8 x iXLen> @lrint_v8f16(<8 x half> %x) { +; LE-I32-LABEL: lrint_v8f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr} +; LE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr} +; LE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} +; LE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} +; LE-I32-NEXT: vmov r0, s7 +; LE-I32-NEXT: vmov.f32 s18, s6 +; LE-I32-NEXT: vmov.f32 s16, s5 +; LE-I32-NEXT: vmov.f32 s20, s4 +; LE-I32-NEXT: vmov.f32 s22, s3 +; LE-I32-NEXT: vmov.f32 s24, s2 +; LE-I32-NEXT: vmov.f32 s26, s1 +; LE-I32-NEXT: vmov.f32 s28, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: mov r8, r0 +; LE-I32-NEXT: vmov r0, s26 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r9, r0 +; LE-I32-NEXT: vmov r0, s22 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r6, r0 +; LE-I32-NEXT: vmov r0, s28 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r7, r0 +; LE-I32-NEXT: vmov r0, s24 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r4, r0 +; LE-I32-NEXT: vmov r0, s18 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r5, r0 +; LE-I32-NEXT: vmov r0, s20 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r5 +; LE-I32-NEXT: vmov.32 d10[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r4 +; LE-I32-NEXT: vmov.32 d11[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r7 +; LE-I32-NEXT: vmov.32 d13[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r6 +; LE-I32-NEXT: vmov.32 d12[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r9 +; LE-I32-NEXT: vmov.32 d13[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d12[1], r0 +; LE-I32-NEXT: vmov r0, s16 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: vmov.32 d11[1], r8 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[1], r0 +; LE-I32-NEXT: vorr q0, q6, q6 +; LE-I32-NEXT: vorr q1, q5, q5 +; LE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} +; LE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc} +; +; LE-I64-LABEL: lrint_v8f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: .pad #4 +; LE-I64-NEXT: sub sp, sp, #4 +; LE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: .pad #8 +; LE-I64-NEXT: sub sp, sp, #8 +; LE-I64-NEXT: vmov r0, s1 +; LE-I64-NEXT: vstr s6, [sp, #4] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s16, s7 +; LE-I64-NEXT: vmov.f32 s18, s5 +; LE-I64-NEXT: vmov.f32 s20, s4 +; LE-I64-NEXT: vmov.f32 s22, s3 +; LE-I64-NEXT: vmov.f32 s24, s2 +; LE-I64-NEXT: vmov.f32 s26, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r9, r0 +; LE-I64-NEXT: vmov r0, s26 +; LE-I64-NEXT: str r1, [sp] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r10, r0 +; LE-I64-NEXT: vmov r0, s22 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s24 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov r0, s18 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: vmov r0, s20 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r4, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r4 +; LE-I64-NEXT: mov r11, r1 +; LE-I64-NEXT: vmov.32 d11[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r6 +; LE-I64-NEXT: mov r8, r1 +; LE-I64-NEXT: vmov.32 d12[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r7 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: vmov.32 d13[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r5 +; LE-I64-NEXT: mov r7, r1 +; LE-I64-NEXT: vmov.32 d14[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r10 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: vmov.32 d15[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vldr s0, [sp, #4] @ 4-byte Reload +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d9[0], r9 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d10[0], r0 +; LE-I64-NEXT: ldr r0, [sp] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d15[1], r5 +; LE-I64-NEXT: vmov.32 d9[1], r0 +; LE-I64-NEXT: vmov.32 d13[1], r6 +; LE-I64-NEXT: vmov.32 d11[1], r11 +; LE-I64-NEXT: vmov.32 d8[1], r4 +; LE-I64-NEXT: vmov.32 d14[1], r7 +; LE-I64-NEXT: vorr q0, q4, q4 +; LE-I64-NEXT: vmov.32 d12[1], r8 +; LE-I64-NEXT: vorr q1, q7, q7 +; LE-I64-NEXT: vmov.32 d10[1], r1 +; LE-I64-NEXT: vorr q2, q6, q6 +; LE-I64-NEXT: vorr q3, q5, q5 +; LE-I64-NEXT: add sp, sp, #8 +; LE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: add sp, sp, #4 +; LE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} +; +; BE-I32-LABEL: lrint_v8f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr} +; BE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr} +; BE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} +; BE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} +; BE-I32-NEXT: vmov r0, s1 +; BE-I32-NEXT: vmov.f32 s18, s7 +; BE-I32-NEXT: vmov.f32 s20, s6 +; BE-I32-NEXT: vmov.f32 s16, s5 +; BE-I32-NEXT: vmov.f32 s22, s4 +; BE-I32-NEXT: vmov.f32 s24, s3 +; BE-I32-NEXT: vmov.f32 s26, s2 +; BE-I32-NEXT: vmov.f32 s28, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: mov r8, r0 +; BE-I32-NEXT: vmov r0, s24 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r9, r0 +; BE-I32-NEXT: vmov r0, s18 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r6, r0 +; BE-I32-NEXT: vmov r0, s26 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r7, r0 +; BE-I32-NEXT: vmov r0, s20 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r4, r0 +; BE-I32-NEXT: vmov r0, s28 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r5, r0 +; BE-I32-NEXT: vmov r0, s22 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r5 +; BE-I32-NEXT: vmov.32 d10[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r4 +; BE-I32-NEXT: vmov.32 d12[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r7 +; BE-I32-NEXT: vmov.32 d11[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r6 +; BE-I32-NEXT: vmov.32 d13[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r9 +; BE-I32-NEXT: vmov.32 d11[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d13[1], r0 +; BE-I32-NEXT: vmov r0, s16 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: vmov.32 d12[1], r8 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d10[1], r0 +; BE-I32-NEXT: vrev64.32 q0, q6 +; BE-I32-NEXT: vrev64.32 q1, q5 +; BE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} +; BE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc} +; +; BE-I64-LABEL: lrint_v8f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: .pad #4 +; BE-I64-NEXT: sub sp, sp, #4 +; BE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} +; BE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} +; BE-I64-NEXT: .pad #8 +; BE-I64-NEXT: sub sp, sp, #8 +; BE-I64-NEXT: vmov r0, s1 +; BE-I64-NEXT: vmov.f32 s18, s7 +; BE-I64-NEXT: vmov.f32 s16, s6 +; BE-I64-NEXT: vmov.f32 s20, s5 +; BE-I64-NEXT: vmov.f32 s22, s4 +; BE-I64-NEXT: vmov.f32 s24, s3 +; BE-I64-NEXT: vmov.f32 s26, s2 +; BE-I64-NEXT: vmov.f32 s28, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r9, r0 +; BE-I64-NEXT: vmov r0, s28 +; BE-I64-NEXT: str r1, [sp, #4] @ 4-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r10, r0 +; BE-I64-NEXT: vmov r0, s24 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r5, r0 +; BE-I64-NEXT: vmov r0, s26 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r7, r0 +; BE-I64-NEXT: vmov r0, s20 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r6, r0 +; BE-I64-NEXT: vmov r0, s22 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov r0, s18 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r4 +; BE-I64-NEXT: mov r11, r1 +; BE-I64-NEXT: vmov.32 d9[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r6 +; BE-I64-NEXT: mov r8, r1 +; BE-I64-NEXT: vmov.32 d10[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r7 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: vmov.32 d11[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r5 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: vmov.32 d12[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r10 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: vmov.32 d13[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d14[0], r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d8[0], r9 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: ldr r0, [sp, #4] @ 4-byte Reload +; BE-I64-NEXT: vmov.32 d13[1], r5 +; BE-I64-NEXT: vmov.32 d8[1], r0 +; BE-I64-NEXT: vmov.32 d11[1], r6 +; BE-I64-NEXT: vmov.32 d9[1], r11 +; BE-I64-NEXT: vmov.32 d14[1], r4 +; BE-I64-NEXT: vmov.32 d12[1], r7 +; BE-I64-NEXT: vmov.32 d10[1], r8 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d8 +; BE-I64-NEXT: vrev64.32 d3, d13 +; BE-I64-NEXT: vrev64.32 d5, d11 +; BE-I64-NEXT: vrev64.32 d7, d9 +; BE-I64-NEXT: vrev64.32 d0, d14 +; BE-I64-NEXT: vrev64.32 d2, d12 +; BE-I64-NEXT: vrev64.32 d4, d10 +; BE-I64-NEXT: vrev64.32 d6, d16 +; BE-I64-NEXT: add sp, sp, #8 +; BE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} +; BE-I64-NEXT: add sp, sp, #4 +; BE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x) + ret <8 x iXLen> %a +} -; define <16 x iXLen> @lrint_v16f16(<16 x half> %x) { -; %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x) -; ret <16 x iXLen> %a -; } +define <16 x iXLen> @lrint_v16f16(<16 x half> %x) { +; LE-I32-LABEL: lrint_v16f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} +; LE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} +; LE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I32-NEXT: .pad #8 +; LE-I32-NEXT: sub sp, sp, #8 +; LE-I32-NEXT: vmov r0, s15 +; LE-I32-NEXT: vstr s13, [sp, #4] @ 4-byte Spill +; LE-I32-NEXT: vmov.f32 s26, s14 +; LE-I32-NEXT: vstr s0, [sp] @ 4-byte Spill +; LE-I32-NEXT: vmov.f32 s20, s12 +; LE-I32-NEXT: vmov.f32 s22, s11 +; LE-I32-NEXT: vmov.f32 s18, s10 +; LE-I32-NEXT: vmov.f32 s17, s9 +; LE-I32-NEXT: vmov.f32 s24, s8 +; LE-I32-NEXT: vmov.f32 s19, s7 +; LE-I32-NEXT: vmov.f32 s30, s6 +; LE-I32-NEXT: vmov.f32 s21, s5 +; LE-I32-NEXT: vmov.f32 s16, s4 +; LE-I32-NEXT: vmov.f32 s23, s3 +; LE-I32-NEXT: vmov.f32 s28, s2 +; LE-I32-NEXT: vmov.f32 s25, s1 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: mov r8, r0 +; LE-I32-NEXT: vmov r0, s17 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r9, r0 +; LE-I32-NEXT: vmov r0, s22 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r10, r0 +; LE-I32-NEXT: vmov r0, s21 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r7, r0 +; LE-I32-NEXT: vmov r0, s19 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r4, r0 +; LE-I32-NEXT: vmov r0, s25 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r5, r0 +; LE-I32-NEXT: vmov r0, s23 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r6, r0 +; LE-I32-NEXT: vmov r0, s20 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[0], r0 +; LE-I32-NEXT: vmov r0, s26 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d11[0], r0 +; LE-I32-NEXT: vmov r0, s24 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d12[0], r0 +; LE-I32-NEXT: vmov r0, s18 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d13[0], r0 +; LE-I32-NEXT: vmov r0, s16 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d8[0], r0 +; LE-I32-NEXT: vmov r0, s30 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d9[0], r0 +; LE-I32-NEXT: vmov r0, s28 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vldr s0, [sp] @ 4-byte Reload +; LE-I32-NEXT: vmov.32 d15[0], r0 +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r6 +; LE-I32-NEXT: vmov.32 d14[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r5 +; LE-I32-NEXT: vmov.32 d15[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r4 +; LE-I32-NEXT: vmov.32 d14[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r7 +; LE-I32-NEXT: vmov.32 d9[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r10 +; LE-I32-NEXT: vmov.32 d8[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r9 +; LE-I32-NEXT: vmov.32 d13[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vldr s0, [sp, #4] @ 4-byte Reload +; LE-I32-NEXT: vmov.32 d12[1], r0 +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: vmov.32 d11[1], r8 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[1], r0 +; LE-I32-NEXT: vorr q0, q7, q7 +; LE-I32-NEXT: vorr q1, q4, q4 +; LE-I32-NEXT: vorr q2, q6, q6 +; LE-I32-NEXT: vorr q3, q5, q5 +; LE-I32-NEXT: add sp, sp, #8 +; LE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} +; +; LE-I64-LABEL: lrint_v16f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: .pad #4 +; LE-I64-NEXT: sub sp, sp, #4 +; LE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: .pad #120 +; LE-I64-NEXT: sub sp, sp, #120 +; LE-I64-NEXT: mov r11, r0 +; LE-I64-NEXT: vmov r0, s7 +; LE-I64-NEXT: vstr s15, [sp, #24] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s23, s13 +; LE-I64-NEXT: vstr s14, [sp, #100] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s25, s12 +; LE-I64-NEXT: vmov.f32 s27, s11 +; LE-I64-NEXT: vstr s10, [sp, #104] @ 4-byte Spill +; LE-I64-NEXT: vstr s9, [sp, #108] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s24, s8 +; LE-I64-NEXT: vmov.f32 s19, s6 +; LE-I64-NEXT: vmov.f32 s29, s5 +; LE-I64-NEXT: vmov.f32 s17, s4 +; LE-I64-NEXT: vmov.f32 s16, s3 +; LE-I64-NEXT: vmov.f32 s21, s2 +; LE-I64-NEXT: vmov.f32 s26, s1 +; LE-I64-NEXT: vmov.f32 s18, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov r0, s25 +; LE-I64-NEXT: str r1, [sp, #56] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s27 +; LE-I64-NEXT: str r1, [sp, #116] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: vmov r0, s29 +; LE-I64-NEXT: str r1, [sp, #112] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d15[0], r0 +; LE-I64-NEXT: vmov r0, s23 +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: add lr, sp, #80 +; LE-I64-NEXT: vmov.32 d17[0], r6 +; LE-I64-NEXT: vstmia lr, {d16, d17} @ 16-byte Spill +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: vmov r0, s17 +; LE-I64-NEXT: vmov r8, s21 +; LE-I64-NEXT: str r1, [sp, #76] @ 4-byte Spill +; LE-I64-NEXT: vmov r10, s19 +; LE-I64-NEXT: vmov.32 d10[0], r5 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: add lr, sp, #40 +; LE-I64-NEXT: vmov.32 d11[0], r6 +; LE-I64-NEXT: vstmia lr, {d10, d11} @ 16-byte Spill +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d14[0], r0 +; LE-I64-NEXT: mov r0, r10 +; LE-I64-NEXT: mov r9, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d11[0], r7 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d10[0], r0 +; LE-I64-NEXT: mov r0, r8 +; LE-I64-NEXT: mov r7, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: ldr r0, [sp, #56] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d11[1], r0 +; LE-I64-NEXT: vmov r0, s18 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: vmov.32 d10[1], r7 +; LE-I64-NEXT: add lr, sp, #56 +; LE-I64-NEXT: vstmia lr, {d10, d11} @ 16-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d15[1], r4 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d9[0], r0 +; LE-I64-NEXT: vmov r0, s26 +; LE-I64-NEXT: add lr, sp, #24 +; LE-I64-NEXT: vmov r8, s24 +; LE-I64-NEXT: vmov.32 d14[1], r9 +; LE-I64-NEXT: mov r10, r1 +; LE-I64-NEXT: vmov s24, r5 +; LE-I64-NEXT: vldr s0, [sp, #24] @ 4-byte Reload +; LE-I64-NEXT: vstmia lr, {d14, d15} @ 16-byte Spill +; LE-I64-NEXT: vmov r7, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s24 +; LE-I64-NEXT: vmov s22, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s22 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: vmov.32 d14[0], r0 +; LE-I64-NEXT: vmov s24, r6 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d15[0], r0 +; LE-I64-NEXT: mov r0, r7 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s24 +; LE-I64-NEXT: vmov s22, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s22 +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: add lr, sp, #8 +; LE-I64-NEXT: mov r9, r1 +; LE-I64-NEXT: vmov.32 d15[1], r6 +; LE-I64-NEXT: vstmia lr, {d8, d9} @ 16-byte Spill +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d13[0], r0 +; LE-I64-NEXT: mov r0, r8 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vldr s0, [sp, #100] @ 4-byte Reload +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov.32 d14[1], r5 +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vldr s0, [sp, #104] @ 4-byte Reload +; LE-I64-NEXT: vmov s20, r0 +; LE-I64-NEXT: vmov.32 d13[1], r6 +; LE-I64-NEXT: vmov r4, s0 +; LE-I64-NEXT: vldr s0, [sp, #108] @ 4-byte Reload +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s20 +; LE-I64-NEXT: vmov s16, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s16 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: vmov.32 d12[0], r0 +; LE-I64-NEXT: vmov s18, r7 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d11[0], r0 +; LE-I64-NEXT: mov r0, r4 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s18 +; LE-I64-NEXT: vmov s16, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s16 +; LE-I64-NEXT: vmov.32 d10[0], r0 +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: vmov.32 d11[1], r6 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: add lr, sp, #80 +; LE-I64-NEXT: vmov.32 d10[1], r4 +; LE-I64-NEXT: vldmia lr, {d16, d17} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #40 +; LE-I64-NEXT: vldmia lr, {d18, d19} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #8 +; LE-I64-NEXT: vmov.32 d16[0], r0 +; LE-I64-NEXT: ldr r0, [sp, #76] @ 4-byte Reload +; LE-I64-NEXT: vldmia lr, {d20, d21} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #24 +; LE-I64-NEXT: vmov.32 d19[1], r0 +; LE-I64-NEXT: ldr r0, [sp, #116] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d21[1], r10 +; LE-I64-NEXT: vmov.32 d18[1], r0 +; LE-I64-NEXT: ldr r0, [sp, #112] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d12[1], r5 +; LE-I64-NEXT: vmov.32 d17[1], r0 +; LE-I64-NEXT: add r0, r11, #64 +; LE-I64-NEXT: vmov.32 d16[1], r1 +; LE-I64-NEXT: vst1.64 {d10, d11}, [r0:128]! +; LE-I64-NEXT: vst1.64 {d16, d17}, [r0:128]! +; LE-I64-NEXT: vst1.64 {d18, d19}, [r0:128]! +; LE-I64-NEXT: vmov.32 d20[1], r9 +; LE-I64-NEXT: vst1.64 {d12, d13}, [r0:128] +; LE-I64-NEXT: vst1.64 {d14, d15}, [r11:128]! +; LE-I64-NEXT: vst1.64 {d20, d21}, [r11:128]! +; LE-I64-NEXT: vldmia lr, {d16, d17} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #56 +; LE-I64-NEXT: vst1.64 {d16, d17}, [r11:128]! +; LE-I64-NEXT: vldmia lr, {d16, d17} @ 16-byte Reload +; LE-I64-NEXT: vst1.64 {d16, d17}, [r11:128] +; LE-I64-NEXT: add sp, sp, #120 +; LE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: add sp, sp, #4 +; LE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} +; +; BE-I32-LABEL: lrint_v16f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} +; BE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} +; BE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I32-NEXT: .pad #16 +; BE-I32-NEXT: sub sp, sp, #16 +; BE-I32-NEXT: vmov r0, s1 +; BE-I32-NEXT: vstr s14, [sp, #4] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s30, s15 +; BE-I32-NEXT: vstr s13, [sp, #12] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s17, s12 +; BE-I32-NEXT: vstr s10, [sp, #8] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s19, s11 +; BE-I32-NEXT: vstr s8, [sp] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s21, s9 +; BE-I32-NEXT: vmov.f32 s23, s7 +; BE-I32-NEXT: vmov.f32 s24, s6 +; BE-I32-NEXT: vmov.f32 s25, s5 +; BE-I32-NEXT: vmov.f32 s26, s4 +; BE-I32-NEXT: vmov.f32 s27, s3 +; BE-I32-NEXT: vmov.f32 s28, s2 +; BE-I32-NEXT: vmov.f32 s29, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: mov r8, r0 +; BE-I32-NEXT: vmov r0, s27 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r9, r0 +; BE-I32-NEXT: vmov r0, s25 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r10, r0 +; BE-I32-NEXT: vmov r0, s23 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r7, r0 +; BE-I32-NEXT: vmov r0, s21 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r4, r0 +; BE-I32-NEXT: vmov r0, s19 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r5, r0 +; BE-I32-NEXT: vmov r0, s30 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r6, r0 +; BE-I32-NEXT: vmov r0, s17 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d8[0], r0 +; BE-I32-NEXT: vmov r0, s29 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d10[0], r0 +; BE-I32-NEXT: vmov r0, s28 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d11[0], r0 +; BE-I32-NEXT: vmov r0, s26 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d14[0], r0 +; BE-I32-NEXT: vmov r0, s24 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d15[0], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp, #4] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d12[0], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp, #8] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d9[0], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r6 +; BE-I32-NEXT: vmov.32 d13[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r5 +; BE-I32-NEXT: vmov.32 d9[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r4 +; BE-I32-NEXT: vmov.32 d13[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r7 +; BE-I32-NEXT: vmov.32 d12[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r10 +; BE-I32-NEXT: vmov.32 d15[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r9 +; BE-I32-NEXT: vmov.32 d14[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp, #12] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d11[1], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: vmov.32 d10[1], r8 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d8[1], r0 +; BE-I32-NEXT: vrev64.32 q0, q5 +; BE-I32-NEXT: vrev64.32 q1, q7 +; BE-I32-NEXT: vrev64.32 q2, q6 +; BE-I32-NEXT: vrev64.32 q3, q4 +; BE-I32-NEXT: add sp, sp, #16 +; BE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} +; +; BE-I64-LABEL: lrint_v16f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: .pad #4 +; BE-I64-NEXT: sub sp, sp, #4 +; BE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I64-NEXT: .pad #112 +; BE-I64-NEXT: sub sp, sp, #112 +; BE-I64-NEXT: mov r11, r0 +; BE-I64-NEXT: vmov r0, s14 +; BE-I64-NEXT: vmov.f32 s17, s15 +; BE-I64-NEXT: vstr s13, [sp, #52] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s21, s12 +; BE-I64-NEXT: vstr s10, [sp, #68] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s23, s11 +; BE-I64-NEXT: vstr s7, [sp, #72] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s19, s9 +; BE-I64-NEXT: vstr s4, [sp, #28] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s26, s8 +; BE-I64-NEXT: vmov.f32 s24, s6 +; BE-I64-NEXT: vmov.f32 s18, s5 +; BE-I64-NEXT: vmov.f32 s25, s3 +; BE-I64-NEXT: vmov.f32 s16, s2 +; BE-I64-NEXT: vmov.f32 s27, s1 +; BE-I64-NEXT: vmov.f32 s29, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r8, r0 +; BE-I64-NEXT: vmov r0, s29 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r9, r0 +; BE-I64-NEXT: vmov r0, s27 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r7, r0 +; BE-I64-NEXT: vmov r0, s21 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r6, r0 +; BE-I64-NEXT: vmov r0, s25 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r5, r0 +; BE-I64-NEXT: vmov r0, s23 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s0, r5 +; BE-I64-NEXT: str r1, [sp, #108] @ 4-byte Spill +; BE-I64-NEXT: vstr d16, [sp, #96] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s0, r6 +; BE-I64-NEXT: str r1, [sp, #92] @ 4-byte Spill +; BE-I64-NEXT: vstr d16, [sp, #80] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s0, r7 +; BE-I64-NEXT: str r1, [sp, #76] @ 4-byte Spill +; BE-I64-NEXT: vstr d16, [sp, #56] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r9 +; BE-I64-NEXT: mov r10, r1 +; BE-I64-NEXT: vmov.32 d14[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d15[0], r0 +; BE-I64-NEXT: vmov r0, s17 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d10[0], r8 +; BE-I64-NEXT: vmov r6, s19 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d11[0], r0 +; BE-I64-NEXT: mov r0, r6 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r6, r0 +; BE-I64-NEXT: vmov r0, s18 +; BE-I64-NEXT: vmov.32 d10[1], r4 +; BE-I64-NEXT: vstr d10, [sp, #40] @ 8-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: vmov.32 d11[1], r7 +; BE-I64-NEXT: vstr d11, [sp, #32] @ 8-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.32 d15[1], r5 +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vstr d15, [sp, #16] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vldr s0, [sp, #28] @ 4-byte Reload +; BE-I64-NEXT: vmov r5, s26 +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s26, r4 +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: mov r8, r1 +; BE-I64-NEXT: vmov.32 d14[1], r10 +; BE-I64-NEXT: vmov r4, s24 +; BE-I64-NEXT: vstr d16, [sp] @ 8-byte Spill +; BE-I64-NEXT: vstr d14, [sp, #8] @ 8-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s26 +; BE-I64-NEXT: vmov s22, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s22 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: vmov.32 d13[0], r0 +; BE-I64-NEXT: vmov s24, r6 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d14[0], r0 +; BE-I64-NEXT: mov r0, r4 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s24 +; BE-I64-NEXT: vmov s22, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s22 +; BE-I64-NEXT: mov r9, r1 +; BE-I64-NEXT: vmov.32 d12[0], r0 +; BE-I64-NEXT: vmov.32 d14[1], r6 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d11[0], r0 +; BE-I64-NEXT: mov r0, r5 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vldr s0, [sp, #52] @ 4-byte Reload +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov.32 d13[1], r7 +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vldr s0, [sp, #68] @ 4-byte Reload +; BE-I64-NEXT: vmov s20, r0 +; BE-I64-NEXT: vmov.32 d11[1], r6 +; BE-I64-NEXT: vmov r7, s0 +; BE-I64-NEXT: vldr s0, [sp, #72] @ 4-byte Reload +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s20 +; BE-I64-NEXT: vmov s16, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s16 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: vmov.32 d10[0], r0 +; BE-I64-NEXT: vmov s18, r4 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d15[0], r0 +; BE-I64-NEXT: mov r0, r7 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s18 +; BE-I64-NEXT: vmov s16, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s16 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: vmov.32 d9[0], r0 +; BE-I64-NEXT: vmov.32 d15[1], r4 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d24[0], r0 +; BE-I64-NEXT: ldr r0, [sp, #76] @ 4-byte Reload +; BE-I64-NEXT: vldr d23, [sp, #56] @ 8-byte Reload +; BE-I64-NEXT: vldr d20, [sp, #8] @ 8-byte Reload +; BE-I64-NEXT: vmov.32 d23[1], r0 +; BE-I64-NEXT: ldr r0, [sp, #92] @ 4-byte Reload +; BE-I64-NEXT: vldr d22, [sp, #80] @ 8-byte Reload +; BE-I64-NEXT: vldr d26, [sp, #16] @ 8-byte Reload +; BE-I64-NEXT: vrev64.32 d21, d20 +; BE-I64-NEXT: vmov.32 d22[1], r0 +; BE-I64-NEXT: ldr r0, [sp, #108] @ 4-byte Reload +; BE-I64-NEXT: vldr d30, [sp] @ 8-byte Reload +; BE-I64-NEXT: vldr d25, [sp, #96] @ 8-byte Reload +; BE-I64-NEXT: vrev64.32 d20, d26 +; BE-I64-NEXT: vldr d26, [sp, #32] @ 8-byte Reload +; BE-I64-NEXT: vmov.32 d10[1], r5 +; BE-I64-NEXT: vmov.32 d12[1], r9 +; BE-I64-NEXT: vldr d28, [sp, #40] @ 8-byte Reload +; BE-I64-NEXT: vrev64.32 d27, d26 +; BE-I64-NEXT: vmov.32 d25[1], r0 +; BE-I64-NEXT: add r0, r11, #64 +; BE-I64-NEXT: vmov.32 d30[1], r8 +; BE-I64-NEXT: vmov.32 d9[1], r6 +; BE-I64-NEXT: vrev64.32 d26, d28 +; BE-I64-NEXT: vrev64.32 d29, d10 +; BE-I64-NEXT: vmov.32 d24[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d12 +; BE-I64-NEXT: vrev64.32 d28, d23 +; BE-I64-NEXT: vrev64.32 d23, d22 +; BE-I64-NEXT: vrev64.32 d22, d30 +; BE-I64-NEXT: vrev64.32 d31, d25 +; BE-I64-NEXT: vrev64.32 d0, d9 +; BE-I64-NEXT: vrev64.32 d30, d24 +; BE-I64-NEXT: vst1.64 {d0, d1}, [r0:128]! +; BE-I64-NEXT: vst1.64 {d30, d31}, [r0:128]! +; BE-I64-NEXT: vst1.64 {d28, d29}, [r0:128]! +; BE-I64-NEXT: vrev64.32 d19, d13 +; BE-I64-NEXT: vst1.64 {d26, d27}, [r0:128] +; BE-I64-NEXT: vst1.64 {d20, d21}, [r11:128]! +; BE-I64-NEXT: vrev64.32 d18, d14 +; BE-I64-NEXT: vst1.64 {d22, d23}, [r11:128]! +; BE-I64-NEXT: vrev64.32 d17, d15 +; BE-I64-NEXT: vrev64.32 d16, d11 +; BE-I64-NEXT: vst1.64 {d18, d19}, [r11:128]! +; BE-I64-NEXT: vst1.64 {d16, d17}, [r11:128] +; BE-I64-NEXT: add sp, sp, #112 +; BE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I64-NEXT: add sp, sp, #4 +; BE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x) + ret <16 x iXLen> %a +} define <1 x iXLen> @lrint_v1f32(<1 x float> %x) { ; LE-I32-LABEL: lrint_v1f32: diff --git a/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir b/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir index 8fa9337..03cb8e3 100644 --- a/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir +++ b/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir @@ -60,9 +60,9 @@ body: | $sp = t2STMDB_UPD $sp, 14, $noreg, $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11 $r4 = t2BICri $r4, 1, 14, $noreg, $noreg $sp = tSUBspi $sp, 34, 14, $noreg - VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d15 + VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $fpscr_rm, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $fpscr_rm, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d15 tBLXNSr 14, $noreg, killed $r4, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $q0, implicit-def $q1, implicit-def $q2, implicit-def $q3, implicit-def $q4, implicit-def $q5, implicit-def $q6, implicit-def $q7 - VLLDM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit-def $d3, implicit-def $d4, implicit-def $d5, implicit-def $d6, implicit-def $d7, implicit-def $d8, implicit-def $d9, implicit-def $d10, implicit-def $d11, implicit-def $d12, implicit-def $d13, implicit-def $d14, implicit-def $d15 + VLLDM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $fpscr_rm, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit-def $d3, implicit-def $d4, implicit-def $d5, implicit-def $d6, implicit-def $d7, implicit-def $d8, implicit-def $d9, implicit-def $d10, implicit-def $d11, implicit-def $d12, implicit-def $d13, implicit-def $d14, implicit-def $d15 $sp = tADDspi $sp, 34, 14, $noreg $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc diff --git a/llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll new file mode 100644 index 0000000..1db8391 --- /dev/null +++ b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll @@ -0,0 +1,60 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt --bpf-check-and-opt-ir -S -mtriple=bpf-pc-linux < %s | FileCheck %s + +@page1 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 +@page2 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 + +define dso_local void @test_memset() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16) to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16), i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8) to ptr), ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8) to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8), ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8), i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) + +define dso_local void @test_memmove() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memmove() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 16) to ptr), ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8) to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memmove.p1.p1.i64(ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 16), ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8), i64 16, i1 false) + ret void +} + +declare void @llvm.memmove.p1.p1.i64(ptr addrspace(1) writeonly captures(none), ptr addrspace(1) readonly captures(none), i64, i1 immarg) + +define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.inline.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16) to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.inline.p1.i64(ptr addrspace(1) nonnull align 8 getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16), i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.inline.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.inline.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8) to ptr), ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8) to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) nonnull align 8 getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8), ptr addrspace(1) nonnull align 8 getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8), i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) diff --git a/llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll new file mode 100644 index 0000000..62fa2e4 --- /dev/null +++ b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt --bpf-check-and-opt-ir -S -mtriple=bpf-pc-linux < %s | FileCheck %s + +@page1 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 +@page2 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 + +define dso_local void @test_memset() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef align 8 dereferenceable(16) @page1, i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page2 to ptr), ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noundef align 8 dereferenceable(16) @page2, ptr addrspace(1) noundef align 8 dereferenceable(16) @page1, i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) + +define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.inline.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.inline.p1.i64(ptr addrspace(1) align 8 @page1, i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.inline.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.inline.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page2 to ptr), ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) align 8 @page2, ptr addrspace(1) align 8 @page1, i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json new file mode 100644 index 0000000..2894fff --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json @@ -0,0 +1,11 @@ +{ + "entities" : { + "ABS_Fp":[1, 2], + "ADC":[3, 4], + "ADD":[5, 6], + "ADDPDrm":[7, 8], + "ADDPDrr":[9, 10], + "ADDPSrr":[11, 12], + "ADDSDrm":[13, 14] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json new file mode 100644 index 0000000..bf04163 --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json @@ -0,0 +1,7 @@ +{ + "entities": { + "ADD": [1.0, 2.0, 3.0], + "SUB": [1.5], + "MUL": [2.0, 3.0] + } +} diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json new file mode 100644 index 0000000..585a85e --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json @@ -0,0 +1,5 @@ +{ + "invalid_structure": { + "ADD": [ 1, 2, 3] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json new file mode 100644 index 0000000..63e8ccbd --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json @@ -0,0 +1,12 @@ +{ + "entities": { + "ADD": [], + "SUB": [], + "MUL": [], + "MOV": [], + "CMP": [], + "JMP": [], + "CALL": [], + "RET": [] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt new file mode 100644 index 0000000..6327cff --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt @@ -0,0 +1,6882 @@ +Key: AAA: [ 0.00 0.00 ] +Key: AAD: [ 0.00 0.00 ] +Key: AADD: [ 0.00 0.00 ] +Key: AAM: [ 0.00 0.00 ] +Key: AAND: [ 0.00 0.00 ] +Key: AAS: [ 0.00 0.00 ] +Key: ABS_F: [ 0.00 0.00 ] +Key: ABS_Fp: [ 1.00 2.00 ] +Key: ADC: [ 3.00 4.00 ] +Key: ADCX: [ 0.00 0.00 ] +Key: ADD: [ 5.00 6.00 ] +Key: ADDPDrm: [ 7.00 8.00 ] +Key: ADDPDrr: [ 9.00 10.00 ] +Key: ADDPSrm: [ 0.00 0.00 ] +Key: ADDPSrr: [ 11.00 12.00 ] +Key: ADDR: [ 0.00 0.00 ] +Key: ADDSDrm: [ 13.00 14.00 ] +Key: ADDSDrm_Int: [ 0.00 0.00 ] +Key: ADDSDrr: [ 0.00 0.00 ] +Key: ADDSDrr_Int: [ 0.00 0.00 ] +Key: ADDSSrm: [ 0.00 0.00 ] +Key: ADDSSrm_Int: [ 0.00 0.00 ] +Key: ADDSSrr: [ 0.00 0.00 ] +Key: ADDSSrr_Int: [ 0.00 0.00 ] +Key: ADDSUBPDrm: [ 0.00 0.00 ] +Key: ADDSUBPDrr: [ 0.00 0.00 ] +Key: ADDSUBPSrm: [ 0.00 0.00 ] +Key: ADDSUBPSrr: [ 0.00 0.00 ] +Key: ADD_F: [ 0.00 0.00 ] +Key: ADD_FI: [ 0.00 0.00 ] +Key: ADD_FPrST: [ 0.00 0.00 ] +Key: ADD_FST: [ 0.00 0.00 ] +Key: ADD_Fp: [ 0.00 0.00 ] +Key: ADD_FpI: [ 0.00 0.00 ] +Key: ADD_FrST: [ 0.00 0.00 ] +Key: ADJCALLSTACKDOWN: [ 0.00 0.00 ] +Key: ADJCALLSTACKUP: [ 0.00 0.00 ] +Key: ADOX: [ 0.00 0.00 ] +Key: AESDEC: [ 0.00 0.00 ] +Key: AESDECLASTrm: [ 0.00 0.00 ] +Key: AESDECLASTrr: [ 0.00 0.00 ] +Key: AESDECWIDE: [ 0.00 0.00 ] +Key: AESDECrm: [ 0.00 0.00 ] +Key: AESDECrr: [ 0.00 0.00 ] +Key: AESENC: [ 0.00 0.00 ] +Key: AESENCLASTrm: [ 0.00 0.00 ] +Key: AESENCLASTrr: [ 0.00 0.00 ] +Key: AESENCWIDE: [ 0.00 0.00 ] +Key: AESENCrm: [ 0.00 0.00 ] +Key: AESENCrr: [ 0.00 0.00 ] +Key: AESIMCrm: [ 0.00 0.00 ] +Key: AESIMCrr: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: AND: [ 0.00 0.00 ] +Key: ANDN: [ 0.00 0.00 ] +Key: ANDNPDrm: [ 0.00 0.00 ] +Key: ANDNPDrr: [ 0.00 0.00 ] +Key: ANDNPSrm: [ 0.00 0.00 ] +Key: ANDNPSrr: [ 0.00 0.00 ] +Key: ANDPDrm: [ 0.00 0.00 ] +Key: ANDPDrr: [ 0.00 0.00 ] +Key: ANDPSrm: [ 0.00 0.00 ] +Key: ANDPSrr: [ 0.00 0.00 ] +Key: ANNOTATION_LABEL: [ 0.00 0.00 ] +Key: AOR: [ 0.00 0.00 ] +Key: ARITH_FENCE: [ 0.00 0.00 ] +Key: ARPL: [ 0.00 0.00 ] +Key: ASAN_CHECK_MEMACCESS: [ 0.00 0.00 ] +Key: AVX: [ 0.00 0.00 ] +Key: AVX_SET: [ 0.00 0.00 ] +Key: AXOR: [ 0.00 0.00 ] +Key: BEXTR: [ 0.00 0.00 ] +Key: BEXTRI: [ 0.00 0.00 ] +Key: BLCFILL: [ 0.00 0.00 ] +Key: BLCI: [ 0.00 0.00 ] +Key: BLCIC: [ 0.00 0.00 ] +Key: BLCMSK: [ 0.00 0.00 ] +Key: BLCS: [ 0.00 0.00 ] +Key: BLENDPDrmi: [ 0.00 0.00 ] +Key: BLENDPDrri: [ 0.00 0.00 ] +Key: BLENDPSrmi: [ 0.00 0.00 ] +Key: BLENDPSrri: [ 0.00 0.00 ] +Key: BLENDVPDrm: [ 0.00 0.00 ] +Key: BLENDVPDrr: [ 0.00 0.00 ] +Key: BLENDVPSrm: [ 0.00 0.00 ] +Key: BLENDVPSrr: [ 0.00 0.00 ] +Key: BLSFILL: [ 0.00 0.00 ] +Key: BLSI: [ 0.00 0.00 ] +Key: BLSIC: [ 0.00 0.00 ] +Key: BLSMSK: [ 0.00 0.00 ] +Key: BLSR: [ 0.00 0.00 ] +Key: BOUNDS: [ 0.00 0.00 ] +Key: BSF: [ 0.00 0.00 ] +Key: BSR: [ 0.00 0.00 ] +Key: BSWAP: [ 0.00 0.00 ] +Key: BT: [ 0.00 0.00 ] +Key: BTC: [ 0.00 0.00 ] +Key: BTR: [ 0.00 0.00 ] +Key: BTS: [ 0.00 0.00 ] +Key: BUNDLE: [ 0.00 0.00 ] +Key: BZHI: [ 0.00 0.00 ] +Key: CALL: [ 0.00 0.00 ] +Key: CALLpcrel: [ 0.00 0.00 ] +Key: CATCHRET: [ 0.00 0.00 ] +Key: CBW: [ 0.00 0.00 ] +Key: CCMP: [ 0.00 0.00 ] +Key: CDQ: [ 0.00 0.00 ] +Key: CDQE: [ 0.00 0.00 ] +Key: CFCMOV: [ 0.00 0.00 ] +Key: CFI_INSTRUCTION: [ 0.00 0.00 ] +Key: CHS_F: [ 0.00 0.00 ] +Key: CHS_Fp: [ 0.00 0.00 ] +Key: CLAC: [ 0.00 0.00 ] +Key: CLC: [ 0.00 0.00 ] +Key: CLD: [ 0.00 0.00 ] +Key: CLDEMOTE: [ 0.00 0.00 ] +Key: CLEANUPRET: [ 0.00 0.00 ] +Key: CLFLUSH: [ 0.00 0.00 ] +Key: CLFLUSHOPT: [ 0.00 0.00 ] +Key: CLGI: [ 0.00 0.00 ] +Key: CLI: [ 0.00 0.00 ] +Key: CLRSSBSY: [ 0.00 0.00 ] +Key: CLTS: [ 0.00 0.00 ] +Key: CLUI: [ 0.00 0.00 ] +Key: CLWB: [ 0.00 0.00 ] +Key: CLZERO: [ 0.00 0.00 ] +Key: CMC: [ 0.00 0.00 ] +Key: CMOV: [ 0.00 0.00 ] +Key: CMOVBE_F: [ 0.00 0.00 ] +Key: CMOVBE_Fp: [ 0.00 0.00 ] +Key: CMOVB_F: [ 0.00 0.00 ] +Key: CMOVB_Fp: [ 0.00 0.00 ] +Key: CMOVE_F: [ 0.00 0.00 ] +Key: CMOVE_Fp: [ 0.00 0.00 ] +Key: CMOVNBE_F: [ 0.00 0.00 ] +Key: CMOVNBE_Fp: [ 0.00 0.00 ] +Key: CMOVNB_F: [ 0.00 0.00 ] +Key: CMOVNB_Fp: [ 0.00 0.00 ] +Key: CMOVNE_F: [ 0.00 0.00 ] +Key: CMOVNE_Fp: [ 0.00 0.00 ] +Key: CMOVNP_F: [ 0.00 0.00 ] +Key: CMOVNP_Fp: [ 0.00 0.00 ] +Key: CMOVP_F: [ 0.00 0.00 ] +Key: CMOVP_Fp: [ 0.00 0.00 ] +Key: CMOV_FR: [ 0.00 0.00 ] +Key: CMOV_GR: [ 0.00 0.00 ] +Key: CMOV_RFP: [ 0.00 0.00 ] +Key: CMOV_VK: [ 0.00 0.00 ] +Key: CMOV_VR: [ 0.00 0.00 ] +Key: CMP: [ 0.00 0.00 ] +Key: CMPCCXADDmr: [ 0.00 0.00 ] +Key: CMPPDrmi: [ 0.00 0.00 ] +Key: CMPPDrri: [ 0.00 0.00 ] +Key: CMPPSrmi: [ 0.00 0.00 ] +Key: CMPPSrri: [ 0.00 0.00 ] +Key: CMPSB: [ 0.00 0.00 ] +Key: CMPSDrmi: [ 0.00 0.00 ] +Key: CMPSDrmi_Int: [ 0.00 0.00 ] +Key: CMPSDrri: [ 0.00 0.00 ] +Key: CMPSDrri_Int: [ 0.00 0.00 ] +Key: CMPSL: [ 0.00 0.00 ] +Key: CMPSQ: [ 0.00 0.00 ] +Key: CMPSSrmi: [ 0.00 0.00 ] +Key: CMPSSrmi_Int: [ 0.00 0.00 ] +Key: CMPSSrri: [ 0.00 0.00 ] +Key: CMPSSrri_Int: [ 0.00 0.00 ] +Key: CMPSW: [ 0.00 0.00 ] +Key: CMPXCHG: [ 0.00 0.00 ] +Key: COMISDrm: [ 0.00 0.00 ] +Key: COMISDrm_Int: [ 0.00 0.00 ] +Key: COMISDrr: [ 0.00 0.00 ] +Key: COMISDrr_Int: [ 0.00 0.00 ] +Key: COMISSrm: [ 0.00 0.00 ] +Key: COMISSrm_Int: [ 0.00 0.00 ] +Key: COMISSrr: [ 0.00 0.00 ] +Key: COMISSrr_Int: [ 0.00 0.00 ] +Key: COMP_FST: [ 0.00 0.00 ] +Key: COM_FIPr: [ 0.00 0.00 ] +Key: COM_FIr: [ 0.00 0.00 ] +Key: COM_FST: [ 0.00 0.00 ] +Key: COM_FpIr: [ 0.00 0.00 ] +Key: COM_Fpr: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ANCHOR: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ENTRY: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_GLUE: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_LOOP: [ 0.00 0.00 ] +Key: COPY: [ 0.00 0.00 ] +Key: COPY_TO_REGCLASS: [ 0.00 0.00 ] +Key: CPUID: [ 0.00 0.00 ] +Key: CQO: [ 0.00 0.00 ] +Key: CRC: [ 0.00 0.00 ] +Key: CS_PREFIX: [ 0.00 0.00 ] +Key: CTEST: [ 0.00 0.00 ] +Key: CVTDQ: [ 0.00 0.00 ] +Key: CVTPD: [ 0.00 0.00 ] +Key: CVTPS: [ 0.00 0.00 ] +Key: CVTSD: [ 0.00 0.00 ] +Key: CVTSI: [ 0.00 0.00 ] +Key: CVTSS: [ 0.00 0.00 ] +Key: CVTTPD: [ 0.00 0.00 ] +Key: CVTTPS: [ 0.00 0.00 ] +Key: CVTTSD: [ 0.00 0.00 ] +Key: CVTTSS: [ 0.00 0.00 ] +Key: CWD: [ 0.00 0.00 ] +Key: CWDE: [ 0.00 0.00 ] +Key: DAA: [ 0.00 0.00 ] +Key: DAS: [ 0.00 0.00 ] +Key: DATA: [ 0.00 0.00 ] +Key: DBG_INSTR_REF: [ 0.00 0.00 ] +Key: DBG_LABEL: [ 0.00 0.00 ] +Key: DBG_PHI: [ 0.00 0.00 ] +Key: DBG_VALUE: [ 0.00 0.00 ] +Key: DBG_VALUE_LIST: [ 0.00 0.00 ] +Key: DEC: [ 0.00 0.00 ] +Key: DIV: [ 0.00 0.00 ] +Key: DIVPDrm: [ 0.00 0.00 ] +Key: DIVPDrr: [ 0.00 0.00 ] +Key: DIVPSrm: [ 0.00 0.00 ] +Key: DIVPSrr: [ 0.00 0.00 ] +Key: DIVR_F: [ 0.00 0.00 ] +Key: DIVR_FI: [ 0.00 0.00 ] +Key: DIVR_FPrST: [ 0.00 0.00 ] +Key: DIVR_FST: [ 0.00 0.00 ] +Key: DIVR_Fp: [ 0.00 0.00 ] +Key: DIVR_FpI: [ 0.00 0.00 ] +Key: DIVR_FrST: [ 0.00 0.00 ] +Key: DIVSDrm: [ 0.00 0.00 ] +Key: DIVSDrm_Int: [ 0.00 0.00 ] +Key: DIVSDrr: [ 0.00 0.00 ] +Key: DIVSDrr_Int: [ 0.00 0.00 ] +Key: DIVSSrm: [ 0.00 0.00 ] +Key: DIVSSrm_Int: [ 0.00 0.00 ] +Key: DIVSSrr: [ 0.00 0.00 ] +Key: DIVSSrr_Int: [ 0.00 0.00 ] +Key: DIV_F: [ 0.00 0.00 ] +Key: DIV_FI: [ 0.00 0.00 ] +Key: DIV_FPrST: [ 0.00 0.00 ] +Key: DIV_FST: [ 0.00 0.00 ] +Key: DIV_Fp: [ 0.00 0.00 ] +Key: DIV_FpI: [ 0.00 0.00 ] +Key: DIV_FrST: [ 0.00 0.00 ] +Key: DPPDrmi: [ 0.00 0.00 ] +Key: DPPDrri: [ 0.00 0.00 ] +Key: DPPSrmi: [ 0.00 0.00 ] +Key: DPPSrri: [ 0.00 0.00 ] +Key: DS_PREFIX: [ 0.00 0.00 ] +Key: DYN_ALLOCA: [ 0.00 0.00 ] +Key: EH_LABEL: [ 0.00 0.00 ] +Key: EH_RETURN: [ 0.00 0.00 ] +Key: EH_SjLj_LongJmp: [ 0.00 0.00 ] +Key: EH_SjLj_SetJmp: [ 0.00 0.00 ] +Key: EH_SjLj_Setup: [ 0.00 0.00 ] +Key: ENCLS: [ 0.00 0.00 ] +Key: ENCLU: [ 0.00 0.00 ] +Key: ENCLV: [ 0.00 0.00 ] +Key: ENCODEKEY: [ 0.00 0.00 ] +Key: ENDBR: [ 0.00 0.00 ] +Key: ENQCMD: [ 0.00 0.00 ] +Key: ENQCMDS: [ 0.00 0.00 ] +Key: ENTER: [ 0.00 0.00 ] +Key: ERETS: [ 0.00 0.00 ] +Key: ERETU: [ 0.00 0.00 ] +Key: ES_PREFIX: [ 0.00 0.00 ] +Key: EXTRACTPSmri: [ 0.00 0.00 ] +Key: EXTRACTPSrri: [ 0.00 0.00 ] +Key: EXTRACT_SUBREG: [ 0.00 0.00 ] +Key: EXTRQ: [ 0.00 0.00 ] +Key: EXTRQI: [ 0.00 0.00 ] +Key: F: [ 0.00 0.00 ] +Key: FAKE_USE: [ 0.00 0.00 ] +Key: FARCALL: [ 0.00 0.00 ] +Key: FARJMP: [ 0.00 0.00 ] +Key: FAULTING_OP: [ 0.00 0.00 ] +Key: FBLDm: [ 0.00 0.00 ] +Key: FBSTPm: [ 0.00 0.00 ] +Key: FCOM: [ 0.00 0.00 ] +Key: FCOMP: [ 0.00 0.00 ] +Key: FCOMPP: [ 0.00 0.00 ] +Key: FCOS: [ 0.00 0.00 ] +Key: FDECSTP: [ 0.00 0.00 ] +Key: FEMMS: [ 0.00 0.00 ] +Key: FENTRY_CALL: [ 0.00 0.00 ] +Key: FFREE: [ 0.00 0.00 ] +Key: FFREEP: [ 0.00 0.00 ] +Key: FICOM: [ 0.00 0.00 ] +Key: FICOMP: [ 0.00 0.00 ] +Key: FINCSTP: [ 0.00 0.00 ] +Key: FLDCW: [ 0.00 0.00 ] +Key: FLDENVm: [ 0.00 0.00 ] +Key: FLDL: [ 0.00 0.00 ] +Key: FLDLG: [ 0.00 0.00 ] +Key: FLDLN: [ 0.00 0.00 ] +Key: FLDPI: [ 0.00 0.00 ] +Key: FNCLEX: [ 0.00 0.00 ] +Key: FNINIT: [ 0.00 0.00 ] +Key: FNOP: [ 0.00 0.00 ] +Key: FNSTCW: [ 0.00 0.00 ] +Key: FNSTSW: [ 0.00 0.00 ] +Key: FNSTSWm: [ 0.00 0.00 ] +Key: FP: [ 0.00 0.00 ] +Key: FPATAN: [ 0.00 0.00 ] +Key: FPREM: [ 0.00 0.00 ] +Key: FPTAN: [ 0.00 0.00 ] +Key: FRNDINT: [ 0.00 0.00 ] +Key: FRSTORm: [ 0.00 0.00 ] +Key: FSAVEm: [ 0.00 0.00 ] +Key: FSCALE: [ 0.00 0.00 ] +Key: FSIN: [ 0.00 0.00 ] +Key: FSINCOS: [ 0.00 0.00 ] +Key: FSTENVm: [ 0.00 0.00 ] +Key: FS_PREFIX: [ 0.00 0.00 ] +Key: FXRSTOR: [ 0.00 0.00 ] +Key: FXSAVE: [ 0.00 0.00 ] +Key: FXTRACT: [ 0.00 0.00 ] +Key: FYL: [ 0.00 0.00 ] +Key: FsFLD: [ 0.00 0.00 ] +Key: GC_LABEL: [ 0.00 0.00 ] +Key: GETSEC: [ 0.00 0.00 ] +Key: GF: [ 0.00 0.00 ] +Key: GS_PREFIX: [ 0.00 0.00 ] +Key: G_ABDS: [ 0.00 0.00 ] +Key: G_ABDU: [ 0.00 0.00 ] +Key: G_ABS: [ 0.00 0.00 ] +Key: G_ADD: [ 0.00 0.00 ] +Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ] +Key: G_AND: [ 0.00 0.00 ] +Key: G_ANYEXT: [ 0.00 0.00 ] +Key: G_ASHR: [ 0.00 0.00 ] +Key: G_ASSERT_ALIGN: [ 0.00 0.00 ] +Key: G_ASSERT_SEXT: [ 0.00 0.00 ] +Key: G_ASSERT_ZEXT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_ADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_AND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAXIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMINIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FSUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_NAND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_OR: [ 0.00 0.00 ] +Key: G_ATOMICRMW_SUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UDEC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UINC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_COND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_SAT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XCHG: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XOR: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG_WITH_SUCCESS: [ 0.00 0.00 ] +Key: G_BITCAST: [ 0.00 0.00 ] +Key: G_BITREVERSE: [ 0.00 0.00 ] +Key: G_BLOCK_ADDR: [ 0.00 0.00 ] +Key: G_BR: [ 0.00 0.00 ] +Key: G_BRCOND: [ 0.00 0.00 ] +Key: G_BRINDIRECT: [ 0.00 0.00 ] +Key: G_BRJT: [ 0.00 0.00 ] +Key: G_BSWAP: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR_TRUNC: [ 0.00 0.00 ] +Key: G_BZERO: [ 0.00 0.00 ] +Key: G_CONCAT_VECTORS: [ 0.00 0.00 ] +Key: G_CONSTANT: [ 0.00 0.00 ] +Key: G_CONSTANT_FOLD_BARRIER: [ 0.00 0.00 ] +Key: G_CONSTANT_POOL: [ 0.00 0.00 ] +Key: G_CTLZ: [ 0.00 0.00 ] +Key: G_CTLZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_CTPOP: [ 0.00 0.00 ] +Key: G_CTTZ: [ 0.00 0.00 ] +Key: G_CTTZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_DEBUGTRAP: [ 0.00 0.00 ] +Key: G_DYN_STACKALLOC: [ 0.00 0.00 ] +Key: G_EXTRACT: [ 0.00 0.00 ] +Key: G_EXTRACT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_EXTRACT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_FABS: [ 0.00 0.00 ] +Key: G_FACOS: [ 0.00 0.00 ] +Key: G_FADD: [ 0.00 0.00 ] +Key: G_FASIN: [ 0.00 0.00 ] +Key: G_FATAN: [ 0.00 0.00 ] +Key: G_FCANONICALIZE: [ 0.00 0.00 ] +Key: G_FCEIL: [ 0.00 0.00 ] +Key: G_FCMP: [ 0.00 0.00 ] +Key: G_FCONSTANT: [ 0.00 0.00 ] +Key: G_FCOPYSIGN: [ 0.00 0.00 ] +Key: G_FCOS: [ 0.00 0.00 ] +Key: G_FCOSH: [ 0.00 0.00 ] +Key: G_FDIV: [ 0.00 0.00 ] +Key: G_FENCE: [ 0.00 0.00 ] +Key: G_FEXP: [ 0.00 0.00 ] +Key: G_FFLOOR: [ 0.00 0.00 ] +Key: G_FFREXP: [ 0.00 0.00 ] +Key: G_FILD: [ 0.00 0.00 ] +Key: G_FIST: [ 0.00 0.00 ] +Key: G_FLDCW: [ 0.00 0.00 ] +Key: G_FLDEXP: [ 0.00 0.00 ] +Key: G_FLOG: [ 0.00 0.00 ] +Key: G_FMA: [ 0.00 0.00 ] +Key: G_FMAD: [ 0.00 0.00 ] +Key: G_FMAXIMUM: [ 0.00 0.00 ] +Key: G_FMAXIMUMNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMINIMUM: [ 0.00 0.00 ] +Key: G_FMINIMUMNUM: [ 0.00 0.00 ] +Key: G_FMINNUM: [ 0.00 0.00 ] +Key: G_FMINNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMODF: [ 0.00 0.00 ] +Key: G_FMUL: [ 0.00 0.00 ] +Key: G_FNEARBYINT: [ 0.00 0.00 ] +Key: G_FNEG: [ 0.00 0.00 ] +Key: G_FNSTCW: [ 0.00 0.00 ] +Key: G_FPEXT: [ 0.00 0.00 ] +Key: G_FPOW: [ 0.00 0.00 ] +Key: G_FPOWI: [ 0.00 0.00 ] +Key: G_FPTOSI: [ 0.00 0.00 ] +Key: G_FPTOSI_SAT: [ 0.00 0.00 ] +Key: G_FPTOUI: [ 0.00 0.00 ] +Key: G_FPTOUI_SAT: [ 0.00 0.00 ] +Key: G_FPTRUNC: [ 0.00 0.00 ] +Key: G_FRAME_INDEX: [ 0.00 0.00 ] +Key: G_FREEZE: [ 0.00 0.00 ] +Key: G_FREM: [ 0.00 0.00 ] +Key: G_FRINT: [ 0.00 0.00 ] +Key: G_FSHL: [ 0.00 0.00 ] +Key: G_FSHR: [ 0.00 0.00 ] +Key: G_FSIN: [ 0.00 0.00 ] +Key: G_FSINCOS: [ 0.00 0.00 ] +Key: G_FSINH: [ 0.00 0.00 ] +Key: G_FSQRT: [ 0.00 0.00 ] +Key: G_FSUB: [ 0.00 0.00 ] +Key: G_FTAN: [ 0.00 0.00 ] +Key: G_FTANH: [ 0.00 0.00 ] +Key: G_GET_FPENV: [ 0.00 0.00 ] +Key: G_GET_FPMODE: [ 0.00 0.00 ] +Key: G_GET_ROUNDING: [ 0.00 0.00 ] +Key: G_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_ICMP: [ 0.00 0.00 ] +Key: G_IMPLICIT_DEF: [ 0.00 0.00 ] +Key: G_INDEXED_LOAD: [ 0.00 0.00 ] +Key: G_INDEXED_SEXTLOAD: [ 0.00 0.00 ] +Key: G_INDEXED_STORE: [ 0.00 0.00 ] +Key: G_INDEXED_ZEXTLOAD: [ 0.00 0.00 ] +Key: G_INSERT: [ 0.00 0.00 ] +Key: G_INSERT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_INSERT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_INTRINSIC: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTRINSIC_FPTRUNC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_LLRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_LRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUNDEVEN: [ 0.00 0.00 ] +Key: G_INTRINSIC_TRUNC: [ 0.00 0.00 ] +Key: G_INTRINSIC_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTTOPTR: [ 0.00 0.00 ] +Key: G_INVOKE_REGION_START: [ 0.00 0.00 ] +Key: G_IS_FPCLASS: [ 0.00 0.00 ] +Key: G_JUMP_TABLE: [ 0.00 0.00 ] +Key: G_LLROUND: [ 0.00 0.00 ] +Key: G_LOAD: [ 0.00 0.00 ] +Key: G_LROUND: [ 0.00 0.00 ] +Key: G_LSHR: [ 0.00 0.00 ] +Key: G_MEMCPY: [ 0.00 0.00 ] +Key: G_MEMCPY_INLINE: [ 0.00 0.00 ] +Key: G_MEMMOVE: [ 0.00 0.00 ] +Key: G_MEMSET: [ 0.00 0.00 ] +Key: G_MERGE_VALUES: [ 0.00 0.00 ] +Key: G_MUL: [ 0.00 0.00 ] +Key: G_OR: [ 0.00 0.00 ] +Key: G_PHI: [ 0.00 0.00 ] +Key: G_PREFETCH: [ 0.00 0.00 ] +Key: G_PTRAUTH_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_PTRMASK: [ 0.00 0.00 ] +Key: G_PTRTOINT: [ 0.00 0.00 ] +Key: G_PTR_ADD: [ 0.00 0.00 ] +Key: G_READCYCLECOUNTER: [ 0.00 0.00 ] +Key: G_READSTEADYCOUNTER: [ 0.00 0.00 ] +Key: G_READ_REGISTER: [ 0.00 0.00 ] +Key: G_RESET_FPENV: [ 0.00 0.00 ] +Key: G_RESET_FPMODE: [ 0.00 0.00 ] +Key: G_ROTL: [ 0.00 0.00 ] +Key: G_ROTR: [ 0.00 0.00 ] +Key: G_SADDE: [ 0.00 0.00 ] +Key: G_SADDO: [ 0.00 0.00 ] +Key: G_SADDSAT: [ 0.00 0.00 ] +Key: G_SBFX: [ 0.00 0.00 ] +Key: G_SCMP: [ 0.00 0.00 ] +Key: G_SDIV: [ 0.00 0.00 ] +Key: G_SDIVFIX: [ 0.00 0.00 ] +Key: G_SDIVFIXSAT: [ 0.00 0.00 ] +Key: G_SDIVREM: [ 0.00 0.00 ] +Key: G_SELECT: [ 0.00 0.00 ] +Key: G_SET_FPENV: [ 0.00 0.00 ] +Key: G_SET_FPMODE: [ 0.00 0.00 ] +Key: G_SET_ROUNDING: [ 0.00 0.00 ] +Key: G_SEXT: [ 0.00 0.00 ] +Key: G_SEXTLOAD: [ 0.00 0.00 ] +Key: G_SEXT_INREG: [ 0.00 0.00 ] +Key: G_SHL: [ 0.00 0.00 ] +Key: G_SHUFFLE_VECTOR: [ 0.00 0.00 ] +Key: G_SITOFP: [ 0.00 0.00 ] +Key: G_SMAX: [ 0.00 0.00 ] +Key: G_SMIN: [ 0.00 0.00 ] +Key: G_SMULFIX: [ 0.00 0.00 ] +Key: G_SMULFIXSAT: [ 0.00 0.00 ] +Key: G_SMULH: [ 0.00 0.00 ] +Key: G_SMULO: [ 0.00 0.00 ] +Key: G_SPLAT_VECTOR: [ 0.00 0.00 ] +Key: G_SREM: [ 0.00 0.00 ] +Key: G_SSHLSAT: [ 0.00 0.00 ] +Key: G_SSUBE: [ 0.00 0.00 ] +Key: G_SSUBO: [ 0.00 0.00 ] +Key: G_SSUBSAT: [ 0.00 0.00 ] +Key: G_STACKRESTORE: [ 0.00 0.00 ] +Key: G_STACKSAVE: [ 0.00 0.00 ] +Key: G_STEP_VECTOR: [ 0.00 0.00 ] +Key: G_STORE: [ 0.00 0.00 ] +Key: G_STRICT_FADD: [ 0.00 0.00 ] +Key: G_STRICT_FDIV: [ 0.00 0.00 ] +Key: G_STRICT_FLDEXP: [ 0.00 0.00 ] +Key: G_STRICT_FMA: [ 0.00 0.00 ] +Key: G_STRICT_FMUL: [ 0.00 0.00 ] +Key: G_STRICT_FREM: [ 0.00 0.00 ] +Key: G_STRICT_FSQRT: [ 0.00 0.00 ] +Key: G_STRICT_FSUB: [ 0.00 0.00 ] +Key: G_SUB: [ 0.00 0.00 ] +Key: G_TRAP: [ 0.00 0.00 ] +Key: G_TRUNC: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ] +Key: G_TRUNC_USAT_U: [ 0.00 0.00 ] +Key: G_UADDE: [ 0.00 0.00 ] +Key: G_UADDO: [ 0.00 0.00 ] +Key: G_UADDSAT: [ 0.00 0.00 ] +Key: G_UBFX: [ 0.00 0.00 ] +Key: G_UBSANTRAP: [ 0.00 0.00 ] +Key: G_UCMP: [ 0.00 0.00 ] +Key: G_UDIV: [ 0.00 0.00 ] +Key: G_UDIVFIX: [ 0.00 0.00 ] +Key: G_UDIVFIXSAT: [ 0.00 0.00 ] +Key: G_UDIVREM: [ 0.00 0.00 ] +Key: G_UITOFP: [ 0.00 0.00 ] +Key: G_UMAX: [ 0.00 0.00 ] +Key: G_UMIN: [ 0.00 0.00 ] +Key: G_UMULFIX: [ 0.00 0.00 ] +Key: G_UMULFIXSAT: [ 0.00 0.00 ] +Key: G_UMULH: [ 0.00 0.00 ] +Key: G_UMULO: [ 0.00 0.00 ] +Key: G_UNMERGE_VALUES: [ 0.00 0.00 ] +Key: G_UREM: [ 0.00 0.00 ] +Key: G_USHLSAT: [ 0.00 0.00 ] +Key: G_USUBE: [ 0.00 0.00 ] +Key: G_USUBO: [ 0.00 0.00 ] +Key: G_USUBSAT: [ 0.00 0.00 ] +Key: G_VAARG: [ 0.00 0.00 ] +Key: G_VASTART: [ 0.00 0.00 ] +Key: G_VECREDUCE_ADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_AND: [ 0.00 0.00 ] +Key: G_VECREDUCE_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAXIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMINIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_MUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_OR: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_XOR: [ 0.00 0.00 ] +Key: G_VECTOR_COMPRESS: [ 0.00 0.00 ] +Key: G_VSCALE: [ 0.00 0.00 ] +Key: G_WRITE_REGISTER: [ 0.00 0.00 ] +Key: G_XOR: [ 0.00 0.00 ] +Key: G_ZEXT: [ 0.00 0.00 ] +Key: G_ZEXTLOAD: [ 0.00 0.00 ] +Key: HADDPDrm: [ 0.00 0.00 ] +Key: HADDPDrr: [ 0.00 0.00 ] +Key: HADDPSrm: [ 0.00 0.00 ] +Key: HADDPSrr: [ 0.00 0.00 ] +Key: HLT: [ 0.00 0.00 ] +Key: HRESET: [ 0.00 0.00 ] +Key: HSUBPDrm: [ 0.00 0.00 ] +Key: HSUBPDrr: [ 0.00 0.00 ] +Key: HSUBPSrm: [ 0.00 0.00 ] +Key: HSUBPSrr: [ 0.00 0.00 ] +Key: ICALL_BRANCH_FUNNEL: [ 0.00 0.00 ] +Key: IDIV: [ 0.00 0.00 ] +Key: ILD_F: [ 0.00 0.00 ] +Key: ILD_Fp: [ 0.00 0.00 ] +Key: IMPLICIT_DEF: [ 0.00 0.00 ] +Key: IMUL: [ 0.00 0.00 ] +Key: IMULZU: [ 0.00 0.00 ] +Key: IN: [ 0.00 0.00 ] +Key: INC: [ 0.00 0.00 ] +Key: INCSSPD: [ 0.00 0.00 ] +Key: INCSSPQ: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_CALL: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_TCRETURN: [ 0.00 0.00 ] +Key: INIT_UNDEF: [ 0.00 0.00 ] +Key: INLINEASM: [ 0.00 0.00 ] +Key: INLINEASM_BR: [ 0.00 0.00 ] +Key: INSB: [ 0.00 0.00 ] +Key: INSERTPSrmi: [ 0.00 0.00 ] +Key: INSERTPSrri: [ 0.00 0.00 ] +Key: INSERTQ: [ 0.00 0.00 ] +Key: INSERTQI: [ 0.00 0.00 ] +Key: INSERT_SUBREG: [ 0.00 0.00 ] +Key: INSL: [ 0.00 0.00 ] +Key: INSW: [ 0.00 0.00 ] +Key: INT: [ 0.00 0.00 ] +Key: INTO: [ 0.00 0.00 ] +Key: INVD: [ 0.00 0.00 ] +Key: INVEPT: [ 0.00 0.00 ] +Key: INVLPG: [ 0.00 0.00 ] +Key: INVLPGA: [ 0.00 0.00 ] +Key: INVLPGB: [ 0.00 0.00 ] +Key: INVPCID: [ 0.00 0.00 ] +Key: INVVPID: [ 0.00 0.00 ] +Key: IRET: [ 0.00 0.00 ] +Key: ISTT_FP: [ 0.00 0.00 ] +Key: ISTT_Fp: [ 0.00 0.00 ] +Key: IST_F: [ 0.00 0.00 ] +Key: IST_FP: [ 0.00 0.00 ] +Key: IST_Fp: [ 0.00 0.00 ] +Key: Int_eh_sjlj_setup_dispatch: [ 0.00 0.00 ] +Key: JCC: [ 0.00 0.00 ] +Key: JCXZ: [ 0.00 0.00 ] +Key: JECXZ: [ 0.00 0.00 ] +Key: JMP: [ 0.00 0.00 ] +Key: JMPABS: [ 0.00 0.00 ] +Key: JRCXZ: [ 0.00 0.00 ] +Key: JUMP_TABLE_DEBUG_INFO: [ 0.00 0.00 ] +Key: KADDBkk: [ 0.00 0.00 ] +Key: KADDDkk: [ 0.00 0.00 ] +Key: KADDQkk: [ 0.00 0.00 ] +Key: KADDWkk: [ 0.00 0.00 ] +Key: KANDBkk: [ 0.00 0.00 ] +Key: KANDDkk: [ 0.00 0.00 ] +Key: KANDNBkk: [ 0.00 0.00 ] +Key: KANDNDkk: [ 0.00 0.00 ] +Key: KANDNQkk: [ 0.00 0.00 ] +Key: KANDNWkk: [ 0.00 0.00 ] +Key: KANDQkk: [ 0.00 0.00 ] +Key: KANDWkk: [ 0.00 0.00 ] +Key: KCFI_CHECK: [ 0.00 0.00 ] +Key: KILL: [ 0.00 0.00 ] +Key: KMOVBkk: [ 0.00 0.00 ] +Key: KMOVBkk_EVEX: [ 0.00 0.00 ] +Key: KMOVBkm: [ 0.00 0.00 ] +Key: KMOVBkm_EVEX: [ 0.00 0.00 ] +Key: KMOVBkr: [ 0.00 0.00 ] +Key: KMOVBkr_EVEX: [ 0.00 0.00 ] +Key: KMOVBmk: [ 0.00 0.00 ] +Key: KMOVBmk_EVEX: [ 0.00 0.00 ] +Key: KMOVBrk: [ 0.00 0.00 ] +Key: KMOVBrk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkk: [ 0.00 0.00 ] +Key: KMOVDkk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkm: [ 0.00 0.00 ] +Key: KMOVDkm_EVEX: [ 0.00 0.00 ] +Key: KMOVDkr: [ 0.00 0.00 ] +Key: KMOVDkr_EVEX: [ 0.00 0.00 ] +Key: KMOVDmk: [ 0.00 0.00 ] +Key: KMOVDmk_EVEX: [ 0.00 0.00 ] +Key: KMOVDrk: [ 0.00 0.00 ] +Key: KMOVDrk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkk: [ 0.00 0.00 ] +Key: KMOVQkk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkm: [ 0.00 0.00 ] +Key: KMOVQkm_EVEX: [ 0.00 0.00 ] +Key: KMOVQkr: [ 0.00 0.00 ] +Key: KMOVQkr_EVEX: [ 0.00 0.00 ] +Key: KMOVQmk: [ 0.00 0.00 ] +Key: KMOVQmk_EVEX: [ 0.00 0.00 ] +Key: KMOVQrk: [ 0.00 0.00 ] +Key: KMOVQrk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkk: [ 0.00 0.00 ] +Key: KMOVWkk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkm: [ 0.00 0.00 ] +Key: KMOVWkm_EVEX: [ 0.00 0.00 ] +Key: KMOVWkr: [ 0.00 0.00 ] +Key: KMOVWkr_EVEX: [ 0.00 0.00 ] +Key: KMOVWmk: [ 0.00 0.00 ] +Key: KMOVWmk_EVEX: [ 0.00 0.00 ] +Key: KMOVWrk: [ 0.00 0.00 ] +Key: KMOVWrk_EVEX: [ 0.00 0.00 ] +Key: KNOTBkk: [ 0.00 0.00 ] +Key: KNOTDkk: [ 0.00 0.00 ] +Key: KNOTQkk: [ 0.00 0.00 ] +Key: KNOTWkk: [ 0.00 0.00 ] +Key: KORBkk: [ 0.00 0.00 ] +Key: KORDkk: [ 0.00 0.00 ] +Key: KORQkk: [ 0.00 0.00 ] +Key: KORTESTBkk: [ 0.00 0.00 ] +Key: KORTESTDkk: [ 0.00 0.00 ] +Key: KORTESTQkk: [ 0.00 0.00 ] +Key: KORTESTWkk: [ 0.00 0.00 ] +Key: KORWkk: [ 0.00 0.00 ] +Key: KSET: [ 0.00 0.00 ] +Key: KSHIFTLBki: [ 0.00 0.00 ] +Key: KSHIFTLDki: [ 0.00 0.00 ] +Key: KSHIFTLQki: [ 0.00 0.00 ] +Key: KSHIFTLWki: [ 0.00 0.00 ] +Key: KSHIFTRBki: [ 0.00 0.00 ] +Key: KSHIFTRDki: [ 0.00 0.00 ] +Key: KSHIFTRQki: [ 0.00 0.00 ] +Key: KSHIFTRWki: [ 0.00 0.00 ] +Key: KTESTBkk: [ 0.00 0.00 ] +Key: KTESTDkk: [ 0.00 0.00 ] +Key: KTESTQkk: [ 0.00 0.00 ] +Key: KTESTWkk: [ 0.00 0.00 ] +Key: KUNPCKBWkk: [ 0.00 0.00 ] +Key: KUNPCKDQkk: [ 0.00 0.00 ] +Key: KUNPCKWDkk: [ 0.00 0.00 ] +Key: KXNORBkk: [ 0.00 0.00 ] +Key: KXNORDkk: [ 0.00 0.00 ] +Key: KXNORQkk: [ 0.00 0.00 ] +Key: KXNORWkk: [ 0.00 0.00 ] +Key: KXORBkk: [ 0.00 0.00 ] +Key: KXORDkk: [ 0.00 0.00 ] +Key: KXORQkk: [ 0.00 0.00 ] +Key: KXORWkk: [ 0.00 0.00 ] +Key: LAHF: [ 0.00 0.00 ] +Key: LAR: [ 0.00 0.00 ] +Key: LCMPXCHG: [ 0.00 0.00 ] +Key: LDDQUrm: [ 0.00 0.00 ] +Key: LDMXCSR: [ 0.00 0.00 ] +Key: LDS: [ 0.00 0.00 ] +Key: LDTILECFG: [ 0.00 0.00 ] +Key: LDTILECFG_EVEX: [ 0.00 0.00 ] +Key: LD_F: [ 0.00 0.00 ] +Key: LD_Fp: [ 0.00 0.00 ] +Key: LD_Frr: [ 0.00 0.00 ] +Key: LEA: [ 0.00 0.00 ] +Key: LEAVE: [ 0.00 0.00 ] +Key: LES: [ 0.00 0.00 ] +Key: LFENCE: [ 0.00 0.00 ] +Key: LFS: [ 0.00 0.00 ] +Key: LGDT: [ 0.00 0.00 ] +Key: LGS: [ 0.00 0.00 ] +Key: LIDT: [ 0.00 0.00 ] +Key: LIFETIME_END: [ 0.00 0.00 ] +Key: LIFETIME_START: [ 0.00 0.00 ] +Key: LKGS: [ 0.00 0.00 ] +Key: LLDT: [ 0.00 0.00 ] +Key: LLWPCB: [ 0.00 0.00 ] +Key: LMSW: [ 0.00 0.00 ] +Key: LOADIWKEY: [ 0.00 0.00 ] +Key: LOAD_STACK_GUARD: [ 0.00 0.00 ] +Key: LOCAL_ESCAPE: [ 0.00 0.00 ] +Key: LOCK_ADD: [ 0.00 0.00 ] +Key: LOCK_AND: [ 0.00 0.00 ] +Key: LOCK_BTC: [ 0.00 0.00 ] +Key: LOCK_BTC_RM: [ 0.00 0.00 ] +Key: LOCK_BTR: [ 0.00 0.00 ] +Key: LOCK_BTR_RM: [ 0.00 0.00 ] +Key: LOCK_BTS: [ 0.00 0.00 ] +Key: LOCK_BTS_RM: [ 0.00 0.00 ] +Key: LOCK_DEC: [ 0.00 0.00 ] +Key: LOCK_INC: [ 0.00 0.00 ] +Key: LOCK_OR: [ 0.00 0.00 ] +Key: LOCK_PREFIX: [ 0.00 0.00 ] +Key: LOCK_SUB: [ 0.00 0.00 ] +Key: LOCK_XOR: [ 0.00 0.00 ] +Key: LODSB: [ 0.00 0.00 ] +Key: LODSL: [ 0.00 0.00 ] +Key: LODSQ: [ 0.00 0.00 ] +Key: LODSW: [ 0.00 0.00 ] +Key: LOOP: [ 0.00 0.00 ] +Key: LOOPE: [ 0.00 0.00 ] +Key: LOOPNE: [ 0.00 0.00 ] +Key: LRET: [ 0.00 0.00 ] +Key: LRETI: [ 0.00 0.00 ] +Key: LSL: [ 0.00 0.00 ] +Key: LSS: [ 0.00 0.00 ] +Key: LTRm: [ 0.00 0.00 ] +Key: LTRr: [ 0.00 0.00 ] +Key: LWPINS: [ 0.00 0.00 ] +Key: LWPVAL: [ 0.00 0.00 ] +Key: LXADD: [ 0.00 0.00 ] +Key: LZCNT: [ 0.00 0.00 ] +Key: MASKMOVDQU: [ 0.00 0.00 ] +Key: MASKPAIR: [ 0.00 0.00 ] +Key: MAXCPDrm: [ 0.00 0.00 ] +Key: MAXCPDrr: [ 0.00 0.00 ] +Key: MAXCPSrm: [ 0.00 0.00 ] +Key: MAXCPSrr: [ 0.00 0.00 ] +Key: MAXCSDrm: [ 0.00 0.00 ] +Key: MAXCSDrr: [ 0.00 0.00 ] +Key: MAXCSSrm: [ 0.00 0.00 ] +Key: MAXCSSrr: [ 0.00 0.00 ] +Key: MAXPDrm: [ 0.00 0.00 ] +Key: MAXPDrr: [ 0.00 0.00 ] +Key: MAXPSrm: [ 0.00 0.00 ] +Key: MAXPSrr: [ 0.00 0.00 ] +Key: MAXSDrm: [ 0.00 0.00 ] +Key: MAXSDrm_Int: [ 0.00 0.00 ] +Key: MAXSDrr: [ 0.00 0.00 ] +Key: MAXSDrr_Int: [ 0.00 0.00 ] +Key: MAXSSrm: [ 0.00 0.00 ] +Key: MAXSSrm_Int: [ 0.00 0.00 ] +Key: MAXSSrr: [ 0.00 0.00 ] +Key: MAXSSrr_Int: [ 0.00 0.00 ] +Key: MEMBARRIER: [ 0.00 0.00 ] +Key: MFENCE: [ 0.00 0.00 ] +Key: MINCPDrm: [ 0.00 0.00 ] +Key: MINCPDrr: [ 0.00 0.00 ] +Key: MINCPSrm: [ 0.00 0.00 ] +Key: MINCPSrr: [ 0.00 0.00 ] +Key: MINCSDrm: [ 0.00 0.00 ] +Key: MINCSDrr: [ 0.00 0.00 ] +Key: MINCSSrm: [ 0.00 0.00 ] +Key: MINCSSrr: [ 0.00 0.00 ] +Key: MINPDrm: [ 0.00 0.00 ] +Key: MINPDrr: [ 0.00 0.00 ] +Key: MINPSrm: [ 0.00 0.00 ] +Key: MINPSrr: [ 0.00 0.00 ] +Key: MINSDrm: [ 0.00 0.00 ] +Key: MINSDrm_Int: [ 0.00 0.00 ] +Key: MINSDrr: [ 0.00 0.00 ] +Key: MINSDrr_Int: [ 0.00 0.00 ] +Key: MINSSrm: [ 0.00 0.00 ] +Key: MINSSrm_Int: [ 0.00 0.00 ] +Key: MINSSrr: [ 0.00 0.00 ] +Key: MINSSrr_Int: [ 0.00 0.00 ] +Key: MMX_CVTPD: [ 0.00 0.00 ] +Key: MMX_CVTPI: [ 0.00 0.00 ] +Key: MMX_CVTPS: [ 0.00 0.00 ] +Key: MMX_CVTTPD: [ 0.00 0.00 ] +Key: MMX_CVTTPS: [ 0.00 0.00 ] +Key: MMX_EMMS: [ 0.00 0.00 ] +Key: MMX_MASKMOVQ: [ 0.00 0.00 ] +Key: MMX_MOVD: [ 0.00 0.00 ] +Key: MMX_MOVDQ: [ 0.00 0.00 ] +Key: MMX_MOVFR: [ 0.00 0.00 ] +Key: MMX_MOVNTQmr: [ 0.00 0.00 ] +Key: MMX_MOVQ: [ 0.00 0.00 ] +Key: MMX_PABSBrm: [ 0.00 0.00 ] +Key: MMX_PABSBrr: [ 0.00 0.00 ] +Key: MMX_PABSDrm: [ 0.00 0.00 ] +Key: MMX_PABSDrr: [ 0.00 0.00 ] +Key: MMX_PABSWrm: [ 0.00 0.00 ] +Key: MMX_PABSWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrm: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrr: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrr: [ 0.00 0.00 ] +Key: MMX_PADDBrm: [ 0.00 0.00 ] +Key: MMX_PADDBrr: [ 0.00 0.00 ] +Key: MMX_PADDDrm: [ 0.00 0.00 ] +Key: MMX_PADDDrr: [ 0.00 0.00 ] +Key: MMX_PADDQrm: [ 0.00 0.00 ] +Key: MMX_PADDQrr: [ 0.00 0.00 ] +Key: MMX_PADDSBrm: [ 0.00 0.00 ] +Key: MMX_PADDSBrr: [ 0.00 0.00 ] +Key: MMX_PADDSWrm: [ 0.00 0.00 ] +Key: MMX_PADDSWrr: [ 0.00 0.00 ] +Key: MMX_PADDUSBrm: [ 0.00 0.00 ] +Key: MMX_PADDUSBrr: [ 0.00 0.00 ] +Key: MMX_PADDUSWrm: [ 0.00 0.00 ] +Key: MMX_PADDUSWrr: [ 0.00 0.00 ] +Key: MMX_PADDWrm: [ 0.00 0.00 ] +Key: MMX_PADDWrr: [ 0.00 0.00 ] +Key: MMX_PALIGNRrmi: [ 0.00 0.00 ] +Key: MMX_PALIGNRrri: [ 0.00 0.00 ] +Key: MMX_PANDNrm: [ 0.00 0.00 ] +Key: MMX_PANDNrr: [ 0.00 0.00 ] +Key: MMX_PANDrm: [ 0.00 0.00 ] +Key: MMX_PANDrr: [ 0.00 0.00 ] +Key: MMX_PAVGBrm: [ 0.00 0.00 ] +Key: MMX_PAVGBrr: [ 0.00 0.00 ] +Key: MMX_PAVGWrm: [ 0.00 0.00 ] +Key: MMX_PAVGWrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrr: [ 0.00 0.00 ] +Key: MMX_PEXTRWrri: [ 0.00 0.00 ] +Key: MMX_PHADDDrm: [ 0.00 0.00 ] +Key: MMX_PHADDDrr: [ 0.00 0.00 ] +Key: MMX_PHADDSWrm: [ 0.00 0.00 ] +Key: MMX_PHADDSWrr: [ 0.00 0.00 ] +Key: MMX_PHADDWrm: [ 0.00 0.00 ] +Key: MMX_PHADDWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBDrm: [ 0.00 0.00 ] +Key: MMX_PHSUBDrr: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBWrr: [ 0.00 0.00 ] +Key: MMX_PINSRWrmi: [ 0.00 0.00 ] +Key: MMX_PINSRWrri: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrm: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrr: [ 0.00 0.00 ] +Key: MMX_PMADDWDrm: [ 0.00 0.00 ] +Key: MMX_PMADDWDrr: [ 0.00 0.00 ] +Key: MMX_PMAXSWrm: [ 0.00 0.00 ] +Key: MMX_PMAXSWrr: [ 0.00 0.00 ] +Key: MMX_PMAXUBrm: [ 0.00 0.00 ] +Key: MMX_PMAXUBrr: [ 0.00 0.00 ] +Key: MMX_PMINSWrm: [ 0.00 0.00 ] +Key: MMX_PMINSWrr: [ 0.00 0.00 ] +Key: MMX_PMINUBrm: [ 0.00 0.00 ] +Key: MMX_PMINUBrr: [ 0.00 0.00 ] +Key: MMX_PMOVMSKBrr: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrm: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrr: [ 0.00 0.00 ] +Key: MMX_PMULHUWrm: [ 0.00 0.00 ] +Key: MMX_PMULHUWrr: [ 0.00 0.00 ] +Key: MMX_PMULHWrm: [ 0.00 0.00 ] +Key: MMX_PMULHWrr: [ 0.00 0.00 ] +Key: MMX_PMULLWrm: [ 0.00 0.00 ] +Key: MMX_PMULLWrr: [ 0.00 0.00 ] +Key: MMX_PMULUDQrm: [ 0.00 0.00 ] +Key: MMX_PMULUDQrr: [ 0.00 0.00 ] +Key: MMX_PORrm: [ 0.00 0.00 ] +Key: MMX_PORrr: [ 0.00 0.00 ] +Key: MMX_PSADBWrm: [ 0.00 0.00 ] +Key: MMX_PSADBWrr: [ 0.00 0.00 ] +Key: MMX_PSHUFBrm: [ 0.00 0.00 ] +Key: MMX_PSHUFBrr: [ 0.00 0.00 ] +Key: MMX_PSHUFWmi: [ 0.00 0.00 ] +Key: MMX_PSHUFWri: [ 0.00 0.00 ] +Key: MMX_PSIGNBrm: [ 0.00 0.00 ] +Key: MMX_PSIGNBrr: [ 0.00 0.00 ] +Key: MMX_PSIGNDrm: [ 0.00 0.00 ] +Key: MMX_PSIGNDrr: [ 0.00 0.00 ] +Key: MMX_PSIGNWrm: [ 0.00 0.00 ] +Key: MMX_PSIGNWrr: [ 0.00 0.00 ] +Key: MMX_PSLLDri: [ 0.00 0.00 ] +Key: MMX_PSLLDrm: [ 0.00 0.00 ] +Key: MMX_PSLLDrr: [ 0.00 0.00 ] +Key: MMX_PSLLQri: [ 0.00 0.00 ] +Key: MMX_PSLLQrm: [ 0.00 0.00 ] +Key: MMX_PSLLQrr: [ 0.00 0.00 ] +Key: MMX_PSLLWri: [ 0.00 0.00 ] +Key: MMX_PSLLWrm: [ 0.00 0.00 ] +Key: MMX_PSLLWrr: [ 0.00 0.00 ] +Key: MMX_PSRADri: [ 0.00 0.00 ] +Key: MMX_PSRADrm: [ 0.00 0.00 ] +Key: MMX_PSRADrr: [ 0.00 0.00 ] +Key: MMX_PSRAWri: [ 0.00 0.00 ] +Key: MMX_PSRAWrm: [ 0.00 0.00 ] +Key: MMX_PSRAWrr: [ 0.00 0.00 ] +Key: MMX_PSRLDri: [ 0.00 0.00 ] +Key: MMX_PSRLDrm: [ 0.00 0.00 ] +Key: MMX_PSRLDrr: [ 0.00 0.00 ] +Key: MMX_PSRLQri: [ 0.00 0.00 ] +Key: MMX_PSRLQrm: [ 0.00 0.00 ] +Key: MMX_PSRLQrr: [ 0.00 0.00 ] +Key: MMX_PSRLWri: [ 0.00 0.00 ] +Key: MMX_PSRLWrm: [ 0.00 0.00 ] +Key: MMX_PSRLWrr: [ 0.00 0.00 ] +Key: MMX_PSUBBrm: [ 0.00 0.00 ] +Key: MMX_PSUBBrr: [ 0.00 0.00 ] +Key: MMX_PSUBDrm: [ 0.00 0.00 ] +Key: MMX_PSUBDrr: [ 0.00 0.00 ] +Key: MMX_PSUBQrm: [ 0.00 0.00 ] +Key: MMX_PSUBQrr: [ 0.00 0.00 ] +Key: MMX_PSUBSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBWrm: [ 0.00 0.00 ] +Key: MMX_PSUBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrr: [ 0.00 0.00 ] +Key: MMX_PXORrm: [ 0.00 0.00 ] +Key: MMX_PXORrr: [ 0.00 0.00 ] +Key: MMX_SET: [ 0.00 0.00 ] +Key: MONITOR: [ 0.00 0.00 ] +Key: MONITORX: [ 0.00 0.00 ] +Key: MONTMUL: [ 0.00 0.00 ] +Key: MORESTACK_RET: [ 0.00 0.00 ] +Key: MORESTACK_RET_RESTORE_R: [ 0.00 0.00 ] +Key: MOV: [ 0.00 0.00 ] +Key: MOVAPDmr: [ 0.00 0.00 ] +Key: MOVAPDrm: [ 0.00 0.00 ] +Key: MOVAPDrr: [ 0.00 0.00 ] +Key: MOVAPDrr_REV: [ 0.00 0.00 ] +Key: MOVAPSmr: [ 0.00 0.00 ] +Key: MOVAPSrm: [ 0.00 0.00 ] +Key: MOVAPSrr: [ 0.00 0.00 ] +Key: MOVAPSrr_REV: [ 0.00 0.00 ] +Key: MOVBE: [ 0.00 0.00 ] +Key: MOVDDUPrm: [ 0.00 0.00 ] +Key: MOVDDUPrr: [ 0.00 0.00 ] +Key: MOVDI: [ 0.00 0.00 ] +Key: MOVDIR: [ 0.00 0.00 ] +Key: MOVDIRI: [ 0.00 0.00 ] +Key: MOVDQAmr: [ 0.00 0.00 ] +Key: MOVDQArm: [ 0.00 0.00 ] +Key: MOVDQArr: [ 0.00 0.00 ] +Key: MOVDQArr_REV: [ 0.00 0.00 ] +Key: MOVDQUmr: [ 0.00 0.00 ] +Key: MOVDQUrm: [ 0.00 0.00 ] +Key: MOVDQUrr: [ 0.00 0.00 ] +Key: MOVDQUrr_REV: [ 0.00 0.00 ] +Key: MOVHLPSrr: [ 0.00 0.00 ] +Key: MOVHPDmr: [ 0.00 0.00 ] +Key: MOVHPDrm: [ 0.00 0.00 ] +Key: MOVHPSmr: [ 0.00 0.00 ] +Key: MOVHPSrm: [ 0.00 0.00 ] +Key: MOVLHPSrr: [ 0.00 0.00 ] +Key: MOVLPDmr: [ 0.00 0.00 ] +Key: MOVLPDrm: [ 0.00 0.00 ] +Key: MOVLPSmr: [ 0.00 0.00 ] +Key: MOVLPSrm: [ 0.00 0.00 ] +Key: MOVMSKPDrr: [ 0.00 0.00 ] +Key: MOVMSKPSrr: [ 0.00 0.00 ] +Key: MOVNTDQArm: [ 0.00 0.00 ] +Key: MOVNTDQmr: [ 0.00 0.00 ] +Key: MOVNTI: [ 0.00 0.00 ] +Key: MOVNTImr: [ 0.00 0.00 ] +Key: MOVNTPDmr: [ 0.00 0.00 ] +Key: MOVNTPSmr: [ 0.00 0.00 ] +Key: MOVNTSD: [ 0.00 0.00 ] +Key: MOVNTSS: [ 0.00 0.00 ] +Key: MOVPC: [ 0.00 0.00 ] +Key: MOVPDI: [ 0.00 0.00 ] +Key: MOVPQI: [ 0.00 0.00 ] +Key: MOVPQIto: [ 0.00 0.00 ] +Key: MOVQI: [ 0.00 0.00 ] +Key: MOVRS: [ 0.00 0.00 ] +Key: MOVSB: [ 0.00 0.00 ] +Key: MOVSDmr: [ 0.00 0.00 ] +Key: MOVSDrm: [ 0.00 0.00 ] +Key: MOVSDrm_alt: [ 0.00 0.00 ] +Key: MOVSDrr: [ 0.00 0.00 ] +Key: MOVSDrr_REV: [ 0.00 0.00 ] +Key: MOVSDto: [ 0.00 0.00 ] +Key: MOVSHDUPrm: [ 0.00 0.00 ] +Key: MOVSHDUPrr: [ 0.00 0.00 ] +Key: MOVSHPmr: [ 0.00 0.00 ] +Key: MOVSHPrm: [ 0.00 0.00 ] +Key: MOVSL: [ 0.00 0.00 ] +Key: MOVSLDUPrm: [ 0.00 0.00 ] +Key: MOVSLDUPrr: [ 0.00 0.00 ] +Key: MOVSQ: [ 0.00 0.00 ] +Key: MOVSS: [ 0.00 0.00 ] +Key: MOVSSmr: [ 0.00 0.00 ] +Key: MOVSSrm: [ 0.00 0.00 ] +Key: MOVSSrm_alt: [ 0.00 0.00 ] +Key: MOVSSrr: [ 0.00 0.00 ] +Key: MOVSSrr_REV: [ 0.00 0.00 ] +Key: MOVSW: [ 0.00 0.00 ] +Key: MOVSX: [ 0.00 0.00 ] +Key: MOVUPDmr: [ 0.00 0.00 ] +Key: MOVUPDrm: [ 0.00 0.00 ] +Key: MOVUPDrr: [ 0.00 0.00 ] +Key: MOVUPDrr_REV: [ 0.00 0.00 ] +Key: MOVUPSmr: [ 0.00 0.00 ] +Key: MOVUPSrm: [ 0.00 0.00 ] +Key: MOVUPSrr: [ 0.00 0.00 ] +Key: MOVUPSrr_REV: [ 0.00 0.00 ] +Key: MOVZPQILo: [ 0.00 0.00 ] +Key: MOVZX: [ 0.00 0.00 ] +Key: MPSADBWrmi: [ 0.00 0.00 ] +Key: MPSADBWrri: [ 0.00 0.00 ] +Key: MUL: [ 0.00 0.00 ] +Key: MULPDrm: [ 0.00 0.00 ] +Key: MULPDrr: [ 0.00 0.00 ] +Key: MULPSrm: [ 0.00 0.00 ] +Key: MULPSrr: [ 0.00 0.00 ] +Key: MULSDrm: [ 0.00 0.00 ] +Key: MULSDrm_Int: [ 0.00 0.00 ] +Key: MULSDrr: [ 0.00 0.00 ] +Key: MULSDrr_Int: [ 0.00 0.00 ] +Key: MULSSrm: [ 0.00 0.00 ] +Key: MULSSrm_Int: [ 0.00 0.00 ] +Key: MULSSrr: [ 0.00 0.00 ] +Key: MULSSrr_Int: [ 0.00 0.00 ] +Key: MULX: [ 0.00 0.00 ] +Key: MUL_F: [ 0.00 0.00 ] +Key: MUL_FI: [ 0.00 0.00 ] +Key: MUL_FPrST: [ 0.00 0.00 ] +Key: MUL_FST: [ 0.00 0.00 ] +Key: MUL_Fp: [ 0.00 0.00 ] +Key: MUL_FpI: [ 0.00 0.00 ] +Key: MUL_FrST: [ 0.00 0.00 ] +Key: MWAITX: [ 0.00 0.00 ] +Key: MWAITX_SAVE_RBX: [ 0.00 0.00 ] +Key: MWAITXrrr: [ 0.00 0.00 ] +Key: MWAITrr: [ 0.00 0.00 ] +Key: NEG: [ 0.00 0.00 ] +Key: NOOP: [ 0.00 0.00 ] +Key: NOOPL: [ 0.00 0.00 ] +Key: NOOPLr: [ 0.00 0.00 ] +Key: NOOPQ: [ 0.00 0.00 ] +Key: NOOPQr: [ 0.00 0.00 ] +Key: NOOPW: [ 0.00 0.00 ] +Key: NOOPWr: [ 0.00 0.00 ] +Key: NOT: [ 0.00 0.00 ] +Key: OR: [ 0.00 0.00 ] +Key: ORPDrm: [ 0.00 0.00 ] +Key: ORPDrr: [ 0.00 0.00 ] +Key: ORPSrm: [ 0.00 0.00 ] +Key: ORPSrr: [ 0.00 0.00 ] +Key: OUT: [ 0.00 0.00 ] +Key: OUTSB: [ 0.00 0.00 ] +Key: OUTSL: [ 0.00 0.00 ] +Key: OUTSW: [ 0.00 0.00 ] +Key: PABSBrm: [ 0.00 0.00 ] +Key: PABSBrr: [ 0.00 0.00 ] +Key: PABSDrm: [ 0.00 0.00 ] +Key: PABSDrr: [ 0.00 0.00 ] +Key: PABSWrm: [ 0.00 0.00 ] +Key: PABSWrr: [ 0.00 0.00 ] +Key: PACKSSDWrm: [ 0.00 0.00 ] +Key: PACKSSDWrr: [ 0.00 0.00 ] +Key: PACKSSWBrm: [ 0.00 0.00 ] +Key: PACKSSWBrr: [ 0.00 0.00 ] +Key: PACKUSDWrm: [ 0.00 0.00 ] +Key: PACKUSDWrr: [ 0.00 0.00 ] +Key: PACKUSWBrm: [ 0.00 0.00 ] +Key: PACKUSWBrr: [ 0.00 0.00 ] +Key: PADDBrm: [ 0.00 0.00 ] +Key: PADDBrr: [ 0.00 0.00 ] +Key: PADDDrm: [ 0.00 0.00 ] +Key: PADDDrr: [ 0.00 0.00 ] +Key: PADDQrm: [ 0.00 0.00 ] +Key: PADDQrr: [ 0.00 0.00 ] +Key: PADDSBrm: [ 0.00 0.00 ] +Key: PADDSBrr: [ 0.00 0.00 ] +Key: PADDSWrm: [ 0.00 0.00 ] +Key: PADDSWrr: [ 0.00 0.00 ] +Key: PADDUSBrm: [ 0.00 0.00 ] +Key: PADDUSBrr: [ 0.00 0.00 ] +Key: PADDUSWrm: [ 0.00 0.00 ] +Key: PADDUSWrr: [ 0.00 0.00 ] +Key: PADDWrm: [ 0.00 0.00 ] +Key: PADDWrr: [ 0.00 0.00 ] +Key: PALIGNRrmi: [ 0.00 0.00 ] +Key: PALIGNRrri: [ 0.00 0.00 ] +Key: PANDNrm: [ 0.00 0.00 ] +Key: PANDNrr: [ 0.00 0.00 ] +Key: PANDrm: [ 0.00 0.00 ] +Key: PANDrr: [ 0.00 0.00 ] +Key: PATCHABLE_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_ENTER: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_EXIT: [ 0.00 0.00 ] +Key: PATCHABLE_OP: [ 0.00 0.00 ] +Key: PATCHABLE_RET: [ 0.00 0.00 ] +Key: PATCHABLE_TAIL_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_TYPED_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHPOINT: [ 0.00 0.00 ] +Key: PAUSE: [ 0.00 0.00 ] +Key: PAVGBrm: [ 0.00 0.00 ] +Key: PAVGBrr: [ 0.00 0.00 ] +Key: PAVGUSBrm: [ 0.00 0.00 ] +Key: PAVGUSBrr: [ 0.00 0.00 ] +Key: PAVGWrm: [ 0.00 0.00 ] +Key: PAVGWrr: [ 0.00 0.00 ] +Key: PBLENDVBrm: [ 0.00 0.00 ] +Key: PBLENDVBrr: [ 0.00 0.00 ] +Key: PBLENDWrmi: [ 0.00 0.00 ] +Key: PBLENDWrri: [ 0.00 0.00 ] +Key: PBNDKB: [ 0.00 0.00 ] +Key: PCLMULQDQrmi: [ 0.00 0.00 ] +Key: PCLMULQDQrri: [ 0.00 0.00 ] +Key: PCMPEQBrm: [ 0.00 0.00 ] +Key: PCMPEQBrr: [ 0.00 0.00 ] +Key: PCMPEQDrm: [ 0.00 0.00 ] +Key: PCMPEQDrr: [ 0.00 0.00 ] +Key: PCMPEQQrm: [ 0.00 0.00 ] +Key: PCMPEQQrr: [ 0.00 0.00 ] +Key: PCMPEQWrm: [ 0.00 0.00 ] +Key: PCMPEQWrr: [ 0.00 0.00 ] +Key: PCMPESTRIrmi: [ 0.00 0.00 ] +Key: PCMPESTRIrri: [ 0.00 0.00 ] +Key: PCMPESTRMrmi: [ 0.00 0.00 ] +Key: PCMPESTRMrri: [ 0.00 0.00 ] +Key: PCMPGTBrm: [ 0.00 0.00 ] +Key: PCMPGTBrr: [ 0.00 0.00 ] +Key: PCMPGTDrm: [ 0.00 0.00 ] +Key: PCMPGTDrr: [ 0.00 0.00 ] +Key: PCMPGTQrm: [ 0.00 0.00 ] +Key: PCMPGTQrr: [ 0.00 0.00 ] +Key: PCMPGTWrm: [ 0.00 0.00 ] +Key: PCMPGTWrr: [ 0.00 0.00 ] +Key: PCMPISTRIrmi: [ 0.00 0.00 ] +Key: PCMPISTRIrri: [ 0.00 0.00 ] +Key: PCMPISTRMrmi: [ 0.00 0.00 ] +Key: PCMPISTRMrri: [ 0.00 0.00 ] +Key: PCONFIG: [ 0.00 0.00 ] +Key: PDEP: [ 0.00 0.00 ] +Key: PEXT: [ 0.00 0.00 ] +Key: PEXTRBmri: [ 0.00 0.00 ] +Key: PEXTRBrri: [ 0.00 0.00 ] +Key: PEXTRDmri: [ 0.00 0.00 ] +Key: PEXTRDrri: [ 0.00 0.00 ] +Key: PEXTRQmri: [ 0.00 0.00 ] +Key: PEXTRQrri: [ 0.00 0.00 ] +Key: PEXTRWmri: [ 0.00 0.00 ] +Key: PEXTRWrri: [ 0.00 0.00 ] +Key: PEXTRWrri_REV: [ 0.00 0.00 ] +Key: PF: [ 0.00 0.00 ] +Key: PFACCrm: [ 0.00 0.00 ] +Key: PFACCrr: [ 0.00 0.00 ] +Key: PFADDrm: [ 0.00 0.00 ] +Key: PFADDrr: [ 0.00 0.00 ] +Key: PFCMPEQrm: [ 0.00 0.00 ] +Key: PFCMPEQrr: [ 0.00 0.00 ] +Key: PFCMPGErm: [ 0.00 0.00 ] +Key: PFCMPGErr: [ 0.00 0.00 ] +Key: PFCMPGTrm: [ 0.00 0.00 ] +Key: PFCMPGTrr: [ 0.00 0.00 ] +Key: PFMAXrm: [ 0.00 0.00 ] +Key: PFMAXrr: [ 0.00 0.00 ] +Key: PFMINrm: [ 0.00 0.00 ] +Key: PFMINrr: [ 0.00 0.00 ] +Key: PFMULrm: [ 0.00 0.00 ] +Key: PFMULrr: [ 0.00 0.00 ] +Key: PFNACCrm: [ 0.00 0.00 ] +Key: PFNACCrr: [ 0.00 0.00 ] +Key: PFPNACCrm: [ 0.00 0.00 ] +Key: PFPNACCrr: [ 0.00 0.00 ] +Key: PFRCPIT: [ 0.00 0.00 ] +Key: PFRCPrm: [ 0.00 0.00 ] +Key: PFRCPrr: [ 0.00 0.00 ] +Key: PFRSQIT: [ 0.00 0.00 ] +Key: PFRSQRTrm: [ 0.00 0.00 ] +Key: PFRSQRTrr: [ 0.00 0.00 ] +Key: PFSUBRrm: [ 0.00 0.00 ] +Key: PFSUBRrr: [ 0.00 0.00 ] +Key: PFSUBrm: [ 0.00 0.00 ] +Key: PFSUBrr: [ 0.00 0.00 ] +Key: PHADDDrm: [ 0.00 0.00 ] +Key: PHADDDrr: [ 0.00 0.00 ] +Key: PHADDSWrm: [ 0.00 0.00 ] +Key: PHADDSWrr: [ 0.00 0.00 ] +Key: PHADDWrm: [ 0.00 0.00 ] +Key: PHADDWrr: [ 0.00 0.00 ] +Key: PHI: [ 0.00 0.00 ] +Key: PHMINPOSUWrm: [ 0.00 0.00 ] +Key: PHMINPOSUWrr: [ 0.00 0.00 ] +Key: PHSUBDrm: [ 0.00 0.00 ] +Key: PHSUBDrr: [ 0.00 0.00 ] +Key: PHSUBSWrm: [ 0.00 0.00 ] +Key: PHSUBSWrr: [ 0.00 0.00 ] +Key: PHSUBWrm: [ 0.00 0.00 ] +Key: PHSUBWrr: [ 0.00 0.00 ] +Key: PI: [ 0.00 0.00 ] +Key: PINSRBrmi: [ 0.00 0.00 ] +Key: PINSRBrri: [ 0.00 0.00 ] +Key: PINSRDrmi: [ 0.00 0.00 ] +Key: PINSRDrri: [ 0.00 0.00 ] +Key: PINSRQrmi: [ 0.00 0.00 ] +Key: PINSRQrri: [ 0.00 0.00 ] +Key: PINSRWrmi: [ 0.00 0.00 ] +Key: PINSRWrri: [ 0.00 0.00 ] +Key: PLDTILECFGV: [ 0.00 0.00 ] +Key: PLEA: [ 0.00 0.00 ] +Key: PMADDUBSWrm: [ 0.00 0.00 ] +Key: PMADDUBSWrr: [ 0.00 0.00 ] +Key: PMADDWDrm: [ 0.00 0.00 ] +Key: PMADDWDrr: [ 0.00 0.00 ] +Key: PMAXSBrm: [ 0.00 0.00 ] +Key: PMAXSBrr: [ 0.00 0.00 ] +Key: PMAXSDrm: [ 0.00 0.00 ] +Key: PMAXSDrr: [ 0.00 0.00 ] +Key: PMAXSWrm: [ 0.00 0.00 ] +Key: PMAXSWrr: [ 0.00 0.00 ] +Key: PMAXUBrm: [ 0.00 0.00 ] +Key: PMAXUBrr: [ 0.00 0.00 ] +Key: PMAXUDrm: [ 0.00 0.00 ] +Key: PMAXUDrr: [ 0.00 0.00 ] +Key: PMAXUWrm: [ 0.00 0.00 ] +Key: PMAXUWrr: [ 0.00 0.00 ] +Key: PMINSBrm: [ 0.00 0.00 ] +Key: PMINSBrr: [ 0.00 0.00 ] +Key: PMINSDrm: [ 0.00 0.00 ] +Key: PMINSDrr: [ 0.00 0.00 ] +Key: PMINSWrm: [ 0.00 0.00 ] +Key: PMINSWrr: [ 0.00 0.00 ] +Key: PMINUBrm: [ 0.00 0.00 ] +Key: PMINUBrr: [ 0.00 0.00 ] +Key: PMINUDrm: [ 0.00 0.00 ] +Key: PMINUDrr: [ 0.00 0.00 ] +Key: PMINUWrm: [ 0.00 0.00 ] +Key: PMINUWrr: [ 0.00 0.00 ] +Key: PMOVMSKBrr: [ 0.00 0.00 ] +Key: PMOVSXBDrm: [ 0.00 0.00 ] +Key: PMOVSXBDrr: [ 0.00 0.00 ] +Key: PMOVSXBQrm: [ 0.00 0.00 ] +Key: PMOVSXBQrr: [ 0.00 0.00 ] +Key: PMOVSXBWrm: [ 0.00 0.00 ] +Key: PMOVSXBWrr: [ 0.00 0.00 ] +Key: PMOVSXDQrm: [ 0.00 0.00 ] +Key: PMOVSXDQrr: [ 0.00 0.00 ] +Key: PMOVSXWDrm: [ 0.00 0.00 ] +Key: PMOVSXWDrr: [ 0.00 0.00 ] +Key: PMOVSXWQrm: [ 0.00 0.00 ] +Key: PMOVSXWQrr: [ 0.00 0.00 ] +Key: PMOVZXBDrm: [ 0.00 0.00 ] +Key: PMOVZXBDrr: [ 0.00 0.00 ] +Key: PMOVZXBQrm: [ 0.00 0.00 ] +Key: PMOVZXBQrr: [ 0.00 0.00 ] +Key: PMOVZXBWrm: [ 0.00 0.00 ] +Key: PMOVZXBWrr: [ 0.00 0.00 ] +Key: PMOVZXDQrm: [ 0.00 0.00 ] +Key: PMOVZXDQrr: [ 0.00 0.00 ] +Key: PMOVZXWDrm: [ 0.00 0.00 ] +Key: PMOVZXWDrr: [ 0.00 0.00 ] +Key: PMOVZXWQrm: [ 0.00 0.00 ] +Key: PMOVZXWQrr: [ 0.00 0.00 ] +Key: PMULDQrm: [ 0.00 0.00 ] +Key: PMULDQrr: [ 0.00 0.00 ] +Key: PMULHRSWrm: [ 0.00 0.00 ] +Key: PMULHRSWrr: [ 0.00 0.00 ] +Key: PMULHRWrm: [ 0.00 0.00 ] +Key: PMULHRWrr: [ 0.00 0.00 ] +Key: PMULHUWrm: [ 0.00 0.00 ] +Key: PMULHUWrr: [ 0.00 0.00 ] +Key: PMULHWrm: [ 0.00 0.00 ] +Key: PMULHWrr: [ 0.00 0.00 ] +Key: PMULLDrm: [ 0.00 0.00 ] +Key: PMULLDrr: [ 0.00 0.00 ] +Key: PMULLWrm: [ 0.00 0.00 ] +Key: PMULLWrr: [ 0.00 0.00 ] +Key: PMULUDQrm: [ 0.00 0.00 ] +Key: PMULUDQrr: [ 0.00 0.00 ] +Key: POP: [ 0.00 0.00 ] +Key: POPA: [ 0.00 0.00 ] +Key: POPCNT: [ 0.00 0.00 ] +Key: POPDS: [ 0.00 0.00 ] +Key: POPES: [ 0.00 0.00 ] +Key: POPF: [ 0.00 0.00 ] +Key: POPFS: [ 0.00 0.00 ] +Key: POPGS: [ 0.00 0.00 ] +Key: POPP: [ 0.00 0.00 ] +Key: POPSS: [ 0.00 0.00 ] +Key: PORrm: [ 0.00 0.00 ] +Key: PORrr: [ 0.00 0.00 ] +Key: PREALLOCATED_ARG: [ 0.00 0.00 ] +Key: PREALLOCATED_SETUP: [ 0.00 0.00 ] +Key: PREFETCH: [ 0.00 0.00 ] +Key: PREFETCHIT: [ 0.00 0.00 ] +Key: PREFETCHNTA: [ 0.00 0.00 ] +Key: PREFETCHRST: [ 0.00 0.00 ] +Key: PREFETCHT: [ 0.00 0.00 ] +Key: PREFETCHW: [ 0.00 0.00 ] +Key: PREFETCHWT: [ 0.00 0.00 ] +Key: PROBED_ALLOCA: [ 0.00 0.00 ] +Key: PSADBWrm: [ 0.00 0.00 ] +Key: PSADBWrr: [ 0.00 0.00 ] +Key: PSEUDO_PROBE: [ 0.00 0.00 ] +Key: PSHUFBrm: [ 0.00 0.00 ] +Key: PSHUFBrr: [ 0.00 0.00 ] +Key: PSHUFDmi: [ 0.00 0.00 ] +Key: PSHUFDri: [ 0.00 0.00 ] +Key: PSHUFHWmi: [ 0.00 0.00 ] +Key: PSHUFHWri: [ 0.00 0.00 ] +Key: PSHUFLWmi: [ 0.00 0.00 ] +Key: PSHUFLWri: [ 0.00 0.00 ] +Key: PSIGNBrm: [ 0.00 0.00 ] +Key: PSIGNBrr: [ 0.00 0.00 ] +Key: PSIGNDrm: [ 0.00 0.00 ] +Key: PSIGNDrr: [ 0.00 0.00 ] +Key: PSIGNWrm: [ 0.00 0.00 ] +Key: PSIGNWrr: [ 0.00 0.00 ] +Key: PSLLDQri: [ 0.00 0.00 ] +Key: PSLLDri: [ 0.00 0.00 ] +Key: PSLLDrm: [ 0.00 0.00 ] +Key: PSLLDrr: [ 0.00 0.00 ] +Key: PSLLQri: [ 0.00 0.00 ] +Key: PSLLQrm: [ 0.00 0.00 ] +Key: PSLLQrr: [ 0.00 0.00 ] +Key: PSLLWri: [ 0.00 0.00 ] +Key: PSLLWrm: [ 0.00 0.00 ] +Key: PSLLWrr: [ 0.00 0.00 ] +Key: PSMASH: [ 0.00 0.00 ] +Key: PSRADri: [ 0.00 0.00 ] +Key: PSRADrm: [ 0.00 0.00 ] +Key: PSRADrr: [ 0.00 0.00 ] +Key: PSRAWri: [ 0.00 0.00 ] +Key: PSRAWrm: [ 0.00 0.00 ] +Key: PSRAWrr: [ 0.00 0.00 ] +Key: PSRLDQri: [ 0.00 0.00 ] +Key: PSRLDri: [ 0.00 0.00 ] +Key: PSRLDrm: [ 0.00 0.00 ] +Key: PSRLDrr: [ 0.00 0.00 ] +Key: PSRLQri: [ 0.00 0.00 ] +Key: PSRLQrm: [ 0.00 0.00 ] +Key: PSRLQrr: [ 0.00 0.00 ] +Key: PSRLWri: [ 0.00 0.00 ] +Key: PSRLWrm: [ 0.00 0.00 ] +Key: PSRLWrr: [ 0.00 0.00 ] +Key: PSUBBrm: [ 0.00 0.00 ] +Key: PSUBBrr: [ 0.00 0.00 ] +Key: PSUBDrm: [ 0.00 0.00 ] +Key: PSUBDrr: [ 0.00 0.00 ] +Key: PSUBQrm: [ 0.00 0.00 ] +Key: PSUBQrr: [ 0.00 0.00 ] +Key: PSUBSBrm: [ 0.00 0.00 ] +Key: PSUBSBrr: [ 0.00 0.00 ] +Key: PSUBSWrm: [ 0.00 0.00 ] +Key: PSUBSWrr: [ 0.00 0.00 ] +Key: PSUBUSBrm: [ 0.00 0.00 ] +Key: PSUBUSBrr: [ 0.00 0.00 ] +Key: PSUBUSWrm: [ 0.00 0.00 ] +Key: PSUBUSWrr: [ 0.00 0.00 ] +Key: PSUBWrm: [ 0.00 0.00 ] +Key: PSUBWrr: [ 0.00 0.00 ] +Key: PSWAPDrm: [ 0.00 0.00 ] +Key: PSWAPDrr: [ 0.00 0.00 ] +Key: PT: [ 0.00 0.00 ] +Key: PTCMMIMFP: [ 0.00 0.00 ] +Key: PTCMMRLFP: [ 0.00 0.00 ] +Key: PTCONJTCMMIMFP: [ 0.00 0.00 ] +Key: PTCONJTFP: [ 0.00 0.00 ] +Key: PTCVTROWD: [ 0.00 0.00 ] +Key: PTCVTROWPS: [ 0.00 0.00 ] +Key: PTDPBF: [ 0.00 0.00 ] +Key: PTDPBHF: [ 0.00 0.00 ] +Key: PTDPBSSD: [ 0.00 0.00 ] +Key: PTDPBSSDV: [ 0.00 0.00 ] +Key: PTDPBSUD: [ 0.00 0.00 ] +Key: PTDPBSUDV: [ 0.00 0.00 ] +Key: PTDPBUSD: [ 0.00 0.00 ] +Key: PTDPBUSDV: [ 0.00 0.00 ] +Key: PTDPBUUD: [ 0.00 0.00 ] +Key: PTDPBUUDV: [ 0.00 0.00 ] +Key: PTDPFP: [ 0.00 0.00 ] +Key: PTDPHBF: [ 0.00 0.00 ] +Key: PTDPHF: [ 0.00 0.00 ] +Key: PTESTrm: [ 0.00 0.00 ] +Key: PTESTrr: [ 0.00 0.00 ] +Key: PTILELOADD: [ 0.00 0.00 ] +Key: PTILELOADDRS: [ 0.00 0.00 ] +Key: PTILELOADDRST: [ 0.00 0.00 ] +Key: PTILELOADDRSV: [ 0.00 0.00 ] +Key: PTILELOADDT: [ 0.00 0.00 ] +Key: PTILELOADDV: [ 0.00 0.00 ] +Key: PTILEMOVROWrre: [ 0.00 0.00 ] +Key: PTILEMOVROWrreV: [ 0.00 0.00 ] +Key: PTILEMOVROWrri: [ 0.00 0.00 ] +Key: PTILEMOVROWrriV: [ 0.00 0.00 ] +Key: PTILEPAIRLOAD: [ 0.00 0.00 ] +Key: PTILEPAIRSTORE: [ 0.00 0.00 ] +Key: PTILESTORED: [ 0.00 0.00 ] +Key: PTILESTOREDV: [ 0.00 0.00 ] +Key: PTILEZERO: [ 0.00 0.00 ] +Key: PTILEZEROV: [ 0.00 0.00 ] +Key: PTMMULTF: [ 0.00 0.00 ] +Key: PTTCMMIMFP: [ 0.00 0.00 ] +Key: PTTCMMRLFP: [ 0.00 0.00 ] +Key: PTTDPBF: [ 0.00 0.00 ] +Key: PTTDPFP: [ 0.00 0.00 ] +Key: PTTMMULTF: [ 0.00 0.00 ] +Key: PTTRANSPOSED: [ 0.00 0.00 ] +Key: PTTRANSPOSEDV: [ 0.00 0.00 ] +Key: PTWRITE: [ 0.00 0.00 ] +Key: PTWRITEm: [ 0.00 0.00 ] +Key: PTWRITEr: [ 0.00 0.00 ] +Key: PUNPCKHBWrm: [ 0.00 0.00 ] +Key: PUNPCKHBWrr: [ 0.00 0.00 ] +Key: PUNPCKHDQrm: [ 0.00 0.00 ] +Key: PUNPCKHDQrr: [ 0.00 0.00 ] +Key: PUNPCKHQDQrm: [ 0.00 0.00 ] +Key: PUNPCKHQDQrr: [ 0.00 0.00 ] +Key: PUNPCKHWDrm: [ 0.00 0.00 ] +Key: PUNPCKHWDrr: [ 0.00 0.00 ] +Key: PUNPCKLBWrm: [ 0.00 0.00 ] +Key: PUNPCKLBWrr: [ 0.00 0.00 ] +Key: PUNPCKLDQrm: [ 0.00 0.00 ] +Key: PUNPCKLDQrr: [ 0.00 0.00 ] +Key: PUNPCKLQDQrm: [ 0.00 0.00 ] +Key: PUNPCKLQDQrr: [ 0.00 0.00 ] +Key: PUNPCKLWDrm: [ 0.00 0.00 ] +Key: PUNPCKLWDrr: [ 0.00 0.00 ] +Key: PUSH: [ 0.00 0.00 ] +Key: PUSHA: [ 0.00 0.00 ] +Key: PUSHCS: [ 0.00 0.00 ] +Key: PUSHDS: [ 0.00 0.00 ] +Key: PUSHES: [ 0.00 0.00 ] +Key: PUSHF: [ 0.00 0.00 ] +Key: PUSHFS: [ 0.00 0.00 ] +Key: PUSHGS: [ 0.00 0.00 ] +Key: PUSHP: [ 0.00 0.00 ] +Key: PUSHSS: [ 0.00 0.00 ] +Key: PVALIDATE: [ 0.00 0.00 ] +Key: PXORrm: [ 0.00 0.00 ] +Key: PXORrr: [ 0.00 0.00 ] +Key: RCL: [ 0.00 0.00 ] +Key: RCPPSm: [ 0.00 0.00 ] +Key: RCPPSr: [ 0.00 0.00 ] +Key: RCPSSm: [ 0.00 0.00 ] +Key: RCPSSm_Int: [ 0.00 0.00 ] +Key: RCPSSr: [ 0.00 0.00 ] +Key: RCPSSr_Int: [ 0.00 0.00 ] +Key: RCR: [ 0.00 0.00 ] +Key: RDFLAGS: [ 0.00 0.00 ] +Key: RDFSBASE: [ 0.00 0.00 ] +Key: RDGSBASE: [ 0.00 0.00 ] +Key: RDMSR: [ 0.00 0.00 ] +Key: RDMSRLIST: [ 0.00 0.00 ] +Key: RDMSRri: [ 0.00 0.00 ] +Key: RDMSRri_EVEX: [ 0.00 0.00 ] +Key: RDPID: [ 0.00 0.00 ] +Key: RDPKRUr: [ 0.00 0.00 ] +Key: RDPMC: [ 0.00 0.00 ] +Key: RDPRU: [ 0.00 0.00 ] +Key: RDRAND: [ 0.00 0.00 ] +Key: RDSEED: [ 0.00 0.00 ] +Key: RDSSPD: [ 0.00 0.00 ] +Key: RDSSPQ: [ 0.00 0.00 ] +Key: RDTSC: [ 0.00 0.00 ] +Key: RDTSCP: [ 0.00 0.00 ] +Key: REG_SEQUENCE: [ 0.00 0.00 ] +Key: REPNE_PREFIX: [ 0.00 0.00 ] +Key: REP_MOVSB: [ 0.00 0.00 ] +Key: REP_MOVSD: [ 0.00 0.00 ] +Key: REP_MOVSQ: [ 0.00 0.00 ] +Key: REP_MOVSW: [ 0.00 0.00 ] +Key: REP_PREFIX: [ 0.00 0.00 ] +Key: REP_STOSB: [ 0.00 0.00 ] +Key: REP_STOSD: [ 0.00 0.00 ] +Key: REP_STOSQ: [ 0.00 0.00 ] +Key: REP_STOSW: [ 0.00 0.00 ] +Key: RET: [ 0.00 0.00 ] +Key: RETI: [ 0.00 0.00 ] +Key: REX: [ 0.00 0.00 ] +Key: RMPADJUST: [ 0.00 0.00 ] +Key: RMPQUERY: [ 0.00 0.00 ] +Key: RMPUPDATE: [ 0.00 0.00 ] +Key: ROL: [ 0.00 0.00 ] +Key: ROR: [ 0.00 0.00 ] +Key: RORX: [ 0.00 0.00 ] +Key: ROUNDPDmi: [ 0.00 0.00 ] +Key: ROUNDPDri: [ 0.00 0.00 ] +Key: ROUNDPSmi: [ 0.00 0.00 ] +Key: ROUNDPSri: [ 0.00 0.00 ] +Key: ROUNDSDmi: [ 0.00 0.00 ] +Key: ROUNDSDmi_Int: [ 0.00 0.00 ] +Key: ROUNDSDri: [ 0.00 0.00 ] +Key: ROUNDSDri_Int: [ 0.00 0.00 ] +Key: ROUNDSSmi: [ 0.00 0.00 ] +Key: ROUNDSSmi_Int: [ 0.00 0.00 ] +Key: ROUNDSSri: [ 0.00 0.00 ] +Key: ROUNDSSri_Int: [ 0.00 0.00 ] +Key: RSM: [ 0.00 0.00 ] +Key: RSQRTPSm: [ 0.00 0.00 ] +Key: RSQRTPSr: [ 0.00 0.00 ] +Key: RSQRTSSm: [ 0.00 0.00 ] +Key: RSQRTSSm_Int: [ 0.00 0.00 ] +Key: RSQRTSSr: [ 0.00 0.00 ] +Key: RSQRTSSr_Int: [ 0.00 0.00 ] +Key: RSTORSSP: [ 0.00 0.00 ] +Key: SAHF: [ 0.00 0.00 ] +Key: SALC: [ 0.00 0.00 ] +Key: SAR: [ 0.00 0.00 ] +Key: SARX: [ 0.00 0.00 ] +Key: SAVEPREVSSP: [ 0.00 0.00 ] +Key: SBB: [ 0.00 0.00 ] +Key: SCASB: [ 0.00 0.00 ] +Key: SCASL: [ 0.00 0.00 ] +Key: SCASQ: [ 0.00 0.00 ] +Key: SCASW: [ 0.00 0.00 ] +Key: SEAMCALL: [ 0.00 0.00 ] +Key: SEAMOPS: [ 0.00 0.00 ] +Key: SEAMRET: [ 0.00 0.00 ] +Key: SEG_ALLOCA: [ 0.00 0.00 ] +Key: SEH_BeginEpilogue: [ 0.00 0.00 ] +Key: SEH_EndEpilogue: [ 0.00 0.00 ] +Key: SEH_EndPrologue: [ 0.00 0.00 ] +Key: SEH_PushFrame: [ 0.00 0.00 ] +Key: SEH_PushReg: [ 0.00 0.00 ] +Key: SEH_SaveReg: [ 0.00 0.00 ] +Key: SEH_SaveXMM: [ 0.00 0.00 ] +Key: SEH_SetFrame: [ 0.00 0.00 ] +Key: SEH_StackAlign: [ 0.00 0.00 ] +Key: SEH_StackAlloc: [ 0.00 0.00 ] +Key: SEH_UnwindV: [ 0.00 0.00 ] +Key: SEH_UnwindVersion: [ 0.00 0.00 ] +Key: SENDUIPI: [ 0.00 0.00 ] +Key: SERIALIZE: [ 0.00 0.00 ] +Key: SETB_C: [ 0.00 0.00 ] +Key: SETCCm: [ 0.00 0.00 ] +Key: SETCCm_EVEX: [ 0.00 0.00 ] +Key: SETCCr: [ 0.00 0.00 ] +Key: SETCCr_EVEX: [ 0.00 0.00 ] +Key: SETSSBSY: [ 0.00 0.00 ] +Key: SETZUCCm: [ 0.00 0.00 ] +Key: SETZUCCr: [ 0.00 0.00 ] +Key: SFENCE: [ 0.00 0.00 ] +Key: SGDT: [ 0.00 0.00 ] +Key: SHA: [ 0.00 0.00 ] +Key: SHL: [ 0.00 0.00 ] +Key: SHLD: [ 0.00 0.00 ] +Key: SHLDROT: [ 0.00 0.00 ] +Key: SHLX: [ 0.00 0.00 ] +Key: SHR: [ 0.00 0.00 ] +Key: SHRD: [ 0.00 0.00 ] +Key: SHRDROT: [ 0.00 0.00 ] +Key: SHRX: [ 0.00 0.00 ] +Key: SHUFPDrmi: [ 0.00 0.00 ] +Key: SHUFPDrri: [ 0.00 0.00 ] +Key: SHUFPSrmi: [ 0.00 0.00 ] +Key: SHUFPSrri: [ 0.00 0.00 ] +Key: SIDT: [ 0.00 0.00 ] +Key: SKINIT: [ 0.00 0.00 ] +Key: SLDT: [ 0.00 0.00 ] +Key: SLWPCB: [ 0.00 0.00 ] +Key: SMSW: [ 0.00 0.00 ] +Key: SQRTPDm: [ 0.00 0.00 ] +Key: SQRTPDr: [ 0.00 0.00 ] +Key: SQRTPSm: [ 0.00 0.00 ] +Key: SQRTPSr: [ 0.00 0.00 ] +Key: SQRTSDm: [ 0.00 0.00 ] +Key: SQRTSDm_Int: [ 0.00 0.00 ] +Key: SQRTSDr: [ 0.00 0.00 ] +Key: SQRTSDr_Int: [ 0.00 0.00 ] +Key: SQRTSSm: [ 0.00 0.00 ] +Key: SQRTSSm_Int: [ 0.00 0.00 ] +Key: SQRTSSr: [ 0.00 0.00 ] +Key: SQRTSSr_Int: [ 0.00 0.00 ] +Key: SQRT_F: [ 0.00 0.00 ] +Key: SQRT_Fp: [ 0.00 0.00 ] +Key: SS_PREFIX: [ 0.00 0.00 ] +Key: STAC: [ 0.00 0.00 ] +Key: STACKALLOC_W_PROBING: [ 0.00 0.00 ] +Key: STACKMAP: [ 0.00 0.00 ] +Key: STATEPOINT: [ 0.00 0.00 ] +Key: STC: [ 0.00 0.00 ] +Key: STD: [ 0.00 0.00 ] +Key: STGI: [ 0.00 0.00 ] +Key: STI: [ 0.00 0.00 ] +Key: STMXCSR: [ 0.00 0.00 ] +Key: STOSB: [ 0.00 0.00 ] +Key: STOSL: [ 0.00 0.00 ] +Key: STOSQ: [ 0.00 0.00 ] +Key: STOSW: [ 0.00 0.00 ] +Key: STR: [ 0.00 0.00 ] +Key: STRm: [ 0.00 0.00 ] +Key: STTILECFG: [ 0.00 0.00 ] +Key: STTILECFG_EVEX: [ 0.00 0.00 ] +Key: STUI: [ 0.00 0.00 ] +Key: ST_F: [ 0.00 0.00 ] +Key: ST_FP: [ 0.00 0.00 ] +Key: ST_FPrr: [ 0.00 0.00 ] +Key: ST_Fp: [ 0.00 0.00 ] +Key: ST_FpP: [ 0.00 0.00 ] +Key: ST_Frr: [ 0.00 0.00 ] +Key: SUB: [ 0.00 0.00 ] +Key: SUBPDrm: [ 0.00 0.00 ] +Key: SUBPDrr: [ 0.00 0.00 ] +Key: SUBPSrm: [ 0.00 0.00 ] +Key: SUBPSrr: [ 0.00 0.00 ] +Key: SUBREG_TO_REG: [ 0.00 0.00 ] +Key: SUBR_F: [ 0.00 0.00 ] +Key: SUBR_FI: [ 0.00 0.00 ] +Key: SUBR_FPrST: [ 0.00 0.00 ] +Key: SUBR_FST: [ 0.00 0.00 ] +Key: SUBR_Fp: [ 0.00 0.00 ] +Key: SUBR_FpI: [ 0.00 0.00 ] +Key: SUBR_FrST: [ 0.00 0.00 ] +Key: SUBSDrm: [ 0.00 0.00 ] +Key: SUBSDrm_Int: [ 0.00 0.00 ] +Key: SUBSDrr: [ 0.00 0.00 ] +Key: SUBSDrr_Int: [ 0.00 0.00 ] +Key: SUBSSrm: [ 0.00 0.00 ] +Key: SUBSSrm_Int: [ 0.00 0.00 ] +Key: SUBSSrr: [ 0.00 0.00 ] +Key: SUBSSrr_Int: [ 0.00 0.00 ] +Key: SUB_F: [ 0.00 0.00 ] +Key: SUB_FI: [ 0.00 0.00 ] +Key: SUB_FPrST: [ 0.00 0.00 ] +Key: SUB_FST: [ 0.00 0.00 ] +Key: SUB_Fp: [ 0.00 0.00 ] +Key: SUB_FpI: [ 0.00 0.00 ] +Key: SUB_FrST: [ 0.00 0.00 ] +Key: SWAPGS: [ 0.00 0.00 ] +Key: SYSCALL: [ 0.00 0.00 ] +Key: SYSENTER: [ 0.00 0.00 ] +Key: SYSEXIT: [ 0.00 0.00 ] +Key: SYSRET: [ 0.00 0.00 ] +Key: T: [ 0.00 0.00 ] +Key: TAILJMPd: [ 0.00 0.00 ] +Key: TAILJMPd_CC: [ 0.00 0.00 ] +Key: TAILJMPm: [ 0.00 0.00 ] +Key: TAILJMPr: [ 0.00 0.00 ] +Key: TCMMIMFP: [ 0.00 0.00 ] +Key: TCMMRLFP: [ 0.00 0.00 ] +Key: TCONJTCMMIMFP: [ 0.00 0.00 ] +Key: TCONJTFP: [ 0.00 0.00 ] +Key: TCRETURN_HIPE: [ 0.00 0.00 ] +Key: TCRETURN_WIN: [ 0.00 0.00 ] +Key: TCRETURN_WINmi: [ 0.00 0.00 ] +Key: TCRETURNdi: [ 0.00 0.00 ] +Key: TCRETURNdicc: [ 0.00 0.00 ] +Key: TCRETURNmi: [ 0.00 0.00 ] +Key: TCRETURNri: [ 0.00 0.00 ] +Key: TCVTROWD: [ 0.00 0.00 ] +Key: TCVTROWPS: [ 0.00 0.00 ] +Key: TDCALL: [ 0.00 0.00 ] +Key: TDPBF: [ 0.00 0.00 ] +Key: TDPBHF: [ 0.00 0.00 ] +Key: TDPBSSD: [ 0.00 0.00 ] +Key: TDPBSUD: [ 0.00 0.00 ] +Key: TDPBUSD: [ 0.00 0.00 ] +Key: TDPBUUD: [ 0.00 0.00 ] +Key: TDPFP: [ 0.00 0.00 ] +Key: TDPHBF: [ 0.00 0.00 ] +Key: TDPHF: [ 0.00 0.00 ] +Key: TEST: [ 0.00 0.00 ] +Key: TESTUI: [ 0.00 0.00 ] +Key: TILELOADD: [ 0.00 0.00 ] +Key: TILELOADDRS: [ 0.00 0.00 ] +Key: TILELOADDRST: [ 0.00 0.00 ] +Key: TILELOADDRS_EVEX: [ 0.00 0.00 ] +Key: TILELOADDT: [ 0.00 0.00 ] +Key: TILELOADD_EVEX: [ 0.00 0.00 ] +Key: TILEMOVROWrre: [ 0.00 0.00 ] +Key: TILEMOVROWrri: [ 0.00 0.00 ] +Key: TILERELEASE: [ 0.00 0.00 ] +Key: TILESTORED: [ 0.00 0.00 ] +Key: TILESTORED_EVEX: [ 0.00 0.00 ] +Key: TILEZERO: [ 0.00 0.00 ] +Key: TLBSYNC: [ 0.00 0.00 ] +Key: TLSCall: [ 0.00 0.00 ] +Key: TLS_addr: [ 0.00 0.00 ] +Key: TLS_addrX: [ 0.00 0.00 ] +Key: TLS_base_addr: [ 0.00 0.00 ] +Key: TLS_base_addrX: [ 0.00 0.00 ] +Key: TLS_desc: [ 0.00 0.00 ] +Key: TMMULTF: [ 0.00 0.00 ] +Key: TPAUSE: [ 0.00 0.00 ] +Key: TRAP: [ 0.00 0.00 ] +Key: TST_F: [ 0.00 0.00 ] +Key: TST_Fp: [ 0.00 0.00 ] +Key: TTCMMIMFP: [ 0.00 0.00 ] +Key: TTCMMRLFP: [ 0.00 0.00 ] +Key: TTDPBF: [ 0.00 0.00 ] +Key: TTDPFP: [ 0.00 0.00 ] +Key: TTMMULTF: [ 0.00 0.00 ] +Key: TTRANSPOSED: [ 0.00 0.00 ] +Key: TZCNT: [ 0.00 0.00 ] +Key: TZMSK: [ 0.00 0.00 ] +Key: UBSAN_UD: [ 0.00 0.00 ] +Key: UCOMISDrm: [ 0.00 0.00 ] +Key: UCOMISDrm_Int: [ 0.00 0.00 ] +Key: UCOMISDrr: [ 0.00 0.00 ] +Key: UCOMISDrr_Int: [ 0.00 0.00 ] +Key: UCOMISSrm: [ 0.00 0.00 ] +Key: UCOMISSrm_Int: [ 0.00 0.00 ] +Key: UCOMISSrr: [ 0.00 0.00 ] +Key: UCOMISSrr_Int: [ 0.00 0.00 ] +Key: UCOM_FIPr: [ 0.00 0.00 ] +Key: UCOM_FIr: [ 0.00 0.00 ] +Key: UCOM_FPPr: [ 0.00 0.00 ] +Key: UCOM_FPr: [ 0.00 0.00 ] +Key: UCOM_FpIr: [ 0.00 0.00 ] +Key: UCOM_Fpr: [ 0.00 0.00 ] +Key: UCOM_Fr: [ 0.00 0.00 ] +Key: UD: [ 0.00 0.00 ] +Key: UIRET: [ 0.00 0.00 ] +Key: UMONITOR: [ 0.00 0.00 ] +Key: UMWAIT: [ 0.00 0.00 ] +Key: UNPCKHPDrm: [ 0.00 0.00 ] +Key: UNPCKHPDrr: [ 0.00 0.00 ] +Key: UNPCKHPSrm: [ 0.00 0.00 ] +Key: UNPCKHPSrr: [ 0.00 0.00 ] +Key: UNPCKLPDrm: [ 0.00 0.00 ] +Key: UNPCKLPDrr: [ 0.00 0.00 ] +Key: UNPCKLPSrm: [ 0.00 0.00 ] +Key: UNPCKLPSrr: [ 0.00 0.00 ] +Key: URDMSRri: [ 0.00 0.00 ] +Key: URDMSRri_EVEX: [ 0.00 0.00 ] +Key: URDMSRrr: [ 0.00 0.00 ] +Key: URDMSRrr_EVEX: [ 0.00 0.00 ] +Key: UWRMSRir: [ 0.00 0.00 ] +Key: UWRMSRir_EVEX: [ 0.00 0.00 ] +Key: UWRMSRrr: [ 0.00 0.00 ] +Key: UWRMSRrr_EVEX: [ 0.00 0.00 ] +Key: V: [ 0.00 0.00 ] +Key: VAARG: [ 0.00 0.00 ] +Key: VAARG_X: [ 0.00 0.00 ] +Key: VADDBF: [ 0.00 0.00 ] +Key: VADDPDYrm: [ 0.00 0.00 ] +Key: VADDPDYrr: [ 0.00 0.00 ] +Key: VADDPDZ: [ 0.00 0.00 ] +Key: VADDPDZrm: [ 0.00 0.00 ] +Key: VADDPDZrmb: [ 0.00 0.00 ] +Key: VADDPDZrmbk: [ 0.00 0.00 ] +Key: VADDPDZrmbkz: [ 0.00 0.00 ] +Key: VADDPDZrmk: [ 0.00 0.00 ] +Key: VADDPDZrmkz: [ 0.00 0.00 ] +Key: VADDPDZrr: [ 0.00 0.00 ] +Key: VADDPDZrrb: [ 0.00 0.00 ] +Key: VADDPDZrrbk: [ 0.00 0.00 ] +Key: VADDPDZrrbkz: [ 0.00 0.00 ] +Key: VADDPDZrrk: [ 0.00 0.00 ] +Key: VADDPDZrrkz: [ 0.00 0.00 ] +Key: VADDPDrm: [ 0.00 0.00 ] +Key: VADDPDrr: [ 0.00 0.00 ] +Key: VADDPHZ: [ 0.00 0.00 ] +Key: VADDPHZrm: [ 0.00 0.00 ] +Key: VADDPHZrmb: [ 0.00 0.00 ] +Key: VADDPHZrmbk: [ 0.00 0.00 ] +Key: VADDPHZrmbkz: [ 0.00 0.00 ] +Key: VADDPHZrmk: [ 0.00 0.00 ] +Key: VADDPHZrmkz: [ 0.00 0.00 ] +Key: VADDPHZrr: [ 0.00 0.00 ] +Key: VADDPHZrrb: [ 0.00 0.00 ] +Key: VADDPHZrrbk: [ 0.00 0.00 ] +Key: VADDPHZrrbkz: [ 0.00 0.00 ] +Key: VADDPHZrrk: [ 0.00 0.00 ] +Key: VADDPHZrrkz: [ 0.00 0.00 ] +Key: VADDPSYrm: [ 0.00 0.00 ] +Key: VADDPSYrr: [ 0.00 0.00 ] +Key: VADDPSZ: [ 0.00 0.00 ] +Key: VADDPSZrm: [ 0.00 0.00 ] +Key: VADDPSZrmb: [ 0.00 0.00 ] +Key: VADDPSZrmbk: [ 0.00 0.00 ] +Key: VADDPSZrmbkz: [ 0.00 0.00 ] +Key: VADDPSZrmk: [ 0.00 0.00 ] +Key: VADDPSZrmkz: [ 0.00 0.00 ] +Key: VADDPSZrr: [ 0.00 0.00 ] +Key: VADDPSZrrb: [ 0.00 0.00 ] +Key: VADDPSZrrbk: [ 0.00 0.00 ] +Key: VADDPSZrrbkz: [ 0.00 0.00 ] +Key: VADDPSZrrk: [ 0.00 0.00 ] +Key: VADDPSZrrkz: [ 0.00 0.00 ] +Key: VADDPSrm: [ 0.00 0.00 ] +Key: VADDPSrr: [ 0.00 0.00 ] +Key: VADDSDZrm: [ 0.00 0.00 ] +Key: VADDSDZrm_Int: [ 0.00 0.00 ] +Key: VADDSDZrmk_Int: [ 0.00 0.00 ] +Key: VADDSDZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrr: [ 0.00 0.00 ] +Key: VADDSDZrr_Int: [ 0.00 0.00 ] +Key: VADDSDZrrb_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrrk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSDrm: [ 0.00 0.00 ] +Key: VADDSDrm_Int: [ 0.00 0.00 ] +Key: VADDSDrr: [ 0.00 0.00 ] +Key: VADDSDrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrm: [ 0.00 0.00 ] +Key: VADDSHZrm_Int: [ 0.00 0.00 ] +Key: VADDSHZrmk_Int: [ 0.00 0.00 ] +Key: VADDSHZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrr: [ 0.00 0.00 ] +Key: VADDSHZrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrrb_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrrk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrm: [ 0.00 0.00 ] +Key: VADDSSZrm_Int: [ 0.00 0.00 ] +Key: VADDSSZrmk_Int: [ 0.00 0.00 ] +Key: VADDSSZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrr: [ 0.00 0.00 ] +Key: VADDSSZrr_Int: [ 0.00 0.00 ] +Key: VADDSSZrrb_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrrk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSrm: [ 0.00 0.00 ] +Key: VADDSSrm_Int: [ 0.00 0.00 ] +Key: VADDSSrr: [ 0.00 0.00 ] +Key: VADDSSrr_Int: [ 0.00 0.00 ] +Key: VADDSUBPDYrm: [ 0.00 0.00 ] +Key: VADDSUBPDYrr: [ 0.00 0.00 ] +Key: VADDSUBPDrm: [ 0.00 0.00 ] +Key: VADDSUBPDrr: [ 0.00 0.00 ] +Key: VADDSUBPSYrm: [ 0.00 0.00 ] +Key: VADDSUBPSYrr: [ 0.00 0.00 ] +Key: VADDSUBPSrm: [ 0.00 0.00 ] +Key: VADDSUBPSrr: [ 0.00 0.00 ] +Key: VAESDECLASTYrm: [ 0.00 0.00 ] +Key: VAESDECLASTYrr: [ 0.00 0.00 ] +Key: VAESDECLASTZ: [ 0.00 0.00 ] +Key: VAESDECLASTZrm: [ 0.00 0.00 ] +Key: VAESDECLASTZrr: [ 0.00 0.00 ] +Key: VAESDECLASTrm: [ 0.00 0.00 ] +Key: VAESDECLASTrr: [ 0.00 0.00 ] +Key: VAESDECYrm: [ 0.00 0.00 ] +Key: VAESDECYrr: [ 0.00 0.00 ] +Key: VAESDECZ: [ 0.00 0.00 ] +Key: VAESDECZrm: [ 0.00 0.00 ] +Key: VAESDECZrr: [ 0.00 0.00 ] +Key: VAESDECrm: [ 0.00 0.00 ] +Key: VAESDECrr: [ 0.00 0.00 ] +Key: VAESENCLASTYrm: [ 0.00 0.00 ] +Key: VAESENCLASTYrr: [ 0.00 0.00 ] +Key: VAESENCLASTZ: [ 0.00 0.00 ] +Key: VAESENCLASTZrm: [ 0.00 0.00 ] +Key: VAESENCLASTZrr: [ 0.00 0.00 ] +Key: VAESENCLASTrm: [ 0.00 0.00 ] +Key: VAESENCLASTrr: [ 0.00 0.00 ] +Key: VAESENCYrm: [ 0.00 0.00 ] +Key: VAESENCYrr: [ 0.00 0.00 ] +Key: VAESENCZ: [ 0.00 0.00 ] +Key: VAESENCZrm: [ 0.00 0.00 ] +Key: VAESENCZrr: [ 0.00 0.00 ] +Key: VAESENCrm: [ 0.00 0.00 ] +Key: VAESENCrr: [ 0.00 0.00 ] +Key: VAESIMCrm: [ 0.00 0.00 ] +Key: VAESIMCrr: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: VALIGNDZ: [ 0.00 0.00 ] +Key: VALIGNDZrmbi: [ 0.00 0.00 ] +Key: VALIGNDZrmbik: [ 0.00 0.00 ] +Key: VALIGNDZrmbikz: [ 0.00 0.00 ] +Key: VALIGNDZrmi: [ 0.00 0.00 ] +Key: VALIGNDZrmik: [ 0.00 0.00 ] +Key: VALIGNDZrmikz: [ 0.00 0.00 ] +Key: VALIGNDZrri: [ 0.00 0.00 ] +Key: VALIGNDZrrik: [ 0.00 0.00 ] +Key: VALIGNDZrrikz: [ 0.00 0.00 ] +Key: VALIGNQZ: [ 0.00 0.00 ] +Key: VALIGNQZrmbi: [ 0.00 0.00 ] +Key: VALIGNQZrmbik: [ 0.00 0.00 ] +Key: VALIGNQZrmbikz: [ 0.00 0.00 ] +Key: VALIGNQZrmi: [ 0.00 0.00 ] +Key: VALIGNQZrmik: [ 0.00 0.00 ] +Key: VALIGNQZrmikz: [ 0.00 0.00 ] +Key: VALIGNQZrri: [ 0.00 0.00 ] +Key: VALIGNQZrrik: [ 0.00 0.00 ] +Key: VALIGNQZrrikz: [ 0.00 0.00 ] +Key: VANDNPDYrm: [ 0.00 0.00 ] +Key: VANDNPDYrr: [ 0.00 0.00 ] +Key: VANDNPDZ: [ 0.00 0.00 ] +Key: VANDNPDZrm: [ 0.00 0.00 ] +Key: VANDNPDZrmb: [ 0.00 0.00 ] +Key: VANDNPDZrmbk: [ 0.00 0.00 ] +Key: VANDNPDZrmbkz: [ 0.00 0.00 ] +Key: VANDNPDZrmk: [ 0.00 0.00 ] +Key: VANDNPDZrmkz: [ 0.00 0.00 ] +Key: VANDNPDZrr: [ 0.00 0.00 ] +Key: VANDNPDZrrk: [ 0.00 0.00 ] +Key: VANDNPDZrrkz: [ 0.00 0.00 ] +Key: VANDNPDrm: [ 0.00 0.00 ] +Key: VANDNPDrr: [ 0.00 0.00 ] +Key: VANDNPSYrm: [ 0.00 0.00 ] +Key: VANDNPSYrr: [ 0.00 0.00 ] +Key: VANDNPSZ: [ 0.00 0.00 ] +Key: VANDNPSZrm: [ 0.00 0.00 ] +Key: VANDNPSZrmb: [ 0.00 0.00 ] +Key: VANDNPSZrmbk: [ 0.00 0.00 ] +Key: VANDNPSZrmbkz: [ 0.00 0.00 ] +Key: VANDNPSZrmk: [ 0.00 0.00 ] +Key: VANDNPSZrmkz: [ 0.00 0.00 ] +Key: VANDNPSZrr: [ 0.00 0.00 ] +Key: VANDNPSZrrk: [ 0.00 0.00 ] +Key: VANDNPSZrrkz: [ 0.00 0.00 ] +Key: VANDNPSrm: [ 0.00 0.00 ] +Key: VANDNPSrr: [ 0.00 0.00 ] +Key: VANDPDYrm: [ 0.00 0.00 ] +Key: VANDPDYrr: [ 0.00 0.00 ] +Key: VANDPDZ: [ 0.00 0.00 ] +Key: VANDPDZrm: [ 0.00 0.00 ] +Key: VANDPDZrmb: [ 0.00 0.00 ] +Key: VANDPDZrmbk: [ 0.00 0.00 ] +Key: VANDPDZrmbkz: [ 0.00 0.00 ] +Key: VANDPDZrmk: [ 0.00 0.00 ] +Key: VANDPDZrmkz: [ 0.00 0.00 ] +Key: VANDPDZrr: [ 0.00 0.00 ] +Key: VANDPDZrrk: [ 0.00 0.00 ] +Key: VANDPDZrrkz: [ 0.00 0.00 ] +Key: VANDPDrm: [ 0.00 0.00 ] +Key: VANDPDrr: [ 0.00 0.00 ] +Key: VANDPSYrm: [ 0.00 0.00 ] +Key: VANDPSYrr: [ 0.00 0.00 ] +Key: VANDPSZ: [ 0.00 0.00 ] +Key: VANDPSZrm: [ 0.00 0.00 ] +Key: VANDPSZrmb: [ 0.00 0.00 ] +Key: VANDPSZrmbk: [ 0.00 0.00 ] +Key: VANDPSZrmbkz: [ 0.00 0.00 ] +Key: VANDPSZrmk: [ 0.00 0.00 ] +Key: VANDPSZrmkz: [ 0.00 0.00 ] +Key: VANDPSZrr: [ 0.00 0.00 ] +Key: VANDPSZrrk: [ 0.00 0.00 ] +Key: VANDPSZrrkz: [ 0.00 0.00 ] +Key: VANDPSrm: [ 0.00 0.00 ] +Key: VANDPSrr: [ 0.00 0.00 ] +Key: VASTART_SAVE_XMM_REGS: [ 0.00 0.00 ] +Key: VBCSTNEBF: [ 0.00 0.00 ] +Key: VBCSTNESH: [ 0.00 0.00 ] +Key: VBLENDMPDZ: [ 0.00 0.00 ] +Key: VBLENDMPDZrm: [ 0.00 0.00 ] +Key: VBLENDMPDZrmb: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrmk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrr: [ 0.00 0.00 ] +Key: VBLENDMPDZrrk: [ 0.00 0.00 ] +Key: VBLENDMPDZrrkz: [ 0.00 0.00 ] +Key: VBLENDMPSZ: [ 0.00 0.00 ] +Key: VBLENDMPSZrm: [ 0.00 0.00 ] +Key: VBLENDMPSZrmb: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrmk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrr: [ 0.00 0.00 ] +Key: VBLENDMPSZrrk: [ 0.00 0.00 ] +Key: VBLENDMPSZrrkz: [ 0.00 0.00 ] +Key: VBLENDPDYrmi: [ 0.00 0.00 ] +Key: VBLENDPDYrri: [ 0.00 0.00 ] +Key: VBLENDPDrmi: [ 0.00 0.00 ] +Key: VBLENDPDrri: [ 0.00 0.00 ] +Key: VBLENDPSYrmi: [ 0.00 0.00 ] +Key: VBLENDPSYrri: [ 0.00 0.00 ] +Key: VBLENDPSrmi: [ 0.00 0.00 ] +Key: VBLENDPSrri: [ 0.00 0.00 ] +Key: VBLENDVPDYrmr: [ 0.00 0.00 ] +Key: VBLENDVPDYrrr: [ 0.00 0.00 ] +Key: VBLENDVPDrmr: [ 0.00 0.00 ] +Key: VBLENDVPDrrr: [ 0.00 0.00 ] +Key: VBLENDVPSYrmr: [ 0.00 0.00 ] +Key: VBLENDVPSYrrr: [ 0.00 0.00 ] +Key: VBLENDVPSrmr: [ 0.00 0.00 ] +Key: VBLENDVPSrrr: [ 0.00 0.00 ] +Key: VBROADCASTF: [ 0.00 0.00 ] +Key: VBROADCASTI: [ 0.00 0.00 ] +Key: VBROADCASTSDYrm: [ 0.00 0.00 ] +Key: VBROADCASTSDYrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZ: [ 0.00 0.00 ] +Key: VBROADCASTSDZrm: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSDZrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSYrm: [ 0.00 0.00 ] +Key: VBROADCASTSSYrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZ: [ 0.00 0.00 ] +Key: VBROADCASTSSZrm: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSSZrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSrm: [ 0.00 0.00 ] +Key: VBROADCASTSSrr: [ 0.00 0.00 ] +Key: VCMPBF: [ 0.00 0.00 ] +Key: VCMPPDYrmi: [ 0.00 0.00 ] +Key: VCMPPDYrri: [ 0.00 0.00 ] +Key: VCMPPDZ: [ 0.00 0.00 ] +Key: VCMPPDZrmbi: [ 0.00 0.00 ] +Key: VCMPPDZrmbik: [ 0.00 0.00 ] +Key: VCMPPDZrmi: [ 0.00 0.00 ] +Key: VCMPPDZrmik: [ 0.00 0.00 ] +Key: VCMPPDZrri: [ 0.00 0.00 ] +Key: VCMPPDZrrib: [ 0.00 0.00 ] +Key: VCMPPDZrribk: [ 0.00 0.00 ] +Key: VCMPPDZrrik: [ 0.00 0.00 ] +Key: VCMPPDrmi: [ 0.00 0.00 ] +Key: VCMPPDrri: [ 0.00 0.00 ] +Key: VCMPPHZ: [ 0.00 0.00 ] +Key: VCMPPHZrmbi: [ 0.00 0.00 ] +Key: VCMPPHZrmbik: [ 0.00 0.00 ] +Key: VCMPPHZrmi: [ 0.00 0.00 ] +Key: VCMPPHZrmik: [ 0.00 0.00 ] +Key: VCMPPHZrri: [ 0.00 0.00 ] +Key: VCMPPHZrrib: [ 0.00 0.00 ] +Key: VCMPPHZrribk: [ 0.00 0.00 ] +Key: VCMPPHZrrik: [ 0.00 0.00 ] +Key: VCMPPSYrmi: [ 0.00 0.00 ] +Key: VCMPPSYrri: [ 0.00 0.00 ] +Key: VCMPPSZ: [ 0.00 0.00 ] +Key: VCMPPSZrmbi: [ 0.00 0.00 ] +Key: VCMPPSZrmbik: [ 0.00 0.00 ] +Key: VCMPPSZrmi: [ 0.00 0.00 ] +Key: VCMPPSZrmik: [ 0.00 0.00 ] +Key: VCMPPSZrri: [ 0.00 0.00 ] +Key: VCMPPSZrrib: [ 0.00 0.00 ] +Key: VCMPPSZrribk: [ 0.00 0.00 ] +Key: VCMPPSZrrik: [ 0.00 0.00 ] +Key: VCMPPSrmi: [ 0.00 0.00 ] +Key: VCMPPSrri: [ 0.00 0.00 ] +Key: VCMPSDZrmi: [ 0.00 0.00 ] +Key: VCMPSDZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSDZrri: [ 0.00 0.00 ] +Key: VCMPSDZrri_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSDZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSDrmi: [ 0.00 0.00 ] +Key: VCMPSDrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDrri: [ 0.00 0.00 ] +Key: VCMPSDrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmi: [ 0.00 0.00 ] +Key: VCMPSHZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSHZrri: [ 0.00 0.00 ] +Key: VCMPSHZrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSHZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmi: [ 0.00 0.00 ] +Key: VCMPSSZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrri: [ 0.00 0.00 ] +Key: VCMPSSZrri_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSSZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSrmi: [ 0.00 0.00 ] +Key: VCMPSSrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSrri: [ 0.00 0.00 ] +Key: VCMPSSrri_Int: [ 0.00 0.00 ] +Key: VCOMISBF: [ 0.00 0.00 ] +Key: VCOMISDZrm: [ 0.00 0.00 ] +Key: VCOMISDZrm_Int: [ 0.00 0.00 ] +Key: VCOMISDZrr: [ 0.00 0.00 ] +Key: VCOMISDZrr_Int: [ 0.00 0.00 ] +Key: VCOMISDZrrb: [ 0.00 0.00 ] +Key: VCOMISDrm: [ 0.00 0.00 ] +Key: VCOMISDrm_Int: [ 0.00 0.00 ] +Key: VCOMISDrr: [ 0.00 0.00 ] +Key: VCOMISDrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrm: [ 0.00 0.00 ] +Key: VCOMISHZrm_Int: [ 0.00 0.00 ] +Key: VCOMISHZrr: [ 0.00 0.00 ] +Key: VCOMISHZrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrrb: [ 0.00 0.00 ] +Key: VCOMISSZrm: [ 0.00 0.00 ] +Key: VCOMISSZrm_Int: [ 0.00 0.00 ] +Key: VCOMISSZrr: [ 0.00 0.00 ] +Key: VCOMISSZrr_Int: [ 0.00 0.00 ] +Key: VCOMISSZrrb: [ 0.00 0.00 ] +Key: VCOMISSrm: [ 0.00 0.00 ] +Key: VCOMISSrm_Int: [ 0.00 0.00 ] +Key: VCOMISSrr: [ 0.00 0.00 ] +Key: VCOMISSrr_Int: [ 0.00 0.00 ] +Key: VCOMPRESSPDZ: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrkz: [ 0.00 0.00 ] +Key: VCOMPRESSPSZ: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrkz: [ 0.00 0.00 ] +Key: VCOMXSDZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrrb_Int: [ 0.00 0.00 ] +Key: VCVT: [ 0.00 0.00 ] +Key: VCVTBF: [ 0.00 0.00 ] +Key: VCVTBIASPH: [ 0.00 0.00 ] +Key: VCVTDQ: [ 0.00 0.00 ] +Key: VCVTHF: [ 0.00 0.00 ] +Key: VCVTNE: [ 0.00 0.00 ] +Key: VCVTNEEBF: [ 0.00 0.00 ] +Key: VCVTNEEPH: [ 0.00 0.00 ] +Key: VCVTNEOBF: [ 0.00 0.00 ] +Key: VCVTNEOPH: [ 0.00 0.00 ] +Key: VCVTNEPS: [ 0.00 0.00 ] +Key: VCVTPD: [ 0.00 0.00 ] +Key: VCVTPH: [ 0.00 0.00 ] +Key: VCVTPS: [ 0.00 0.00 ] +Key: VCVTQQ: [ 0.00 0.00 ] +Key: VCVTSD: [ 0.00 0.00 ] +Key: VCVTSH: [ 0.00 0.00 ] +Key: VCVTSI: [ 0.00 0.00 ] +Key: VCVTSS: [ 0.00 0.00 ] +Key: VCVTTBF: [ 0.00 0.00 ] +Key: VCVTTPD: [ 0.00 0.00 ] +Key: VCVTTPH: [ 0.00 0.00 ] +Key: VCVTTPS: [ 0.00 0.00 ] +Key: VCVTTSD: [ 0.00 0.00 ] +Key: VCVTTSH: [ 0.00 0.00 ] +Key: VCVTTSS: [ 0.00 0.00 ] +Key: VCVTUDQ: [ 0.00 0.00 ] +Key: VCVTUQQ: [ 0.00 0.00 ] +Key: VCVTUSI: [ 0.00 0.00 ] +Key: VCVTUW: [ 0.00 0.00 ] +Key: VCVTW: [ 0.00 0.00 ] +Key: VDBPSADBWZ: [ 0.00 0.00 ] +Key: VDBPSADBWZrmi: [ 0.00 0.00 ] +Key: VDBPSADBWZrmik: [ 0.00 0.00 ] +Key: VDBPSADBWZrmikz: [ 0.00 0.00 ] +Key: VDBPSADBWZrri: [ 0.00 0.00 ] +Key: VDBPSADBWZrrik: [ 0.00 0.00 ] +Key: VDBPSADBWZrrikz: [ 0.00 0.00 ] +Key: VDIVBF: [ 0.00 0.00 ] +Key: VDIVPDYrm: [ 0.00 0.00 ] +Key: VDIVPDYrr: [ 0.00 0.00 ] +Key: VDIVPDZ: [ 0.00 0.00 ] +Key: VDIVPDZrm: [ 0.00 0.00 ] +Key: VDIVPDZrmb: [ 0.00 0.00 ] +Key: VDIVPDZrmbk: [ 0.00 0.00 ] +Key: VDIVPDZrmbkz: [ 0.00 0.00 ] +Key: VDIVPDZrmk: [ 0.00 0.00 ] +Key: VDIVPDZrmkz: [ 0.00 0.00 ] +Key: VDIVPDZrr: [ 0.00 0.00 ] +Key: VDIVPDZrrb: [ 0.00 0.00 ] +Key: VDIVPDZrrbk: [ 0.00 0.00 ] +Key: VDIVPDZrrbkz: [ 0.00 0.00 ] +Key: VDIVPDZrrk: [ 0.00 0.00 ] +Key: VDIVPDZrrkz: [ 0.00 0.00 ] +Key: VDIVPDrm: [ 0.00 0.00 ] +Key: VDIVPDrr: [ 0.00 0.00 ] +Key: VDIVPHZ: [ 0.00 0.00 ] +Key: VDIVPHZrm: [ 0.00 0.00 ] +Key: VDIVPHZrmb: [ 0.00 0.00 ] +Key: VDIVPHZrmbk: [ 0.00 0.00 ] +Key: VDIVPHZrmbkz: [ 0.00 0.00 ] +Key: VDIVPHZrmk: [ 0.00 0.00 ] +Key: VDIVPHZrmkz: [ 0.00 0.00 ] +Key: VDIVPHZrr: [ 0.00 0.00 ] +Key: VDIVPHZrrb: [ 0.00 0.00 ] +Key: VDIVPHZrrbk: [ 0.00 0.00 ] +Key: VDIVPHZrrbkz: [ 0.00 0.00 ] +Key: VDIVPHZrrk: [ 0.00 0.00 ] +Key: VDIVPHZrrkz: [ 0.00 0.00 ] +Key: VDIVPSYrm: [ 0.00 0.00 ] +Key: VDIVPSYrr: [ 0.00 0.00 ] +Key: VDIVPSZ: [ 0.00 0.00 ] +Key: VDIVPSZrm: [ 0.00 0.00 ] +Key: VDIVPSZrmb: [ 0.00 0.00 ] +Key: VDIVPSZrmbk: [ 0.00 0.00 ] +Key: VDIVPSZrmbkz: [ 0.00 0.00 ] +Key: VDIVPSZrmk: [ 0.00 0.00 ] +Key: VDIVPSZrmkz: [ 0.00 0.00 ] +Key: VDIVPSZrr: [ 0.00 0.00 ] +Key: VDIVPSZrrb: [ 0.00 0.00 ] +Key: VDIVPSZrrbk: [ 0.00 0.00 ] +Key: VDIVPSZrrbkz: [ 0.00 0.00 ] +Key: VDIVPSZrrk: [ 0.00 0.00 ] +Key: VDIVPSZrrkz: [ 0.00 0.00 ] +Key: VDIVPSrm: [ 0.00 0.00 ] +Key: VDIVPSrr: [ 0.00 0.00 ] +Key: VDIVSDZrm: [ 0.00 0.00 ] +Key: VDIVSDZrm_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrr: [ 0.00 0.00 ] +Key: VDIVSDZrr_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSDrm: [ 0.00 0.00 ] +Key: VDIVSDrm_Int: [ 0.00 0.00 ] +Key: VDIVSDrr: [ 0.00 0.00 ] +Key: VDIVSDrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrm: [ 0.00 0.00 ] +Key: VDIVSHZrm_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrr: [ 0.00 0.00 ] +Key: VDIVSHZrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrm: [ 0.00 0.00 ] +Key: VDIVSSZrm_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrr: [ 0.00 0.00 ] +Key: VDIVSSZrr_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSrm: [ 0.00 0.00 ] +Key: VDIVSSrm_Int: [ 0.00 0.00 ] +Key: VDIVSSrr: [ 0.00 0.00 ] +Key: VDIVSSrr_Int: [ 0.00 0.00 ] +Key: VDPBF: [ 0.00 0.00 ] +Key: VDPPDrmi: [ 0.00 0.00 ] +Key: VDPPDrri: [ 0.00 0.00 ] +Key: VDPPHPSZ: [ 0.00 0.00 ] +Key: VDPPHPSZm: [ 0.00 0.00 ] +Key: VDPPHPSZmb: [ 0.00 0.00 ] +Key: VDPPHPSZmbk: [ 0.00 0.00 ] +Key: VDPPHPSZmbkz: [ 0.00 0.00 ] +Key: VDPPHPSZmk: [ 0.00 0.00 ] +Key: VDPPHPSZmkz: [ 0.00 0.00 ] +Key: VDPPHPSZr: [ 0.00 0.00 ] +Key: VDPPHPSZrk: [ 0.00 0.00 ] +Key: VDPPHPSZrkz: [ 0.00 0.00 ] +Key: VDPPSYrmi: [ 0.00 0.00 ] +Key: VDPPSYrri: [ 0.00 0.00 ] +Key: VDPPSrmi: [ 0.00 0.00 ] +Key: VDPPSrri: [ 0.00 0.00 ] +Key: VERRm: [ 0.00 0.00 ] +Key: VERRr: [ 0.00 0.00 ] +Key: VERWm: [ 0.00 0.00 ] +Key: VERWr: [ 0.00 0.00 ] +Key: VEXP: [ 0.00 0.00 ] +Key: VEXPANDPDZ: [ 0.00 0.00 ] +Key: VEXPANDPDZrm: [ 0.00 0.00 ] +Key: VEXPANDPDZrmk: [ 0.00 0.00 ] +Key: VEXPANDPDZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPDZrr: [ 0.00 0.00 ] +Key: VEXPANDPDZrrk: [ 0.00 0.00 ] +Key: VEXPANDPDZrrkz: [ 0.00 0.00 ] +Key: VEXPANDPSZ: [ 0.00 0.00 ] +Key: VEXPANDPSZrm: [ 0.00 0.00 ] +Key: VEXPANDPSZrmk: [ 0.00 0.00 ] +Key: VEXPANDPSZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPSZrr: [ 0.00 0.00 ] +Key: VEXPANDPSZrrk: [ 0.00 0.00 ] +Key: VEXPANDPSZrrkz: [ 0.00 0.00 ] +Key: VEXTRACTF: [ 0.00 0.00 ] +Key: VEXTRACTI: [ 0.00 0.00 ] +Key: VEXTRACTPSZmri: [ 0.00 0.00 ] +Key: VEXTRACTPSZrri: [ 0.00 0.00 ] +Key: VEXTRACTPSmri: [ 0.00 0.00 ] +Key: VEXTRACTPSrri: [ 0.00 0.00 ] +Key: VFCMADDCPHZ: [ 0.00 0.00 ] +Key: VFCMADDCPHZm: [ 0.00 0.00 ] +Key: VFCMADDCPHZmb: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZmk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZr: [ 0.00 0.00 ] +Key: VFCMADDCPHZrb: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZrk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZm: [ 0.00 0.00 ] +Key: VFCMADDCSHZmk: [ 0.00 0.00 ] +Key: VFCMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZr: [ 0.00 0.00 ] +Key: VFCMADDCSHZrb: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZrk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFCMULCPHZ: [ 0.00 0.00 ] +Key: VFCMULCPHZrm: [ 0.00 0.00 ] +Key: VFCMULCPHZrmb: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrmk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrr: [ 0.00 0.00 ] +Key: VFCMULCPHZrrb: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrrk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrm: [ 0.00 0.00 ] +Key: VFCMULCSHZrmk: [ 0.00 0.00 ] +Key: VFCMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrr: [ 0.00 0.00 ] +Key: VFCMULCSHZrrb: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrrk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrikz: [ 0.00 0.00 ] +Key: VFMADD: [ 0.00 0.00 ] +Key: VFMADDCPHZ: [ 0.00 0.00 ] +Key: VFMADDCPHZm: [ 0.00 0.00 ] +Key: VFMADDCPHZmb: [ 0.00 0.00 ] +Key: VFMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZmk: [ 0.00 0.00 ] +Key: VFMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFMADDCPHZr: [ 0.00 0.00 ] +Key: VFMADDCPHZrb: [ 0.00 0.00 ] +Key: VFMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZrk: [ 0.00 0.00 ] +Key: VFMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFMADDCSHZm: [ 0.00 0.00 ] +Key: VFMADDCSHZmk: [ 0.00 0.00 ] +Key: VFMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFMADDCSHZr: [ 0.00 0.00 ] +Key: VFMADDCSHZrb: [ 0.00 0.00 ] +Key: VFMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCSHZrk: [ 0.00 0.00 ] +Key: VFMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFMADDPD: [ 0.00 0.00 ] +Key: VFMADDPS: [ 0.00 0.00 ] +Key: VFMADDSD: [ 0.00 0.00 ] +Key: VFMADDSS: [ 0.00 0.00 ] +Key: VFMADDSUB: [ 0.00 0.00 ] +Key: VFMADDSUBPD: [ 0.00 0.00 ] +Key: VFMADDSUBPS: [ 0.00 0.00 ] +Key: VFMSUB: [ 0.00 0.00 ] +Key: VFMSUBADD: [ 0.00 0.00 ] +Key: VFMSUBADDPD: [ 0.00 0.00 ] +Key: VFMSUBADDPS: [ 0.00 0.00 ] +Key: VFMSUBPD: [ 0.00 0.00 ] +Key: VFMSUBPS: [ 0.00 0.00 ] +Key: VFMSUBSD: [ 0.00 0.00 ] +Key: VFMSUBSS: [ 0.00 0.00 ] +Key: VFMULCPHZ: [ 0.00 0.00 ] +Key: VFMULCPHZrm: [ 0.00 0.00 ] +Key: VFMULCPHZrmb: [ 0.00 0.00 ] +Key: VFMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrmk: [ 0.00 0.00 ] +Key: VFMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFMULCPHZrr: [ 0.00 0.00 ] +Key: VFMULCPHZrrb: [ 0.00 0.00 ] +Key: VFMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrrk: [ 0.00 0.00 ] +Key: VFMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFMULCSHZrm: [ 0.00 0.00 ] +Key: VFMULCSHZrmk: [ 0.00 0.00 ] +Key: VFMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFMULCSHZrr: [ 0.00 0.00 ] +Key: VFMULCSHZrrb: [ 0.00 0.00 ] +Key: VFMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCSHZrrk: [ 0.00 0.00 ] +Key: VFMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFNMADD: [ 0.00 0.00 ] +Key: VFNMADDPD: [ 0.00 0.00 ] +Key: VFNMADDPS: [ 0.00 0.00 ] +Key: VFNMADDSD: [ 0.00 0.00 ] +Key: VFNMADDSS: [ 0.00 0.00 ] +Key: VFNMSUB: [ 0.00 0.00 ] +Key: VFNMSUBPD: [ 0.00 0.00 ] +Key: VFNMSUBPS: [ 0.00 0.00 ] +Key: VFNMSUBSD: [ 0.00 0.00 ] +Key: VFNMSUBSS: [ 0.00 0.00 ] +Key: VFPCLASSBF: [ 0.00 0.00 ] +Key: VFPCLASSPDZ: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPDZmi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmik: [ 0.00 0.00 ] +Key: VFPCLASSPDZri: [ 0.00 0.00 ] +Key: VFPCLASSPDZrik: [ 0.00 0.00 ] +Key: VFPCLASSPHZ: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPHZmi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmik: [ 0.00 0.00 ] +Key: VFPCLASSPHZri: [ 0.00 0.00 ] +Key: VFPCLASSPHZrik: [ 0.00 0.00 ] +Key: VFPCLASSPSZ: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPSZmi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmik: [ 0.00 0.00 ] +Key: VFPCLASSPSZri: [ 0.00 0.00 ] +Key: VFPCLASSPSZrik: [ 0.00 0.00 ] +Key: VFPCLASSSDZmi: [ 0.00 0.00 ] +Key: VFPCLASSSDZmik: [ 0.00 0.00 ] +Key: VFPCLASSSDZri: [ 0.00 0.00 ] +Key: VFPCLASSSDZrik: [ 0.00 0.00 ] +Key: VFPCLASSSHZmi: [ 0.00 0.00 ] +Key: VFPCLASSSHZmik: [ 0.00 0.00 ] +Key: VFPCLASSSHZri: [ 0.00 0.00 ] +Key: VFPCLASSSHZrik: [ 0.00 0.00 ] +Key: VFPCLASSSSZmi: [ 0.00 0.00 ] +Key: VFPCLASSSSZmik: [ 0.00 0.00 ] +Key: VFPCLASSSSZri: [ 0.00 0.00 ] +Key: VFPCLASSSSZrik: [ 0.00 0.00 ] +Key: VFRCZPDYrm: [ 0.00 0.00 ] +Key: VFRCZPDYrr: [ 0.00 0.00 ] +Key: VFRCZPDrm: [ 0.00 0.00 ] +Key: VFRCZPDrr: [ 0.00 0.00 ] +Key: VFRCZPSYrm: [ 0.00 0.00 ] +Key: VFRCZPSYrr: [ 0.00 0.00 ] +Key: VFRCZPSrm: [ 0.00 0.00 ] +Key: VFRCZPSrr: [ 0.00 0.00 ] +Key: VFRCZSDrm: [ 0.00 0.00 ] +Key: VFRCZSDrr: [ 0.00 0.00 ] +Key: VFRCZSSrm: [ 0.00 0.00 ] +Key: VFRCZSSrr: [ 0.00 0.00 ] +Key: VGATHERDPDYrm: [ 0.00 0.00 ] +Key: VGATHERDPDZ: [ 0.00 0.00 ] +Key: VGATHERDPDZrm: [ 0.00 0.00 ] +Key: VGATHERDPDrm: [ 0.00 0.00 ] +Key: VGATHERDPSYrm: [ 0.00 0.00 ] +Key: VGATHERDPSZ: [ 0.00 0.00 ] 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VGETEXPPHZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZmk: [ 0.00 0.00 ] +Key: VGETEXPPHZmkz: [ 0.00 0.00 ] +Key: VGETEXPPHZr: [ 0.00 0.00 ] +Key: VGETEXPPHZrb: [ 0.00 0.00 ] +Key: VGETEXPPHZrbk: [ 0.00 0.00 ] +Key: VGETEXPPHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZrk: [ 0.00 0.00 ] +Key: VGETEXPPHZrkz: [ 0.00 0.00 ] +Key: VGETEXPPSZ: [ 0.00 0.00 ] +Key: VGETEXPPSZm: [ 0.00 0.00 ] +Key: VGETEXPPSZmb: [ 0.00 0.00 ] +Key: VGETEXPPSZmbk: [ 0.00 0.00 ] +Key: VGETEXPPSZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZmk: [ 0.00 0.00 ] +Key: VGETEXPPSZmkz: [ 0.00 0.00 ] +Key: VGETEXPPSZr: [ 0.00 0.00 ] +Key: VGETEXPPSZrb: [ 0.00 0.00 ] +Key: VGETEXPPSZrbk: [ 0.00 0.00 ] +Key: VGETEXPPSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZrk: [ 0.00 0.00 ] +Key: VGETEXPPSZrkz: [ 0.00 0.00 ] +Key: VGETEXPSDZm: [ 0.00 0.00 ] +Key: VGETEXPSDZmk: [ 0.00 0.00 ] +Key: VGETEXPSDZmkz: [ 0.00 0.00 ] +Key: VGETEXPSDZr: [ 0.00 0.00 ] +Key: VGETEXPSDZrb: [ 0.00 0.00 ] +Key: VGETEXPSDZrbk: [ 0.00 0.00 ] +Key: VGETEXPSDZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSDZrk: [ 0.00 0.00 ] +Key: VGETEXPSDZrkz: [ 0.00 0.00 ] +Key: VGETEXPSHZm: [ 0.00 0.00 ] +Key: VGETEXPSHZmk: [ 0.00 0.00 ] +Key: VGETEXPSHZmkz: [ 0.00 0.00 ] +Key: VGETEXPSHZr: [ 0.00 0.00 ] +Key: VGETEXPSHZrb: [ 0.00 0.00 ] +Key: VGETEXPSHZrbk: [ 0.00 0.00 ] +Key: VGETEXPSHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSHZrk: [ 0.00 0.00 ] +Key: VGETEXPSHZrkz: [ 0.00 0.00 ] +Key: VGETEXPSSZm: [ 0.00 0.00 ] +Key: VGETEXPSSZmk: [ 0.00 0.00 ] +Key: VGETEXPSSZmkz: [ 0.00 0.00 ] +Key: VGETEXPSSZr: [ 0.00 0.00 ] +Key: VGETEXPSSZrb: [ 0.00 0.00 ] +Key: VGETEXPSSZrbk: [ 0.00 0.00 ] +Key: VGETEXPSSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSSZrk: [ 0.00 0.00 ] +Key: VGETEXPSSZrkz: [ 0.00 0.00 ] +Key: VGETMANTBF: [ 0.00 0.00 ] +Key: VGETMANTPDZ: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrmi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrri: [ 0.00 0.00 ] +Key: VGETMANTPDZrrib: [ 0.00 0.00 ] +Key: VGETMANTPDZrribk: [ 0.00 0.00 ] +Key: VGETMANTPDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPDZrrik: [ 0.00 0.00 ] +Key: VGETMANTPDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPHZ: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrmi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrri: [ 0.00 0.00 ] +Key: VGETMANTPHZrrib: [ 0.00 0.00 ] +Key: VGETMANTPHZrribk: [ 0.00 0.00 ] +Key: VGETMANTPHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPHZrrik: [ 0.00 0.00 ] +Key: VGETMANTPHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPSZ: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrmi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrri: [ 0.00 0.00 ] +Key: VGETMANTPSZrrib: [ 0.00 0.00 ] +Key: VGETMANTPSZrribk: [ 0.00 0.00 ] +Key: VGETMANTPSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPSZrrik: [ 0.00 0.00 ] +Key: VGETMANTPSZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrmi: [ 0.00 0.00 ] +Key: VGETMANTSDZrmik: [ 0.00 0.00 ] +Key: VGETMANTSDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrri: [ 0.00 0.00 ] +Key: VGETMANTSDZrrib: [ 0.00 0.00 ] +Key: VGETMANTSDZrribk: [ 0.00 0.00 ] +Key: VGETMANTSDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSDZrrik: [ 0.00 0.00 ] +Key: VGETMANTSDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrmi: [ 0.00 0.00 ] +Key: VGETMANTSHZrmik: [ 0.00 0.00 ] +Key: VGETMANTSHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrri: [ 0.00 0.00 ] +Key: VGETMANTSHZrrib: [ 0.00 0.00 ] +Key: VGETMANTSHZrribk: [ 0.00 0.00 ] +Key: VGETMANTSHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSHZrrik: [ 0.00 0.00 ] +Key: VGETMANTSHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrmi: [ 0.00 0.00 ] +Key: VGETMANTSSZrmik: [ 0.00 0.00 ] +Key: VGETMANTSSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrri: [ 0.00 0.00 ] +Key: VGETMANTSSZrrib: [ 0.00 0.00 ] +Key: VGETMANTSSZrribk: [ 0.00 0.00 ] +Key: VGETMANTSSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSSZrrik: [ 0.00 0.00 ] +Key: VGETMANTSSZrrikz: [ 0.00 0.00 ] +Key: VGF: [ 0.00 0.00 ] +Key: VHADDPDYrm: [ 0.00 0.00 ] +Key: VHADDPDYrr: [ 0.00 0.00 ] +Key: VHADDPDrm: [ 0.00 0.00 ] +Key: VHADDPDrr: [ 0.00 0.00 ] +Key: VHADDPSYrm: [ 0.00 0.00 ] +Key: VHADDPSYrr: [ 0.00 0.00 ] +Key: VHADDPSrm: [ 0.00 0.00 ] +Key: VHADDPSrr: [ 0.00 0.00 ] +Key: VHSUBPDYrm: [ 0.00 0.00 ] +Key: VHSUBPDYrr: [ 0.00 0.00 ] +Key: VHSUBPDrm: [ 0.00 0.00 ] +Key: VHSUBPDrr: [ 0.00 0.00 ] +Key: VHSUBPSYrm: [ 0.00 0.00 ] +Key: VHSUBPSYrr: [ 0.00 0.00 ] +Key: VHSUBPSrm: [ 0.00 0.00 ] +Key: VHSUBPSrr: [ 0.00 0.00 ] +Key: VINSERTF: [ 0.00 0.00 ] +Key: VINSERTI: [ 0.00 0.00 ] +Key: VINSERTPSZrmi: [ 0.00 0.00 ] +Key: VINSERTPSZrri: [ 0.00 0.00 ] +Key: VINSERTPSrmi: [ 0.00 0.00 ] +Key: VINSERTPSrri: [ 0.00 0.00 ] +Key: VLDDQUYrm: [ 0.00 0.00 ] +Key: VLDDQUrm: [ 0.00 0.00 ] +Key: VLDMXCSR: [ 0.00 0.00 ] +Key: VMASKMOVDQU: [ 0.00 0.00 ] +Key: VMASKMOVPDYmr: [ 0.00 0.00 ] +Key: VMASKMOVPDYrm: [ 0.00 0.00 ] +Key: VMASKMOVPDmr: [ 0.00 0.00 ] +Key: VMASKMOVPDrm: [ 0.00 0.00 ] +Key: VMASKMOVPSYmr: [ 0.00 0.00 ] +Key: VMASKMOVPSYrm: [ 0.00 0.00 ] +Key: VMASKMOVPSmr: [ 0.00 0.00 ] +Key: VMASKMOVPSrm: [ 0.00 0.00 ] +Key: VMAXBF: [ 0.00 0.00 ] +Key: VMAXCPDYrm: [ 0.00 0.00 ] +Key: VMAXCPDYrr: [ 0.00 0.00 ] +Key: VMAXCPDZ: [ 0.00 0.00 ] +Key: VMAXCPDZrm: [ 0.00 0.00 ] +Key: VMAXCPDZrmb: [ 0.00 0.00 ] +Key: VMAXCPDZrmbk: [ 0.00 0.00 ] +Key: VMAXCPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPDZrmk: [ 0.00 0.00 ] +Key: VMAXCPDZrmkz: [ 0.00 0.00 ] +Key: VMAXCPDZrr: [ 0.00 0.00 ] +Key: VMAXCPDZrrk: [ 0.00 0.00 ] +Key: VMAXCPDZrrkz: [ 0.00 0.00 ] +Key: VMAXCPDrm: [ 0.00 0.00 ] +Key: VMAXCPDrr: [ 0.00 0.00 ] +Key: VMAXCPHZ: [ 0.00 0.00 ] +Key: VMAXCPHZrm: [ 0.00 0.00 ] +Key: VMAXCPHZrmb: [ 0.00 0.00 ] +Key: VMAXCPHZrmbk: [ 0.00 0.00 ] +Key: VMAXCPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPHZrmk: [ 0.00 0.00 ] +Key: VMAXCPHZrmkz: [ 0.00 0.00 ] +Key: VMAXCPHZrr: [ 0.00 0.00 ] +Key: VMAXCPHZrrk: [ 0.00 0.00 ] +Key: VMAXCPHZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSYrm: [ 0.00 0.00 ] +Key: VMAXCPSYrr: [ 0.00 0.00 ] +Key: VMAXCPSZ: [ 0.00 0.00 ] +Key: VMAXCPSZrm: [ 0.00 0.00 ] +Key: VMAXCPSZrmb: [ 0.00 0.00 ] +Key: VMAXCPSZrmbk: [ 0.00 0.00 ] +Key: VMAXCPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPSZrmk: [ 0.00 0.00 ] +Key: VMAXCPSZrmkz: [ 0.00 0.00 ] +Key: VMAXCPSZrr: [ 0.00 0.00 ] +Key: VMAXCPSZrrk: [ 0.00 0.00 ] +Key: VMAXCPSZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSrm: [ 0.00 0.00 ] +Key: VMAXCPSrr: [ 0.00 0.00 ] +Key: VMAXCSDZrm: [ 0.00 0.00 ] +Key: VMAXCSDZrr: [ 0.00 0.00 ] +Key: VMAXCSDrm: [ 0.00 0.00 ] +Key: VMAXCSDrr: [ 0.00 0.00 ] +Key: VMAXCSHZrm: [ 0.00 0.00 ] +Key: VMAXCSHZrr: [ 0.00 0.00 ] +Key: VMAXCSSZrm: [ 0.00 0.00 ] +Key: VMAXCSSZrr: [ 0.00 0.00 ] +Key: VMAXCSSrm: [ 0.00 0.00 ] +Key: VMAXCSSrr: [ 0.00 0.00 ] +Key: VMAXPDYrm: [ 0.00 0.00 ] +Key: VMAXPDYrr: [ 0.00 0.00 ] +Key: VMAXPDZ: [ 0.00 0.00 ] +Key: VMAXPDZrm: [ 0.00 0.00 ] +Key: VMAXPDZrmb: [ 0.00 0.00 ] +Key: VMAXPDZrmbk: [ 0.00 0.00 ] +Key: VMAXPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXPDZrmk: [ 0.00 0.00 ] +Key: VMAXPDZrmkz: [ 0.00 0.00 ] +Key: VMAXPDZrr: [ 0.00 0.00 ] +Key: VMAXPDZrrb: [ 0.00 0.00 ] +Key: VMAXPDZrrbk: [ 0.00 0.00 ] +Key: VMAXPDZrrbkz: [ 0.00 0.00 ] +Key: VMAXPDZrrk: [ 0.00 0.00 ] +Key: VMAXPDZrrkz: [ 0.00 0.00 ] +Key: VMAXPDrm: [ 0.00 0.00 ] +Key: VMAXPDrr: [ 0.00 0.00 ] +Key: VMAXPHZ: [ 0.00 0.00 ] +Key: VMAXPHZrm: [ 0.00 0.00 ] +Key: VMAXPHZrmb: [ 0.00 0.00 ] +Key: VMAXPHZrmbk: [ 0.00 0.00 ] +Key: VMAXPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXPHZrmk: [ 0.00 0.00 ] +Key: VMAXPHZrmkz: [ 0.00 0.00 ] +Key: VMAXPHZrr: [ 0.00 0.00 ] +Key: VMAXPHZrrb: [ 0.00 0.00 ] +Key: VMAXPHZrrbk: [ 0.00 0.00 ] +Key: VMAXPHZrrbkz: [ 0.00 0.00 ] +Key: VMAXPHZrrk: [ 0.00 0.00 ] +Key: VMAXPHZrrkz: [ 0.00 0.00 ] +Key: VMAXPSYrm: [ 0.00 0.00 ] +Key: VMAXPSYrr: [ 0.00 0.00 ] +Key: VMAXPSZ: [ 0.00 0.00 ] +Key: VMAXPSZrm: [ 0.00 0.00 ] +Key: VMAXPSZrmb: [ 0.00 0.00 ] +Key: VMAXPSZrmbk: [ 0.00 0.00 ] +Key: VMAXPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXPSZrmk: [ 0.00 0.00 ] +Key: VMAXPSZrmkz: [ 0.00 0.00 ] +Key: VMAXPSZrr: [ 0.00 0.00 ] +Key: VMAXPSZrrb: [ 0.00 0.00 ] +Key: VMAXPSZrrbk: [ 0.00 0.00 ] +Key: VMAXPSZrrbkz: [ 0.00 0.00 ] +Key: VMAXPSZrrk: [ 0.00 0.00 ] +Key: VMAXPSZrrkz: [ 0.00 0.00 ] +Key: VMAXPSrm: [ 0.00 0.00 ] +Key: VMAXPSrr: [ 0.00 0.00 ] +Key: VMAXSDZrm: [ 0.00 0.00 ] +Key: VMAXSDZrm_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrr: [ 0.00 0.00 ] +Key: VMAXSDZrr_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSDrm: [ 0.00 0.00 ] +Key: VMAXSDrm_Int: [ 0.00 0.00 ] +Key: VMAXSDrr: [ 0.00 0.00 ] +Key: VMAXSDrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrm: [ 0.00 0.00 ] +Key: VMAXSHZrm_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrr: [ 0.00 0.00 ] +Key: VMAXSHZrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrm: [ 0.00 0.00 ] +Key: VMAXSSZrm_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrr: [ 0.00 0.00 ] +Key: VMAXSSZrr_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSrm: [ 0.00 0.00 ] +Key: VMAXSSrm_Int: [ 0.00 0.00 ] +Key: VMAXSSrr: [ 0.00 0.00 ] +Key: VMAXSSrr_Int: [ 0.00 0.00 ] +Key: VMCALL: [ 0.00 0.00 ] +Key: VMCLEARm: [ 0.00 0.00 ] +Key: VMFUNC: [ 0.00 0.00 ] +Key: VMINBF: [ 0.00 0.00 ] +Key: VMINCPDYrm: [ 0.00 0.00 ] +Key: VMINCPDYrr: [ 0.00 0.00 ] +Key: VMINCPDZ: [ 0.00 0.00 ] +Key: VMINCPDZrm: [ 0.00 0.00 ] +Key: VMINCPDZrmb: [ 0.00 0.00 ] +Key: VMINCPDZrmbk: [ 0.00 0.00 ] +Key: VMINCPDZrmbkz: [ 0.00 0.00 ] +Key: VMINCPDZrmk: [ 0.00 0.00 ] +Key: VMINCPDZrmkz: [ 0.00 0.00 ] +Key: VMINCPDZrr: [ 0.00 0.00 ] +Key: VMINCPDZrrk: [ 0.00 0.00 ] +Key: VMINCPDZrrkz: [ 0.00 0.00 ] +Key: VMINCPDrm: [ 0.00 0.00 ] +Key: VMINCPDrr: [ 0.00 0.00 ] +Key: VMINCPHZ: [ 0.00 0.00 ] +Key: VMINCPHZrm: [ 0.00 0.00 ] +Key: VMINCPHZrmb: [ 0.00 0.00 ] +Key: VMINCPHZrmbk: [ 0.00 0.00 ] +Key: VMINCPHZrmbkz: [ 0.00 0.00 ] +Key: VMINCPHZrmk: [ 0.00 0.00 ] +Key: VMINCPHZrmkz: [ 0.00 0.00 ] +Key: VMINCPHZrr: [ 0.00 0.00 ] +Key: VMINCPHZrrk: [ 0.00 0.00 ] +Key: VMINCPHZrrkz: [ 0.00 0.00 ] +Key: VMINCPSYrm: [ 0.00 0.00 ] +Key: VMINCPSYrr: [ 0.00 0.00 ] +Key: VMINCPSZ: [ 0.00 0.00 ] +Key: VMINCPSZrm: [ 0.00 0.00 ] +Key: VMINCPSZrmb: [ 0.00 0.00 ] +Key: VMINCPSZrmbk: [ 0.00 0.00 ] +Key: VMINCPSZrmbkz: [ 0.00 0.00 ] +Key: VMINCPSZrmk: [ 0.00 0.00 ] +Key: VMINCPSZrmkz: [ 0.00 0.00 ] +Key: VMINCPSZrr: [ 0.00 0.00 ] +Key: VMINCPSZrrk: [ 0.00 0.00 ] +Key: VMINCPSZrrkz: [ 0.00 0.00 ] +Key: VMINCPSrm: [ 0.00 0.00 ] +Key: VMINCPSrr: [ 0.00 0.00 ] +Key: VMINCSDZrm: [ 0.00 0.00 ] +Key: VMINCSDZrr: [ 0.00 0.00 ] +Key: VMINCSDrm: [ 0.00 0.00 ] +Key: VMINCSDrr: [ 0.00 0.00 ] +Key: VMINCSHZrm: [ 0.00 0.00 ] +Key: VMINCSHZrr: [ 0.00 0.00 ] +Key: VMINCSSZrm: [ 0.00 0.00 ] +Key: VMINCSSZrr: [ 0.00 0.00 ] +Key: VMINCSSrm: [ 0.00 0.00 ] +Key: VMINCSSrr: [ 0.00 0.00 ] +Key: VMINMAXBF: [ 0.00 0.00 ] +Key: VMINMAXPDZ: [ 0.00 0.00 ] +Key: VMINMAXPDZrmbi: [ 0.00 0.00 ] +Key: VMINMAXPDZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPDZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPDZrmi: [ 0.00 0.00 ] +Key: VMINMAXPDZrmik: [ 0.00 0.00 ] +Key: VMINMAXPDZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPDZrri: [ 0.00 0.00 ] +Key: VMINMAXPDZrrib: [ 0.00 0.00 ] +Key: VMINMAXPDZrribk: [ 0.00 0.00 ] +Key: VMINMAXPDZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPDZrrik: [ 0.00 0.00 ] +Key: VMINMAXPDZrrikz: [ 0.00 0.00 ] +Key: VMINMAXPHZ: [ 0.00 0.00 ] +Key: VMINMAXPHZrmbi: [ 0.00 0.00 ] +Key: VMINMAXPHZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPHZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPHZrmi: [ 0.00 0.00 ] +Key: VMINMAXPHZrmik: [ 0.00 0.00 ] +Key: VMINMAXPHZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPHZrri: [ 0.00 0.00 ] +Key: VMINMAXPHZrrib: [ 0.00 0.00 ] +Key: VMINMAXPHZrribk: [ 0.00 0.00 ] +Key: VMINMAXPHZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPHZrrik: [ 0.00 0.00 ] +Key: VMINMAXPHZrrikz: [ 0.00 0.00 ] +Key: VMINMAXPSZ: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbi: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrmi: [ 0.00 0.00 ] +Key: VMINMAXPSZrmik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrri: [ 0.00 0.00 ] +Key: VMINMAXPSZrrib: [ 0.00 0.00 ] +Key: VMINMAXPSZrribk: [ 0.00 0.00 ] +Key: VMINMAXPSZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPSZrrik: [ 0.00 0.00 ] +Key: VMINMAXPSZrrikz: [ 0.00 0.00 ] +Key: VMINMAXSDrmi: [ 0.00 0.00 ] +Key: VMINMAXSDrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrri: [ 0.00 0.00 ] +Key: VMINMAXSDrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmi: [ 0.00 0.00 ] +Key: VMINMAXSHrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrri: [ 0.00 0.00 ] +Key: VMINMAXSHrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmi: [ 0.00 0.00 ] +Key: VMINMAXSSrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrri: [ 0.00 0.00 ] +Key: VMINMAXSSrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrikz_Int: [ 0.00 0.00 ] +Key: VMINPDYrm: [ 0.00 0.00 ] +Key: VMINPDYrr: [ 0.00 0.00 ] +Key: VMINPDZ: [ 0.00 0.00 ] +Key: VMINPDZrm: [ 0.00 0.00 ] +Key: VMINPDZrmb: [ 0.00 0.00 ] +Key: VMINPDZrmbk: [ 0.00 0.00 ] +Key: VMINPDZrmbkz: [ 0.00 0.00 ] +Key: VMINPDZrmk: [ 0.00 0.00 ] +Key: VMINPDZrmkz: [ 0.00 0.00 ] +Key: VMINPDZrr: [ 0.00 0.00 ] +Key: VMINPDZrrb: [ 0.00 0.00 ] +Key: VMINPDZrrbk: [ 0.00 0.00 ] +Key: VMINPDZrrbkz: [ 0.00 0.00 ] +Key: VMINPDZrrk: [ 0.00 0.00 ] +Key: VMINPDZrrkz: [ 0.00 0.00 ] +Key: VMINPDrm: [ 0.00 0.00 ] +Key: VMINPDrr: [ 0.00 0.00 ] +Key: VMINPHZ: [ 0.00 0.00 ] +Key: VMINPHZrm: [ 0.00 0.00 ] +Key: VMINPHZrmb: [ 0.00 0.00 ] +Key: VMINPHZrmbk: [ 0.00 0.00 ] +Key: VMINPHZrmbkz: [ 0.00 0.00 ] +Key: VMINPHZrmk: [ 0.00 0.00 ] +Key: VMINPHZrmkz: [ 0.00 0.00 ] +Key: VMINPHZrr: [ 0.00 0.00 ] +Key: VMINPHZrrb: [ 0.00 0.00 ] +Key: VMINPHZrrbk: [ 0.00 0.00 ] +Key: VMINPHZrrbkz: [ 0.00 0.00 ] +Key: VMINPHZrrk: [ 0.00 0.00 ] +Key: VMINPHZrrkz: [ 0.00 0.00 ] +Key: VMINPSYrm: [ 0.00 0.00 ] +Key: VMINPSYrr: [ 0.00 0.00 ] +Key: VMINPSZ: [ 0.00 0.00 ] +Key: VMINPSZrm: [ 0.00 0.00 ] +Key: VMINPSZrmb: [ 0.00 0.00 ] +Key: VMINPSZrmbk: [ 0.00 0.00 ] +Key: VMINPSZrmbkz: [ 0.00 0.00 ] +Key: VMINPSZrmk: [ 0.00 0.00 ] +Key: VMINPSZrmkz: [ 0.00 0.00 ] +Key: VMINPSZrr: [ 0.00 0.00 ] +Key: VMINPSZrrb: [ 0.00 0.00 ] +Key: VMINPSZrrbk: [ 0.00 0.00 ] +Key: VMINPSZrrbkz: [ 0.00 0.00 ] +Key: VMINPSZrrk: [ 0.00 0.00 ] +Key: VMINPSZrrkz: [ 0.00 0.00 ] +Key: VMINPSrm: [ 0.00 0.00 ] +Key: VMINPSrr: [ 0.00 0.00 ] +Key: VMINSDZrm: [ 0.00 0.00 ] +Key: VMINSDZrm_Int: [ 0.00 0.00 ] +Key: VMINSDZrmk_Int: [ 0.00 0.00 ] +Key: VMINSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSDZrr: [ 0.00 0.00 ] +Key: VMINSDZrr_Int: [ 0.00 0.00 ] +Key: VMINSDZrrb_Int: [ 0.00 0.00 ] +Key: VMINSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSDZrrk_Int: [ 0.00 0.00 ] +Key: VMINSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSDrm: [ 0.00 0.00 ] +Key: VMINSDrm_Int: [ 0.00 0.00 ] +Key: VMINSDrr: [ 0.00 0.00 ] +Key: VMINSDrr_Int: [ 0.00 0.00 ] +Key: VMINSHZrm: [ 0.00 0.00 ] +Key: VMINSHZrm_Int: [ 0.00 0.00 ] +Key: VMINSHZrmk_Int: [ 0.00 0.00 ] +Key: VMINSHZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSHZrr: [ 0.00 0.00 ] +Key: VMINSHZrr_Int: [ 0.00 0.00 ] +Key: VMINSHZrrb_Int: [ 0.00 0.00 ] +Key: VMINSHZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSHZrrk_Int: [ 0.00 0.00 ] +Key: VMINSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrm: [ 0.00 0.00 ] +Key: VMINSSZrm_Int: [ 0.00 0.00 ] +Key: VMINSSZrmk_Int: [ 0.00 0.00 ] +Key: VMINSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrr: [ 0.00 0.00 ] +Key: VMINSSZrr_Int: [ 0.00 0.00 ] +Key: VMINSSZrrb_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrrk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSrm: [ 0.00 0.00 ] +Key: VMINSSrm_Int: [ 0.00 0.00 ] +Key: VMINSSrr: [ 0.00 0.00 ] +Key: VMINSSrr_Int: [ 0.00 0.00 ] +Key: VMLAUNCH: [ 0.00 0.00 ] +Key: VMLOAD: [ 0.00 0.00 ] +Key: VMMCALL: [ 0.00 0.00 ] +Key: VMOV: [ 0.00 0.00 ] +Key: VMOVAPDYmr: [ 0.00 0.00 ] +Key: VMOVAPDYrm: [ 0.00 0.00 ] +Key: VMOVAPDYrr: [ 0.00 0.00 ] +Key: VMOVAPDYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZ: [ 0.00 0.00 ] +Key: VMOVAPDZmr: [ 0.00 0.00 ] +Key: VMOVAPDZmrk: [ 0.00 0.00 ] +Key: VMOVAPDZrm: [ 0.00 0.00 ] +Key: VMOVAPDZrmk: [ 0.00 0.00 ] +Key: VMOVAPDZrmkz: [ 0.00 0.00 ] +Key: VMOVAPDZrr: [ 0.00 0.00 ] +Key: VMOVAPDZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrk: [ 0.00 0.00 ] +Key: VMOVAPDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPDmr: [ 0.00 0.00 ] +Key: VMOVAPDrm: [ 0.00 0.00 ] +Key: VMOVAPDrr: [ 0.00 0.00 ] +Key: VMOVAPDrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSYmr: [ 0.00 0.00 ] +Key: VMOVAPSYrm: [ 0.00 0.00 ] +Key: VMOVAPSYrr: [ 0.00 0.00 ] +Key: VMOVAPSYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZ: [ 0.00 0.00 ] +Key: VMOVAPSZmr: [ 0.00 0.00 ] +Key: VMOVAPSZmrk: [ 0.00 0.00 ] +Key: VMOVAPSZrm: [ 0.00 0.00 ] +Key: VMOVAPSZrmk: [ 0.00 0.00 ] +Key: VMOVAPSZrmkz: [ 0.00 0.00 ] +Key: VMOVAPSZrr: [ 0.00 0.00 ] +Key: VMOVAPSZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrk: [ 0.00 0.00 ] +Key: VMOVAPSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPSmr: [ 0.00 0.00 ] +Key: VMOVAPSrm: [ 0.00 0.00 ] +Key: VMOVAPSrr: [ 0.00 0.00 ] +Key: VMOVAPSrr_REV: [ 0.00 0.00 ] +Key: VMOVDDUPYrm: [ 0.00 0.00 ] +Key: VMOVDDUPYrr: [ 0.00 0.00 ] +Key: VMOVDDUPZ: [ 0.00 0.00 ] +Key: VMOVDDUPZrm: [ 0.00 0.00 ] +Key: VMOVDDUPZrmk: [ 0.00 0.00 ] +Key: VMOVDDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVDDUPZrr: [ 0.00 0.00 ] +Key: VMOVDDUPZrrk: [ 0.00 0.00 ] +Key: VMOVDDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVDDUPrm: [ 0.00 0.00 ] +Key: VMOVDDUPrr: [ 0.00 0.00 ] +Key: VMOVDI: [ 0.00 0.00 ] +Key: VMOVDQA: [ 0.00 0.00 ] +Key: VMOVDQAYmr: [ 0.00 0.00 ] +Key: VMOVDQAYrm: [ 0.00 0.00 ] +Key: VMOVDQAYrr: [ 0.00 0.00 ] +Key: VMOVDQAYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQAmr: [ 0.00 0.00 ] +Key: VMOVDQArm: [ 0.00 0.00 ] +Key: VMOVDQArr: [ 0.00 0.00 ] +Key: VMOVDQArr_REV: [ 0.00 0.00 ] +Key: VMOVDQU: [ 0.00 0.00 ] +Key: VMOVDQUYmr: [ 0.00 0.00 ] +Key: VMOVDQUYrm: [ 0.00 0.00 ] +Key: VMOVDQUYrr: [ 0.00 0.00 ] +Key: VMOVDQUYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQUmr: [ 0.00 0.00 ] +Key: VMOVDQUrm: [ 0.00 0.00 ] +Key: VMOVDQUrr: [ 0.00 0.00 ] +Key: VMOVDQUrr_REV: [ 0.00 0.00 ] +Key: VMOVHLPSZrr: [ 0.00 0.00 ] +Key: VMOVHLPSrr: [ 0.00 0.00 ] +Key: VMOVHPDZ: [ 0.00 0.00 ] +Key: VMOVHPDmr: [ 0.00 0.00 ] +Key: VMOVHPDrm: [ 0.00 0.00 ] +Key: VMOVHPSZ: [ 0.00 0.00 ] +Key: VMOVHPSmr: [ 0.00 0.00 ] +Key: VMOVHPSrm: [ 0.00 0.00 ] +Key: VMOVLHPSZrr: [ 0.00 0.00 ] +Key: VMOVLHPSrr: [ 0.00 0.00 ] +Key: VMOVLPDZ: [ 0.00 0.00 ] +Key: VMOVLPDmr: [ 0.00 0.00 ] +Key: VMOVLPDrm: [ 0.00 0.00 ] +Key: VMOVLPSZ: [ 0.00 0.00 ] +Key: VMOVLPSmr: [ 0.00 0.00 ] +Key: VMOVLPSrm: [ 0.00 0.00 ] +Key: VMOVMSKPDYrr: [ 0.00 0.00 ] +Key: VMOVMSKPDrr: [ 0.00 0.00 ] +Key: VMOVMSKPSYrr: [ 0.00 0.00 ] +Key: VMOVMSKPSrr: [ 0.00 0.00 ] +Key: VMOVNTDQAYrm: [ 0.00 0.00 ] +Key: VMOVNTDQAZ: [ 0.00 0.00 ] +Key: VMOVNTDQAZrm: [ 0.00 0.00 ] +Key: VMOVNTDQArm: [ 0.00 0.00 ] +Key: VMOVNTDQYmr: [ 0.00 0.00 ] +Key: VMOVNTDQZ: [ 0.00 0.00 ] +Key: VMOVNTDQZmr: [ 0.00 0.00 ] +Key: VMOVNTDQmr: [ 0.00 0.00 ] +Key: VMOVNTPDYmr: [ 0.00 0.00 ] +Key: VMOVNTPDZ: [ 0.00 0.00 ] +Key: VMOVNTPDZmr: [ 0.00 0.00 ] +Key: VMOVNTPDmr: [ 0.00 0.00 ] +Key: VMOVNTPSYmr: [ 0.00 0.00 ] +Key: VMOVNTPSZ: [ 0.00 0.00 ] +Key: VMOVNTPSZmr: [ 0.00 0.00 ] +Key: VMOVNTPSmr: [ 0.00 0.00 ] +Key: VMOVPDI: [ 0.00 0.00 ] +Key: VMOVPQI: [ 0.00 0.00 ] +Key: VMOVPQIto: [ 0.00 0.00 ] +Key: VMOVQI: [ 0.00 0.00 ] +Key: VMOVRSBZ: [ 0.00 0.00 ] +Key: VMOVRSBZm: [ 0.00 0.00 ] +Key: VMOVRSBZmk: [ 0.00 0.00 ] +Key: VMOVRSBZmkz: [ 0.00 0.00 ] +Key: VMOVRSDZ: [ 0.00 0.00 ] +Key: VMOVRSDZm: [ 0.00 0.00 ] +Key: VMOVRSDZmk: [ 0.00 0.00 ] +Key: VMOVRSDZmkz: [ 0.00 0.00 ] +Key: VMOVRSQZ: [ 0.00 0.00 ] +Key: VMOVRSQZm: [ 0.00 0.00 ] +Key: VMOVRSQZmk: [ 0.00 0.00 ] +Key: VMOVRSQZmkz: [ 0.00 0.00 ] +Key: VMOVRSWZ: [ 0.00 0.00 ] +Key: VMOVRSWZm: [ 0.00 0.00 ] +Key: VMOVRSWZmk: [ 0.00 0.00 ] +Key: VMOVRSWZmkz: [ 0.00 0.00 ] +Key: VMOVSDZmr: [ 0.00 0.00 ] +Key: VMOVSDZmrk: [ 0.00 0.00 ] +Key: VMOVSDZrm: [ 0.00 0.00 ] +Key: VMOVSDZrm_alt: [ 0.00 0.00 ] +Key: VMOVSDZrmk: [ 0.00 0.00 ] +Key: VMOVSDZrmkz: [ 0.00 0.00 ] +Key: VMOVSDZrr: [ 0.00 0.00 ] +Key: VMOVSDZrr_REV: [ 0.00 0.00 ] +Key: VMOVSDZrrk: [ 0.00 0.00 ] +Key: VMOVSDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVSDZrrkz: [ 0.00 0.00 ] +Key: VMOVSDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVSDmr: [ 0.00 0.00 ] +Key: VMOVSDrm: [ 0.00 0.00 ] +Key: VMOVSDrm_alt: [ 0.00 0.00 ] +Key: VMOVSDrr: [ 0.00 0.00 ] +Key: VMOVSDrr_REV: [ 0.00 0.00 ] +Key: VMOVSDto: [ 0.00 0.00 ] +Key: VMOVSH: [ 0.00 0.00 ] +Key: VMOVSHDUPYrm: [ 0.00 0.00 ] +Key: VMOVSHDUPYrr: [ 0.00 0.00 ] +Key: VMOVSHDUPZ: [ 0.00 0.00 ] +Key: VMOVSHDUPZrm: [ 0.00 0.00 ] +Key: VMOVSHDUPZrmk: [ 0.00 0.00 ] +Key: VMOVSHDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVSHDUPZrr: [ 0.00 0.00 ] +Key: VMOVSHDUPZrrk: [ 0.00 0.00 ] +Key: VMOVSHDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVSHDUPrm: [ 0.00 0.00 ] +Key: VMOVSHDUPrr: [ 0.00 0.00 ] +Key: VMOVSHZmr: [ 0.00 0.00 ] +Key: VMOVSHZmrk: [ 0.00 0.00 ] +Key: VMOVSHZrm: [ 0.00 0.00 ] +Key: VMOVSHZrm_alt: [ 0.00 0.00 ] +Key: VMOVSHZrmk: [ 0.00 0.00 ] +Key: VMOVSHZrmkz: [ 0.00 0.00 ] +Key: VMOVSHZrr: [ 0.00 0.00 ] +Key: VMOVSHZrr_REV: [ 0.00 0.00 ] +Key: VMOVSHZrrk: [ 0.00 0.00 ] +Key: VMOVSHZrrk_REV: [ 0.00 0.00 ] +Key: VMOVSHZrrkz: [ 0.00 0.00 ] +Key: VMOVSHZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVSHtoW: [ 0.00 0.00 ] +Key: VMOVSLDUPYrm: [ 0.00 0.00 ] +Key: VMOVSLDUPYrr: [ 0.00 0.00 ] +Key: VMOVSLDUPZ: [ 0.00 0.00 ] +Key: VMOVSLDUPZrm: [ 0.00 0.00 ] +Key: VMOVSLDUPZrmk: [ 0.00 0.00 ] +Key: VMOVSLDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVSLDUPZrr: [ 0.00 0.00 ] +Key: VMOVSLDUPZrrk: [ 0.00 0.00 ] +Key: VMOVSLDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVSLDUPrm: [ 0.00 0.00 ] +Key: VMOVSLDUPrr: [ 0.00 0.00 ] +Key: VMOVSS: [ 0.00 0.00 ] +Key: VMOVSSZmr: [ 0.00 0.00 ] +Key: VMOVSSZmrk: [ 0.00 0.00 ] +Key: VMOVSSZrm: [ 0.00 0.00 ] +Key: VMOVSSZrm_alt: [ 0.00 0.00 ] +Key: VMOVSSZrmk: [ 0.00 0.00 ] +Key: VMOVSSZrmkz: [ 0.00 0.00 ] +Key: VMOVSSZrr: [ 0.00 0.00 ] +Key: VMOVSSZrr_REV: [ 0.00 0.00 ] +Key: VMOVSSZrrk: [ 0.00 0.00 ] +Key: VMOVSSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVSSZrrkz: [ 0.00 0.00 ] +Key: VMOVSSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVSSmr: [ 0.00 0.00 ] +Key: VMOVSSrm: [ 0.00 0.00 ] +Key: VMOVSSrm_alt: [ 0.00 0.00 ] +Key: VMOVSSrr: [ 0.00 0.00 ] +Key: VMOVSSrr_REV: [ 0.00 0.00 ] +Key: VMOVUPDYmr: [ 0.00 0.00 ] +Key: VMOVUPDYrm: [ 0.00 0.00 ] +Key: VMOVUPDYrr: [ 0.00 0.00 ] +Key: VMOVUPDYrr_REV: [ 0.00 0.00 ] +Key: VMOVUPDZ: [ 0.00 0.00 ] +Key: VMOVUPDZmr: [ 0.00 0.00 ] +Key: VMOVUPDZmrk: [ 0.00 0.00 ] +Key: VMOVUPDZrm: [ 0.00 0.00 ] +Key: VMOVUPDZrmk: [ 0.00 0.00 ] +Key: VMOVUPDZrmkz: [ 0.00 0.00 ] +Key: VMOVUPDZrr: [ 0.00 0.00 ] +Key: VMOVUPDZrr_REV: [ 0.00 0.00 ] +Key: VMOVUPDZrrk: [ 0.00 0.00 ] +Key: VMOVUPDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVUPDZrrkz: [ 0.00 0.00 ] +Key: VMOVUPDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVUPDmr: [ 0.00 0.00 ] +Key: VMOVUPDrm: [ 0.00 0.00 ] +Key: VMOVUPDrr: [ 0.00 0.00 ] +Key: VMOVUPDrr_REV: [ 0.00 0.00 ] +Key: VMOVUPSYmr: [ 0.00 0.00 ] +Key: VMOVUPSYrm: [ 0.00 0.00 ] +Key: VMOVUPSYrr: [ 0.00 0.00 ] +Key: VMOVUPSYrr_REV: [ 0.00 0.00 ] +Key: VMOVUPSZ: [ 0.00 0.00 ] +Key: VMOVUPSZmr: [ 0.00 0.00 ] +Key: VMOVUPSZmrk: [ 0.00 0.00 ] +Key: VMOVUPSZrm: [ 0.00 0.00 ] +Key: VMOVUPSZrmk: [ 0.00 0.00 ] +Key: VMOVUPSZrmkz: [ 0.00 0.00 ] +Key: VMOVUPSZrr: [ 0.00 0.00 ] +Key: VMOVUPSZrr_REV: [ 0.00 0.00 ] +Key: VMOVUPSZrrk: [ 0.00 0.00 ] +Key: VMOVUPSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVUPSZrrkz: [ 0.00 0.00 ] +Key: VMOVUPSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVUPSmr: [ 0.00 0.00 ] +Key: VMOVUPSrm: [ 0.00 0.00 ] +Key: VMOVUPSrr: [ 0.00 0.00 ] +Key: VMOVUPSrr_REV: [ 0.00 0.00 ] +Key: VMOVW: [ 0.00 0.00 ] +Key: VMOVWmr: [ 0.00 0.00 ] +Key: VMOVWrm: [ 0.00 0.00 ] +Key: VMOVZPDILo: [ 0.00 0.00 ] +Key: VMOVZPQILo: [ 0.00 0.00 ] +Key: VMOVZPWILo: [ 0.00 0.00 ] +Key: VMPSADBWYrmi: [ 0.00 0.00 ] +Key: VMPSADBWYrri: [ 0.00 0.00 ] +Key: VMPSADBWZ: [ 0.00 0.00 ] +Key: VMPSADBWZrmi: [ 0.00 0.00 ] +Key: VMPSADBWZrmik: [ 0.00 0.00 ] +Key: VMPSADBWZrmikz: [ 0.00 0.00 ] +Key: VMPSADBWZrri: [ 0.00 0.00 ] +Key: VMPSADBWZrrik: [ 0.00 0.00 ] +Key: VMPSADBWZrrikz: [ 0.00 0.00 ] +Key: VMPSADBWrmi: [ 0.00 0.00 ] +Key: VMPSADBWrri: [ 0.00 0.00 ] +Key: VMPTRLDm: [ 0.00 0.00 ] +Key: VMPTRSTm: [ 0.00 0.00 ] +Key: VMREAD: [ 0.00 0.00 ] +Key: VMRESUME: [ 0.00 0.00 ] +Key: VMRUN: [ 0.00 0.00 ] +Key: VMSAVE: [ 0.00 0.00 ] +Key: VMULBF: [ 0.00 0.00 ] +Key: VMULPDYrm: [ 0.00 0.00 ] +Key: VMULPDYrr: [ 0.00 0.00 ] +Key: VMULPDZ: [ 0.00 0.00 ] +Key: VMULPDZrm: [ 0.00 0.00 ] +Key: VMULPDZrmb: [ 0.00 0.00 ] +Key: VMULPDZrmbk: [ 0.00 0.00 ] +Key: VMULPDZrmbkz: [ 0.00 0.00 ] +Key: VMULPDZrmk: [ 0.00 0.00 ] +Key: VMULPDZrmkz: [ 0.00 0.00 ] +Key: VMULPDZrr: [ 0.00 0.00 ] +Key: VMULPDZrrb: [ 0.00 0.00 ] +Key: VMULPDZrrbk: [ 0.00 0.00 ] +Key: VMULPDZrrbkz: [ 0.00 0.00 ] +Key: VMULPDZrrk: [ 0.00 0.00 ] +Key: VMULPDZrrkz: [ 0.00 0.00 ] +Key: VMULPDrm: [ 0.00 0.00 ] +Key: VMULPDrr: [ 0.00 0.00 ] +Key: VMULPHZ: [ 0.00 0.00 ] +Key: VMULPHZrm: [ 0.00 0.00 ] +Key: VMULPHZrmb: [ 0.00 0.00 ] +Key: VMULPHZrmbk: [ 0.00 0.00 ] +Key: VMULPHZrmbkz: [ 0.00 0.00 ] +Key: VMULPHZrmk: [ 0.00 0.00 ] +Key: VMULPHZrmkz: [ 0.00 0.00 ] +Key: VMULPHZrr: [ 0.00 0.00 ] +Key: VMULPHZrrb: [ 0.00 0.00 ] +Key: VMULPHZrrbk: [ 0.00 0.00 ] +Key: VMULPHZrrbkz: [ 0.00 0.00 ] +Key: VMULPHZrrk: [ 0.00 0.00 ] +Key: VMULPHZrrkz: [ 0.00 0.00 ] +Key: VMULPSYrm: [ 0.00 0.00 ] +Key: VMULPSYrr: [ 0.00 0.00 ] +Key: VMULPSZ: [ 0.00 0.00 ] +Key: VMULPSZrm: [ 0.00 0.00 ] +Key: VMULPSZrmb: [ 0.00 0.00 ] +Key: VMULPSZrmbk: [ 0.00 0.00 ] +Key: VMULPSZrmbkz: [ 0.00 0.00 ] +Key: VMULPSZrmk: [ 0.00 0.00 ] +Key: VMULPSZrmkz: [ 0.00 0.00 ] +Key: VMULPSZrr: [ 0.00 0.00 ] +Key: VMULPSZrrb: [ 0.00 0.00 ] +Key: VMULPSZrrbk: [ 0.00 0.00 ] +Key: VMULPSZrrbkz: [ 0.00 0.00 ] +Key: VMULPSZrrk: [ 0.00 0.00 ] +Key: VMULPSZrrkz: [ 0.00 0.00 ] +Key: VMULPSrm: [ 0.00 0.00 ] +Key: VMULPSrr: [ 0.00 0.00 ] +Key: VMULSDZrm: [ 0.00 0.00 ] +Key: VMULSDZrm_Int: [ 0.00 0.00 ] +Key: VMULSDZrmk_Int: [ 0.00 0.00 ] +Key: VMULSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMULSDZrr: [ 0.00 0.00 ] +Key: VMULSDZrr_Int: [ 0.00 0.00 ] +Key: VMULSDZrrb_Int: [ 0.00 0.00 ] +Key: VMULSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMULSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMULSDZrrk_Int: [ 0.00 0.00 ] +Key: VMULSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMULSDrm: [ 0.00 0.00 ] +Key: VMULSDrm_Int: [ 0.00 0.00 ] +Key: VMULSDrr: [ 0.00 0.00 ] +Key: VMULSDrr_Int: [ 0.00 0.00 ] +Key: VMULSHZrm: [ 0.00 0.00 ] +Key: VMULSHZrm_Int: [ 0.00 0.00 ] +Key: VMULSHZrmk_Int: [ 0.00 0.00 ] +Key: VMULSHZrmkz_Int: [ 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VPCONFLICTDZrmk: [ 0.00 0.00 ] +Key: VPCONFLICTDZrmkz: [ 0.00 0.00 ] +Key: VPCONFLICTDZrr: [ 0.00 0.00 ] +Key: VPCONFLICTDZrrk: [ 0.00 0.00 ] +Key: VPCONFLICTDZrrkz: [ 0.00 0.00 ] +Key: VPCONFLICTQZ: [ 0.00 0.00 ] +Key: VPCONFLICTQZrm: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmb: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmbk: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmbkz: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmk: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmkz: [ 0.00 0.00 ] +Key: VPCONFLICTQZrr: [ 0.00 0.00 ] +Key: VPCONFLICTQZrrk: [ 0.00 0.00 ] +Key: VPCONFLICTQZrrkz: [ 0.00 0.00 ] +Key: VPDPBSSDSYrm: [ 0.00 0.00 ] +Key: VPDPBSSDSYrr: [ 0.00 0.00 ] +Key: VPDPBSSDSZ: [ 0.00 0.00 ] +Key: VPDPBSSDSZrm: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmb: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmbk: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmbkz: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmk: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmkz: [ 0.00 0.00 ] +Key: VPDPBSSDSZrr: [ 0.00 0.00 ] +Key: VPDPBSSDSZrrk: [ 0.00 0.00 ] +Key: VPDPBSSDSZrrkz: [ 0.00 0.00 ] +Key: VPDPBSSDSrm: [ 0.00 0.00 ] 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] +Key: VPHADDBQrm: [ 0.00 0.00 ] +Key: VPHADDBQrr: [ 0.00 0.00 ] +Key: VPHADDBWrm: [ 0.00 0.00 ] +Key: VPHADDBWrr: [ 0.00 0.00 ] +Key: VPHADDDQrm: [ 0.00 0.00 ] +Key: VPHADDDQrr: [ 0.00 0.00 ] +Key: VPHADDDYrm: [ 0.00 0.00 ] +Key: VPHADDDYrr: [ 0.00 0.00 ] +Key: VPHADDDrm: [ 0.00 0.00 ] +Key: VPHADDDrr: [ 0.00 0.00 ] +Key: VPHADDSWYrm: [ 0.00 0.00 ] +Key: VPHADDSWYrr: [ 0.00 0.00 ] +Key: VPHADDSWrm: [ 0.00 0.00 ] +Key: VPHADDSWrr: [ 0.00 0.00 ] +Key: VPHADDUBDrm: [ 0.00 0.00 ] +Key: VPHADDUBDrr: [ 0.00 0.00 ] +Key: VPHADDUBQrm: [ 0.00 0.00 ] +Key: VPHADDUBQrr: [ 0.00 0.00 ] +Key: VPHADDUBWrm: [ 0.00 0.00 ] +Key: VPHADDUBWrr: [ 0.00 0.00 ] +Key: VPHADDUDQrm: [ 0.00 0.00 ] +Key: VPHADDUDQrr: [ 0.00 0.00 ] +Key: VPHADDUWDrm: [ 0.00 0.00 ] +Key: VPHADDUWDrr: [ 0.00 0.00 ] +Key: VPHADDUWQrm: [ 0.00 0.00 ] +Key: VPHADDUWQrr: [ 0.00 0.00 ] +Key: VPHADDWDrm: [ 0.00 0.00 ] +Key: VPHADDWDrr: [ 0.00 0.00 ] +Key: VPHADDWQrm: [ 0.00 0.00 ] +Key: VPHADDWQrr: [ 0.00 0.00 ] +Key: VPHADDWYrm: [ 0.00 0.00 ] +Key: VPHADDWYrr: [ 0.00 0.00 ] +Key: VPHADDWrm: [ 0.00 0.00 ] +Key: VPHADDWrr: [ 0.00 0.00 ] +Key: VPHMINPOSUWrm: [ 0.00 0.00 ] +Key: VPHMINPOSUWrr: [ 0.00 0.00 ] +Key: VPHSUBBWrm: [ 0.00 0.00 ] +Key: VPHSUBBWrr: [ 0.00 0.00 ] +Key: VPHSUBDQrm: [ 0.00 0.00 ] +Key: VPHSUBDQrr: [ 0.00 0.00 ] +Key: VPHSUBDYrm: [ 0.00 0.00 ] +Key: VPHSUBDYrr: [ 0.00 0.00 ] +Key: VPHSUBDrm: [ 0.00 0.00 ] +Key: VPHSUBDrr: [ 0.00 0.00 ] +Key: VPHSUBSWYrm: [ 0.00 0.00 ] +Key: VPHSUBSWYrr: [ 0.00 0.00 ] +Key: VPHSUBSWrm: [ 0.00 0.00 ] +Key: VPHSUBSWrr: [ 0.00 0.00 ] +Key: VPHSUBWDrm: [ 0.00 0.00 ] +Key: VPHSUBWDrr: [ 0.00 0.00 ] +Key: VPHSUBWYrm: [ 0.00 0.00 ] +Key: VPHSUBWYrr: [ 0.00 0.00 ] +Key: VPHSUBWrm: [ 0.00 0.00 ] +Key: VPHSUBWrr: [ 0.00 0.00 ] +Key: VPINSRBZrmi: [ 0.00 0.00 ] +Key: VPINSRBZrri: [ 0.00 0.00 ] +Key: VPINSRBrmi: [ 0.00 0.00 ] +Key: VPINSRBrri: [ 0.00 0.00 ] +Key: VPINSRDZrmi: [ 0.00 0.00 ] +Key: VPINSRDZrri: [ 0.00 0.00 ] +Key: VPINSRDrmi: [ 0.00 0.00 ] +Key: VPINSRDrri: [ 0.00 0.00 ] +Key: VPINSRQZrmi: [ 0.00 0.00 ] +Key: VPINSRQZrri: [ 0.00 0.00 ] +Key: VPINSRQrmi: [ 0.00 0.00 ] +Key: VPINSRQrri: [ 0.00 0.00 ] +Key: VPINSRWZrmi: [ 0.00 0.00 ] +Key: VPINSRWZrri: [ 0.00 0.00 ] +Key: VPINSRWrmi: [ 0.00 0.00 ] +Key: VPINSRWrri: [ 0.00 0.00 ] +Key: VPLZCNTDZ: [ 0.00 0.00 ] +Key: VPLZCNTDZrm: [ 0.00 0.00 ] +Key: VPLZCNTDZrmb: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrmk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrr: [ 0.00 0.00 ] +Key: VPLZCNTDZrrk: [ 0.00 0.00 ] +Key: VPLZCNTDZrrkz: [ 0.00 0.00 ] +Key: VPLZCNTQZ: [ 0.00 0.00 ] +Key: VPLZCNTQZrm: [ 0.00 0.00 ] +Key: VPLZCNTQZrmb: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrmk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrr: [ 0.00 0.00 ] +Key: VPLZCNTQZrrk: [ 0.00 0.00 ] +Key: VPLZCNTQZrrkz: [ 0.00 0.00 ] +Key: VPMACSDDrm: [ 0.00 0.00 ] +Key: VPMACSDDrr: [ 0.00 0.00 ] +Key: VPMACSDQHrm: [ 0.00 0.00 ] +Key: VPMACSDQHrr: [ 0.00 0.00 ] +Key: VPMACSDQLrm: [ 0.00 0.00 ] +Key: VPMACSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSDDrm: [ 0.00 0.00 ] +Key: VPMACSSDDrr: [ 0.00 0.00 ] +Key: VPMACSSDQHrm: [ 0.00 0.00 ] +Key: VPMACSSDQHrr: [ 0.00 0.00 ] +Key: VPMACSSDQLrm: [ 0.00 0.00 ] +Key: VPMACSSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSWDrm: [ 0.00 0.00 ] +Key: VPMACSSWDrr: [ 0.00 0.00 ] +Key: VPMACSSWWrm: [ 0.00 0.00 ] +Key: VPMACSSWWrr: [ 0.00 0.00 ] +Key: VPMACSWDrm: [ 0.00 0.00 ] +Key: VPMACSWDrr: [ 0.00 0.00 ] +Key: VPMACSWWrm: [ 0.00 0.00 ] +Key: VPMACSWWrr: [ 0.00 0.00 ] +Key: VPMADCSSWDrm: [ 0.00 0.00 ] +Key: VPMADCSSWDrr: [ 0.00 0.00 ] +Key: VPMADCSWDrm: [ 0.00 0.00 ] +Key: VPMADCSWDrr: [ 0.00 0.00 ] +Key: VPMADD: [ 0.00 0.00 ] +Key: VPMADDUBSWYrm: [ 0.00 0.00 ] +Key: VPMADDUBSWYrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZ: [ 0.00 0.00 ] +Key: VPMADDUBSWZrm: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmkz: [ 0.00 0.00 ] +Key: VPMADDUBSWZrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrkz: [ 0.00 0.00 ] +Key: VPMADDUBSWrm: [ 0.00 0.00 ] +Key: VPMADDUBSWrr: [ 0.00 0.00 ] +Key: VPMADDWDYrm: [ 0.00 0.00 ] +Key: VPMADDWDYrr: [ 0.00 0.00 ] +Key: VPMADDWDZ: [ 0.00 0.00 ] +Key: VPMADDWDZrm: [ 0.00 0.00 ] +Key: VPMADDWDZrmk: [ 0.00 0.00 ] +Key: VPMADDWDZrmkz: [ 0.00 0.00 ] +Key: VPMADDWDZrr: [ 0.00 0.00 ] +Key: VPMADDWDZrrk: [ 0.00 0.00 ] +Key: VPMADDWDZrrkz: [ 0.00 0.00 ] +Key: VPMADDWDrm: [ 0.00 0.00 ] +Key: VPMADDWDrr: [ 0.00 0.00 ] +Key: VPMASKMOVDYmr: [ 0.00 0.00 ] +Key: VPMASKMOVDYrm: [ 0.00 0.00 ] +Key: VPMASKMOVDmr: [ 0.00 0.00 ] +Key: VPMASKMOVDrm: [ 0.00 0.00 ] +Key: VPMASKMOVQYmr: [ 0.00 0.00 ] +Key: VPMASKMOVQYrm: [ 0.00 0.00 ] +Key: VPMASKMOVQmr: [ 0.00 0.00 ] +Key: VPMASKMOVQrm: [ 0.00 0.00 ] +Key: VPMAXSBYrm: [ 0.00 0.00 ] +Key: VPMAXSBYrr: [ 0.00 0.00 ] +Key: VPMAXSBZ: [ 0.00 0.00 ] +Key: VPMAXSBZrm: [ 0.00 0.00 ] +Key: VPMAXSBZrmk: [ 0.00 0.00 ] +Key: VPMAXSBZrmkz: [ 0.00 0.00 ] +Key: VPMAXSBZrr: [ 0.00 0.00 ] +Key: VPMAXSBZrrk: [ 0.00 0.00 ] +Key: VPMAXSBZrrkz: [ 0.00 0.00 ] +Key: VPMAXSBrm: [ 0.00 0.00 ] +Key: VPMAXSBrr: [ 0.00 0.00 ] +Key: VPMAXSDYrm: [ 0.00 0.00 ] +Key: VPMAXSDYrr: [ 0.00 0.00 ] +Key: VPMAXSDZ: [ 0.00 0.00 ] +Key: VPMAXSDZrm: [ 0.00 0.00 ] +Key: VPMAXSDZrmb: [ 0.00 0.00 ] +Key: VPMAXSDZrmbk: [ 0.00 0.00 ] +Key: VPMAXSDZrmbkz: [ 0.00 0.00 ] +Key: VPMAXSDZrmk: [ 0.00 0.00 ] +Key: VPMAXSDZrmkz: [ 0.00 0.00 ] +Key: VPMAXSDZrr: [ 0.00 0.00 ] +Key: VPMAXSDZrrk: [ 0.00 0.00 ] +Key: VPMAXSDZrrkz: [ 0.00 0.00 ] +Key: VPMAXSDrm: [ 0.00 0.00 ] +Key: VPMAXSDrr: [ 0.00 0.00 ] +Key: VPMAXSQZ: [ 0.00 0.00 ] +Key: VPMAXSQZrm: [ 0.00 0.00 ] +Key: VPMAXSQZrmb: [ 0.00 0.00 ] +Key: VPMAXSQZrmbk: [ 0.00 0.00 ] +Key: VPMAXSQZrmbkz: [ 0.00 0.00 ] +Key: VPMAXSQZrmk: [ 0.00 0.00 ] +Key: VPMAXSQZrmkz: [ 0.00 0.00 ] +Key: VPMAXSQZrr: [ 0.00 0.00 ] +Key: VPMAXSQZrrk: [ 0.00 0.00 ] +Key: VPMAXSQZrrkz: [ 0.00 0.00 ] +Key: VPMAXSWYrm: [ 0.00 0.00 ] +Key: VPMAXSWYrr: [ 0.00 0.00 ] +Key: VPMAXSWZ: [ 0.00 0.00 ] +Key: VPMAXSWZrm: [ 0.00 0.00 ] +Key: VPMAXSWZrmk: [ 0.00 0.00 ] +Key: VPMAXSWZrmkz: [ 0.00 0.00 ] +Key: VPMAXSWZrr: [ 0.00 0.00 ] +Key: VPMAXSWZrrk: [ 0.00 0.00 ] +Key: VPMAXSWZrrkz: [ 0.00 0.00 ] +Key: VPMAXSWrm: [ 0.00 0.00 ] +Key: VPMAXSWrr: [ 0.00 0.00 ] +Key: VPMAXUBYrm: [ 0.00 0.00 ] +Key: VPMAXUBYrr: [ 0.00 0.00 ] +Key: VPMAXUBZ: [ 0.00 0.00 ] +Key: VPMAXUBZrm: [ 0.00 0.00 ] +Key: VPMAXUBZrmk: [ 0.00 0.00 ] +Key: VPMAXUBZrmkz: [ 0.00 0.00 ] +Key: VPMAXUBZrr: [ 0.00 0.00 ] +Key: VPMAXUBZrrk: [ 0.00 0.00 ] +Key: VPMAXUBZrrkz: [ 0.00 0.00 ] +Key: VPMAXUBrm: [ 0.00 0.00 ] +Key: VPMAXUBrr: [ 0.00 0.00 ] +Key: VPMAXUDYrm: [ 0.00 0.00 ] +Key: VPMAXUDYrr: [ 0.00 0.00 ] +Key: VPMAXUDZ: [ 0.00 0.00 ] +Key: VPMAXUDZrm: [ 0.00 0.00 ] +Key: VPMAXUDZrmb: [ 0.00 0.00 ] +Key: VPMAXUDZrmbk: [ 0.00 0.00 ] +Key: VPMAXUDZrmbkz: [ 0.00 0.00 ] +Key: VPMAXUDZrmk: [ 0.00 0.00 ] +Key: VPMAXUDZrmkz: [ 0.00 0.00 ] +Key: VPMAXUDZrr: [ 0.00 0.00 ] +Key: VPMAXUDZrrk: [ 0.00 0.00 ] +Key: VPMAXUDZrrkz: [ 0.00 0.00 ] +Key: VPMAXUDrm: [ 0.00 0.00 ] +Key: VPMAXUDrr: [ 0.00 0.00 ] +Key: VPMAXUQZ: [ 0.00 0.00 ] +Key: VPMAXUQZrm: [ 0.00 0.00 ] +Key: VPMAXUQZrmb: [ 0.00 0.00 ] +Key: VPMAXUQZrmbk: [ 0.00 0.00 ] +Key: VPMAXUQZrmbkz: [ 0.00 0.00 ] +Key: VPMAXUQZrmk: [ 0.00 0.00 ] +Key: VPMAXUQZrmkz: [ 0.00 0.00 ] +Key: VPMAXUQZrr: [ 0.00 0.00 ] +Key: VPMAXUQZrrk: [ 0.00 0.00 ] +Key: VPMAXUQZrrkz: [ 0.00 0.00 ] +Key: VPMAXUWYrm: [ 0.00 0.00 ] +Key: VPMAXUWYrr: [ 0.00 0.00 ] +Key: VPMAXUWZ: [ 0.00 0.00 ] +Key: VPMAXUWZrm: [ 0.00 0.00 ] +Key: VPMAXUWZrmk: [ 0.00 0.00 ] +Key: VPMAXUWZrmkz: [ 0.00 0.00 ] +Key: VPMAXUWZrr: [ 0.00 0.00 ] +Key: VPMAXUWZrrk: [ 0.00 0.00 ] +Key: VPMAXUWZrrkz: [ 0.00 0.00 ] +Key: VPMAXUWrm: [ 0.00 0.00 ] +Key: VPMAXUWrr: [ 0.00 0.00 ] +Key: VPMINSBYrm: [ 0.00 0.00 ] +Key: VPMINSBYrr: [ 0.00 0.00 ] +Key: VPMINSBZ: [ 0.00 0.00 ] +Key: VPMINSBZrm: [ 0.00 0.00 ] +Key: VPMINSBZrmk: [ 0.00 0.00 ] +Key: VPMINSBZrmkz: [ 0.00 0.00 ] +Key: VPMINSBZrr: [ 0.00 0.00 ] +Key: VPMINSBZrrk: [ 0.00 0.00 ] +Key: VPMINSBZrrkz: [ 0.00 0.00 ] +Key: VPMINSBrm: [ 0.00 0.00 ] +Key: VPMINSBrr: [ 0.00 0.00 ] +Key: VPMINSDYrm: [ 0.00 0.00 ] +Key: VPMINSDYrr: [ 0.00 0.00 ] +Key: VPMINSDZ: [ 0.00 0.00 ] +Key: VPMINSDZrm: [ 0.00 0.00 ] +Key: VPMINSDZrmb: [ 0.00 0.00 ] +Key: VPMINSDZrmbk: [ 0.00 0.00 ] +Key: VPMINSDZrmbkz: [ 0.00 0.00 ] +Key: VPMINSDZrmk: [ 0.00 0.00 ] +Key: VPMINSDZrmkz: [ 0.00 0.00 ] +Key: VPMINSDZrr: [ 0.00 0.00 ] +Key: VPMINSDZrrk: [ 0.00 0.00 ] +Key: VPMINSDZrrkz: [ 0.00 0.00 ] +Key: VPMINSDrm: [ 0.00 0.00 ] +Key: VPMINSDrr: [ 0.00 0.00 ] +Key: VPMINSQZ: [ 0.00 0.00 ] +Key: VPMINSQZrm: [ 0.00 0.00 ] +Key: VPMINSQZrmb: [ 0.00 0.00 ] +Key: VPMINSQZrmbk: [ 0.00 0.00 ] +Key: VPMINSQZrmbkz: [ 0.00 0.00 ] +Key: VPMINSQZrmk: [ 0.00 0.00 ] +Key: VPMINSQZrmkz: [ 0.00 0.00 ] +Key: VPMINSQZrr: [ 0.00 0.00 ] +Key: VPMINSQZrrk: [ 0.00 0.00 ] +Key: VPMINSQZrrkz: [ 0.00 0.00 ] +Key: VPMINSWYrm: [ 0.00 0.00 ] +Key: VPMINSWYrr: [ 0.00 0.00 ] +Key: VPMINSWZ: [ 0.00 0.00 ] +Key: VPMINSWZrm: [ 0.00 0.00 ] +Key: VPMINSWZrmk: [ 0.00 0.00 ] +Key: VPMINSWZrmkz: [ 0.00 0.00 ] +Key: VPMINSWZrr: [ 0.00 0.00 ] +Key: VPMINSWZrrk: [ 0.00 0.00 ] +Key: VPMINSWZrrkz: [ 0.00 0.00 ] +Key: VPMINSWrm: [ 0.00 0.00 ] +Key: VPMINSWrr: [ 0.00 0.00 ] +Key: VPMINUBYrm: [ 0.00 0.00 ] +Key: VPMINUBYrr: [ 0.00 0.00 ] +Key: VPMINUBZ: [ 0.00 0.00 ] +Key: VPMINUBZrm: [ 0.00 0.00 ] +Key: VPMINUBZrmk: [ 0.00 0.00 ] +Key: VPMINUBZrmkz: [ 0.00 0.00 ] +Key: VPMINUBZrr: [ 0.00 0.00 ] +Key: VPMINUBZrrk: [ 0.00 0.00 ] +Key: VPMINUBZrrkz: [ 0.00 0.00 ] +Key: VPMINUBrm: [ 0.00 0.00 ] +Key: VPMINUBrr: [ 0.00 0.00 ] +Key: VPMINUDYrm: [ 0.00 0.00 ] +Key: VPMINUDYrr: [ 0.00 0.00 ] +Key: VPMINUDZ: [ 0.00 0.00 ] +Key: VPMINUDZrm: [ 0.00 0.00 ] +Key: VPMINUDZrmb: [ 0.00 0.00 ] +Key: VPMINUDZrmbk: [ 0.00 0.00 ] +Key: VPMINUDZrmbkz: [ 0.00 0.00 ] +Key: VPMINUDZrmk: [ 0.00 0.00 ] +Key: VPMINUDZrmkz: [ 0.00 0.00 ] +Key: VPMINUDZrr: [ 0.00 0.00 ] +Key: VPMINUDZrrk: [ 0.00 0.00 ] +Key: VPMINUDZrrkz: [ 0.00 0.00 ] +Key: VPMINUDrm: [ 0.00 0.00 ] +Key: VPMINUDrr: [ 0.00 0.00 ] +Key: VPMINUQZ: [ 0.00 0.00 ] +Key: VPMINUQZrm: [ 0.00 0.00 ] +Key: VPMINUQZrmb: [ 0.00 0.00 ] +Key: VPMINUQZrmbk: [ 0.00 0.00 ] +Key: VPMINUQZrmbkz: [ 0.00 0.00 ] +Key: VPMINUQZrmk: [ 0.00 0.00 ] +Key: VPMINUQZrmkz: [ 0.00 0.00 ] +Key: VPMINUQZrr: [ 0.00 0.00 ] +Key: VPMINUQZrrk: [ 0.00 0.00 ] +Key: VPMINUQZrrkz: [ 0.00 0.00 ] +Key: VPMINUWYrm: [ 0.00 0.00 ] +Key: VPMINUWYrr: [ 0.00 0.00 ] +Key: VPMINUWZ: [ 0.00 0.00 ] +Key: VPMINUWZrm: [ 0.00 0.00 ] +Key: VPMINUWZrmk: [ 0.00 0.00 ] +Key: VPMINUWZrmkz: [ 0.00 0.00 ] +Key: VPMINUWZrr: [ 0.00 0.00 ] +Key: VPMINUWZrrk: [ 0.00 0.00 ] +Key: VPMINUWZrrkz: [ 0.00 0.00 ] +Key: VPMINUWrm: [ 0.00 0.00 ] +Key: VPMINUWrr: [ 0.00 0.00 ] +Key: VPMOVB: [ 0.00 0.00 ] +Key: VPMOVD: [ 0.00 0.00 ] +Key: VPMOVDBZ: [ 0.00 0.00 ] +Key: VPMOVDBZmr: [ 0.00 0.00 ] +Key: VPMOVDBZmrk: [ 0.00 0.00 ] +Key: VPMOVDBZrr: [ 0.00 0.00 ] +Key: VPMOVDBZrrk: [ 0.00 0.00 ] +Key: VPMOVDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVDWZ: [ 0.00 0.00 ] +Key: VPMOVDWZmr: [ 0.00 0.00 ] +Key: VPMOVDWZmrk: [ 0.00 0.00 ] +Key: VPMOVDWZrr: [ 0.00 0.00 ] +Key: VPMOVDWZrrk: [ 0.00 0.00 ] +Key: VPMOVDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVM: [ 0.00 0.00 ] +Key: VPMOVMSKBYrr: [ 0.00 0.00 ] +Key: VPMOVMSKBrr: [ 0.00 0.00 ] +Key: VPMOVQ: [ 0.00 0.00 ] +Key: VPMOVQBZ: [ 0.00 0.00 ] +Key: VPMOVQBZmr: [ 0.00 0.00 ] +Key: VPMOVQBZmrk: [ 0.00 0.00 ] +Key: VPMOVQBZrr: [ 0.00 0.00 ] +Key: VPMOVQBZrrk: [ 0.00 0.00 ] +Key: VPMOVQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVQDZ: [ 0.00 0.00 ] +Key: VPMOVQDZmr: [ 0.00 0.00 ] +Key: VPMOVQDZmrk: [ 0.00 0.00 ] +Key: VPMOVQDZrr: [ 0.00 0.00 ] +Key: VPMOVQDZrrk: [ 0.00 0.00 ] +Key: VPMOVQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVQWZ: [ 0.00 0.00 ] +Key: VPMOVQWZmr: [ 0.00 0.00 ] +Key: VPMOVQWZmrk: [ 0.00 0.00 ] +Key: VPMOVQWZrr: [ 0.00 0.00 ] +Key: VPMOVQWZrrk: [ 0.00 0.00 ] +Key: VPMOVQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSDBZ: [ 0.00 0.00 ] +Key: VPMOVSDBZmr: [ 0.00 0.00 ] +Key: VPMOVSDBZmrk: [ 0.00 0.00 ] +Key: VPMOVSDBZrr: [ 0.00 0.00 ] +Key: VPMOVSDBZrrk: [ 0.00 0.00 ] +Key: VPMOVSDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVSDWZ: [ 0.00 0.00 ] +Key: VPMOVSDWZmr: [ 0.00 0.00 ] +Key: VPMOVSDWZmrk: [ 0.00 0.00 ] +Key: VPMOVSDWZrr: [ 0.00 0.00 ] +Key: VPMOVSDWZrrk: [ 0.00 0.00 ] +Key: VPMOVSDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSQBZ: [ 0.00 0.00 ] +Key: VPMOVSQBZmr: [ 0.00 0.00 ] +Key: VPMOVSQBZmrk: [ 0.00 0.00 ] +Key: VPMOVSQBZrr: [ 0.00 0.00 ] +Key: VPMOVSQBZrrk: [ 0.00 0.00 ] +Key: VPMOVSQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVSQDZ: [ 0.00 0.00 ] +Key: VPMOVSQDZmr: [ 0.00 0.00 ] +Key: VPMOVSQDZmrk: [ 0.00 0.00 ] +Key: VPMOVSQDZrr: [ 0.00 0.00 ] +Key: VPMOVSQDZrrk: [ 0.00 0.00 ] +Key: VPMOVSQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVSQWZ: [ 0.00 0.00 ] +Key: VPMOVSQWZmr: [ 0.00 0.00 ] +Key: VPMOVSQWZmrk: [ 0.00 0.00 ] +Key: VPMOVSQWZrr: [ 0.00 0.00 ] +Key: VPMOVSQWZrrk: [ 0.00 0.00 ] +Key: VPMOVSQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSWBZ: [ 0.00 0.00 ] +Key: VPMOVSWBZmr: [ 0.00 0.00 ] +Key: VPMOVSWBZmrk: [ 0.00 0.00 ] +Key: VPMOVSWBZrr: [ 0.00 0.00 ] +Key: VPMOVSWBZrrk: [ 0.00 0.00 ] +Key: VPMOVSWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBDYrm: [ 0.00 0.00 ] +Key: VPMOVSXBDYrr: [ 0.00 0.00 ] +Key: VPMOVSXBDZ: [ 0.00 0.00 ] +Key: VPMOVSXBDZrm: [ 0.00 0.00 ] +Key: VPMOVSXBDZrmk: [ 0.00 0.00 ] +Key: VPMOVSXBDZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXBDZrr: [ 0.00 0.00 ] +Key: VPMOVSXBDZrrk: [ 0.00 0.00 ] +Key: VPMOVSXBDZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBDrm: [ 0.00 0.00 ] +Key: VPMOVSXBDrr: [ 0.00 0.00 ] +Key: VPMOVSXBQYrm: [ 0.00 0.00 ] +Key: VPMOVSXBQYrr: [ 0.00 0.00 ] +Key: VPMOVSXBQZ: [ 0.00 0.00 ] +Key: VPMOVSXBQZrm: [ 0.00 0.00 ] +Key: VPMOVSXBQZrmk: [ 0.00 0.00 ] +Key: VPMOVSXBQZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXBQZrr: [ 0.00 0.00 ] +Key: VPMOVSXBQZrrk: [ 0.00 0.00 ] +Key: VPMOVSXBQZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBQrm: [ 0.00 0.00 ] +Key: VPMOVSXBQrr: [ 0.00 0.00 ] +Key: VPMOVSXBWYrm: [ 0.00 0.00 ] +Key: VPMOVSXBWYrr: [ 0.00 0.00 ] +Key: VPMOVSXBWZ: [ 0.00 0.00 ] +Key: VPMOVSXBWZrm: [ 0.00 0.00 ] +Key: VPMOVSXBWZrmk: [ 0.00 0.00 ] +Key: VPMOVSXBWZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXBWZrr: [ 0.00 0.00 ] +Key: VPMOVSXBWZrrk: [ 0.00 0.00 ] +Key: VPMOVSXBWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBWrm: [ 0.00 0.00 ] +Key: VPMOVSXBWrr: [ 0.00 0.00 ] +Key: VPMOVSXDQYrm: [ 0.00 0.00 ] +Key: VPMOVSXDQYrr: [ 0.00 0.00 ] +Key: VPMOVSXDQZ: [ 0.00 0.00 ] +Key: VPMOVSXDQZrm: [ 0.00 0.00 ] +Key: VPMOVSXDQZrmk: [ 0.00 0.00 ] +Key: VPMOVSXDQZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXDQZrr: [ 0.00 0.00 ] +Key: VPMOVSXDQZrrk: [ 0.00 0.00 ] +Key: VPMOVSXDQZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXDQrm: [ 0.00 0.00 ] +Key: VPMOVSXDQrr: [ 0.00 0.00 ] +Key: VPMOVSXWDYrm: [ 0.00 0.00 ] +Key: VPMOVSXWDYrr: [ 0.00 0.00 ] +Key: VPMOVSXWDZ: [ 0.00 0.00 ] +Key: VPMOVSXWDZrm: [ 0.00 0.00 ] +Key: VPMOVSXWDZrmk: [ 0.00 0.00 ] +Key: VPMOVSXWDZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXWDZrr: [ 0.00 0.00 ] +Key: VPMOVSXWDZrrk: [ 0.00 0.00 ] +Key: VPMOVSXWDZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXWDrm: [ 0.00 0.00 ] +Key: VPMOVSXWDrr: [ 0.00 0.00 ] +Key: VPMOVSXWQYrm: [ 0.00 0.00 ] +Key: VPMOVSXWQYrr: [ 0.00 0.00 ] +Key: VPMOVSXWQZ: [ 0.00 0.00 ] +Key: VPMOVSXWQZrm: [ 0.00 0.00 ] +Key: VPMOVSXWQZrmk: [ 0.00 0.00 ] +Key: VPMOVSXWQZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXWQZrr: [ 0.00 0.00 ] +Key: VPMOVSXWQZrrk: [ 0.00 0.00 ] +Key: VPMOVSXWQZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXWQrm: [ 0.00 0.00 ] +Key: VPMOVSXWQrr: [ 0.00 0.00 ] +Key: VPMOVUSDBZ: [ 0.00 0.00 ] +Key: VPMOVUSDBZmr: [ 0.00 0.00 ] +Key: VPMOVUSDBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSDBZrr: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSDWZ: [ 0.00 0.00 ] +Key: VPMOVUSDWZmr: [ 0.00 0.00 ] +Key: VPMOVUSDWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrr: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQBZ: [ 0.00 0.00 ] +Key: VPMOVUSQBZmr: [ 0.00 0.00 ] +Key: VPMOVUSQBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrr: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQDZ: [ 0.00 0.00 ] +Key: VPMOVUSQDZmr: [ 0.00 0.00 ] +Key: VPMOVUSQDZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrr: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQWZ: [ 0.00 0.00 ] +Key: VPMOVUSQWZmr: [ 0.00 0.00 ] +Key: VPMOVUSQWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrr: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSWBZ: [ 0.00 0.00 ] +Key: VPMOVUSWBZmr: [ 0.00 0.00 ] +Key: VPMOVUSWBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrr: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVW: [ 0.00 0.00 ] +Key: VPMOVWBZ: [ 0.00 0.00 ] +Key: VPMOVWBZmr: [ 0.00 0.00 ] +Key: VPMOVWBZmrk: [ 0.00 0.00 ] +Key: VPMOVWBZrr: [ 0.00 0.00 ] +Key: VPMOVWBZrrk: [ 0.00 0.00 ] +Key: VPMOVWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDYrm: [ 0.00 0.00 ] +Key: VPMOVZXBDYrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZ: [ 0.00 0.00 ] +Key: VPMOVZXBDZrm: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBDZrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDrm: [ 0.00 0.00 ] +Key: VPMOVZXBDrr: [ 0.00 0.00 ] +Key: VPMOVZXBQYrm: [ 0.00 0.00 ] +Key: VPMOVZXBQYrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZ: [ 0.00 0.00 ] +Key: VPMOVZXBQZrm: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBQZrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBQrm: [ 0.00 0.00 ] +Key: VPMOVZXBQrr: [ 0.00 0.00 ] +Key: VPMOVZXBWYrm: [ 0.00 0.00 ] +Key: VPMOVZXBWYrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZ: [ 0.00 0.00 ] +Key: VPMOVZXBWZrm: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBWZrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBWrm: [ 0.00 0.00 ] +Key: VPMOVZXBWrr: [ 0.00 0.00 ] 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VPMOVZXWQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXWQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXWQrm: [ 0.00 0.00 ] +Key: VPMOVZXWQrr: [ 0.00 0.00 ] +Key: VPMULDQYrm: [ 0.00 0.00 ] +Key: VPMULDQYrr: [ 0.00 0.00 ] +Key: VPMULDQZ: [ 0.00 0.00 ] +Key: VPMULDQZrm: [ 0.00 0.00 ] +Key: VPMULDQZrmb: [ 0.00 0.00 ] +Key: VPMULDQZrmbk: [ 0.00 0.00 ] +Key: VPMULDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULDQZrmk: [ 0.00 0.00 ] +Key: VPMULDQZrmkz: [ 0.00 0.00 ] +Key: VPMULDQZrr: [ 0.00 0.00 ] +Key: VPMULDQZrrk: [ 0.00 0.00 ] +Key: VPMULDQZrrkz: [ 0.00 0.00 ] +Key: VPMULDQrm: [ 0.00 0.00 ] +Key: VPMULDQrr: [ 0.00 0.00 ] +Key: VPMULHRSWYrm: [ 0.00 0.00 ] +Key: VPMULHRSWYrr: [ 0.00 0.00 ] +Key: VPMULHRSWZ: [ 0.00 0.00 ] +Key: VPMULHRSWZrm: [ 0.00 0.00 ] +Key: VPMULHRSWZrmk: [ 0.00 0.00 ] +Key: VPMULHRSWZrmkz: [ 0.00 0.00 ] +Key: VPMULHRSWZrr: [ 0.00 0.00 ] +Key: VPMULHRSWZrrk: [ 0.00 0.00 ] +Key: VPMULHRSWZrrkz: [ 0.00 0.00 ] +Key: VPMULHRSWrm: [ 0.00 0.00 ] +Key: VPMULHRSWrr: [ 0.00 0.00 ] +Key: VPMULHUWYrm: [ 0.00 0.00 ] +Key: VPMULHUWYrr: [ 0.00 0.00 ] +Key: VPMULHUWZ: [ 0.00 0.00 ] +Key: VPMULHUWZrm: [ 0.00 0.00 ] +Key: VPMULHUWZrmk: [ 0.00 0.00 ] +Key: VPMULHUWZrmkz: [ 0.00 0.00 ] +Key: VPMULHUWZrr: [ 0.00 0.00 ] +Key: VPMULHUWZrrk: [ 0.00 0.00 ] +Key: VPMULHUWZrrkz: [ 0.00 0.00 ] +Key: VPMULHUWrm: [ 0.00 0.00 ] +Key: VPMULHUWrr: [ 0.00 0.00 ] +Key: VPMULHWYrm: [ 0.00 0.00 ] +Key: VPMULHWYrr: [ 0.00 0.00 ] +Key: VPMULHWZ: [ 0.00 0.00 ] +Key: VPMULHWZrm: [ 0.00 0.00 ] +Key: VPMULHWZrmk: [ 0.00 0.00 ] +Key: VPMULHWZrmkz: [ 0.00 0.00 ] +Key: VPMULHWZrr: [ 0.00 0.00 ] +Key: VPMULHWZrrk: [ 0.00 0.00 ] +Key: VPMULHWZrrkz: [ 0.00 0.00 ] +Key: VPMULHWrm: [ 0.00 0.00 ] +Key: VPMULHWrr: [ 0.00 0.00 ] +Key: VPMULLDYrm: [ 0.00 0.00 ] +Key: VPMULLDYrr: [ 0.00 0.00 ] +Key: VPMULLDZ: [ 0.00 0.00 ] +Key: VPMULLDZrm: [ 0.00 0.00 ] +Key: VPMULLDZrmb: [ 0.00 0.00 ] +Key: VPMULLDZrmbk: [ 0.00 0.00 ] +Key: VPMULLDZrmbkz: [ 0.00 0.00 ] +Key: VPMULLDZrmk: [ 0.00 0.00 ] +Key: VPMULLDZrmkz: [ 0.00 0.00 ] +Key: VPMULLDZrr: [ 0.00 0.00 ] +Key: VPMULLDZrrk: [ 0.00 0.00 ] +Key: VPMULLDZrrkz: [ 0.00 0.00 ] +Key: VPMULLDrm: [ 0.00 0.00 ] +Key: VPMULLDrr: [ 0.00 0.00 ] +Key: VPMULLQZ: [ 0.00 0.00 ] +Key: VPMULLQZrm: [ 0.00 0.00 ] +Key: VPMULLQZrmb: [ 0.00 0.00 ] +Key: VPMULLQZrmbk: [ 0.00 0.00 ] +Key: VPMULLQZrmbkz: [ 0.00 0.00 ] +Key: VPMULLQZrmk: [ 0.00 0.00 ] +Key: VPMULLQZrmkz: [ 0.00 0.00 ] +Key: VPMULLQZrr: [ 0.00 0.00 ] +Key: VPMULLQZrrk: [ 0.00 0.00 ] +Key: VPMULLQZrrkz: [ 0.00 0.00 ] +Key: VPMULLWYrm: [ 0.00 0.00 ] +Key: VPMULLWYrr: [ 0.00 0.00 ] +Key: VPMULLWZ: [ 0.00 0.00 ] +Key: VPMULLWZrm: [ 0.00 0.00 ] +Key: VPMULLWZrmk: [ 0.00 0.00 ] +Key: VPMULLWZrmkz: [ 0.00 0.00 ] +Key: VPMULLWZrr: [ 0.00 0.00 ] +Key: VPMULLWZrrk: [ 0.00 0.00 ] +Key: VPMULLWZrrkz: [ 0.00 0.00 ] +Key: VPMULLWrm: [ 0.00 0.00 ] +Key: VPMULLWrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZ: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrm: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmb: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQYrm: [ 0.00 0.00 ] +Key: VPMULUDQYrr: [ 0.00 0.00 ] +Key: VPMULUDQZ: [ 0.00 0.00 ] +Key: VPMULUDQZrm: [ 0.00 0.00 ] +Key: VPMULUDQZrmb: [ 0.00 0.00 ] +Key: VPMULUDQZrmbk: [ 0.00 0.00 ] +Key: VPMULUDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULUDQZrmk: [ 0.00 0.00 ] +Key: VPMULUDQZrmkz: [ 0.00 0.00 ] +Key: VPMULUDQZrr: [ 0.00 0.00 ] +Key: VPMULUDQZrrk: [ 0.00 0.00 ] +Key: VPMULUDQZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQrm: [ 0.00 0.00 ] +Key: VPMULUDQrr: [ 0.00 0.00 ] +Key: VPOPCNTBZ: [ 0.00 0.00 ] +Key: VPOPCNTBZrm: [ 0.00 0.00 ] +Key: VPOPCNTBZrmk: [ 0.00 0.00 ] +Key: VPOPCNTBZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTBZrr: [ 0.00 0.00 ] +Key: VPOPCNTBZrrk: [ 0.00 0.00 ] +Key: VPOPCNTBZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTDZ: [ 0.00 0.00 ] +Key: VPOPCNTDZrm: [ 0.00 0.00 ] +Key: VPOPCNTDZrmb: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrmk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrr: [ 0.00 0.00 ] +Key: VPOPCNTDZrrk: [ 0.00 0.00 ] +Key: VPOPCNTDZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTQZ: [ 0.00 0.00 ] +Key: VPOPCNTQZrm: [ 0.00 0.00 ] +Key: VPOPCNTQZrmb: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrmk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrr: [ 0.00 0.00 ] +Key: VPOPCNTQZrrk: [ 0.00 0.00 ] +Key: VPOPCNTQZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTWZ: [ 0.00 0.00 ] +Key: VPOPCNTWZrm: [ 0.00 0.00 ] +Key: VPOPCNTWZrmk: [ 0.00 0.00 ] +Key: VPOPCNTWZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTWZrr: [ 0.00 0.00 ] +Key: VPOPCNTWZrrk: [ 0.00 0.00 ] +Key: VPOPCNTWZrrkz: [ 0.00 0.00 ] +Key: VPORDZ: [ 0.00 0.00 ] +Key: VPORDZrm: [ 0.00 0.00 ] +Key: VPORDZrmb: [ 0.00 0.00 ] +Key: VPORDZrmbk: [ 0.00 0.00 ] +Key: VPORDZrmbkz: [ 0.00 0.00 ] +Key: VPORDZrmk: [ 0.00 0.00 ] +Key: VPORDZrmkz: [ 0.00 0.00 ] +Key: VPORDZrr: [ 0.00 0.00 ] +Key: VPORDZrrk: [ 0.00 0.00 ] +Key: VPORDZrrkz: [ 0.00 0.00 ] +Key: VPORQZ: [ 0.00 0.00 ] +Key: VPORQZrm: [ 0.00 0.00 ] +Key: VPORQZrmb: [ 0.00 0.00 ] +Key: VPORQZrmbk: [ 0.00 0.00 ] +Key: VPORQZrmbkz: [ 0.00 0.00 ] +Key: VPORQZrmk: [ 0.00 0.00 ] +Key: VPORQZrmkz: [ 0.00 0.00 ] +Key: VPORQZrr: [ 0.00 0.00 ] +Key: VPORQZrrk: [ 0.00 0.00 ] +Key: VPORQZrrkz: [ 0.00 0.00 ] +Key: VPORYrm: [ 0.00 0.00 ] +Key: VPORYrr: [ 0.00 0.00 ] +Key: VPORrm: [ 0.00 0.00 ] +Key: VPORrr: [ 0.00 0.00 ] +Key: VPPERMrmr: [ 0.00 0.00 ] +Key: VPPERMrrm: [ 0.00 0.00 ] +Key: VPPERMrrr: [ 0.00 0.00 ] +Key: VPPERMrrr_REV: [ 0.00 0.00 ] +Key: VPROLDZ: [ 0.00 0.00 ] +Key: VPROLDZmbi: [ 0.00 0.00 ] +Key: VPROLDZmbik: [ 0.00 0.00 ] +Key: VPROLDZmbikz: [ 0.00 0.00 ] +Key: VPROLDZmi: [ 0.00 0.00 ] +Key: VPROLDZmik: [ 0.00 0.00 ] +Key: VPROLDZmikz: [ 0.00 0.00 ] +Key: VPROLDZri: [ 0.00 0.00 ] +Key: VPROLDZrik: [ 0.00 0.00 ] +Key: VPROLDZrikz: [ 0.00 0.00 ] +Key: VPROLQZ: [ 0.00 0.00 ] +Key: VPROLQZmbi: [ 0.00 0.00 ] +Key: VPROLQZmbik: [ 0.00 0.00 ] +Key: VPROLQZmbikz: [ 0.00 0.00 ] +Key: VPROLQZmi: [ 0.00 0.00 ] +Key: VPROLQZmik: [ 0.00 0.00 ] +Key: VPROLQZmikz: [ 0.00 0.00 ] +Key: VPROLQZri: [ 0.00 0.00 ] +Key: VPROLQZrik: [ 0.00 0.00 ] +Key: VPROLQZrikz: [ 0.00 0.00 ] +Key: VPROLVDZ: [ 0.00 0.00 ] +Key: VPROLVDZrm: [ 0.00 0.00 ] +Key: VPROLVDZrmb: [ 0.00 0.00 ] +Key: VPROLVDZrmbk: [ 0.00 0.00 ] +Key: VPROLVDZrmbkz: [ 0.00 0.00 ] +Key: VPROLVDZrmk: [ 0.00 0.00 ] +Key: VPROLVDZrmkz: [ 0.00 0.00 ] +Key: VPROLVDZrr: [ 0.00 0.00 ] +Key: VPROLVDZrrk: [ 0.00 0.00 ] +Key: VPROLVDZrrkz: [ 0.00 0.00 ] +Key: VPROLVQZ: [ 0.00 0.00 ] +Key: VPROLVQZrm: [ 0.00 0.00 ] +Key: VPROLVQZrmb: [ 0.00 0.00 ] +Key: VPROLVQZrmbk: [ 0.00 0.00 ] +Key: VPROLVQZrmbkz: [ 0.00 0.00 ] +Key: VPROLVQZrmk: [ 0.00 0.00 ] +Key: VPROLVQZrmkz: [ 0.00 0.00 ] +Key: VPROLVQZrr: [ 0.00 0.00 ] +Key: VPROLVQZrrk: [ 0.00 0.00 ] +Key: VPROLVQZrrkz: [ 0.00 0.00 ] +Key: VPRORDZ: [ 0.00 0.00 ] +Key: VPRORDZmbi: [ 0.00 0.00 ] +Key: VPRORDZmbik: [ 0.00 0.00 ] +Key: VPRORDZmbikz: [ 0.00 0.00 ] +Key: VPRORDZmi: [ 0.00 0.00 ] +Key: VPRORDZmik: [ 0.00 0.00 ] +Key: VPRORDZmikz: [ 0.00 0.00 ] +Key: VPRORDZri: [ 0.00 0.00 ] +Key: VPRORDZrik: [ 0.00 0.00 ] +Key: VPRORDZrikz: [ 0.00 0.00 ] +Key: VPRORQZ: [ 0.00 0.00 ] +Key: VPRORQZmbi: [ 0.00 0.00 ] +Key: VPRORQZmbik: [ 0.00 0.00 ] +Key: VPRORQZmbikz: [ 0.00 0.00 ] +Key: VPRORQZmi: [ 0.00 0.00 ] +Key: VPRORQZmik: [ 0.00 0.00 ] +Key: VPRORQZmikz: [ 0.00 0.00 ] +Key: VPRORQZri: [ 0.00 0.00 ] +Key: VPRORQZrik: [ 0.00 0.00 ] +Key: VPRORQZrikz: [ 0.00 0.00 ] +Key: VPRORVDZ: [ 0.00 0.00 ] +Key: VPRORVDZrm: [ 0.00 0.00 ] +Key: VPRORVDZrmb: [ 0.00 0.00 ] +Key: VPRORVDZrmbk: [ 0.00 0.00 ] +Key: VPRORVDZrmbkz: [ 0.00 0.00 ] +Key: VPRORVDZrmk: [ 0.00 0.00 ] +Key: VPRORVDZrmkz: [ 0.00 0.00 ] +Key: VPRORVDZrr: [ 0.00 0.00 ] +Key: VPRORVDZrrk: [ 0.00 0.00 ] +Key: VPRORVDZrrkz: [ 0.00 0.00 ] +Key: VPRORVQZ: [ 0.00 0.00 ] +Key: VPRORVQZrm: [ 0.00 0.00 ] +Key: VPRORVQZrmb: [ 0.00 0.00 ] +Key: VPRORVQZrmbk: [ 0.00 0.00 ] +Key: VPRORVQZrmbkz: [ 0.00 0.00 ] +Key: VPRORVQZrmk: [ 0.00 0.00 ] +Key: VPRORVQZrmkz: [ 0.00 0.00 ] +Key: VPRORVQZrr: [ 0.00 0.00 ] +Key: VPRORVQZrrk: [ 0.00 0.00 ] +Key: VPRORVQZrrkz: [ 0.00 0.00 ] +Key: VPROTBmi: [ 0.00 0.00 ] +Key: VPROTBmr: [ 0.00 0.00 ] +Key: VPROTBri: [ 0.00 0.00 ] +Key: VPROTBrm: [ 0.00 0.00 ] +Key: VPROTBrr: [ 0.00 0.00 ] +Key: VPROTBrr_REV: [ 0.00 0.00 ] +Key: VPROTDmi: [ 0.00 0.00 ] +Key: VPROTDmr: [ 0.00 0.00 ] +Key: VPROTDri: [ 0.00 0.00 ] +Key: VPROTDrm: [ 0.00 0.00 ] +Key: VPROTDrr: [ 0.00 0.00 ] +Key: VPROTDrr_REV: [ 0.00 0.00 ] +Key: VPROTQmi: [ 0.00 0.00 ] +Key: VPROTQmr: [ 0.00 0.00 ] +Key: VPROTQri: [ 0.00 0.00 ] +Key: VPROTQrm: [ 0.00 0.00 ] +Key: VPROTQrr: [ 0.00 0.00 ] +Key: VPROTQrr_REV: [ 0.00 0.00 ] +Key: VPROTWmi: [ 0.00 0.00 ] +Key: VPROTWmr: [ 0.00 0.00 ] +Key: VPROTWri: [ 0.00 0.00 ] +Key: VPROTWrm: [ 0.00 0.00 ] +Key: VPROTWrr: [ 0.00 0.00 ] +Key: VPROTWrr_REV: [ 0.00 0.00 ] +Key: VPSADBWYrm: [ 0.00 0.00 ] +Key: VPSADBWYrr: [ 0.00 0.00 ] +Key: VPSADBWZ: [ 0.00 0.00 ] +Key: VPSADBWZrm: [ 0.00 0.00 ] +Key: VPSADBWZrr: [ 0.00 0.00 ] +Key: VPSADBWrm: [ 0.00 0.00 ] +Key: VPSADBWrr: [ 0.00 0.00 ] +Key: VPSCATTERDDZ: [ 0.00 0.00 ] +Key: VPSCATTERDDZmr: [ 0.00 0.00 ] +Key: VPSCATTERDQZ: [ 0.00 0.00 ] +Key: VPSCATTERDQZmr: [ 0.00 0.00 ] +Key: VPSCATTERQDZ: [ 0.00 0.00 ] +Key: VPSCATTERQDZmr: [ 0.00 0.00 ] +Key: VPSCATTERQQZ: [ 0.00 0.00 ] +Key: VPSCATTERQQZmr: [ 0.00 0.00 ] +Key: VPSHABmr: [ 0.00 0.00 ] +Key: VPSHABrm: [ 0.00 0.00 ] +Key: VPSHABrr: [ 0.00 0.00 ] +Key: VPSHABrr_REV: [ 0.00 0.00 ] +Key: VPSHADmr: [ 0.00 0.00 ] +Key: VPSHADrm: [ 0.00 0.00 ] +Key: VPSHADrr: [ 0.00 0.00 ] +Key: VPSHADrr_REV: [ 0.00 0.00 ] +Key: VPSHAQmr: [ 0.00 0.00 ] +Key: VPSHAQrm: [ 0.00 0.00 ] +Key: VPSHAQrr: [ 0.00 0.00 ] +Key: VPSHAQrr_REV: [ 0.00 0.00 ] +Key: VPSHAWmr: [ 0.00 0.00 ] +Key: VPSHAWrm: [ 0.00 0.00 ] +Key: VPSHAWrr: [ 0.00 0.00 ] +Key: VPSHAWrr_REV: [ 0.00 0.00 ] +Key: VPSHLBmr: [ 0.00 0.00 ] +Key: VPSHLBrm: [ 0.00 0.00 ] +Key: VPSHLBrr: [ 0.00 0.00 ] +Key: VPSHLBrr_REV: [ 0.00 0.00 ] +Key: VPSHLDDZ: [ 0.00 0.00 ] +Key: VPSHLDDZrmbi: [ 0.00 0.00 ] +Key: VPSHLDDZrmbik: [ 0.00 0.00 ] +Key: VPSHLDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDDZrmi: [ 0.00 0.00 ] +Key: VPSHLDDZrmik: [ 0.00 0.00 ] +Key: VPSHLDDZrmikz: [ 0.00 0.00 ] +Key: VPSHLDDZrri: [ 0.00 0.00 ] +Key: VPSHLDDZrrik: [ 0.00 0.00 ] +Key: VPSHLDDZrrikz: [ 0.00 0.00 ] +Key: VPSHLDQZ: [ 0.00 0.00 ] +Key: VPSHLDQZrmbi: [ 0.00 0.00 ] +Key: VPSHLDQZrmbik: [ 0.00 0.00 ] +Key: VPSHLDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDQZrmi: [ 0.00 0.00 ] +Key: VPSHLDQZrmik: [ 0.00 0.00 ] +Key: VPSHLDQZrmikz: [ 0.00 0.00 ] +Key: VPSHLDQZrri: [ 0.00 0.00 ] +Key: VPSHLDQZrrik: [ 0.00 0.00 ] +Key: VPSHLDQZrrikz: [ 0.00 0.00 ] +Key: VPSHLDVDZ: [ 0.00 0.00 ] +Key: VPSHLDVDZm: [ 0.00 0.00 ] +Key: VPSHLDVDZmb: [ 0.00 0.00 ] +Key: VPSHLDVDZmbk: [ 0.00 0.00 ] +Key: VPSHLDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVDZmk: [ 0.00 0.00 ] +Key: VPSHLDVDZmkz: [ 0.00 0.00 ] +Key: VPSHLDVDZr: [ 0.00 0.00 ] +Key: VPSHLDVDZrk: [ 0.00 0.00 ] +Key: VPSHLDVDZrkz: [ 0.00 0.00 ] +Key: VPSHLDVQZ: [ 0.00 0.00 ] +Key: VPSHLDVQZm: [ 0.00 0.00 ] +Key: VPSHLDVQZmb: [ 0.00 0.00 ] +Key: VPSHLDVQZmbk: [ 0.00 0.00 ] +Key: VPSHLDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVQZmk: [ 0.00 0.00 ] +Key: VPSHLDVQZmkz: [ 0.00 0.00 ] +Key: VPSHLDVQZr: [ 0.00 0.00 ] +Key: VPSHLDVQZrk: [ 0.00 0.00 ] +Key: VPSHLDVQZrkz: [ 0.00 0.00 ] +Key: VPSHLDVWZ: [ 0.00 0.00 ] +Key: VPSHLDVWZm: [ 0.00 0.00 ] +Key: VPSHLDVWZmk: [ 0.00 0.00 ] +Key: VPSHLDVWZmkz: [ 0.00 0.00 ] +Key: VPSHLDVWZr: [ 0.00 0.00 ] +Key: VPSHLDVWZrk: [ 0.00 0.00 ] +Key: VPSHLDVWZrkz: [ 0.00 0.00 ] +Key: VPSHLDWZ: [ 0.00 0.00 ] +Key: VPSHLDWZrmi: [ 0.00 0.00 ] +Key: VPSHLDWZrmik: [ 0.00 0.00 ] +Key: VPSHLDWZrmikz: [ 0.00 0.00 ] +Key: VPSHLDWZrri: [ 0.00 0.00 ] +Key: VPSHLDWZrrik: [ 0.00 0.00 ] +Key: VPSHLDWZrrikz: [ 0.00 0.00 ] +Key: VPSHLDmr: [ 0.00 0.00 ] +Key: VPSHLDrm: [ 0.00 0.00 ] +Key: VPSHLDrr: [ 0.00 0.00 ] +Key: VPSHLDrr_REV: [ 0.00 0.00 ] +Key: VPSHLQmr: [ 0.00 0.00 ] +Key: VPSHLQrm: [ 0.00 0.00 ] +Key: VPSHLQrr: [ 0.00 0.00 ] +Key: VPSHLQrr_REV: [ 0.00 0.00 ] +Key: VPSHLWmr: [ 0.00 0.00 ] +Key: VPSHLWrm: [ 0.00 0.00 ] +Key: VPSHLWrr: [ 0.00 0.00 ] +Key: VPSHLWrr_REV: [ 0.00 0.00 ] +Key: VPSHRDDZ: [ 0.00 0.00 ] +Key: VPSHRDDZrmbi: [ 0.00 0.00 ] +Key: VPSHRDDZrmbik: [ 0.00 0.00 ] +Key: VPSHRDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDDZrmi: [ 0.00 0.00 ] +Key: VPSHRDDZrmik: [ 0.00 0.00 ] +Key: VPSHRDDZrmikz: [ 0.00 0.00 ] +Key: VPSHRDDZrri: [ 0.00 0.00 ] +Key: VPSHRDDZrrik: [ 0.00 0.00 ] +Key: VPSHRDDZrrikz: [ 0.00 0.00 ] +Key: VPSHRDQZ: [ 0.00 0.00 ] +Key: VPSHRDQZrmbi: [ 0.00 0.00 ] +Key: VPSHRDQZrmbik: [ 0.00 0.00 ] +Key: VPSHRDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDQZrmi: [ 0.00 0.00 ] +Key: VPSHRDQZrmik: [ 0.00 0.00 ] +Key: VPSHRDQZrmikz: [ 0.00 0.00 ] +Key: VPSHRDQZrri: [ 0.00 0.00 ] +Key: VPSHRDQZrrik: [ 0.00 0.00 ] +Key: VPSHRDQZrrikz: [ 0.00 0.00 ] +Key: VPSHRDVDZ: [ 0.00 0.00 ] +Key: VPSHRDVDZm: [ 0.00 0.00 ] +Key: VPSHRDVDZmb: [ 0.00 0.00 ] +Key: VPSHRDVDZmbk: [ 0.00 0.00 ] +Key: VPSHRDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVDZmk: [ 0.00 0.00 ] +Key: VPSHRDVDZmkz: [ 0.00 0.00 ] +Key: VPSHRDVDZr: [ 0.00 0.00 ] +Key: VPSHRDVDZrk: [ 0.00 0.00 ] +Key: VPSHRDVDZrkz: [ 0.00 0.00 ] +Key: VPSHRDVQZ: [ 0.00 0.00 ] +Key: VPSHRDVQZm: [ 0.00 0.00 ] +Key: VPSHRDVQZmb: [ 0.00 0.00 ] +Key: VPSHRDVQZmbk: [ 0.00 0.00 ] +Key: VPSHRDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVQZmk: [ 0.00 0.00 ] +Key: VPSHRDVQZmkz: [ 0.00 0.00 ] +Key: VPSHRDVQZr: [ 0.00 0.00 ] +Key: VPSHRDVQZrk: [ 0.00 0.00 ] +Key: VPSHRDVQZrkz: [ 0.00 0.00 ] +Key: VPSHRDVWZ: [ 0.00 0.00 ] +Key: VPSHRDVWZm: [ 0.00 0.00 ] +Key: VPSHRDVWZmk: [ 0.00 0.00 ] +Key: VPSHRDVWZmkz: [ 0.00 0.00 ] +Key: VPSHRDVWZr: [ 0.00 0.00 ] +Key: VPSHRDVWZrk: [ 0.00 0.00 ] +Key: VPSHRDVWZrkz: [ 0.00 0.00 ] +Key: VPSHRDWZ: [ 0.00 0.00 ] +Key: VPSHRDWZrmi: [ 0.00 0.00 ] +Key: VPSHRDWZrmik: [ 0.00 0.00 ] +Key: VPSHRDWZrmikz: [ 0.00 0.00 ] +Key: VPSHRDWZrri: [ 0.00 0.00 ] +Key: VPSHRDWZrrik: [ 0.00 0.00 ] +Key: VPSHRDWZrrikz: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZ: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrm: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrr: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBYrm: [ 0.00 0.00 ] +Key: VPSHUFBYrr: [ 0.00 0.00 ] +Key: VPSHUFBZ: [ 0.00 0.00 ] +Key: VPSHUFBZrm: [ 0.00 0.00 ] +Key: VPSHUFBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBZrmkz: [ 0.00 0.00 ] +Key: VPSHUFBZrr: [ 0.00 0.00 ] +Key: VPSHUFBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBZrrkz: [ 0.00 0.00 ] +Key: VPSHUFBrm: [ 0.00 0.00 ] +Key: VPSHUFBrr: [ 0.00 0.00 ] +Key: VPSHUFDYmi: [ 0.00 0.00 ] +Key: VPSHUFDYri: [ 0.00 0.00 ] +Key: VPSHUFDZ: [ 0.00 0.00 ] +Key: VPSHUFDZmbi: [ 0.00 0.00 ] +Key: VPSHUFDZmbik: [ 0.00 0.00 ] +Key: VPSHUFDZmbikz: [ 0.00 0.00 ] +Key: VPSHUFDZmi: [ 0.00 0.00 ] +Key: VPSHUFDZmik: [ 0.00 0.00 ] +Key: VPSHUFDZmikz: [ 0.00 0.00 ] +Key: VPSHUFDZri: [ 0.00 0.00 ] +Key: VPSHUFDZrik: [ 0.00 0.00 ] +Key: VPSHUFDZrikz: [ 0.00 0.00 ] +Key: VPSHUFDmi: [ 0.00 0.00 ] +Key: VPSHUFDri: [ 0.00 0.00 ] +Key: VPSHUFHWYmi: [ 0.00 0.00 ] +Key: VPSHUFHWYri: [ 0.00 0.00 ] +Key: VPSHUFHWZ: [ 0.00 0.00 ] +Key: VPSHUFHWZmi: [ 0.00 0.00 ] +Key: VPSHUFHWZmik: [ 0.00 0.00 ] +Key: VPSHUFHWZmikz: [ 0.00 0.00 ] +Key: VPSHUFHWZri: [ 0.00 0.00 ] +Key: VPSHUFHWZrik: [ 0.00 0.00 ] +Key: VPSHUFHWZrikz: [ 0.00 0.00 ] +Key: VPSHUFHWmi: [ 0.00 0.00 ] +Key: VPSHUFHWri: [ 0.00 0.00 ] +Key: VPSHUFLWYmi: [ 0.00 0.00 ] +Key: VPSHUFLWYri: [ 0.00 0.00 ] +Key: VPSHUFLWZ: [ 0.00 0.00 ] +Key: VPSHUFLWZmi: [ 0.00 0.00 ] +Key: VPSHUFLWZmik: [ 0.00 0.00 ] +Key: VPSHUFLWZmikz: [ 0.00 0.00 ] +Key: VPSHUFLWZri: [ 0.00 0.00 ] +Key: VPSHUFLWZrik: [ 0.00 0.00 ] +Key: VPSHUFLWZrikz: [ 0.00 0.00 ] +Key: VPSHUFLWmi: [ 0.00 0.00 ] +Key: VPSHUFLWri: [ 0.00 0.00 ] +Key: VPSIGNBYrm: [ 0.00 0.00 ] +Key: VPSIGNBYrr: [ 0.00 0.00 ] +Key: VPSIGNBrm: [ 0.00 0.00 ] +Key: VPSIGNBrr: [ 0.00 0.00 ] +Key: VPSIGNDYrm: [ 0.00 0.00 ] +Key: VPSIGNDYrr: [ 0.00 0.00 ] +Key: VPSIGNDrm: [ 0.00 0.00 ] +Key: VPSIGNDrr: [ 0.00 0.00 ] +Key: VPSIGNWYrm: [ 0.00 0.00 ] +Key: VPSIGNWYrr: [ 0.00 0.00 ] +Key: VPSIGNWrm: [ 0.00 0.00 ] +Key: VPSIGNWrr: [ 0.00 0.00 ] +Key: VPSLLDQYri: [ 0.00 0.00 ] +Key: VPSLLDQZ: [ 0.00 0.00 ] +Key: VPSLLDQZmi: [ 0.00 0.00 ] +Key: VPSLLDQZri: [ 0.00 0.00 ] +Key: VPSLLDQri: [ 0.00 0.00 ] +Key: VPSLLDYri: [ 0.00 0.00 ] +Key: VPSLLDYrm: [ 0.00 0.00 ] +Key: VPSLLDYrr: [ 0.00 0.00 ] +Key: VPSLLDZ: [ 0.00 0.00 ] +Key: VPSLLDZmbi: [ 0.00 0.00 ] +Key: VPSLLDZmbik: [ 0.00 0.00 ] +Key: VPSLLDZmbikz: [ 0.00 0.00 ] +Key: VPSLLDZmi: [ 0.00 0.00 ] +Key: VPSLLDZmik: [ 0.00 0.00 ] +Key: VPSLLDZmikz: [ 0.00 0.00 ] +Key: VPSLLDZri: [ 0.00 0.00 ] +Key: VPSLLDZrik: [ 0.00 0.00 ] +Key: VPSLLDZrikz: [ 0.00 0.00 ] +Key: VPSLLDZrm: [ 0.00 0.00 ] +Key: VPSLLDZrmk: [ 0.00 0.00 ] +Key: VPSLLDZrmkz: [ 0.00 0.00 ] +Key: VPSLLDZrr: [ 0.00 0.00 ] +Key: VPSLLDZrrk: [ 0.00 0.00 ] +Key: VPSLLDZrrkz: [ 0.00 0.00 ] +Key: VPSLLDri: [ 0.00 0.00 ] +Key: VPSLLDrm: [ 0.00 0.00 ] +Key: VPSLLDrr: [ 0.00 0.00 ] +Key: VPSLLQYri: [ 0.00 0.00 ] +Key: VPSLLQYrm: [ 0.00 0.00 ] +Key: VPSLLQYrr: [ 0.00 0.00 ] +Key: VPSLLQZ: [ 0.00 0.00 ] +Key: VPSLLQZmbi: [ 0.00 0.00 ] +Key: VPSLLQZmbik: [ 0.00 0.00 ] +Key: VPSLLQZmbikz: [ 0.00 0.00 ] +Key: VPSLLQZmi: [ 0.00 0.00 ] +Key: VPSLLQZmik: [ 0.00 0.00 ] +Key: VPSLLQZmikz: [ 0.00 0.00 ] +Key: VPSLLQZri: [ 0.00 0.00 ] +Key: VPSLLQZrik: [ 0.00 0.00 ] +Key: VPSLLQZrikz: [ 0.00 0.00 ] +Key: VPSLLQZrm: [ 0.00 0.00 ] +Key: VPSLLQZrmk: [ 0.00 0.00 ] +Key: VPSLLQZrmkz: [ 0.00 0.00 ] +Key: VPSLLQZrr: [ 0.00 0.00 ] +Key: VPSLLQZrrk: [ 0.00 0.00 ] +Key: VPSLLQZrrkz: [ 0.00 0.00 ] +Key: VPSLLQri: [ 0.00 0.00 ] +Key: VPSLLQrm: [ 0.00 0.00 ] +Key: VPSLLQrr: [ 0.00 0.00 ] +Key: VPSLLVDYrm: [ 0.00 0.00 ] +Key: VPSLLVDYrr: [ 0.00 0.00 ] +Key: VPSLLVDZ: [ 0.00 0.00 ] +Key: VPSLLVDZrm: [ 0.00 0.00 ] +Key: VPSLLVDZrmb: [ 0.00 0.00 ] +Key: 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VRANGESSZrribkz: [ 0.00 0.00 ] +Key: VRANGESSZrrik: [ 0.00 0.00 ] +Key: VRANGESSZrrikz: [ 0.00 0.00 ] +Key: VRCP: [ 0.00 0.00 ] +Key: VRCPBF: [ 0.00 0.00 ] +Key: VRCPPHZ: [ 0.00 0.00 ] +Key: VRCPPHZm: [ 0.00 0.00 ] +Key: VRCPPHZmb: [ 0.00 0.00 ] +Key: VRCPPHZmbk: [ 0.00 0.00 ] +Key: VRCPPHZmbkz: [ 0.00 0.00 ] +Key: VRCPPHZmk: [ 0.00 0.00 ] +Key: VRCPPHZmkz: [ 0.00 0.00 ] +Key: VRCPPHZr: [ 0.00 0.00 ] +Key: VRCPPHZrk: [ 0.00 0.00 ] +Key: VRCPPHZrkz: [ 0.00 0.00 ] +Key: VRCPPSYm: [ 0.00 0.00 ] +Key: VRCPPSYr: [ 0.00 0.00 ] +Key: VRCPPSm: [ 0.00 0.00 ] +Key: VRCPPSr: [ 0.00 0.00 ] +Key: VRCPSHZrm: [ 0.00 0.00 ] +Key: VRCPSHZrmk: [ 0.00 0.00 ] +Key: VRCPSHZrmkz: [ 0.00 0.00 ] +Key: VRCPSHZrr: [ 0.00 0.00 ] +Key: VRCPSHZrrk: [ 0.00 0.00 ] +Key: VRCPSHZrrkz: [ 0.00 0.00 ] +Key: VRCPSSm: [ 0.00 0.00 ] +Key: VRCPSSm_Int: [ 0.00 0.00 ] +Key: VRCPSSr: [ 0.00 0.00 ] +Key: VRCPSSr_Int: [ 0.00 0.00 ] +Key: VREDUCEBF: [ 0.00 0.00 ] +Key: VREDUCEPDZ: [ 0.00 0.00 ] +Key: VREDUCEPDZrmbi: [ 0.00 0.00 ] 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VSUBSDZrmkz_Int: [ 0.00 0.00 ] +Key: VSUBSDZrr: [ 0.00 0.00 ] +Key: VSUBSDZrr_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrb_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrbk_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrk_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrkz_Int: [ 0.00 0.00 ] +Key: VSUBSDrm: [ 0.00 0.00 ] +Key: VSUBSDrm_Int: [ 0.00 0.00 ] +Key: VSUBSDrr: [ 0.00 0.00 ] +Key: VSUBSDrr_Int: [ 0.00 0.00 ] +Key: VSUBSHZrm: [ 0.00 0.00 ] +Key: VSUBSHZrm_Int: [ 0.00 0.00 ] +Key: VSUBSHZrmk_Int: [ 0.00 0.00 ] +Key: VSUBSHZrmkz_Int: [ 0.00 0.00 ] +Key: VSUBSHZrr: [ 0.00 0.00 ] +Key: VSUBSHZrr_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrb_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrbk_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrk_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrkz_Int: [ 0.00 0.00 ] +Key: VSUBSSZrm: [ 0.00 0.00 ] +Key: VSUBSSZrm_Int: [ 0.00 0.00 ] +Key: VSUBSSZrmk_Int: [ 0.00 0.00 ] +Key: VSUBSSZrmkz_Int: [ 0.00 0.00 ] +Key: VSUBSSZrr: [ 0.00 0.00 ] +Key: VSUBSSZrr_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrb_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrbk_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrk_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrkz_Int: [ 0.00 0.00 ] +Key: VSUBSSrm: [ 0.00 0.00 ] +Key: VSUBSSrm_Int: [ 0.00 0.00 ] +Key: VSUBSSrr: [ 0.00 0.00 ] +Key: VSUBSSrr_Int: [ 0.00 0.00 ] +Key: VTESTPDYrm: [ 0.00 0.00 ] +Key: VTESTPDYrr: [ 0.00 0.00 ] +Key: VTESTPDrm: [ 0.00 0.00 ] +Key: VTESTPDrr: [ 0.00 0.00 ] +Key: VTESTPSYrm: [ 0.00 0.00 ] +Key: VTESTPSYrr: [ 0.00 0.00 ] +Key: VTESTPSrm: [ 0.00 0.00 ] +Key: VTESTPSrr: [ 0.00 0.00 ] +Key: VUCOMISDZrm: [ 0.00 0.00 ] +Key: VUCOMISDZrm_Int: [ 0.00 0.00 ] +Key: VUCOMISDZrr: [ 0.00 0.00 ] +Key: VUCOMISDZrr_Int: [ 0.00 0.00 ] +Key: VUCOMISDZrrb: [ 0.00 0.00 ] +Key: VUCOMISDrm: [ 0.00 0.00 ] +Key: VUCOMISDrm_Int: [ 0.00 0.00 ] +Key: VUCOMISDrr: [ 0.00 0.00 ] +Key: VUCOMISDrr_Int: [ 0.00 0.00 ] +Key: VUCOMISHZrm: [ 0.00 0.00 ] +Key: VUCOMISHZrm_Int: [ 0.00 0.00 ] +Key: VUCOMISHZrr: [ 0.00 0.00 ] +Key: VUCOMISHZrr_Int: [ 0.00 0.00 ] +Key: VUCOMISHZrrb: [ 0.00 0.00 ] +Key: VUCOMISSZrm: [ 0.00 0.00 ] +Key: VUCOMISSZrm_Int: [ 0.00 0.00 ] +Key: VUCOMISSZrr: [ 0.00 0.00 ] +Key: VUCOMISSZrr_Int: [ 0.00 0.00 ] +Key: VUCOMISSZrrb: [ 0.00 0.00 ] +Key: VUCOMISSrm: [ 0.00 0.00 ] +Key: VUCOMISSrm_Int: [ 0.00 0.00 ] +Key: VUCOMISSrr: [ 0.00 0.00 ] +Key: VUCOMISSrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSDZrm: [ 0.00 0.00 ] +Key: VUCOMXSDZrm_Int: [ 0.00 0.00 ] +Key: VUCOMXSDZrr: [ 0.00 0.00 ] +Key: VUCOMXSDZrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSDZrrb_Int: [ 0.00 0.00 ] +Key: VUCOMXSHZrm: [ 0.00 0.00 ] +Key: VUCOMXSHZrm_Int: [ 0.00 0.00 ] +Key: VUCOMXSHZrr: [ 0.00 0.00 ] +Key: VUCOMXSHZrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSHZrrb_Int: [ 0.00 0.00 ] +Key: VUCOMXSSZrm: [ 0.00 0.00 ] +Key: VUCOMXSSZrm_Int: [ 0.00 0.00 ] +Key: VUCOMXSSZrr: [ 0.00 0.00 ] +Key: VUCOMXSSZrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSSZrrb_Int: [ 0.00 0.00 ] +Key: VUNPCKHPDYrm: [ 0.00 0.00 ] +Key: VUNPCKHPDYrr: [ 0.00 0.00 ] +Key: VUNPCKHPDZ: [ 0.00 0.00 ] +Key: VUNPCKHPDZrm: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmb: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmbk: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmk: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmkz: [ 0.00 0.00 ] +Key: VUNPCKHPDZrr: [ 0.00 0.00 ] +Key: VUNPCKHPDZrrk: [ 0.00 0.00 ] +Key: VUNPCKHPDZrrkz: [ 0.00 0.00 ] +Key: VUNPCKHPDrm: [ 0.00 0.00 ] +Key: VUNPCKHPDrr: [ 0.00 0.00 ] +Key: VUNPCKHPSYrm: [ 0.00 0.00 ] +Key: VUNPCKHPSYrr: [ 0.00 0.00 ] +Key: VUNPCKHPSZ: [ 0.00 0.00 ] +Key: VUNPCKHPSZrm: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmb: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmbk: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmk: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmkz: [ 0.00 0.00 ] +Key: VUNPCKHPSZrr: [ 0.00 0.00 ] +Key: VUNPCKHPSZrrk: [ 0.00 0.00 ] +Key: VUNPCKHPSZrrkz: [ 0.00 0.00 ] +Key: VUNPCKHPSrm: [ 0.00 0.00 ] +Key: VUNPCKHPSrr: [ 0.00 0.00 ] +Key: VUNPCKLPDYrm: [ 0.00 0.00 ] +Key: VUNPCKLPDYrr: [ 0.00 0.00 ] +Key: VUNPCKLPDZ: [ 0.00 0.00 ] +Key: VUNPCKLPDZrm: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmb: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmbk: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmk: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmkz: [ 0.00 0.00 ] +Key: VUNPCKLPDZrr: [ 0.00 0.00 ] +Key: VUNPCKLPDZrrk: [ 0.00 0.00 ] +Key: VUNPCKLPDZrrkz: [ 0.00 0.00 ] +Key: VUNPCKLPDrm: [ 0.00 0.00 ] +Key: VUNPCKLPDrr: [ 0.00 0.00 ] +Key: VUNPCKLPSYrm: [ 0.00 0.00 ] +Key: VUNPCKLPSYrr: [ 0.00 0.00 ] +Key: VUNPCKLPSZ: [ 0.00 0.00 ] +Key: VUNPCKLPSZrm: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmb: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmbk: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmk: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmkz: [ 0.00 0.00 ] +Key: VUNPCKLPSZrr: [ 0.00 0.00 ] +Key: VUNPCKLPSZrrk: [ 0.00 0.00 ] +Key: VUNPCKLPSZrrkz: [ 0.00 0.00 ] +Key: VUNPCKLPSrm: [ 0.00 0.00 ] +Key: VUNPCKLPSrr: [ 0.00 0.00 ] +Key: VXORPDYrm: [ 0.00 0.00 ] +Key: VXORPDYrr: [ 0.00 0.00 ] +Key: VXORPDZ: [ 0.00 0.00 ] +Key: VXORPDZrm: [ 0.00 0.00 ] +Key: VXORPDZrmb: [ 0.00 0.00 ] +Key: VXORPDZrmbk: [ 0.00 0.00 ] +Key: VXORPDZrmbkz: [ 0.00 0.00 ] +Key: VXORPDZrmk: [ 0.00 0.00 ] +Key: VXORPDZrmkz: [ 0.00 0.00 ] +Key: VXORPDZrr: [ 0.00 0.00 ] +Key: VXORPDZrrk: [ 0.00 0.00 ] +Key: VXORPDZrrkz: [ 0.00 0.00 ] +Key: VXORPDrm: [ 0.00 0.00 ] +Key: VXORPDrr: [ 0.00 0.00 ] +Key: VXORPSYrm: [ 0.00 0.00 ] +Key: VXORPSYrr: [ 0.00 0.00 ] +Key: VXORPSZ: [ 0.00 0.00 ] +Key: VXORPSZrm: [ 0.00 0.00 ] +Key: VXORPSZrmb: [ 0.00 0.00 ] +Key: VXORPSZrmbk: [ 0.00 0.00 ] +Key: VXORPSZrmbkz: [ 0.00 0.00 ] +Key: VXORPSZrmk: [ 0.00 0.00 ] +Key: VXORPSZrmkz: [ 0.00 0.00 ] +Key: VXORPSZrr: [ 0.00 0.00 ] +Key: VXORPSZrrk: [ 0.00 0.00 ] +Key: VXORPSZrrkz: [ 0.00 0.00 ] +Key: VXORPSrm: [ 0.00 0.00 ] +Key: VXORPSrr: [ 0.00 0.00 ] +Key: VZEROALL: [ 0.00 0.00 ] +Key: VZEROUPPER: [ 0.00 0.00 ] +Key: V_SET: [ 0.00 0.00 ] +Key: V_SETALLONES: [ 0.00 0.00 ] +Key: WAIT: [ 0.00 0.00 ] +Key: WBINVD: [ 0.00 0.00 ] +Key: WBNOINVD: [ 0.00 0.00 ] +Key: WRFLAGS: [ 0.00 0.00 ] +Key: WRFSBASE: [ 0.00 0.00 ] +Key: WRGSBASE: [ 0.00 0.00 ] +Key: WRMSR: [ 0.00 0.00 ] +Key: WRMSRLIST: [ 0.00 0.00 ] +Key: WRMSRNS: [ 0.00 0.00 ] +Key: WRMSRNSir: [ 0.00 0.00 ] +Key: WRMSRNSir_EVEX: [ 0.00 0.00 ] +Key: WRPKRUr: [ 0.00 0.00 ] +Key: WRSSD: [ 0.00 0.00 ] +Key: WRSSD_EVEX: [ 0.00 0.00 ] +Key: WRSSQ: [ 0.00 0.00 ] +Key: WRSSQ_EVEX: [ 0.00 0.00 ] +Key: WRUSSD: [ 0.00 0.00 ] +Key: WRUSSD_EVEX: [ 0.00 0.00 ] +Key: WRUSSQ: [ 0.00 0.00 ] +Key: WRUSSQ_EVEX: [ 0.00 0.00 ] +Key: XABORT: [ 0.00 0.00 ] +Key: XABORT_DEF: [ 0.00 0.00 ] +Key: XACQUIRE_PREFIX: [ 0.00 0.00 ] +Key: XADD: [ 0.00 0.00 ] +Key: XAM_F: [ 0.00 0.00 ] +Key: XAM_Fp: [ 0.00 0.00 ] +Key: XBEGIN: [ 0.00 0.00 ] +Key: XCHG: [ 0.00 0.00 ] +Key: XCH_F: [ 0.00 0.00 ] +Key: XCRYPTCBC: [ 0.00 0.00 ] +Key: XCRYPTCFB: [ 0.00 0.00 ] +Key: XCRYPTCTR: [ 0.00 0.00 ] +Key: XCRYPTECB: [ 0.00 0.00 ] +Key: XCRYPTOFB: [ 0.00 0.00 ] +Key: XEND: [ 0.00 0.00 ] +Key: XGETBV: [ 0.00 0.00 ] +Key: XLAT: [ 0.00 0.00 ] +Key: XOR: [ 0.00 0.00 ] +Key: XORPDrm: [ 0.00 0.00 ] +Key: XORPDrr: [ 0.00 0.00 ] +Key: XORPSrm: [ 0.00 0.00 ] +Key: XORPSrr: [ 0.00 0.00 ] +Key: XRELEASE_PREFIX: [ 0.00 0.00 ] +Key: XRESLDTRK: [ 0.00 0.00 ] +Key: XRSTOR: [ 0.00 0.00 ] +Key: XRSTORS: [ 0.00 0.00 ] +Key: XSAVE: [ 0.00 0.00 ] +Key: XSAVEC: [ 0.00 0.00 ] +Key: XSAVEOPT: [ 0.00 0.00 ] +Key: XSAVES: [ 0.00 0.00 ] +Key: XSETBV: [ 0.00 0.00 ] +Key: XSHA: [ 0.00 0.00 ] +Key: XSTORE: [ 0.00 0.00 ] +Key: XSUSLDTRK: [ 0.00 0.00 ] +Key: XTEST: [ 0.00 0.00 ] diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt new file mode 100644 index 0000000..4409e6d --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt @@ -0,0 +1,6882 @@ +Key: AAA: [ 0.00 0.00 ] +Key: AAD: [ 0.00 0.00 ] +Key: AADD: [ 0.00 0.00 ] +Key: AAM: [ 0.00 0.00 ] +Key: AAND: [ 0.00 0.00 ] +Key: AAS: [ 0.00 0.00 ] +Key: ABS_F: [ 0.00 0.00 ] +Key: ABS_Fp: [ 0.50 1.00 ] +Key: ADC: [ 1.50 2.00 ] +Key: ADCX: [ 0.00 0.00 ] +Key: ADD: [ 2.50 3.00 ] +Key: ADDPDrm: [ 3.50 4.00 ] +Key: ADDPDrr: [ 4.50 5.00 ] +Key: ADDPSrm: [ 0.00 0.00 ] +Key: ADDPSrr: [ 5.50 6.00 ] +Key: ADDR: [ 0.00 0.00 ] +Key: ADDSDrm: [ 6.50 7.00 ] +Key: ADDSDrm_Int: [ 0.00 0.00 ] +Key: ADDSDrr: [ 0.00 0.00 ] +Key: ADDSDrr_Int: [ 0.00 0.00 ] +Key: ADDSSrm: [ 0.00 0.00 ] +Key: ADDSSrm_Int: [ 0.00 0.00 ] +Key: ADDSSrr: [ 0.00 0.00 ] +Key: ADDSSrr_Int: [ 0.00 0.00 ] +Key: ADDSUBPDrm: [ 0.00 0.00 ] +Key: ADDSUBPDrr: [ 0.00 0.00 ] +Key: ADDSUBPSrm: [ 0.00 0.00 ] +Key: ADDSUBPSrr: [ 0.00 0.00 ] +Key: ADD_F: [ 0.00 0.00 ] +Key: ADD_FI: [ 0.00 0.00 ] +Key: ADD_FPrST: [ 0.00 0.00 ] +Key: ADD_FST: [ 0.00 0.00 ] +Key: ADD_Fp: [ 0.00 0.00 ] +Key: ADD_FpI: [ 0.00 0.00 ] +Key: ADD_FrST: [ 0.00 0.00 ] +Key: ADJCALLSTACKDOWN: [ 0.00 0.00 ] +Key: ADJCALLSTACKUP: [ 0.00 0.00 ] +Key: ADOX: [ 0.00 0.00 ] +Key: AESDEC: [ 0.00 0.00 ] +Key: AESDECLASTrm: [ 0.00 0.00 ] +Key: AESDECLASTrr: [ 0.00 0.00 ] +Key: AESDECWIDE: [ 0.00 0.00 ] +Key: AESDECrm: [ 0.00 0.00 ] +Key: AESDECrr: [ 0.00 0.00 ] +Key: AESENC: [ 0.00 0.00 ] +Key: AESENCLASTrm: [ 0.00 0.00 ] +Key: AESENCLASTrr: [ 0.00 0.00 ] +Key: AESENCWIDE: [ 0.00 0.00 ] +Key: AESENCrm: [ 0.00 0.00 ] +Key: AESENCrr: [ 0.00 0.00 ] +Key: AESIMCrm: [ 0.00 0.00 ] +Key: AESIMCrr: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: AND: [ 0.00 0.00 ] +Key: ANDN: [ 0.00 0.00 ] +Key: ANDNPDrm: [ 0.00 0.00 ] +Key: ANDNPDrr: [ 0.00 0.00 ] +Key: ANDNPSrm: [ 0.00 0.00 ] +Key: ANDNPSrr: [ 0.00 0.00 ] +Key: ANDPDrm: [ 0.00 0.00 ] +Key: ANDPDrr: [ 0.00 0.00 ] +Key: ANDPSrm: [ 0.00 0.00 ] +Key: ANDPSrr: [ 0.00 0.00 ] +Key: ANNOTATION_LABEL: [ 0.00 0.00 ] +Key: AOR: [ 0.00 0.00 ] +Key: ARITH_FENCE: [ 0.00 0.00 ] +Key: ARPL: [ 0.00 0.00 ] +Key: ASAN_CHECK_MEMACCESS: [ 0.00 0.00 ] +Key: AVX: [ 0.00 0.00 ] +Key: AVX_SET: [ 0.00 0.00 ] +Key: AXOR: [ 0.00 0.00 ] +Key: BEXTR: [ 0.00 0.00 ] +Key: BEXTRI: [ 0.00 0.00 ] +Key: BLCFILL: [ 0.00 0.00 ] +Key: BLCI: [ 0.00 0.00 ] +Key: BLCIC: [ 0.00 0.00 ] +Key: BLCMSK: [ 0.00 0.00 ] +Key: BLCS: [ 0.00 0.00 ] +Key: BLENDPDrmi: [ 0.00 0.00 ] +Key: BLENDPDrri: [ 0.00 0.00 ] +Key: BLENDPSrmi: [ 0.00 0.00 ] +Key: BLENDPSrri: [ 0.00 0.00 ] +Key: BLENDVPDrm: [ 0.00 0.00 ] +Key: BLENDVPDrr: [ 0.00 0.00 ] +Key: BLENDVPSrm: [ 0.00 0.00 ] +Key: BLENDVPSrr: [ 0.00 0.00 ] +Key: BLSFILL: [ 0.00 0.00 ] +Key: BLSI: [ 0.00 0.00 ] +Key: BLSIC: [ 0.00 0.00 ] +Key: BLSMSK: [ 0.00 0.00 ] +Key: BLSR: [ 0.00 0.00 ] +Key: BOUNDS: [ 0.00 0.00 ] +Key: BSF: [ 0.00 0.00 ] +Key: BSR: [ 0.00 0.00 ] +Key: BSWAP: [ 0.00 0.00 ] +Key: BT: [ 0.00 0.00 ] +Key: BTC: [ 0.00 0.00 ] +Key: BTR: [ 0.00 0.00 ] +Key: BTS: [ 0.00 0.00 ] +Key: BUNDLE: [ 0.00 0.00 ] +Key: BZHI: [ 0.00 0.00 ] +Key: CALL: [ 0.00 0.00 ] +Key: CALLpcrel: [ 0.00 0.00 ] +Key: CATCHRET: [ 0.00 0.00 ] +Key: CBW: [ 0.00 0.00 ] +Key: CCMP: [ 0.00 0.00 ] +Key: CDQ: [ 0.00 0.00 ] +Key: CDQE: [ 0.00 0.00 ] +Key: CFCMOV: [ 0.00 0.00 ] +Key: CFI_INSTRUCTION: [ 0.00 0.00 ] +Key: CHS_F: [ 0.00 0.00 ] +Key: CHS_Fp: [ 0.00 0.00 ] +Key: CLAC: [ 0.00 0.00 ] +Key: CLC: [ 0.00 0.00 ] +Key: CLD: [ 0.00 0.00 ] +Key: CLDEMOTE: [ 0.00 0.00 ] +Key: CLEANUPRET: [ 0.00 0.00 ] +Key: CLFLUSH: [ 0.00 0.00 ] +Key: CLFLUSHOPT: [ 0.00 0.00 ] +Key: CLGI: [ 0.00 0.00 ] +Key: CLI: [ 0.00 0.00 ] +Key: CLRSSBSY: [ 0.00 0.00 ] +Key: CLTS: [ 0.00 0.00 ] +Key: CLUI: [ 0.00 0.00 ] +Key: CLWB: [ 0.00 0.00 ] +Key: CLZERO: [ 0.00 0.00 ] +Key: CMC: [ 0.00 0.00 ] +Key: CMOV: [ 0.00 0.00 ] +Key: CMOVBE_F: [ 0.00 0.00 ] +Key: CMOVBE_Fp: [ 0.00 0.00 ] +Key: CMOVB_F: [ 0.00 0.00 ] +Key: CMOVB_Fp: [ 0.00 0.00 ] +Key: CMOVE_F: [ 0.00 0.00 ] +Key: CMOVE_Fp: [ 0.00 0.00 ] +Key: CMOVNBE_F: [ 0.00 0.00 ] +Key: CMOVNBE_Fp: [ 0.00 0.00 ] +Key: CMOVNB_F: [ 0.00 0.00 ] +Key: CMOVNB_Fp: [ 0.00 0.00 ] +Key: CMOVNE_F: [ 0.00 0.00 ] +Key: CMOVNE_Fp: [ 0.00 0.00 ] +Key: CMOVNP_F: [ 0.00 0.00 ] +Key: CMOVNP_Fp: [ 0.00 0.00 ] +Key: CMOVP_F: [ 0.00 0.00 ] +Key: CMOVP_Fp: [ 0.00 0.00 ] +Key: CMOV_FR: [ 0.00 0.00 ] +Key: CMOV_GR: [ 0.00 0.00 ] +Key: CMOV_RFP: [ 0.00 0.00 ] +Key: CMOV_VK: [ 0.00 0.00 ] +Key: CMOV_VR: [ 0.00 0.00 ] +Key: CMP: [ 0.00 0.00 ] +Key: CMPCCXADDmr: [ 0.00 0.00 ] +Key: CMPPDrmi: [ 0.00 0.00 ] +Key: CMPPDrri: [ 0.00 0.00 ] +Key: CMPPSrmi: [ 0.00 0.00 ] +Key: CMPPSrri: [ 0.00 0.00 ] +Key: CMPSB: [ 0.00 0.00 ] +Key: CMPSDrmi: [ 0.00 0.00 ] +Key: CMPSDrmi_Int: [ 0.00 0.00 ] +Key: CMPSDrri: [ 0.00 0.00 ] +Key: CMPSDrri_Int: [ 0.00 0.00 ] +Key: CMPSL: [ 0.00 0.00 ] +Key: CMPSQ: [ 0.00 0.00 ] +Key: CMPSSrmi: [ 0.00 0.00 ] +Key: CMPSSrmi_Int: [ 0.00 0.00 ] +Key: CMPSSrri: [ 0.00 0.00 ] +Key: CMPSSrri_Int: [ 0.00 0.00 ] +Key: CMPSW: [ 0.00 0.00 ] +Key: CMPXCHG: [ 0.00 0.00 ] +Key: COMISDrm: [ 0.00 0.00 ] +Key: COMISDrm_Int: [ 0.00 0.00 ] +Key: COMISDrr: [ 0.00 0.00 ] +Key: COMISDrr_Int: [ 0.00 0.00 ] +Key: COMISSrm: [ 0.00 0.00 ] +Key: COMISSrm_Int: [ 0.00 0.00 ] +Key: COMISSrr: [ 0.00 0.00 ] +Key: COMISSrr_Int: [ 0.00 0.00 ] +Key: COMP_FST: [ 0.00 0.00 ] +Key: COM_FIPr: [ 0.00 0.00 ] +Key: COM_FIr: [ 0.00 0.00 ] +Key: COM_FST: [ 0.00 0.00 ] +Key: COM_FpIr: [ 0.00 0.00 ] +Key: COM_Fpr: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ANCHOR: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ENTRY: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_GLUE: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_LOOP: [ 0.00 0.00 ] +Key: COPY: [ 0.00 0.00 ] +Key: COPY_TO_REGCLASS: [ 0.00 0.00 ] +Key: CPUID: [ 0.00 0.00 ] +Key: CQO: [ 0.00 0.00 ] +Key: CRC: [ 0.00 0.00 ] +Key: CS_PREFIX: [ 0.00 0.00 ] +Key: CTEST: [ 0.00 0.00 ] +Key: CVTDQ: [ 0.00 0.00 ] +Key: CVTPD: [ 0.00 0.00 ] +Key: CVTPS: [ 0.00 0.00 ] +Key: CVTSD: [ 0.00 0.00 ] +Key: CVTSI: [ 0.00 0.00 ] +Key: CVTSS: [ 0.00 0.00 ] +Key: CVTTPD: [ 0.00 0.00 ] +Key: CVTTPS: [ 0.00 0.00 ] +Key: CVTTSD: [ 0.00 0.00 ] +Key: CVTTSS: [ 0.00 0.00 ] +Key: CWD: [ 0.00 0.00 ] +Key: CWDE: [ 0.00 0.00 ] +Key: DAA: [ 0.00 0.00 ] +Key: DAS: [ 0.00 0.00 ] +Key: DATA: [ 0.00 0.00 ] +Key: DBG_INSTR_REF: [ 0.00 0.00 ] +Key: DBG_LABEL: [ 0.00 0.00 ] +Key: DBG_PHI: [ 0.00 0.00 ] +Key: DBG_VALUE: [ 0.00 0.00 ] +Key: DBG_VALUE_LIST: [ 0.00 0.00 ] +Key: DEC: [ 0.00 0.00 ] +Key: DIV: [ 0.00 0.00 ] +Key: DIVPDrm: [ 0.00 0.00 ] +Key: DIVPDrr: [ 0.00 0.00 ] +Key: DIVPSrm: [ 0.00 0.00 ] +Key: DIVPSrr: [ 0.00 0.00 ] +Key: DIVR_F: [ 0.00 0.00 ] +Key: DIVR_FI: [ 0.00 0.00 ] +Key: DIVR_FPrST: [ 0.00 0.00 ] +Key: DIVR_FST: [ 0.00 0.00 ] +Key: DIVR_Fp: [ 0.00 0.00 ] +Key: DIVR_FpI: [ 0.00 0.00 ] +Key: DIVR_FrST: [ 0.00 0.00 ] +Key: DIVSDrm: [ 0.00 0.00 ] +Key: DIVSDrm_Int: [ 0.00 0.00 ] +Key: DIVSDrr: [ 0.00 0.00 ] +Key: DIVSDrr_Int: [ 0.00 0.00 ] +Key: DIVSSrm: [ 0.00 0.00 ] +Key: DIVSSrm_Int: [ 0.00 0.00 ] +Key: DIVSSrr: [ 0.00 0.00 ] +Key: DIVSSrr_Int: [ 0.00 0.00 ] +Key: DIV_F: [ 0.00 0.00 ] +Key: DIV_FI: [ 0.00 0.00 ] +Key: DIV_FPrST: [ 0.00 0.00 ] +Key: DIV_FST: [ 0.00 0.00 ] +Key: DIV_Fp: [ 0.00 0.00 ] +Key: DIV_FpI: [ 0.00 0.00 ] +Key: DIV_FrST: [ 0.00 0.00 ] +Key: DPPDrmi: [ 0.00 0.00 ] +Key: DPPDrri: [ 0.00 0.00 ] +Key: DPPSrmi: [ 0.00 0.00 ] +Key: DPPSrri: [ 0.00 0.00 ] +Key: DS_PREFIX: [ 0.00 0.00 ] +Key: DYN_ALLOCA: [ 0.00 0.00 ] +Key: EH_LABEL: [ 0.00 0.00 ] +Key: EH_RETURN: [ 0.00 0.00 ] +Key: EH_SjLj_LongJmp: [ 0.00 0.00 ] +Key: EH_SjLj_SetJmp: [ 0.00 0.00 ] +Key: EH_SjLj_Setup: [ 0.00 0.00 ] +Key: ENCLS: [ 0.00 0.00 ] +Key: ENCLU: [ 0.00 0.00 ] +Key: ENCLV: [ 0.00 0.00 ] +Key: ENCODEKEY: [ 0.00 0.00 ] +Key: ENDBR: [ 0.00 0.00 ] +Key: ENQCMD: [ 0.00 0.00 ] +Key: ENQCMDS: [ 0.00 0.00 ] +Key: ENTER: [ 0.00 0.00 ] +Key: ERETS: [ 0.00 0.00 ] +Key: ERETU: [ 0.00 0.00 ] +Key: ES_PREFIX: [ 0.00 0.00 ] +Key: EXTRACTPSmri: [ 0.00 0.00 ] +Key: EXTRACTPSrri: [ 0.00 0.00 ] +Key: EXTRACT_SUBREG: [ 0.00 0.00 ] +Key: EXTRQ: [ 0.00 0.00 ] +Key: EXTRQI: [ 0.00 0.00 ] +Key: F: [ 0.00 0.00 ] +Key: FAKE_USE: [ 0.00 0.00 ] +Key: FARCALL: [ 0.00 0.00 ] +Key: FARJMP: [ 0.00 0.00 ] +Key: FAULTING_OP: [ 0.00 0.00 ] +Key: FBLDm: [ 0.00 0.00 ] +Key: FBSTPm: [ 0.00 0.00 ] +Key: FCOM: [ 0.00 0.00 ] +Key: FCOMP: [ 0.00 0.00 ] +Key: FCOMPP: [ 0.00 0.00 ] +Key: FCOS: [ 0.00 0.00 ] +Key: FDECSTP: [ 0.00 0.00 ] +Key: FEMMS: [ 0.00 0.00 ] +Key: FENTRY_CALL: [ 0.00 0.00 ] +Key: FFREE: [ 0.00 0.00 ] +Key: FFREEP: [ 0.00 0.00 ] +Key: FICOM: [ 0.00 0.00 ] +Key: FICOMP: [ 0.00 0.00 ] +Key: FINCSTP: [ 0.00 0.00 ] +Key: FLDCW: [ 0.00 0.00 ] +Key: FLDENVm: [ 0.00 0.00 ] +Key: FLDL: [ 0.00 0.00 ] +Key: FLDLG: [ 0.00 0.00 ] +Key: FLDLN: [ 0.00 0.00 ] +Key: FLDPI: [ 0.00 0.00 ] +Key: FNCLEX: [ 0.00 0.00 ] +Key: FNINIT: [ 0.00 0.00 ] +Key: FNOP: [ 0.00 0.00 ] +Key: FNSTCW: [ 0.00 0.00 ] +Key: FNSTSW: [ 0.00 0.00 ] +Key: FNSTSWm: [ 0.00 0.00 ] +Key: FP: [ 0.00 0.00 ] +Key: FPATAN: [ 0.00 0.00 ] +Key: FPREM: [ 0.00 0.00 ] +Key: FPTAN: [ 0.00 0.00 ] +Key: FRNDINT: [ 0.00 0.00 ] +Key: FRSTORm: [ 0.00 0.00 ] +Key: FSAVEm: [ 0.00 0.00 ] +Key: FSCALE: [ 0.00 0.00 ] +Key: FSIN: [ 0.00 0.00 ] +Key: FSINCOS: [ 0.00 0.00 ] +Key: FSTENVm: [ 0.00 0.00 ] +Key: FS_PREFIX: [ 0.00 0.00 ] +Key: FXRSTOR: [ 0.00 0.00 ] +Key: FXSAVE: [ 0.00 0.00 ] +Key: FXTRACT: [ 0.00 0.00 ] +Key: FYL: [ 0.00 0.00 ] +Key: FsFLD: [ 0.00 0.00 ] +Key: GC_LABEL: [ 0.00 0.00 ] +Key: GETSEC: [ 0.00 0.00 ] +Key: GF: [ 0.00 0.00 ] +Key: GS_PREFIX: [ 0.00 0.00 ] +Key: G_ABDS: [ 0.00 0.00 ] +Key: G_ABDU: [ 0.00 0.00 ] +Key: G_ABS: [ 0.00 0.00 ] +Key: G_ADD: [ 0.00 0.00 ] +Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ] +Key: G_AND: [ 0.00 0.00 ] +Key: G_ANYEXT: [ 0.00 0.00 ] +Key: G_ASHR: [ 0.00 0.00 ] +Key: G_ASSERT_ALIGN: [ 0.00 0.00 ] +Key: G_ASSERT_SEXT: [ 0.00 0.00 ] +Key: G_ASSERT_ZEXT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_ADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_AND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAXIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMINIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FSUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_NAND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_OR: [ 0.00 0.00 ] +Key: G_ATOMICRMW_SUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UDEC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UINC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_COND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_SAT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XCHG: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XOR: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG_WITH_SUCCESS: [ 0.00 0.00 ] +Key: G_BITCAST: [ 0.00 0.00 ] +Key: G_BITREVERSE: [ 0.00 0.00 ] +Key: G_BLOCK_ADDR: [ 0.00 0.00 ] +Key: G_BR: [ 0.00 0.00 ] +Key: G_BRCOND: [ 0.00 0.00 ] +Key: G_BRINDIRECT: [ 0.00 0.00 ] +Key: G_BRJT: [ 0.00 0.00 ] +Key: G_BSWAP: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR_TRUNC: [ 0.00 0.00 ] +Key: G_BZERO: [ 0.00 0.00 ] +Key: G_CONCAT_VECTORS: [ 0.00 0.00 ] +Key: G_CONSTANT: [ 0.00 0.00 ] +Key: G_CONSTANT_FOLD_BARRIER: [ 0.00 0.00 ] +Key: G_CONSTANT_POOL: [ 0.00 0.00 ] +Key: G_CTLZ: [ 0.00 0.00 ] +Key: G_CTLZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_CTPOP: [ 0.00 0.00 ] +Key: G_CTTZ: [ 0.00 0.00 ] +Key: G_CTTZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_DEBUGTRAP: [ 0.00 0.00 ] +Key: G_DYN_STACKALLOC: [ 0.00 0.00 ] +Key: G_EXTRACT: [ 0.00 0.00 ] +Key: G_EXTRACT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_EXTRACT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_FABS: [ 0.00 0.00 ] +Key: G_FACOS: [ 0.00 0.00 ] +Key: G_FADD: [ 0.00 0.00 ] +Key: G_FASIN: [ 0.00 0.00 ] +Key: G_FATAN: [ 0.00 0.00 ] +Key: G_FCANONICALIZE: [ 0.00 0.00 ] +Key: G_FCEIL: [ 0.00 0.00 ] +Key: G_FCMP: [ 0.00 0.00 ] +Key: G_FCONSTANT: [ 0.00 0.00 ] +Key: G_FCOPYSIGN: [ 0.00 0.00 ] +Key: G_FCOS: [ 0.00 0.00 ] +Key: G_FCOSH: [ 0.00 0.00 ] +Key: G_FDIV: [ 0.00 0.00 ] +Key: G_FENCE: [ 0.00 0.00 ] +Key: G_FEXP: [ 0.00 0.00 ] +Key: G_FFLOOR: [ 0.00 0.00 ] +Key: G_FFREXP: [ 0.00 0.00 ] +Key: G_FILD: [ 0.00 0.00 ] +Key: G_FIST: [ 0.00 0.00 ] +Key: G_FLDCW: [ 0.00 0.00 ] +Key: G_FLDEXP: [ 0.00 0.00 ] +Key: G_FLOG: [ 0.00 0.00 ] +Key: G_FMA: [ 0.00 0.00 ] +Key: G_FMAD: [ 0.00 0.00 ] +Key: G_FMAXIMUM: [ 0.00 0.00 ] +Key: G_FMAXIMUMNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMINIMUM: [ 0.00 0.00 ] +Key: G_FMINIMUMNUM: [ 0.00 0.00 ] +Key: G_FMINNUM: [ 0.00 0.00 ] +Key: G_FMINNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMODF: [ 0.00 0.00 ] +Key: G_FMUL: [ 0.00 0.00 ] +Key: G_FNEARBYINT: [ 0.00 0.00 ] +Key: G_FNEG: [ 0.00 0.00 ] +Key: G_FNSTCW: [ 0.00 0.00 ] +Key: G_FPEXT: [ 0.00 0.00 ] +Key: G_FPOW: [ 0.00 0.00 ] +Key: G_FPOWI: [ 0.00 0.00 ] +Key: G_FPTOSI: [ 0.00 0.00 ] +Key: G_FPTOSI_SAT: [ 0.00 0.00 ] +Key: G_FPTOUI: [ 0.00 0.00 ] +Key: G_FPTOUI_SAT: [ 0.00 0.00 ] +Key: G_FPTRUNC: [ 0.00 0.00 ] +Key: G_FRAME_INDEX: [ 0.00 0.00 ] +Key: G_FREEZE: [ 0.00 0.00 ] +Key: G_FREM: [ 0.00 0.00 ] +Key: G_FRINT: [ 0.00 0.00 ] +Key: G_FSHL: [ 0.00 0.00 ] +Key: G_FSHR: [ 0.00 0.00 ] +Key: G_FSIN: [ 0.00 0.00 ] +Key: G_FSINCOS: [ 0.00 0.00 ] +Key: G_FSINH: [ 0.00 0.00 ] +Key: G_FSQRT: [ 0.00 0.00 ] +Key: G_FSUB: [ 0.00 0.00 ] +Key: G_FTAN: [ 0.00 0.00 ] +Key: G_FTANH: [ 0.00 0.00 ] +Key: G_GET_FPENV: [ 0.00 0.00 ] +Key: G_GET_FPMODE: [ 0.00 0.00 ] +Key: G_GET_ROUNDING: [ 0.00 0.00 ] +Key: G_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_ICMP: [ 0.00 0.00 ] +Key: G_IMPLICIT_DEF: [ 0.00 0.00 ] +Key: G_INDEXED_LOAD: [ 0.00 0.00 ] +Key: G_INDEXED_SEXTLOAD: [ 0.00 0.00 ] +Key: G_INDEXED_STORE: [ 0.00 0.00 ] +Key: G_INDEXED_ZEXTLOAD: [ 0.00 0.00 ] +Key: G_INSERT: [ 0.00 0.00 ] +Key: G_INSERT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_INSERT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_INTRINSIC: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTRINSIC_FPTRUNC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_LLRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_LRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUNDEVEN: [ 0.00 0.00 ] +Key: G_INTRINSIC_TRUNC: [ 0.00 0.00 ] +Key: G_INTRINSIC_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTTOPTR: [ 0.00 0.00 ] +Key: G_INVOKE_REGION_START: [ 0.00 0.00 ] +Key: G_IS_FPCLASS: [ 0.00 0.00 ] +Key: G_JUMP_TABLE: [ 0.00 0.00 ] +Key: G_LLROUND: [ 0.00 0.00 ] +Key: G_LOAD: [ 0.00 0.00 ] +Key: G_LROUND: [ 0.00 0.00 ] +Key: G_LSHR: [ 0.00 0.00 ] +Key: G_MEMCPY: [ 0.00 0.00 ] +Key: G_MEMCPY_INLINE: [ 0.00 0.00 ] +Key: G_MEMMOVE: [ 0.00 0.00 ] +Key: G_MEMSET: [ 0.00 0.00 ] +Key: G_MERGE_VALUES: [ 0.00 0.00 ] +Key: G_MUL: [ 0.00 0.00 ] +Key: G_OR: [ 0.00 0.00 ] +Key: G_PHI: [ 0.00 0.00 ] +Key: G_PREFETCH: [ 0.00 0.00 ] +Key: G_PTRAUTH_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_PTRMASK: [ 0.00 0.00 ] +Key: G_PTRTOINT: [ 0.00 0.00 ] +Key: G_PTR_ADD: [ 0.00 0.00 ] +Key: G_READCYCLECOUNTER: [ 0.00 0.00 ] +Key: G_READSTEADYCOUNTER: [ 0.00 0.00 ] +Key: G_READ_REGISTER: [ 0.00 0.00 ] +Key: G_RESET_FPENV: [ 0.00 0.00 ] +Key: G_RESET_FPMODE: [ 0.00 0.00 ] +Key: G_ROTL: [ 0.00 0.00 ] +Key: G_ROTR: [ 0.00 0.00 ] +Key: G_SADDE: [ 0.00 0.00 ] +Key: G_SADDO: [ 0.00 0.00 ] +Key: G_SADDSAT: [ 0.00 0.00 ] +Key: G_SBFX: [ 0.00 0.00 ] +Key: G_SCMP: [ 0.00 0.00 ] +Key: G_SDIV: [ 0.00 0.00 ] +Key: G_SDIVFIX: [ 0.00 0.00 ] +Key: G_SDIVFIXSAT: [ 0.00 0.00 ] +Key: G_SDIVREM: [ 0.00 0.00 ] +Key: G_SELECT: [ 0.00 0.00 ] +Key: G_SET_FPENV: [ 0.00 0.00 ] +Key: G_SET_FPMODE: [ 0.00 0.00 ] +Key: G_SET_ROUNDING: [ 0.00 0.00 ] +Key: G_SEXT: [ 0.00 0.00 ] +Key: G_SEXTLOAD: [ 0.00 0.00 ] +Key: G_SEXT_INREG: [ 0.00 0.00 ] +Key: G_SHL: [ 0.00 0.00 ] +Key: G_SHUFFLE_VECTOR: [ 0.00 0.00 ] +Key: G_SITOFP: [ 0.00 0.00 ] +Key: G_SMAX: [ 0.00 0.00 ] +Key: G_SMIN: [ 0.00 0.00 ] +Key: G_SMULFIX: [ 0.00 0.00 ] +Key: G_SMULFIXSAT: [ 0.00 0.00 ] +Key: G_SMULH: [ 0.00 0.00 ] +Key: G_SMULO: [ 0.00 0.00 ] +Key: G_SPLAT_VECTOR: [ 0.00 0.00 ] +Key: G_SREM: [ 0.00 0.00 ] +Key: G_SSHLSAT: [ 0.00 0.00 ] +Key: G_SSUBE: [ 0.00 0.00 ] +Key: G_SSUBO: [ 0.00 0.00 ] +Key: G_SSUBSAT: [ 0.00 0.00 ] +Key: G_STACKRESTORE: [ 0.00 0.00 ] +Key: G_STACKSAVE: [ 0.00 0.00 ] +Key: G_STEP_VECTOR: [ 0.00 0.00 ] +Key: G_STORE: [ 0.00 0.00 ] +Key: G_STRICT_FADD: [ 0.00 0.00 ] +Key: G_STRICT_FDIV: [ 0.00 0.00 ] +Key: G_STRICT_FLDEXP: [ 0.00 0.00 ] +Key: G_STRICT_FMA: [ 0.00 0.00 ] +Key: G_STRICT_FMUL: [ 0.00 0.00 ] +Key: G_STRICT_FREM: [ 0.00 0.00 ] +Key: G_STRICT_FSQRT: [ 0.00 0.00 ] +Key: G_STRICT_FSUB: [ 0.00 0.00 ] +Key: G_SUB: [ 0.00 0.00 ] +Key: G_TRAP: [ 0.00 0.00 ] +Key: G_TRUNC: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ] +Key: G_TRUNC_USAT_U: [ 0.00 0.00 ] +Key: G_UADDE: [ 0.00 0.00 ] +Key: G_UADDO: [ 0.00 0.00 ] +Key: G_UADDSAT: [ 0.00 0.00 ] +Key: G_UBFX: [ 0.00 0.00 ] +Key: G_UBSANTRAP: [ 0.00 0.00 ] +Key: G_UCMP: [ 0.00 0.00 ] +Key: G_UDIV: [ 0.00 0.00 ] +Key: G_UDIVFIX: [ 0.00 0.00 ] +Key: G_UDIVFIXSAT: [ 0.00 0.00 ] +Key: G_UDIVREM: [ 0.00 0.00 ] +Key: G_UITOFP: [ 0.00 0.00 ] +Key: G_UMAX: [ 0.00 0.00 ] +Key: G_UMIN: [ 0.00 0.00 ] +Key: G_UMULFIX: [ 0.00 0.00 ] +Key: G_UMULFIXSAT: [ 0.00 0.00 ] +Key: G_UMULH: [ 0.00 0.00 ] +Key: G_UMULO: [ 0.00 0.00 ] +Key: G_UNMERGE_VALUES: [ 0.00 0.00 ] +Key: G_UREM: [ 0.00 0.00 ] +Key: G_USHLSAT: [ 0.00 0.00 ] +Key: G_USUBE: [ 0.00 0.00 ] +Key: G_USUBO: [ 0.00 0.00 ] +Key: G_USUBSAT: [ 0.00 0.00 ] +Key: G_VAARG: [ 0.00 0.00 ] +Key: G_VASTART: [ 0.00 0.00 ] +Key: G_VECREDUCE_ADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_AND: [ 0.00 0.00 ] +Key: G_VECREDUCE_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAXIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMINIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_MUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_OR: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_XOR: [ 0.00 0.00 ] +Key: G_VECTOR_COMPRESS: [ 0.00 0.00 ] +Key: G_VSCALE: [ 0.00 0.00 ] +Key: G_WRITE_REGISTER: [ 0.00 0.00 ] +Key: G_XOR: [ 0.00 0.00 ] +Key: G_ZEXT: [ 0.00 0.00 ] +Key: G_ZEXTLOAD: [ 0.00 0.00 ] +Key: HADDPDrm: [ 0.00 0.00 ] +Key: HADDPDrr: [ 0.00 0.00 ] +Key: HADDPSrm: [ 0.00 0.00 ] +Key: HADDPSrr: [ 0.00 0.00 ] +Key: HLT: [ 0.00 0.00 ] +Key: HRESET: [ 0.00 0.00 ] +Key: HSUBPDrm: [ 0.00 0.00 ] +Key: HSUBPDrr: [ 0.00 0.00 ] +Key: HSUBPSrm: [ 0.00 0.00 ] +Key: HSUBPSrr: [ 0.00 0.00 ] +Key: ICALL_BRANCH_FUNNEL: [ 0.00 0.00 ] +Key: IDIV: [ 0.00 0.00 ] +Key: ILD_F: [ 0.00 0.00 ] +Key: ILD_Fp: [ 0.00 0.00 ] +Key: IMPLICIT_DEF: [ 0.00 0.00 ] +Key: IMUL: [ 0.00 0.00 ] +Key: IMULZU: [ 0.00 0.00 ] +Key: IN: [ 0.00 0.00 ] +Key: INC: [ 0.00 0.00 ] +Key: INCSSPD: [ 0.00 0.00 ] +Key: INCSSPQ: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_CALL: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_TCRETURN: [ 0.00 0.00 ] +Key: INIT_UNDEF: [ 0.00 0.00 ] +Key: INLINEASM: [ 0.00 0.00 ] +Key: INLINEASM_BR: [ 0.00 0.00 ] +Key: INSB: [ 0.00 0.00 ] +Key: INSERTPSrmi: [ 0.00 0.00 ] +Key: INSERTPSrri: [ 0.00 0.00 ] +Key: INSERTQ: [ 0.00 0.00 ] +Key: INSERTQI: [ 0.00 0.00 ] +Key: INSERT_SUBREG: [ 0.00 0.00 ] +Key: INSL: [ 0.00 0.00 ] +Key: INSW: [ 0.00 0.00 ] +Key: INT: [ 0.00 0.00 ] +Key: INTO: [ 0.00 0.00 ] +Key: INVD: [ 0.00 0.00 ] +Key: INVEPT: [ 0.00 0.00 ] +Key: INVLPG: [ 0.00 0.00 ] +Key: INVLPGA: [ 0.00 0.00 ] +Key: INVLPGB: [ 0.00 0.00 ] +Key: INVPCID: [ 0.00 0.00 ] +Key: INVVPID: [ 0.00 0.00 ] +Key: IRET: [ 0.00 0.00 ] +Key: ISTT_FP: [ 0.00 0.00 ] +Key: ISTT_Fp: [ 0.00 0.00 ] +Key: IST_F: [ 0.00 0.00 ] +Key: IST_FP: [ 0.00 0.00 ] +Key: IST_Fp: [ 0.00 0.00 ] +Key: Int_eh_sjlj_setup_dispatch: [ 0.00 0.00 ] +Key: JCC: [ 0.00 0.00 ] +Key: JCXZ: [ 0.00 0.00 ] +Key: JECXZ: [ 0.00 0.00 ] +Key: JMP: [ 0.00 0.00 ] +Key: JMPABS: [ 0.00 0.00 ] +Key: JRCXZ: [ 0.00 0.00 ] +Key: JUMP_TABLE_DEBUG_INFO: [ 0.00 0.00 ] +Key: KADDBkk: [ 0.00 0.00 ] +Key: KADDDkk: [ 0.00 0.00 ] +Key: KADDQkk: [ 0.00 0.00 ] +Key: KADDWkk: [ 0.00 0.00 ] +Key: KANDBkk: [ 0.00 0.00 ] +Key: KANDDkk: [ 0.00 0.00 ] +Key: KANDNBkk: [ 0.00 0.00 ] +Key: KANDNDkk: [ 0.00 0.00 ] +Key: KANDNQkk: [ 0.00 0.00 ] +Key: KANDNWkk: [ 0.00 0.00 ] +Key: KANDQkk: [ 0.00 0.00 ] +Key: KANDWkk: [ 0.00 0.00 ] +Key: KCFI_CHECK: [ 0.00 0.00 ] +Key: KILL: [ 0.00 0.00 ] +Key: KMOVBkk: [ 0.00 0.00 ] +Key: KMOVBkk_EVEX: [ 0.00 0.00 ] +Key: KMOVBkm: [ 0.00 0.00 ] +Key: KMOVBkm_EVEX: [ 0.00 0.00 ] +Key: KMOVBkr: [ 0.00 0.00 ] +Key: KMOVBkr_EVEX: [ 0.00 0.00 ] +Key: KMOVBmk: [ 0.00 0.00 ] +Key: KMOVBmk_EVEX: [ 0.00 0.00 ] +Key: KMOVBrk: [ 0.00 0.00 ] +Key: KMOVBrk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkk: [ 0.00 0.00 ] +Key: KMOVDkk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkm: [ 0.00 0.00 ] +Key: KMOVDkm_EVEX: [ 0.00 0.00 ] +Key: KMOVDkr: [ 0.00 0.00 ] +Key: KMOVDkr_EVEX: [ 0.00 0.00 ] +Key: KMOVDmk: [ 0.00 0.00 ] +Key: KMOVDmk_EVEX: [ 0.00 0.00 ] +Key: KMOVDrk: [ 0.00 0.00 ] +Key: KMOVDrk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkk: [ 0.00 0.00 ] +Key: KMOVQkk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkm: [ 0.00 0.00 ] +Key: KMOVQkm_EVEX: [ 0.00 0.00 ] +Key: KMOVQkr: [ 0.00 0.00 ] +Key: KMOVQkr_EVEX: [ 0.00 0.00 ] +Key: KMOVQmk: [ 0.00 0.00 ] +Key: KMOVQmk_EVEX: [ 0.00 0.00 ] +Key: KMOVQrk: [ 0.00 0.00 ] +Key: KMOVQrk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkk: [ 0.00 0.00 ] +Key: KMOVWkk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkm: [ 0.00 0.00 ] +Key: KMOVWkm_EVEX: [ 0.00 0.00 ] +Key: KMOVWkr: [ 0.00 0.00 ] +Key: KMOVWkr_EVEX: [ 0.00 0.00 ] +Key: KMOVWmk: [ 0.00 0.00 ] +Key: KMOVWmk_EVEX: [ 0.00 0.00 ] +Key: KMOVWrk: [ 0.00 0.00 ] +Key: KMOVWrk_EVEX: [ 0.00 0.00 ] +Key: KNOTBkk: [ 0.00 0.00 ] +Key: KNOTDkk: [ 0.00 0.00 ] +Key: KNOTQkk: [ 0.00 0.00 ] +Key: KNOTWkk: [ 0.00 0.00 ] +Key: KORBkk: [ 0.00 0.00 ] +Key: KORDkk: [ 0.00 0.00 ] +Key: KORQkk: [ 0.00 0.00 ] +Key: KORTESTBkk: [ 0.00 0.00 ] +Key: KORTESTDkk: [ 0.00 0.00 ] +Key: KORTESTQkk: [ 0.00 0.00 ] +Key: KORTESTWkk: [ 0.00 0.00 ] +Key: KORWkk: [ 0.00 0.00 ] +Key: KSET: [ 0.00 0.00 ] +Key: KSHIFTLBki: [ 0.00 0.00 ] +Key: KSHIFTLDki: [ 0.00 0.00 ] +Key: KSHIFTLQki: [ 0.00 0.00 ] +Key: KSHIFTLWki: [ 0.00 0.00 ] +Key: KSHIFTRBki: [ 0.00 0.00 ] +Key: KSHIFTRDki: [ 0.00 0.00 ] +Key: KSHIFTRQki: [ 0.00 0.00 ] +Key: KSHIFTRWki: [ 0.00 0.00 ] +Key: KTESTBkk: [ 0.00 0.00 ] +Key: KTESTDkk: [ 0.00 0.00 ] +Key: KTESTQkk: [ 0.00 0.00 ] +Key: KTESTWkk: [ 0.00 0.00 ] +Key: KUNPCKBWkk: [ 0.00 0.00 ] +Key: KUNPCKDQkk: [ 0.00 0.00 ] +Key: KUNPCKWDkk: [ 0.00 0.00 ] +Key: KXNORBkk: [ 0.00 0.00 ] +Key: KXNORDkk: [ 0.00 0.00 ] +Key: KXNORQkk: [ 0.00 0.00 ] +Key: KXNORWkk: [ 0.00 0.00 ] +Key: KXORBkk: [ 0.00 0.00 ] +Key: KXORDkk: [ 0.00 0.00 ] +Key: KXORQkk: [ 0.00 0.00 ] +Key: KXORWkk: [ 0.00 0.00 ] +Key: LAHF: [ 0.00 0.00 ] +Key: LAR: [ 0.00 0.00 ] +Key: LCMPXCHG: [ 0.00 0.00 ] +Key: LDDQUrm: [ 0.00 0.00 ] +Key: LDMXCSR: [ 0.00 0.00 ] +Key: LDS: [ 0.00 0.00 ] +Key: LDTILECFG: [ 0.00 0.00 ] +Key: LDTILECFG_EVEX: [ 0.00 0.00 ] +Key: LD_F: [ 0.00 0.00 ] +Key: LD_Fp: [ 0.00 0.00 ] +Key: LD_Frr: [ 0.00 0.00 ] +Key: LEA: [ 0.00 0.00 ] +Key: LEAVE: [ 0.00 0.00 ] +Key: LES: [ 0.00 0.00 ] +Key: LFENCE: [ 0.00 0.00 ] +Key: LFS: [ 0.00 0.00 ] +Key: LGDT: [ 0.00 0.00 ] +Key: LGS: [ 0.00 0.00 ] +Key: LIDT: [ 0.00 0.00 ] +Key: LIFETIME_END: [ 0.00 0.00 ] +Key: LIFETIME_START: [ 0.00 0.00 ] +Key: LKGS: [ 0.00 0.00 ] +Key: LLDT: [ 0.00 0.00 ] +Key: LLWPCB: [ 0.00 0.00 ] +Key: LMSW: [ 0.00 0.00 ] +Key: LOADIWKEY: [ 0.00 0.00 ] +Key: LOAD_STACK_GUARD: [ 0.00 0.00 ] +Key: LOCAL_ESCAPE: [ 0.00 0.00 ] +Key: LOCK_ADD: [ 0.00 0.00 ] +Key: LOCK_AND: [ 0.00 0.00 ] +Key: LOCK_BTC: [ 0.00 0.00 ] +Key: LOCK_BTC_RM: [ 0.00 0.00 ] +Key: LOCK_BTR: [ 0.00 0.00 ] +Key: LOCK_BTR_RM: [ 0.00 0.00 ] +Key: LOCK_BTS: [ 0.00 0.00 ] +Key: LOCK_BTS_RM: [ 0.00 0.00 ] +Key: LOCK_DEC: [ 0.00 0.00 ] +Key: LOCK_INC: [ 0.00 0.00 ] +Key: LOCK_OR: [ 0.00 0.00 ] +Key: LOCK_PREFIX: [ 0.00 0.00 ] +Key: LOCK_SUB: [ 0.00 0.00 ] +Key: LOCK_XOR: [ 0.00 0.00 ] +Key: LODSB: [ 0.00 0.00 ] +Key: LODSL: [ 0.00 0.00 ] +Key: LODSQ: [ 0.00 0.00 ] +Key: LODSW: [ 0.00 0.00 ] +Key: LOOP: [ 0.00 0.00 ] +Key: LOOPE: [ 0.00 0.00 ] +Key: LOOPNE: [ 0.00 0.00 ] +Key: LRET: [ 0.00 0.00 ] +Key: LRETI: [ 0.00 0.00 ] +Key: LSL: [ 0.00 0.00 ] +Key: LSS: [ 0.00 0.00 ] +Key: LTRm: [ 0.00 0.00 ] +Key: LTRr: [ 0.00 0.00 ] +Key: LWPINS: [ 0.00 0.00 ] +Key: LWPVAL: [ 0.00 0.00 ] +Key: LXADD: [ 0.00 0.00 ] +Key: LZCNT: [ 0.00 0.00 ] +Key: MASKMOVDQU: [ 0.00 0.00 ] +Key: MASKPAIR: [ 0.00 0.00 ] +Key: MAXCPDrm: [ 0.00 0.00 ] +Key: MAXCPDrr: [ 0.00 0.00 ] +Key: MAXCPSrm: [ 0.00 0.00 ] +Key: MAXCPSrr: [ 0.00 0.00 ] +Key: MAXCSDrm: [ 0.00 0.00 ] +Key: MAXCSDrr: [ 0.00 0.00 ] +Key: MAXCSSrm: [ 0.00 0.00 ] +Key: MAXCSSrr: [ 0.00 0.00 ] +Key: MAXPDrm: [ 0.00 0.00 ] +Key: MAXPDrr: [ 0.00 0.00 ] +Key: MAXPSrm: [ 0.00 0.00 ] +Key: MAXPSrr: [ 0.00 0.00 ] +Key: MAXSDrm: [ 0.00 0.00 ] +Key: MAXSDrm_Int: [ 0.00 0.00 ] +Key: MAXSDrr: [ 0.00 0.00 ] +Key: MAXSDrr_Int: [ 0.00 0.00 ] +Key: MAXSSrm: [ 0.00 0.00 ] +Key: MAXSSrm_Int: [ 0.00 0.00 ] +Key: MAXSSrr: [ 0.00 0.00 ] +Key: MAXSSrr_Int: [ 0.00 0.00 ] +Key: MEMBARRIER: [ 0.00 0.00 ] +Key: MFENCE: [ 0.00 0.00 ] +Key: MINCPDrm: [ 0.00 0.00 ] +Key: MINCPDrr: [ 0.00 0.00 ] +Key: MINCPSrm: [ 0.00 0.00 ] +Key: MINCPSrr: [ 0.00 0.00 ] +Key: MINCSDrm: [ 0.00 0.00 ] +Key: MINCSDrr: [ 0.00 0.00 ] +Key: MINCSSrm: [ 0.00 0.00 ] +Key: MINCSSrr: [ 0.00 0.00 ] +Key: MINPDrm: [ 0.00 0.00 ] +Key: MINPDrr: [ 0.00 0.00 ] +Key: MINPSrm: [ 0.00 0.00 ] +Key: MINPSrr: [ 0.00 0.00 ] +Key: MINSDrm: [ 0.00 0.00 ] +Key: MINSDrm_Int: [ 0.00 0.00 ] +Key: MINSDrr: [ 0.00 0.00 ] +Key: MINSDrr_Int: [ 0.00 0.00 ] +Key: MINSSrm: [ 0.00 0.00 ] +Key: MINSSrm_Int: [ 0.00 0.00 ] +Key: MINSSrr: [ 0.00 0.00 ] +Key: MINSSrr_Int: [ 0.00 0.00 ] +Key: MMX_CVTPD: [ 0.00 0.00 ] +Key: MMX_CVTPI: [ 0.00 0.00 ] +Key: MMX_CVTPS: [ 0.00 0.00 ] +Key: MMX_CVTTPD: [ 0.00 0.00 ] +Key: MMX_CVTTPS: [ 0.00 0.00 ] +Key: MMX_EMMS: [ 0.00 0.00 ] +Key: MMX_MASKMOVQ: [ 0.00 0.00 ] +Key: MMX_MOVD: [ 0.00 0.00 ] +Key: MMX_MOVDQ: [ 0.00 0.00 ] +Key: MMX_MOVFR: [ 0.00 0.00 ] +Key: MMX_MOVNTQmr: [ 0.00 0.00 ] +Key: MMX_MOVQ: [ 0.00 0.00 ] +Key: MMX_PABSBrm: [ 0.00 0.00 ] +Key: MMX_PABSBrr: [ 0.00 0.00 ] +Key: MMX_PABSDrm: [ 0.00 0.00 ] +Key: MMX_PABSDrr: [ 0.00 0.00 ] +Key: MMX_PABSWrm: [ 0.00 0.00 ] +Key: MMX_PABSWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrm: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrr: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrr: [ 0.00 0.00 ] +Key: MMX_PADDBrm: [ 0.00 0.00 ] +Key: MMX_PADDBrr: [ 0.00 0.00 ] +Key: MMX_PADDDrm: [ 0.00 0.00 ] +Key: MMX_PADDDrr: [ 0.00 0.00 ] +Key: MMX_PADDQrm: [ 0.00 0.00 ] +Key: MMX_PADDQrr: [ 0.00 0.00 ] +Key: MMX_PADDSBrm: [ 0.00 0.00 ] +Key: MMX_PADDSBrr: [ 0.00 0.00 ] +Key: MMX_PADDSWrm: [ 0.00 0.00 ] +Key: MMX_PADDSWrr: [ 0.00 0.00 ] +Key: MMX_PADDUSBrm: [ 0.00 0.00 ] +Key: MMX_PADDUSBrr: [ 0.00 0.00 ] +Key: MMX_PADDUSWrm: [ 0.00 0.00 ] +Key: MMX_PADDUSWrr: [ 0.00 0.00 ] +Key: MMX_PADDWrm: [ 0.00 0.00 ] +Key: MMX_PADDWrr: [ 0.00 0.00 ] +Key: MMX_PALIGNRrmi: [ 0.00 0.00 ] +Key: MMX_PALIGNRrri: [ 0.00 0.00 ] +Key: MMX_PANDNrm: [ 0.00 0.00 ] +Key: MMX_PANDNrr: [ 0.00 0.00 ] +Key: MMX_PANDrm: [ 0.00 0.00 ] +Key: MMX_PANDrr: [ 0.00 0.00 ] +Key: MMX_PAVGBrm: [ 0.00 0.00 ] +Key: MMX_PAVGBrr: [ 0.00 0.00 ] +Key: MMX_PAVGWrm: [ 0.00 0.00 ] +Key: MMX_PAVGWrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrr: [ 0.00 0.00 ] +Key: MMX_PEXTRWrri: [ 0.00 0.00 ] +Key: MMX_PHADDDrm: [ 0.00 0.00 ] +Key: MMX_PHADDDrr: [ 0.00 0.00 ] +Key: MMX_PHADDSWrm: [ 0.00 0.00 ] +Key: MMX_PHADDSWrr: [ 0.00 0.00 ] +Key: MMX_PHADDWrm: [ 0.00 0.00 ] +Key: MMX_PHADDWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBDrm: [ 0.00 0.00 ] +Key: MMX_PHSUBDrr: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBWrr: [ 0.00 0.00 ] +Key: MMX_PINSRWrmi: [ 0.00 0.00 ] +Key: MMX_PINSRWrri: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrm: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrr: [ 0.00 0.00 ] +Key: MMX_PMADDWDrm: [ 0.00 0.00 ] +Key: MMX_PMADDWDrr: [ 0.00 0.00 ] +Key: MMX_PMAXSWrm: [ 0.00 0.00 ] +Key: MMX_PMAXSWrr: [ 0.00 0.00 ] +Key: MMX_PMAXUBrm: [ 0.00 0.00 ] +Key: MMX_PMAXUBrr: [ 0.00 0.00 ] +Key: MMX_PMINSWrm: [ 0.00 0.00 ] +Key: MMX_PMINSWrr: [ 0.00 0.00 ] +Key: MMX_PMINUBrm: [ 0.00 0.00 ] +Key: MMX_PMINUBrr: [ 0.00 0.00 ] +Key: MMX_PMOVMSKBrr: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrm: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrr: [ 0.00 0.00 ] +Key: MMX_PMULHUWrm: [ 0.00 0.00 ] +Key: MMX_PMULHUWrr: [ 0.00 0.00 ] +Key: MMX_PMULHWrm: [ 0.00 0.00 ] +Key: MMX_PMULHWrr: [ 0.00 0.00 ] +Key: MMX_PMULLWrm: [ 0.00 0.00 ] +Key: MMX_PMULLWrr: [ 0.00 0.00 ] +Key: MMX_PMULUDQrm: [ 0.00 0.00 ] +Key: MMX_PMULUDQrr: [ 0.00 0.00 ] +Key: MMX_PORrm: [ 0.00 0.00 ] +Key: MMX_PORrr: [ 0.00 0.00 ] +Key: MMX_PSADBWrm: [ 0.00 0.00 ] +Key: MMX_PSADBWrr: [ 0.00 0.00 ] +Key: MMX_PSHUFBrm: [ 0.00 0.00 ] +Key: MMX_PSHUFBrr: [ 0.00 0.00 ] +Key: MMX_PSHUFWmi: [ 0.00 0.00 ] +Key: MMX_PSHUFWri: [ 0.00 0.00 ] +Key: MMX_PSIGNBrm: [ 0.00 0.00 ] +Key: MMX_PSIGNBrr: [ 0.00 0.00 ] +Key: MMX_PSIGNDrm: [ 0.00 0.00 ] +Key: MMX_PSIGNDrr: [ 0.00 0.00 ] +Key: MMX_PSIGNWrm: [ 0.00 0.00 ] +Key: MMX_PSIGNWrr: [ 0.00 0.00 ] +Key: MMX_PSLLDri: [ 0.00 0.00 ] +Key: MMX_PSLLDrm: [ 0.00 0.00 ] +Key: MMX_PSLLDrr: [ 0.00 0.00 ] +Key: MMX_PSLLQri: [ 0.00 0.00 ] +Key: MMX_PSLLQrm: [ 0.00 0.00 ] +Key: MMX_PSLLQrr: [ 0.00 0.00 ] +Key: MMX_PSLLWri: [ 0.00 0.00 ] +Key: MMX_PSLLWrm: [ 0.00 0.00 ] +Key: MMX_PSLLWrr: [ 0.00 0.00 ] +Key: MMX_PSRADri: [ 0.00 0.00 ] +Key: MMX_PSRADrm: [ 0.00 0.00 ] +Key: MMX_PSRADrr: [ 0.00 0.00 ] +Key: MMX_PSRAWri: [ 0.00 0.00 ] +Key: MMX_PSRAWrm: [ 0.00 0.00 ] +Key: MMX_PSRAWrr: [ 0.00 0.00 ] +Key: MMX_PSRLDri: [ 0.00 0.00 ] +Key: MMX_PSRLDrm: [ 0.00 0.00 ] +Key: MMX_PSRLDrr: [ 0.00 0.00 ] +Key: MMX_PSRLQri: [ 0.00 0.00 ] +Key: MMX_PSRLQrm: [ 0.00 0.00 ] +Key: MMX_PSRLQrr: [ 0.00 0.00 ] +Key: MMX_PSRLWri: [ 0.00 0.00 ] +Key: MMX_PSRLWrm: [ 0.00 0.00 ] +Key: MMX_PSRLWrr: [ 0.00 0.00 ] +Key: MMX_PSUBBrm: [ 0.00 0.00 ] +Key: MMX_PSUBBrr: [ 0.00 0.00 ] +Key: MMX_PSUBDrm: [ 0.00 0.00 ] +Key: MMX_PSUBDrr: [ 0.00 0.00 ] +Key: MMX_PSUBQrm: [ 0.00 0.00 ] +Key: MMX_PSUBQrr: [ 0.00 0.00 ] +Key: MMX_PSUBSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBWrm: [ 0.00 0.00 ] +Key: MMX_PSUBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrr: [ 0.00 0.00 ] +Key: MMX_PXORrm: [ 0.00 0.00 ] +Key: MMX_PXORrr: [ 0.00 0.00 ] +Key: MMX_SET: [ 0.00 0.00 ] +Key: MONITOR: [ 0.00 0.00 ] +Key: MONITORX: [ 0.00 0.00 ] +Key: MONTMUL: [ 0.00 0.00 ] +Key: MORESTACK_RET: [ 0.00 0.00 ] +Key: MORESTACK_RET_RESTORE_R: [ 0.00 0.00 ] +Key: MOV: [ 0.00 0.00 ] +Key: MOVAPDmr: [ 0.00 0.00 ] +Key: MOVAPDrm: [ 0.00 0.00 ] +Key: MOVAPDrr: [ 0.00 0.00 ] +Key: MOVAPDrr_REV: [ 0.00 0.00 ] +Key: MOVAPSmr: [ 0.00 0.00 ] +Key: MOVAPSrm: [ 0.00 0.00 ] +Key: MOVAPSrr: [ 0.00 0.00 ] +Key: MOVAPSrr_REV: [ 0.00 0.00 ] +Key: MOVBE: [ 0.00 0.00 ] +Key: MOVDDUPrm: [ 0.00 0.00 ] +Key: MOVDDUPrr: [ 0.00 0.00 ] +Key: MOVDI: [ 0.00 0.00 ] +Key: MOVDIR: [ 0.00 0.00 ] +Key: MOVDIRI: [ 0.00 0.00 ] +Key: MOVDQAmr: [ 0.00 0.00 ] +Key: MOVDQArm: [ 0.00 0.00 ] +Key: MOVDQArr: [ 0.00 0.00 ] +Key: MOVDQArr_REV: [ 0.00 0.00 ] +Key: MOVDQUmr: [ 0.00 0.00 ] +Key: MOVDQUrm: [ 0.00 0.00 ] +Key: MOVDQUrr: [ 0.00 0.00 ] +Key: MOVDQUrr_REV: [ 0.00 0.00 ] +Key: MOVHLPSrr: [ 0.00 0.00 ] +Key: MOVHPDmr: [ 0.00 0.00 ] +Key: MOVHPDrm: [ 0.00 0.00 ] +Key: MOVHPSmr: [ 0.00 0.00 ] +Key: MOVHPSrm: [ 0.00 0.00 ] +Key: MOVLHPSrr: [ 0.00 0.00 ] +Key: MOVLPDmr: [ 0.00 0.00 ] +Key: MOVLPDrm: [ 0.00 0.00 ] +Key: MOVLPSmr: [ 0.00 0.00 ] +Key: MOVLPSrm: [ 0.00 0.00 ] +Key: MOVMSKPDrr: [ 0.00 0.00 ] +Key: MOVMSKPSrr: [ 0.00 0.00 ] +Key: MOVNTDQArm: [ 0.00 0.00 ] +Key: MOVNTDQmr: [ 0.00 0.00 ] +Key: MOVNTI: [ 0.00 0.00 ] +Key: MOVNTImr: [ 0.00 0.00 ] +Key: MOVNTPDmr: [ 0.00 0.00 ] +Key: MOVNTPSmr: [ 0.00 0.00 ] +Key: MOVNTSD: [ 0.00 0.00 ] +Key: MOVNTSS: [ 0.00 0.00 ] +Key: MOVPC: [ 0.00 0.00 ] +Key: MOVPDI: [ 0.00 0.00 ] +Key: MOVPQI: [ 0.00 0.00 ] +Key: MOVPQIto: [ 0.00 0.00 ] +Key: MOVQI: [ 0.00 0.00 ] +Key: MOVRS: [ 0.00 0.00 ] +Key: MOVSB: [ 0.00 0.00 ] +Key: MOVSDmr: [ 0.00 0.00 ] +Key: MOVSDrm: [ 0.00 0.00 ] +Key: MOVSDrm_alt: [ 0.00 0.00 ] +Key: MOVSDrr: [ 0.00 0.00 ] +Key: MOVSDrr_REV: [ 0.00 0.00 ] +Key: MOVSDto: [ 0.00 0.00 ] +Key: MOVSHDUPrm: [ 0.00 0.00 ] +Key: MOVSHDUPrr: [ 0.00 0.00 ] +Key: MOVSHPmr: [ 0.00 0.00 ] +Key: MOVSHPrm: [ 0.00 0.00 ] +Key: MOVSL: [ 0.00 0.00 ] +Key: MOVSLDUPrm: [ 0.00 0.00 ] +Key: MOVSLDUPrr: [ 0.00 0.00 ] +Key: MOVSQ: [ 0.00 0.00 ] +Key: MOVSS: [ 0.00 0.00 ] +Key: MOVSSmr: [ 0.00 0.00 ] +Key: MOVSSrm: [ 0.00 0.00 ] +Key: MOVSSrm_alt: [ 0.00 0.00 ] +Key: MOVSSrr: [ 0.00 0.00 ] +Key: MOVSSrr_REV: [ 0.00 0.00 ] +Key: MOVSW: [ 0.00 0.00 ] +Key: MOVSX: [ 0.00 0.00 ] +Key: MOVUPDmr: [ 0.00 0.00 ] +Key: MOVUPDrm: [ 0.00 0.00 ] +Key: MOVUPDrr: [ 0.00 0.00 ] +Key: MOVUPDrr_REV: [ 0.00 0.00 ] +Key: MOVUPSmr: [ 0.00 0.00 ] +Key: MOVUPSrm: [ 0.00 0.00 ] +Key: MOVUPSrr: [ 0.00 0.00 ] +Key: MOVUPSrr_REV: [ 0.00 0.00 ] +Key: MOVZPQILo: [ 0.00 0.00 ] +Key: MOVZX: [ 0.00 0.00 ] +Key: MPSADBWrmi: [ 0.00 0.00 ] +Key: MPSADBWrri: [ 0.00 0.00 ] +Key: MUL: [ 0.00 0.00 ] +Key: MULPDrm: [ 0.00 0.00 ] +Key: MULPDrr: [ 0.00 0.00 ] +Key: MULPSrm: [ 0.00 0.00 ] +Key: MULPSrr: [ 0.00 0.00 ] +Key: MULSDrm: [ 0.00 0.00 ] +Key: MULSDrm_Int: [ 0.00 0.00 ] +Key: MULSDrr: [ 0.00 0.00 ] +Key: MULSDrr_Int: [ 0.00 0.00 ] +Key: MULSSrm: [ 0.00 0.00 ] +Key: MULSSrm_Int: [ 0.00 0.00 ] +Key: MULSSrr: [ 0.00 0.00 ] +Key: MULSSrr_Int: [ 0.00 0.00 ] +Key: MULX: [ 0.00 0.00 ] +Key: MUL_F: [ 0.00 0.00 ] +Key: MUL_FI: [ 0.00 0.00 ] +Key: MUL_FPrST: [ 0.00 0.00 ] +Key: MUL_FST: [ 0.00 0.00 ] +Key: MUL_Fp: [ 0.00 0.00 ] +Key: MUL_FpI: [ 0.00 0.00 ] +Key: MUL_FrST: [ 0.00 0.00 ] +Key: MWAITX: [ 0.00 0.00 ] +Key: MWAITX_SAVE_RBX: [ 0.00 0.00 ] +Key: MWAITXrrr: [ 0.00 0.00 ] +Key: MWAITrr: [ 0.00 0.00 ] +Key: NEG: [ 0.00 0.00 ] +Key: NOOP: [ 0.00 0.00 ] +Key: NOOPL: [ 0.00 0.00 ] +Key: NOOPLr: [ 0.00 0.00 ] +Key: NOOPQ: [ 0.00 0.00 ] +Key: NOOPQr: [ 0.00 0.00 ] +Key: NOOPW: [ 0.00 0.00 ] +Key: NOOPWr: [ 0.00 0.00 ] +Key: NOT: [ 0.00 0.00 ] +Key: OR: [ 0.00 0.00 ] +Key: ORPDrm: [ 0.00 0.00 ] +Key: ORPDrr: [ 0.00 0.00 ] +Key: ORPSrm: [ 0.00 0.00 ] +Key: ORPSrr: [ 0.00 0.00 ] +Key: OUT: [ 0.00 0.00 ] +Key: OUTSB: [ 0.00 0.00 ] +Key: OUTSL: [ 0.00 0.00 ] +Key: OUTSW: [ 0.00 0.00 ] +Key: PABSBrm: [ 0.00 0.00 ] +Key: PABSBrr: [ 0.00 0.00 ] +Key: PABSDrm: [ 0.00 0.00 ] +Key: PABSDrr: [ 0.00 0.00 ] +Key: PABSWrm: [ 0.00 0.00 ] +Key: PABSWrr: [ 0.00 0.00 ] +Key: PACKSSDWrm: [ 0.00 0.00 ] +Key: PACKSSDWrr: [ 0.00 0.00 ] +Key: PACKSSWBrm: [ 0.00 0.00 ] +Key: PACKSSWBrr: [ 0.00 0.00 ] +Key: PACKUSDWrm: [ 0.00 0.00 ] +Key: PACKUSDWrr: [ 0.00 0.00 ] +Key: PACKUSWBrm: [ 0.00 0.00 ] +Key: PACKUSWBrr: [ 0.00 0.00 ] +Key: PADDBrm: [ 0.00 0.00 ] +Key: PADDBrr: [ 0.00 0.00 ] +Key: PADDDrm: [ 0.00 0.00 ] +Key: PADDDrr: [ 0.00 0.00 ] +Key: PADDQrm: [ 0.00 0.00 ] +Key: PADDQrr: [ 0.00 0.00 ] +Key: PADDSBrm: [ 0.00 0.00 ] +Key: PADDSBrr: [ 0.00 0.00 ] +Key: PADDSWrm: [ 0.00 0.00 ] +Key: PADDSWrr: [ 0.00 0.00 ] +Key: PADDUSBrm: [ 0.00 0.00 ] +Key: PADDUSBrr: [ 0.00 0.00 ] +Key: PADDUSWrm: [ 0.00 0.00 ] +Key: PADDUSWrr: [ 0.00 0.00 ] +Key: PADDWrm: [ 0.00 0.00 ] +Key: PADDWrr: [ 0.00 0.00 ] +Key: PALIGNRrmi: [ 0.00 0.00 ] +Key: PALIGNRrri: [ 0.00 0.00 ] +Key: PANDNrm: [ 0.00 0.00 ] +Key: PANDNrr: [ 0.00 0.00 ] +Key: PANDrm: [ 0.00 0.00 ] +Key: PANDrr: [ 0.00 0.00 ] +Key: PATCHABLE_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_ENTER: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_EXIT: [ 0.00 0.00 ] +Key: PATCHABLE_OP: [ 0.00 0.00 ] +Key: PATCHABLE_RET: [ 0.00 0.00 ] +Key: PATCHABLE_TAIL_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_TYPED_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHPOINT: [ 0.00 0.00 ] +Key: PAUSE: [ 0.00 0.00 ] +Key: PAVGBrm: [ 0.00 0.00 ] +Key: PAVGBrr: [ 0.00 0.00 ] +Key: PAVGUSBrm: [ 0.00 0.00 ] +Key: PAVGUSBrr: [ 0.00 0.00 ] +Key: PAVGWrm: [ 0.00 0.00 ] +Key: PAVGWrr: [ 0.00 0.00 ] +Key: PBLENDVBrm: [ 0.00 0.00 ] +Key: PBLENDVBrr: [ 0.00 0.00 ] +Key: PBLENDWrmi: [ 0.00 0.00 ] +Key: PBLENDWrri: [ 0.00 0.00 ] +Key: PBNDKB: [ 0.00 0.00 ] +Key: PCLMULQDQrmi: [ 0.00 0.00 ] +Key: PCLMULQDQrri: [ 0.00 0.00 ] +Key: PCMPEQBrm: [ 0.00 0.00 ] +Key: PCMPEQBrr: [ 0.00 0.00 ] +Key: PCMPEQDrm: [ 0.00 0.00 ] +Key: PCMPEQDrr: [ 0.00 0.00 ] +Key: PCMPEQQrm: [ 0.00 0.00 ] +Key: PCMPEQQrr: [ 0.00 0.00 ] +Key: PCMPEQWrm: [ 0.00 0.00 ] +Key: PCMPEQWrr: [ 0.00 0.00 ] +Key: PCMPESTRIrmi: [ 0.00 0.00 ] +Key: PCMPESTRIrri: [ 0.00 0.00 ] +Key: PCMPESTRMrmi: [ 0.00 0.00 ] +Key: PCMPESTRMrri: [ 0.00 0.00 ] +Key: PCMPGTBrm: [ 0.00 0.00 ] +Key: PCMPGTBrr: [ 0.00 0.00 ] +Key: PCMPGTDrm: [ 0.00 0.00 ] +Key: PCMPGTDrr: [ 0.00 0.00 ] +Key: PCMPGTQrm: [ 0.00 0.00 ] +Key: PCMPGTQrr: [ 0.00 0.00 ] +Key: PCMPGTWrm: [ 0.00 0.00 ] +Key: PCMPGTWrr: [ 0.00 0.00 ] +Key: PCMPISTRIrmi: [ 0.00 0.00 ] +Key: PCMPISTRIrri: [ 0.00 0.00 ] +Key: PCMPISTRMrmi: [ 0.00 0.00 ] +Key: PCMPISTRMrri: [ 0.00 0.00 ] +Key: PCONFIG: [ 0.00 0.00 ] +Key: PDEP: [ 0.00 0.00 ] +Key: PEXT: [ 0.00 0.00 ] +Key: PEXTRBmri: [ 0.00 0.00 ] +Key: PEXTRBrri: [ 0.00 0.00 ] +Key: PEXTRDmri: [ 0.00 0.00 ] +Key: PEXTRDrri: [ 0.00 0.00 ] +Key: PEXTRQmri: [ 0.00 0.00 ] +Key: PEXTRQrri: [ 0.00 0.00 ] +Key: PEXTRWmri: [ 0.00 0.00 ] +Key: PEXTRWrri: [ 0.00 0.00 ] +Key: PEXTRWrri_REV: [ 0.00 0.00 ] +Key: PF: [ 0.00 0.00 ] +Key: PFACCrm: [ 0.00 0.00 ] +Key: PFACCrr: [ 0.00 0.00 ] +Key: PFADDrm: [ 0.00 0.00 ] +Key: PFADDrr: [ 0.00 0.00 ] +Key: PFCMPEQrm: [ 0.00 0.00 ] +Key: PFCMPEQrr: [ 0.00 0.00 ] +Key: PFCMPGErm: [ 0.00 0.00 ] +Key: PFCMPGErr: [ 0.00 0.00 ] +Key: PFCMPGTrm: [ 0.00 0.00 ] +Key: PFCMPGTrr: [ 0.00 0.00 ] +Key: PFMAXrm: [ 0.00 0.00 ] +Key: PFMAXrr: [ 0.00 0.00 ] +Key: PFMINrm: [ 0.00 0.00 ] +Key: PFMINrr: [ 0.00 0.00 ] +Key: PFMULrm: [ 0.00 0.00 ] +Key: PFMULrr: [ 0.00 0.00 ] +Key: PFNACCrm: [ 0.00 0.00 ] +Key: PFNACCrr: [ 0.00 0.00 ] +Key: PFPNACCrm: [ 0.00 0.00 ] +Key: PFPNACCrr: [ 0.00 0.00 ] +Key: PFRCPIT: [ 0.00 0.00 ] +Key: PFRCPrm: [ 0.00 0.00 ] +Key: PFRCPrr: [ 0.00 0.00 ] +Key: PFRSQIT: [ 0.00 0.00 ] +Key: PFRSQRTrm: [ 0.00 0.00 ] +Key: PFRSQRTrr: [ 0.00 0.00 ] +Key: PFSUBRrm: [ 0.00 0.00 ] +Key: PFSUBRrr: [ 0.00 0.00 ] +Key: PFSUBrm: [ 0.00 0.00 ] +Key: PFSUBrr: [ 0.00 0.00 ] +Key: PHADDDrm: [ 0.00 0.00 ] +Key: PHADDDrr: [ 0.00 0.00 ] +Key: PHADDSWrm: [ 0.00 0.00 ] +Key: PHADDSWrr: [ 0.00 0.00 ] +Key: PHADDWrm: [ 0.00 0.00 ] +Key: PHADDWrr: [ 0.00 0.00 ] +Key: PHI: [ 0.00 0.00 ] +Key: PHMINPOSUWrm: [ 0.00 0.00 ] +Key: PHMINPOSUWrr: [ 0.00 0.00 ] +Key: PHSUBDrm: [ 0.00 0.00 ] +Key: PHSUBDrr: [ 0.00 0.00 ] +Key: PHSUBSWrm: [ 0.00 0.00 ] +Key: PHSUBSWrr: [ 0.00 0.00 ] +Key: PHSUBWrm: [ 0.00 0.00 ] +Key: PHSUBWrr: [ 0.00 0.00 ] +Key: PI: [ 0.00 0.00 ] +Key: PINSRBrmi: [ 0.00 0.00 ] +Key: PINSRBrri: [ 0.00 0.00 ] +Key: PINSRDrmi: [ 0.00 0.00 ] +Key: PINSRDrri: [ 0.00 0.00 ] +Key: PINSRQrmi: [ 0.00 0.00 ] +Key: PINSRQrri: [ 0.00 0.00 ] +Key: PINSRWrmi: [ 0.00 0.00 ] +Key: PINSRWrri: [ 0.00 0.00 ] +Key: PLDTILECFGV: [ 0.00 0.00 ] +Key: PLEA: [ 0.00 0.00 ] +Key: PMADDUBSWrm: [ 0.00 0.00 ] +Key: PMADDUBSWrr: [ 0.00 0.00 ] +Key: PMADDWDrm: [ 0.00 0.00 ] +Key: PMADDWDrr: [ 0.00 0.00 ] +Key: PMAXSBrm: [ 0.00 0.00 ] +Key: PMAXSBrr: [ 0.00 0.00 ] +Key: PMAXSDrm: [ 0.00 0.00 ] +Key: PMAXSDrr: [ 0.00 0.00 ] +Key: PMAXSWrm: [ 0.00 0.00 ] +Key: PMAXSWrr: [ 0.00 0.00 ] +Key: PMAXUBrm: [ 0.00 0.00 ] +Key: PMAXUBrr: [ 0.00 0.00 ] +Key: PMAXUDrm: [ 0.00 0.00 ] +Key: PMAXUDrr: [ 0.00 0.00 ] +Key: PMAXUWrm: [ 0.00 0.00 ] +Key: PMAXUWrr: [ 0.00 0.00 ] +Key: PMINSBrm: [ 0.00 0.00 ] +Key: PMINSBrr: [ 0.00 0.00 ] +Key: PMINSDrm: [ 0.00 0.00 ] +Key: PMINSDrr: [ 0.00 0.00 ] +Key: PMINSWrm: [ 0.00 0.00 ] +Key: PMINSWrr: [ 0.00 0.00 ] +Key: PMINUBrm: [ 0.00 0.00 ] +Key: PMINUBrr: [ 0.00 0.00 ] +Key: PMINUDrm: [ 0.00 0.00 ] +Key: PMINUDrr: [ 0.00 0.00 ] +Key: PMINUWrm: [ 0.00 0.00 ] +Key: PMINUWrr: [ 0.00 0.00 ] +Key: PMOVMSKBrr: [ 0.00 0.00 ] +Key: PMOVSXBDrm: [ 0.00 0.00 ] +Key: PMOVSXBDrr: [ 0.00 0.00 ] +Key: PMOVSXBQrm: [ 0.00 0.00 ] +Key: PMOVSXBQrr: [ 0.00 0.00 ] +Key: PMOVSXBWrm: [ 0.00 0.00 ] +Key: PMOVSXBWrr: [ 0.00 0.00 ] +Key: PMOVSXDQrm: [ 0.00 0.00 ] +Key: PMOVSXDQrr: [ 0.00 0.00 ] +Key: PMOVSXWDrm: [ 0.00 0.00 ] +Key: PMOVSXWDrr: [ 0.00 0.00 ] +Key: PMOVSXWQrm: [ 0.00 0.00 ] +Key: PMOVSXWQrr: [ 0.00 0.00 ] +Key: PMOVZXBDrm: [ 0.00 0.00 ] +Key: PMOVZXBDrr: [ 0.00 0.00 ] +Key: PMOVZXBQrm: [ 0.00 0.00 ] +Key: PMOVZXBQrr: [ 0.00 0.00 ] +Key: PMOVZXBWrm: [ 0.00 0.00 ] +Key: PMOVZXBWrr: [ 0.00 0.00 ] +Key: PMOVZXDQrm: [ 0.00 0.00 ] +Key: PMOVZXDQrr: [ 0.00 0.00 ] +Key: PMOVZXWDrm: [ 0.00 0.00 ] +Key: PMOVZXWDrr: [ 0.00 0.00 ] +Key: PMOVZXWQrm: [ 0.00 0.00 ] +Key: PMOVZXWQrr: [ 0.00 0.00 ] +Key: PMULDQrm: [ 0.00 0.00 ] +Key: PMULDQrr: [ 0.00 0.00 ] +Key: PMULHRSWrm: [ 0.00 0.00 ] +Key: PMULHRSWrr: [ 0.00 0.00 ] +Key: PMULHRWrm: [ 0.00 0.00 ] +Key: PMULHRWrr: [ 0.00 0.00 ] +Key: PMULHUWrm: [ 0.00 0.00 ] +Key: PMULHUWrr: [ 0.00 0.00 ] +Key: PMULHWrm: [ 0.00 0.00 ] +Key: PMULHWrr: [ 0.00 0.00 ] +Key: PMULLDrm: [ 0.00 0.00 ] +Key: PMULLDrr: [ 0.00 0.00 ] +Key: PMULLWrm: [ 0.00 0.00 ] +Key: PMULLWrr: [ 0.00 0.00 ] +Key: PMULUDQrm: [ 0.00 0.00 ] +Key: PMULUDQrr: [ 0.00 0.00 ] +Key: POP: [ 0.00 0.00 ] +Key: POPA: [ 0.00 0.00 ] +Key: POPCNT: [ 0.00 0.00 ] +Key: POPDS: [ 0.00 0.00 ] +Key: POPES: [ 0.00 0.00 ] +Key: POPF: [ 0.00 0.00 ] +Key: POPFS: [ 0.00 0.00 ] +Key: POPGS: [ 0.00 0.00 ] +Key: POPP: [ 0.00 0.00 ] +Key: POPSS: [ 0.00 0.00 ] +Key: PORrm: [ 0.00 0.00 ] +Key: PORrr: [ 0.00 0.00 ] +Key: PREALLOCATED_ARG: [ 0.00 0.00 ] +Key: PREALLOCATED_SETUP: [ 0.00 0.00 ] +Key: PREFETCH: [ 0.00 0.00 ] +Key: PREFETCHIT: [ 0.00 0.00 ] +Key: PREFETCHNTA: [ 0.00 0.00 ] +Key: PREFETCHRST: [ 0.00 0.00 ] +Key: PREFETCHT: [ 0.00 0.00 ] +Key: PREFETCHW: [ 0.00 0.00 ] +Key: PREFETCHWT: [ 0.00 0.00 ] +Key: PROBED_ALLOCA: [ 0.00 0.00 ] +Key: PSADBWrm: [ 0.00 0.00 ] +Key: PSADBWrr: [ 0.00 0.00 ] +Key: PSEUDO_PROBE: [ 0.00 0.00 ] +Key: PSHUFBrm: [ 0.00 0.00 ] +Key: PSHUFBrr: [ 0.00 0.00 ] +Key: PSHUFDmi: [ 0.00 0.00 ] +Key: PSHUFDri: [ 0.00 0.00 ] +Key: PSHUFHWmi: [ 0.00 0.00 ] +Key: PSHUFHWri: [ 0.00 0.00 ] +Key: PSHUFLWmi: [ 0.00 0.00 ] +Key: PSHUFLWri: [ 0.00 0.00 ] +Key: PSIGNBrm: [ 0.00 0.00 ] +Key: PSIGNBrr: [ 0.00 0.00 ] +Key: PSIGNDrm: [ 0.00 0.00 ] +Key: PSIGNDrr: [ 0.00 0.00 ] +Key: PSIGNWrm: [ 0.00 0.00 ] +Key: PSIGNWrr: [ 0.00 0.00 ] +Key: PSLLDQri: [ 0.00 0.00 ] +Key: PSLLDri: [ 0.00 0.00 ] +Key: PSLLDrm: [ 0.00 0.00 ] +Key: PSLLDrr: [ 0.00 0.00 ] +Key: PSLLQri: [ 0.00 0.00 ] +Key: PSLLQrm: [ 0.00 0.00 ] +Key: PSLLQrr: [ 0.00 0.00 ] +Key: PSLLWri: [ 0.00 0.00 ] +Key: PSLLWrm: [ 0.00 0.00 ] +Key: PSLLWrr: [ 0.00 0.00 ] +Key: PSMASH: [ 0.00 0.00 ] +Key: PSRADri: [ 0.00 0.00 ] +Key: PSRADrm: [ 0.00 0.00 ] +Key: PSRADrr: [ 0.00 0.00 ] +Key: PSRAWri: [ 0.00 0.00 ] +Key: PSRAWrm: [ 0.00 0.00 ] +Key: PSRAWrr: [ 0.00 0.00 ] +Key: PSRLDQri: [ 0.00 0.00 ] +Key: PSRLDri: [ 0.00 0.00 ] +Key: PSRLDrm: [ 0.00 0.00 ] +Key: PSRLDrr: [ 0.00 0.00 ] +Key: PSRLQri: [ 0.00 0.00 ] +Key: PSRLQrm: [ 0.00 0.00 ] +Key: PSRLQrr: [ 0.00 0.00 ] +Key: PSRLWri: [ 0.00 0.00 ] +Key: PSRLWrm: [ 0.00 0.00 ] +Key: PSRLWrr: [ 0.00 0.00 ] +Key: PSUBBrm: [ 0.00 0.00 ] +Key: PSUBBrr: [ 0.00 0.00 ] +Key: PSUBDrm: [ 0.00 0.00 ] +Key: PSUBDrr: [ 0.00 0.00 ] +Key: PSUBQrm: [ 0.00 0.00 ] +Key: PSUBQrr: [ 0.00 0.00 ] +Key: PSUBSBrm: [ 0.00 0.00 ] +Key: PSUBSBrr: [ 0.00 0.00 ] +Key: PSUBSWrm: [ 0.00 0.00 ] +Key: PSUBSWrr: [ 0.00 0.00 ] +Key: PSUBUSBrm: [ 0.00 0.00 ] +Key: PSUBUSBrr: [ 0.00 0.00 ] +Key: PSUBUSWrm: [ 0.00 0.00 ] +Key: PSUBUSWrr: [ 0.00 0.00 ] +Key: PSUBWrm: [ 0.00 0.00 ] +Key: PSUBWrr: [ 0.00 0.00 ] +Key: PSWAPDrm: [ 0.00 0.00 ] +Key: PSWAPDrr: [ 0.00 0.00 ] +Key: PT: [ 0.00 0.00 ] +Key: PTCMMIMFP: [ 0.00 0.00 ] +Key: PTCMMRLFP: [ 0.00 0.00 ] +Key: PTCONJTCMMIMFP: [ 0.00 0.00 ] +Key: PTCONJTFP: [ 0.00 0.00 ] +Key: PTCVTROWD: [ 0.00 0.00 ] +Key: PTCVTROWPS: [ 0.00 0.00 ] +Key: PTDPBF: [ 0.00 0.00 ] +Key: PTDPBHF: [ 0.00 0.00 ] +Key: PTDPBSSD: [ 0.00 0.00 ] +Key: PTDPBSSDV: [ 0.00 0.00 ] +Key: PTDPBSUD: [ 0.00 0.00 ] +Key: PTDPBSUDV: [ 0.00 0.00 ] +Key: PTDPBUSD: [ 0.00 0.00 ] +Key: PTDPBUSDV: [ 0.00 0.00 ] +Key: PTDPBUUD: [ 0.00 0.00 ] +Key: PTDPBUUDV: [ 0.00 0.00 ] +Key: PTDPFP: [ 0.00 0.00 ] +Key: PTDPHBF: [ 0.00 0.00 ] +Key: PTDPHF: [ 0.00 0.00 ] +Key: PTESTrm: [ 0.00 0.00 ] +Key: PTESTrr: [ 0.00 0.00 ] +Key: PTILELOADD: [ 0.00 0.00 ] +Key: PTILELOADDRS: [ 0.00 0.00 ] +Key: PTILELOADDRST: [ 0.00 0.00 ] +Key: PTILELOADDRSV: [ 0.00 0.00 ] +Key: PTILELOADDT: [ 0.00 0.00 ] +Key: PTILELOADDV: [ 0.00 0.00 ] +Key: PTILEMOVROWrre: [ 0.00 0.00 ] +Key: PTILEMOVROWrreV: [ 0.00 0.00 ] +Key: PTILEMOVROWrri: [ 0.00 0.00 ] +Key: PTILEMOVROWrriV: [ 0.00 0.00 ] +Key: PTILEPAIRLOAD: [ 0.00 0.00 ] +Key: PTILEPAIRSTORE: [ 0.00 0.00 ] +Key: PTILESTORED: [ 0.00 0.00 ] +Key: PTILESTOREDV: [ 0.00 0.00 ] +Key: PTILEZERO: [ 0.00 0.00 ] +Key: PTILEZEROV: [ 0.00 0.00 ] +Key: PTMMULTF: [ 0.00 0.00 ] +Key: PTTCMMIMFP: [ 0.00 0.00 ] +Key: PTTCMMRLFP: [ 0.00 0.00 ] +Key: PTTDPBF: [ 0.00 0.00 ] +Key: PTTDPFP: [ 0.00 0.00 ] +Key: PTTMMULTF: [ 0.00 0.00 ] +Key: PTTRANSPOSED: [ 0.00 0.00 ] +Key: PTTRANSPOSEDV: [ 0.00 0.00 ] +Key: PTWRITE: [ 0.00 0.00 ] +Key: PTWRITEm: [ 0.00 0.00 ] +Key: PTWRITEr: [ 0.00 0.00 ] +Key: PUNPCKHBWrm: [ 0.00 0.00 ] +Key: PUNPCKHBWrr: [ 0.00 0.00 ] +Key: PUNPCKHDQrm: [ 0.00 0.00 ] +Key: PUNPCKHDQrr: [ 0.00 0.00 ] +Key: PUNPCKHQDQrm: [ 0.00 0.00 ] +Key: PUNPCKHQDQrr: [ 0.00 0.00 ] +Key: PUNPCKHWDrm: [ 0.00 0.00 ] +Key: PUNPCKHWDrr: [ 0.00 0.00 ] +Key: PUNPCKLBWrm: [ 0.00 0.00 ] +Key: PUNPCKLBWrr: [ 0.00 0.00 ] +Key: PUNPCKLDQrm: [ 0.00 0.00 ] +Key: PUNPCKLDQrr: [ 0.00 0.00 ] +Key: PUNPCKLQDQrm: [ 0.00 0.00 ] +Key: PUNPCKLQDQrr: [ 0.00 0.00 ] +Key: PUNPCKLWDrm: [ 0.00 0.00 ] +Key: PUNPCKLWDrr: [ 0.00 0.00 ] +Key: PUSH: [ 0.00 0.00 ] +Key: PUSHA: [ 0.00 0.00 ] +Key: PUSHCS: [ 0.00 0.00 ] +Key: PUSHDS: [ 0.00 0.00 ] +Key: PUSHES: [ 0.00 0.00 ] +Key: PUSHF: [ 0.00 0.00 ] +Key: PUSHFS: [ 0.00 0.00 ] +Key: PUSHGS: [ 0.00 0.00 ] +Key: PUSHP: [ 0.00 0.00 ] +Key: PUSHSS: [ 0.00 0.00 ] +Key: PVALIDATE: [ 0.00 0.00 ] +Key: PXORrm: [ 0.00 0.00 ] +Key: PXORrr: [ 0.00 0.00 ] +Key: RCL: [ 0.00 0.00 ] +Key: RCPPSm: [ 0.00 0.00 ] +Key: RCPPSr: [ 0.00 0.00 ] +Key: RCPSSm: [ 0.00 0.00 ] +Key: RCPSSm_Int: [ 0.00 0.00 ] +Key: RCPSSr: [ 0.00 0.00 ] +Key: RCPSSr_Int: [ 0.00 0.00 ] +Key: RCR: [ 0.00 0.00 ] +Key: RDFLAGS: [ 0.00 0.00 ] +Key: RDFSBASE: [ 0.00 0.00 ] +Key: RDGSBASE: [ 0.00 0.00 ] +Key: RDMSR: [ 0.00 0.00 ] +Key: RDMSRLIST: [ 0.00 0.00 ] +Key: RDMSRri: [ 0.00 0.00 ] +Key: RDMSRri_EVEX: [ 0.00 0.00 ] +Key: RDPID: [ 0.00 0.00 ] +Key: RDPKRUr: [ 0.00 0.00 ] +Key: RDPMC: [ 0.00 0.00 ] +Key: RDPRU: [ 0.00 0.00 ] +Key: RDRAND: [ 0.00 0.00 ] +Key: RDSEED: [ 0.00 0.00 ] +Key: RDSSPD: [ 0.00 0.00 ] +Key: RDSSPQ: [ 0.00 0.00 ] +Key: RDTSC: [ 0.00 0.00 ] +Key: RDTSCP: [ 0.00 0.00 ] +Key: REG_SEQUENCE: [ 0.00 0.00 ] +Key: REPNE_PREFIX: [ 0.00 0.00 ] +Key: REP_MOVSB: [ 0.00 0.00 ] +Key: REP_MOVSD: [ 0.00 0.00 ] +Key: REP_MOVSQ: [ 0.00 0.00 ] +Key: REP_MOVSW: [ 0.00 0.00 ] +Key: REP_PREFIX: [ 0.00 0.00 ] +Key: REP_STOSB: [ 0.00 0.00 ] +Key: REP_STOSD: [ 0.00 0.00 ] +Key: REP_STOSQ: [ 0.00 0.00 ] +Key: REP_STOSW: [ 0.00 0.00 ] +Key: RET: [ 0.00 0.00 ] +Key: RETI: [ 0.00 0.00 ] +Key: REX: [ 0.00 0.00 ] +Key: RMPADJUST: [ 0.00 0.00 ] +Key: RMPQUERY: [ 0.00 0.00 ] +Key: RMPUPDATE: [ 0.00 0.00 ] +Key: ROL: [ 0.00 0.00 ] +Key: ROR: [ 0.00 0.00 ] +Key: RORX: [ 0.00 0.00 ] +Key: ROUNDPDmi: [ 0.00 0.00 ] +Key: ROUNDPDri: [ 0.00 0.00 ] +Key: ROUNDPSmi: [ 0.00 0.00 ] +Key: ROUNDPSri: [ 0.00 0.00 ] +Key: ROUNDSDmi: [ 0.00 0.00 ] +Key: ROUNDSDmi_Int: [ 0.00 0.00 ] +Key: ROUNDSDri: [ 0.00 0.00 ] +Key: ROUNDSDri_Int: [ 0.00 0.00 ] +Key: ROUNDSSmi: [ 0.00 0.00 ] +Key: ROUNDSSmi_Int: [ 0.00 0.00 ] +Key: ROUNDSSri: [ 0.00 0.00 ] +Key: ROUNDSSri_Int: [ 0.00 0.00 ] +Key: RSM: [ 0.00 0.00 ] +Key: RSQRTPSm: [ 0.00 0.00 ] +Key: RSQRTPSr: [ 0.00 0.00 ] +Key: RSQRTSSm: [ 0.00 0.00 ] +Key: RSQRTSSm_Int: [ 0.00 0.00 ] +Key: RSQRTSSr: [ 0.00 0.00 ] +Key: RSQRTSSr_Int: [ 0.00 0.00 ] +Key: RSTORSSP: [ 0.00 0.00 ] +Key: SAHF: [ 0.00 0.00 ] +Key: SALC: [ 0.00 0.00 ] +Key: SAR: [ 0.00 0.00 ] +Key: SARX: [ 0.00 0.00 ] +Key: SAVEPREVSSP: [ 0.00 0.00 ] +Key: SBB: [ 0.00 0.00 ] +Key: SCASB: [ 0.00 0.00 ] +Key: SCASL: [ 0.00 0.00 ] +Key: SCASQ: [ 0.00 0.00 ] +Key: SCASW: [ 0.00 0.00 ] +Key: SEAMCALL: [ 0.00 0.00 ] +Key: SEAMOPS: [ 0.00 0.00 ] +Key: SEAMRET: [ 0.00 0.00 ] +Key: SEG_ALLOCA: [ 0.00 0.00 ] +Key: SEH_BeginEpilogue: [ 0.00 0.00 ] +Key: SEH_EndEpilogue: [ 0.00 0.00 ] +Key: SEH_EndPrologue: [ 0.00 0.00 ] +Key: SEH_PushFrame: [ 0.00 0.00 ] +Key: SEH_PushReg: [ 0.00 0.00 ] +Key: SEH_SaveReg: [ 0.00 0.00 ] +Key: SEH_SaveXMM: [ 0.00 0.00 ] +Key: SEH_SetFrame: [ 0.00 0.00 ] +Key: SEH_StackAlign: [ 0.00 0.00 ] +Key: SEH_StackAlloc: [ 0.00 0.00 ] +Key: SEH_UnwindV: [ 0.00 0.00 ] +Key: SEH_UnwindVersion: [ 0.00 0.00 ] +Key: SENDUIPI: [ 0.00 0.00 ] +Key: SERIALIZE: [ 0.00 0.00 ] +Key: SETB_C: [ 0.00 0.00 ] +Key: SETCCm: [ 0.00 0.00 ] +Key: SETCCm_EVEX: [ 0.00 0.00 ] +Key: SETCCr: [ 0.00 0.00 ] +Key: SETCCr_EVEX: [ 0.00 0.00 ] +Key: SETSSBSY: [ 0.00 0.00 ] +Key: SETZUCCm: [ 0.00 0.00 ] +Key: SETZUCCr: [ 0.00 0.00 ] +Key: SFENCE: [ 0.00 0.00 ] +Key: SGDT: [ 0.00 0.00 ] +Key: SHA: [ 0.00 0.00 ] +Key: SHL: [ 0.00 0.00 ] +Key: SHLD: [ 0.00 0.00 ] +Key: SHLDROT: [ 0.00 0.00 ] +Key: SHLX: [ 0.00 0.00 ] +Key: SHR: [ 0.00 0.00 ] +Key: SHRD: [ 0.00 0.00 ] +Key: SHRDROT: [ 0.00 0.00 ] +Key: SHRX: [ 0.00 0.00 ] +Key: SHUFPDrmi: [ 0.00 0.00 ] +Key: SHUFPDrri: [ 0.00 0.00 ] +Key: SHUFPSrmi: [ 0.00 0.00 ] +Key: SHUFPSrri: [ 0.00 0.00 ] +Key: SIDT: [ 0.00 0.00 ] +Key: SKINIT: [ 0.00 0.00 ] +Key: SLDT: [ 0.00 0.00 ] +Key: SLWPCB: [ 0.00 0.00 ] +Key: SMSW: [ 0.00 0.00 ] +Key: SQRTPDm: [ 0.00 0.00 ] +Key: SQRTPDr: [ 0.00 0.00 ] +Key: SQRTPSm: [ 0.00 0.00 ] +Key: SQRTPSr: [ 0.00 0.00 ] +Key: SQRTSDm: [ 0.00 0.00 ] +Key: SQRTSDm_Int: [ 0.00 0.00 ] +Key: SQRTSDr: [ 0.00 0.00 ] +Key: SQRTSDr_Int: [ 0.00 0.00 ] +Key: SQRTSSm: [ 0.00 0.00 ] +Key: SQRTSSm_Int: [ 0.00 0.00 ] +Key: SQRTSSr: [ 0.00 0.00 ] +Key: SQRTSSr_Int: [ 0.00 0.00 ] +Key: SQRT_F: [ 0.00 0.00 ] +Key: SQRT_Fp: [ 0.00 0.00 ] +Key: SS_PREFIX: [ 0.00 0.00 ] +Key: STAC: [ 0.00 0.00 ] +Key: STACKALLOC_W_PROBING: [ 0.00 0.00 ] +Key: STACKMAP: [ 0.00 0.00 ] +Key: STATEPOINT: [ 0.00 0.00 ] +Key: STC: [ 0.00 0.00 ] +Key: STD: [ 0.00 0.00 ] +Key: STGI: [ 0.00 0.00 ] +Key: STI: [ 0.00 0.00 ] +Key: STMXCSR: [ 0.00 0.00 ] +Key: STOSB: [ 0.00 0.00 ] +Key: STOSL: [ 0.00 0.00 ] +Key: STOSQ: [ 0.00 0.00 ] +Key: STOSW: [ 0.00 0.00 ] +Key: STR: [ 0.00 0.00 ] +Key: STRm: [ 0.00 0.00 ] +Key: STTILECFG: [ 0.00 0.00 ] +Key: STTILECFG_EVEX: [ 0.00 0.00 ] +Key: STUI: [ 0.00 0.00 ] +Key: ST_F: [ 0.00 0.00 ] +Key: ST_FP: [ 0.00 0.00 ] +Key: ST_FPrr: [ 0.00 0.00 ] +Key: ST_Fp: [ 0.00 0.00 ] +Key: ST_FpP: [ 0.00 0.00 ] +Key: ST_Frr: [ 0.00 0.00 ] +Key: SUB: [ 0.00 0.00 ] +Key: SUBPDrm: [ 0.00 0.00 ] +Key: SUBPDrr: [ 0.00 0.00 ] +Key: SUBPSrm: [ 0.00 0.00 ] +Key: SUBPSrr: [ 0.00 0.00 ] +Key: SUBREG_TO_REG: [ 0.00 0.00 ] +Key: SUBR_F: [ 0.00 0.00 ] +Key: SUBR_FI: [ 0.00 0.00 ] +Key: SUBR_FPrST: [ 0.00 0.00 ] +Key: SUBR_FST: [ 0.00 0.00 ] +Key: SUBR_Fp: [ 0.00 0.00 ] +Key: SUBR_FpI: [ 0.00 0.00 ] +Key: SUBR_FrST: [ 0.00 0.00 ] +Key: SUBSDrm: [ 0.00 0.00 ] +Key: SUBSDrm_Int: [ 0.00 0.00 ] +Key: SUBSDrr: [ 0.00 0.00 ] +Key: SUBSDrr_Int: [ 0.00 0.00 ] +Key: SUBSSrm: [ 0.00 0.00 ] +Key: SUBSSrm_Int: [ 0.00 0.00 ] +Key: SUBSSrr: [ 0.00 0.00 ] +Key: SUBSSrr_Int: [ 0.00 0.00 ] +Key: SUB_F: [ 0.00 0.00 ] +Key: SUB_FI: [ 0.00 0.00 ] +Key: SUB_FPrST: [ 0.00 0.00 ] +Key: SUB_FST: [ 0.00 0.00 ] +Key: SUB_Fp: [ 0.00 0.00 ] +Key: SUB_FpI: [ 0.00 0.00 ] +Key: SUB_FrST: [ 0.00 0.00 ] +Key: SWAPGS: [ 0.00 0.00 ] +Key: SYSCALL: [ 0.00 0.00 ] +Key: SYSENTER: [ 0.00 0.00 ] +Key: SYSEXIT: [ 0.00 0.00 ] +Key: SYSRET: [ 0.00 0.00 ] +Key: T: [ 0.00 0.00 ] +Key: TAILJMPd: [ 0.00 0.00 ] +Key: TAILJMPd_CC: [ 0.00 0.00 ] +Key: TAILJMPm: [ 0.00 0.00 ] +Key: TAILJMPr: [ 0.00 0.00 ] +Key: TCMMIMFP: [ 0.00 0.00 ] +Key: TCMMRLFP: [ 0.00 0.00 ] +Key: TCONJTCMMIMFP: [ 0.00 0.00 ] +Key: TCONJTFP: [ 0.00 0.00 ] +Key: TCRETURN_HIPE: [ 0.00 0.00 ] +Key: TCRETURN_WIN: [ 0.00 0.00 ] +Key: TCRETURN_WINmi: [ 0.00 0.00 ] +Key: TCRETURNdi: [ 0.00 0.00 ] +Key: TCRETURNdicc: [ 0.00 0.00 ] +Key: TCRETURNmi: [ 0.00 0.00 ] +Key: TCRETURNri: [ 0.00 0.00 ] +Key: TCVTROWD: [ 0.00 0.00 ] +Key: TCVTROWPS: [ 0.00 0.00 ] +Key: TDCALL: [ 0.00 0.00 ] +Key: TDPBF: [ 0.00 0.00 ] +Key: TDPBHF: [ 0.00 0.00 ] +Key: TDPBSSD: [ 0.00 0.00 ] +Key: TDPBSUD: [ 0.00 0.00 ] +Key: TDPBUSD: [ 0.00 0.00 ] +Key: TDPBUUD: [ 0.00 0.00 ] +Key: TDPFP: [ 0.00 0.00 ] +Key: TDPHBF: [ 0.00 0.00 ] +Key: TDPHF: [ 0.00 0.00 ] +Key: TEST: [ 0.00 0.00 ] +Key: TESTUI: [ 0.00 0.00 ] +Key: TILELOADD: [ 0.00 0.00 ] +Key: TILELOADDRS: [ 0.00 0.00 ] +Key: TILELOADDRST: [ 0.00 0.00 ] +Key: TILELOADDRS_EVEX: [ 0.00 0.00 ] +Key: TILELOADDT: [ 0.00 0.00 ] +Key: TILELOADD_EVEX: [ 0.00 0.00 ] +Key: TILEMOVROWrre: [ 0.00 0.00 ] +Key: TILEMOVROWrri: [ 0.00 0.00 ] +Key: TILERELEASE: [ 0.00 0.00 ] +Key: TILESTORED: [ 0.00 0.00 ] +Key: TILESTORED_EVEX: [ 0.00 0.00 ] +Key: TILEZERO: [ 0.00 0.00 ] +Key: TLBSYNC: [ 0.00 0.00 ] +Key: TLSCall: [ 0.00 0.00 ] +Key: TLS_addr: [ 0.00 0.00 ] +Key: TLS_addrX: [ 0.00 0.00 ] +Key: TLS_base_addr: [ 0.00 0.00 ] +Key: TLS_base_addrX: [ 0.00 0.00 ] +Key: TLS_desc: [ 0.00 0.00 ] +Key: TMMULTF: [ 0.00 0.00 ] +Key: TPAUSE: [ 0.00 0.00 ] +Key: TRAP: [ 0.00 0.00 ] +Key: TST_F: [ 0.00 0.00 ] +Key: TST_Fp: [ 0.00 0.00 ] +Key: TTCMMIMFP: [ 0.00 0.00 ] +Key: TTCMMRLFP: [ 0.00 0.00 ] +Key: TTDPBF: [ 0.00 0.00 ] +Key: TTDPFP: [ 0.00 0.00 ] +Key: TTMMULTF: [ 0.00 0.00 ] +Key: TTRANSPOSED: [ 0.00 0.00 ] +Key: TZCNT: [ 0.00 0.00 ] +Key: TZMSK: [ 0.00 0.00 ] +Key: UBSAN_UD: [ 0.00 0.00 ] +Key: UCOMISDrm: [ 0.00 0.00 ] +Key: UCOMISDrm_Int: [ 0.00 0.00 ] +Key: UCOMISDrr: [ 0.00 0.00 ] +Key: UCOMISDrr_Int: [ 0.00 0.00 ] +Key: UCOMISSrm: [ 0.00 0.00 ] +Key: UCOMISSrm_Int: [ 0.00 0.00 ] +Key: UCOMISSrr: [ 0.00 0.00 ] +Key: UCOMISSrr_Int: [ 0.00 0.00 ] +Key: UCOM_FIPr: [ 0.00 0.00 ] +Key: UCOM_FIr: [ 0.00 0.00 ] +Key: UCOM_FPPr: [ 0.00 0.00 ] +Key: UCOM_FPr: [ 0.00 0.00 ] +Key: UCOM_FpIr: [ 0.00 0.00 ] +Key: UCOM_Fpr: [ 0.00 0.00 ] +Key: UCOM_Fr: [ 0.00 0.00 ] +Key: UD: [ 0.00 0.00 ] +Key: UIRET: [ 0.00 0.00 ] +Key: UMONITOR: [ 0.00 0.00 ] +Key: UMWAIT: [ 0.00 0.00 ] +Key: UNPCKHPDrm: [ 0.00 0.00 ] +Key: UNPCKHPDrr: [ 0.00 0.00 ] +Key: UNPCKHPSrm: [ 0.00 0.00 ] +Key: UNPCKHPSrr: [ 0.00 0.00 ] +Key: UNPCKLPDrm: [ 0.00 0.00 ] +Key: UNPCKLPDrr: [ 0.00 0.00 ] +Key: UNPCKLPSrm: [ 0.00 0.00 ] +Key: UNPCKLPSrr: [ 0.00 0.00 ] +Key: URDMSRri: [ 0.00 0.00 ] +Key: URDMSRri_EVEX: [ 0.00 0.00 ] +Key: URDMSRrr: [ 0.00 0.00 ] +Key: URDMSRrr_EVEX: [ 0.00 0.00 ] +Key: UWRMSRir: [ 0.00 0.00 ] +Key: UWRMSRir_EVEX: [ 0.00 0.00 ] +Key: UWRMSRrr: [ 0.00 0.00 ] +Key: UWRMSRrr_EVEX: [ 0.00 0.00 ] +Key: V: [ 0.00 0.00 ] +Key: VAARG: [ 0.00 0.00 ] +Key: VAARG_X: [ 0.00 0.00 ] +Key: VADDBF: [ 0.00 0.00 ] +Key: VADDPDYrm: [ 0.00 0.00 ] +Key: VADDPDYrr: [ 0.00 0.00 ] +Key: VADDPDZ: [ 0.00 0.00 ] +Key: VADDPDZrm: [ 0.00 0.00 ] +Key: VADDPDZrmb: [ 0.00 0.00 ] +Key: VADDPDZrmbk: [ 0.00 0.00 ] +Key: VADDPDZrmbkz: [ 0.00 0.00 ] +Key: VADDPDZrmk: [ 0.00 0.00 ] +Key: VADDPDZrmkz: [ 0.00 0.00 ] +Key: VADDPDZrr: [ 0.00 0.00 ] +Key: VADDPDZrrb: [ 0.00 0.00 ] +Key: VADDPDZrrbk: [ 0.00 0.00 ] +Key: VADDPDZrrbkz: [ 0.00 0.00 ] +Key: VADDPDZrrk: [ 0.00 0.00 ] +Key: VADDPDZrrkz: [ 0.00 0.00 ] +Key: VADDPDrm: [ 0.00 0.00 ] +Key: VADDPDrr: [ 0.00 0.00 ] +Key: VADDPHZ: [ 0.00 0.00 ] +Key: VADDPHZrm: [ 0.00 0.00 ] +Key: VADDPHZrmb: [ 0.00 0.00 ] +Key: VADDPHZrmbk: [ 0.00 0.00 ] +Key: VADDPHZrmbkz: [ 0.00 0.00 ] +Key: VADDPHZrmk: [ 0.00 0.00 ] +Key: VADDPHZrmkz: [ 0.00 0.00 ] +Key: VADDPHZrr: [ 0.00 0.00 ] +Key: VADDPHZrrb: [ 0.00 0.00 ] +Key: VADDPHZrrbk: [ 0.00 0.00 ] +Key: VADDPHZrrbkz: [ 0.00 0.00 ] +Key: VADDPHZrrk: [ 0.00 0.00 ] +Key: VADDPHZrrkz: [ 0.00 0.00 ] +Key: VADDPSYrm: [ 0.00 0.00 ] +Key: VADDPSYrr: [ 0.00 0.00 ] +Key: VADDPSZ: [ 0.00 0.00 ] +Key: VADDPSZrm: [ 0.00 0.00 ] +Key: VADDPSZrmb: [ 0.00 0.00 ] +Key: VADDPSZrmbk: [ 0.00 0.00 ] +Key: VADDPSZrmbkz: [ 0.00 0.00 ] +Key: VADDPSZrmk: [ 0.00 0.00 ] +Key: VADDPSZrmkz: [ 0.00 0.00 ] +Key: VADDPSZrr: [ 0.00 0.00 ] +Key: VADDPSZrrb: [ 0.00 0.00 ] +Key: VADDPSZrrbk: [ 0.00 0.00 ] +Key: VADDPSZrrbkz: [ 0.00 0.00 ] +Key: VADDPSZrrk: [ 0.00 0.00 ] +Key: VADDPSZrrkz: [ 0.00 0.00 ] +Key: VADDPSrm: [ 0.00 0.00 ] +Key: VADDPSrr: [ 0.00 0.00 ] +Key: VADDSDZrm: [ 0.00 0.00 ] +Key: VADDSDZrm_Int: [ 0.00 0.00 ] +Key: VADDSDZrmk_Int: [ 0.00 0.00 ] +Key: VADDSDZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrr: [ 0.00 0.00 ] +Key: VADDSDZrr_Int: [ 0.00 0.00 ] +Key: VADDSDZrrb_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrrk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSDrm: [ 0.00 0.00 ] +Key: VADDSDrm_Int: [ 0.00 0.00 ] +Key: VADDSDrr: [ 0.00 0.00 ] +Key: VADDSDrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrm: [ 0.00 0.00 ] +Key: VADDSHZrm_Int: [ 0.00 0.00 ] +Key: VADDSHZrmk_Int: [ 0.00 0.00 ] +Key: VADDSHZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrr: [ 0.00 0.00 ] +Key: VADDSHZrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrrb_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrrk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrm: [ 0.00 0.00 ] +Key: VADDSSZrm_Int: [ 0.00 0.00 ] +Key: VADDSSZrmk_Int: [ 0.00 0.00 ] +Key: VADDSSZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrr: [ 0.00 0.00 ] +Key: VADDSSZrr_Int: [ 0.00 0.00 ] +Key: VADDSSZrrb_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrrk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSrm: [ 0.00 0.00 ] +Key: VADDSSrm_Int: [ 0.00 0.00 ] +Key: VADDSSrr: [ 0.00 0.00 ] +Key: VADDSSrr_Int: [ 0.00 0.00 ] +Key: VADDSUBPDYrm: [ 0.00 0.00 ] +Key: VADDSUBPDYrr: [ 0.00 0.00 ] +Key: VADDSUBPDrm: [ 0.00 0.00 ] +Key: VADDSUBPDrr: [ 0.00 0.00 ] +Key: VADDSUBPSYrm: [ 0.00 0.00 ] +Key: VADDSUBPSYrr: [ 0.00 0.00 ] +Key: VADDSUBPSrm: [ 0.00 0.00 ] +Key: VADDSUBPSrr: [ 0.00 0.00 ] +Key: VAESDECLASTYrm: [ 0.00 0.00 ] +Key: VAESDECLASTYrr: [ 0.00 0.00 ] +Key: VAESDECLASTZ: [ 0.00 0.00 ] +Key: VAESDECLASTZrm: [ 0.00 0.00 ] +Key: VAESDECLASTZrr: [ 0.00 0.00 ] +Key: VAESDECLASTrm: [ 0.00 0.00 ] +Key: VAESDECLASTrr: [ 0.00 0.00 ] +Key: VAESDECYrm: [ 0.00 0.00 ] +Key: VAESDECYrr: [ 0.00 0.00 ] +Key: VAESDECZ: [ 0.00 0.00 ] +Key: VAESDECZrm: [ 0.00 0.00 ] +Key: VAESDECZrr: [ 0.00 0.00 ] +Key: VAESDECrm: [ 0.00 0.00 ] +Key: VAESDECrr: [ 0.00 0.00 ] +Key: VAESENCLASTYrm: [ 0.00 0.00 ] +Key: VAESENCLASTYrr: [ 0.00 0.00 ] +Key: VAESENCLASTZ: [ 0.00 0.00 ] +Key: VAESENCLASTZrm: [ 0.00 0.00 ] +Key: VAESENCLASTZrr: [ 0.00 0.00 ] +Key: VAESENCLASTrm: [ 0.00 0.00 ] +Key: VAESENCLASTrr: [ 0.00 0.00 ] +Key: VAESENCYrm: [ 0.00 0.00 ] +Key: VAESENCYrr: [ 0.00 0.00 ] +Key: VAESENCZ: [ 0.00 0.00 ] +Key: VAESENCZrm: [ 0.00 0.00 ] +Key: VAESENCZrr: [ 0.00 0.00 ] +Key: VAESENCrm: [ 0.00 0.00 ] +Key: VAESENCrr: [ 0.00 0.00 ] +Key: VAESIMCrm: [ 0.00 0.00 ] +Key: VAESIMCrr: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: VALIGNDZ: [ 0.00 0.00 ] +Key: VALIGNDZrmbi: [ 0.00 0.00 ] +Key: VALIGNDZrmbik: [ 0.00 0.00 ] +Key: VALIGNDZrmbikz: [ 0.00 0.00 ] +Key: VALIGNDZrmi: [ 0.00 0.00 ] +Key: VALIGNDZrmik: [ 0.00 0.00 ] +Key: VALIGNDZrmikz: [ 0.00 0.00 ] +Key: VALIGNDZrri: [ 0.00 0.00 ] +Key: VALIGNDZrrik: [ 0.00 0.00 ] +Key: VALIGNDZrrikz: [ 0.00 0.00 ] +Key: VALIGNQZ: [ 0.00 0.00 ] +Key: VALIGNQZrmbi: [ 0.00 0.00 ] +Key: VALIGNQZrmbik: [ 0.00 0.00 ] +Key: VALIGNQZrmbikz: [ 0.00 0.00 ] +Key: VALIGNQZrmi: [ 0.00 0.00 ] +Key: VALIGNQZrmik: [ 0.00 0.00 ] +Key: VALIGNQZrmikz: [ 0.00 0.00 ] +Key: VALIGNQZrri: [ 0.00 0.00 ] +Key: VALIGNQZrrik: [ 0.00 0.00 ] +Key: VALIGNQZrrikz: [ 0.00 0.00 ] +Key: VANDNPDYrm: [ 0.00 0.00 ] +Key: VANDNPDYrr: [ 0.00 0.00 ] +Key: VANDNPDZ: [ 0.00 0.00 ] +Key: VANDNPDZrm: [ 0.00 0.00 ] +Key: VANDNPDZrmb: [ 0.00 0.00 ] +Key: VANDNPDZrmbk: [ 0.00 0.00 ] +Key: VANDNPDZrmbkz: [ 0.00 0.00 ] +Key: VANDNPDZrmk: [ 0.00 0.00 ] +Key: VANDNPDZrmkz: [ 0.00 0.00 ] +Key: VANDNPDZrr: [ 0.00 0.00 ] +Key: VANDNPDZrrk: [ 0.00 0.00 ] +Key: VANDNPDZrrkz: [ 0.00 0.00 ] +Key: VANDNPDrm: [ 0.00 0.00 ] +Key: VANDNPDrr: [ 0.00 0.00 ] +Key: VANDNPSYrm: [ 0.00 0.00 ] +Key: VANDNPSYrr: [ 0.00 0.00 ] +Key: VANDNPSZ: [ 0.00 0.00 ] +Key: VANDNPSZrm: [ 0.00 0.00 ] +Key: VANDNPSZrmb: [ 0.00 0.00 ] +Key: VANDNPSZrmbk: [ 0.00 0.00 ] +Key: VANDNPSZrmbkz: [ 0.00 0.00 ] +Key: VANDNPSZrmk: [ 0.00 0.00 ] +Key: VANDNPSZrmkz: [ 0.00 0.00 ] +Key: VANDNPSZrr: [ 0.00 0.00 ] +Key: VANDNPSZrrk: [ 0.00 0.00 ] +Key: VANDNPSZrrkz: [ 0.00 0.00 ] +Key: VANDNPSrm: [ 0.00 0.00 ] +Key: VANDNPSrr: [ 0.00 0.00 ] +Key: VANDPDYrm: [ 0.00 0.00 ] +Key: VANDPDYrr: [ 0.00 0.00 ] +Key: VANDPDZ: [ 0.00 0.00 ] +Key: VANDPDZrm: [ 0.00 0.00 ] +Key: VANDPDZrmb: [ 0.00 0.00 ] +Key: VANDPDZrmbk: [ 0.00 0.00 ] +Key: VANDPDZrmbkz: [ 0.00 0.00 ] +Key: VANDPDZrmk: [ 0.00 0.00 ] +Key: VANDPDZrmkz: [ 0.00 0.00 ] +Key: VANDPDZrr: [ 0.00 0.00 ] +Key: VANDPDZrrk: [ 0.00 0.00 ] +Key: VANDPDZrrkz: [ 0.00 0.00 ] +Key: VANDPDrm: [ 0.00 0.00 ] +Key: VANDPDrr: [ 0.00 0.00 ] +Key: VANDPSYrm: [ 0.00 0.00 ] +Key: VANDPSYrr: [ 0.00 0.00 ] +Key: VANDPSZ: [ 0.00 0.00 ] +Key: VANDPSZrm: [ 0.00 0.00 ] +Key: VANDPSZrmb: [ 0.00 0.00 ] +Key: VANDPSZrmbk: [ 0.00 0.00 ] +Key: VANDPSZrmbkz: [ 0.00 0.00 ] +Key: VANDPSZrmk: [ 0.00 0.00 ] +Key: VANDPSZrmkz: [ 0.00 0.00 ] +Key: VANDPSZrr: [ 0.00 0.00 ] +Key: VANDPSZrrk: [ 0.00 0.00 ] +Key: VANDPSZrrkz: [ 0.00 0.00 ] +Key: VANDPSrm: [ 0.00 0.00 ] +Key: VANDPSrr: [ 0.00 0.00 ] +Key: VASTART_SAVE_XMM_REGS: [ 0.00 0.00 ] +Key: VBCSTNEBF: [ 0.00 0.00 ] +Key: VBCSTNESH: [ 0.00 0.00 ] +Key: VBLENDMPDZ: [ 0.00 0.00 ] +Key: VBLENDMPDZrm: [ 0.00 0.00 ] +Key: VBLENDMPDZrmb: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrmk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrr: [ 0.00 0.00 ] +Key: VBLENDMPDZrrk: [ 0.00 0.00 ] +Key: VBLENDMPDZrrkz: [ 0.00 0.00 ] +Key: VBLENDMPSZ: [ 0.00 0.00 ] +Key: VBLENDMPSZrm: [ 0.00 0.00 ] +Key: VBLENDMPSZrmb: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrmk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrr: [ 0.00 0.00 ] +Key: VBLENDMPSZrrk: [ 0.00 0.00 ] +Key: VBLENDMPSZrrkz: [ 0.00 0.00 ] +Key: VBLENDPDYrmi: [ 0.00 0.00 ] +Key: VBLENDPDYrri: [ 0.00 0.00 ] +Key: VBLENDPDrmi: [ 0.00 0.00 ] +Key: VBLENDPDrri: [ 0.00 0.00 ] +Key: VBLENDPSYrmi: [ 0.00 0.00 ] +Key: VBLENDPSYrri: [ 0.00 0.00 ] +Key: VBLENDPSrmi: [ 0.00 0.00 ] +Key: VBLENDPSrri: [ 0.00 0.00 ] +Key: VBLENDVPDYrmr: [ 0.00 0.00 ] +Key: VBLENDVPDYrrr: [ 0.00 0.00 ] +Key: VBLENDVPDrmr: [ 0.00 0.00 ] +Key: VBLENDVPDrrr: [ 0.00 0.00 ] +Key: VBLENDVPSYrmr: [ 0.00 0.00 ] +Key: VBLENDVPSYrrr: [ 0.00 0.00 ] +Key: VBLENDVPSrmr: [ 0.00 0.00 ] +Key: VBLENDVPSrrr: [ 0.00 0.00 ] +Key: VBROADCASTF: [ 0.00 0.00 ] +Key: VBROADCASTI: [ 0.00 0.00 ] +Key: VBROADCASTSDYrm: [ 0.00 0.00 ] +Key: VBROADCASTSDYrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZ: [ 0.00 0.00 ] +Key: VBROADCASTSDZrm: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSDZrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSYrm: [ 0.00 0.00 ] +Key: VBROADCASTSSYrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZ: [ 0.00 0.00 ] +Key: VBROADCASTSSZrm: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSSZrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSrm: [ 0.00 0.00 ] +Key: VBROADCASTSSrr: [ 0.00 0.00 ] +Key: VCMPBF: [ 0.00 0.00 ] +Key: VCMPPDYrmi: [ 0.00 0.00 ] +Key: VCMPPDYrri: [ 0.00 0.00 ] +Key: VCMPPDZ: [ 0.00 0.00 ] +Key: VCMPPDZrmbi: [ 0.00 0.00 ] +Key: VCMPPDZrmbik: [ 0.00 0.00 ] +Key: VCMPPDZrmi: [ 0.00 0.00 ] +Key: VCMPPDZrmik: [ 0.00 0.00 ] +Key: VCMPPDZrri: [ 0.00 0.00 ] +Key: VCMPPDZrrib: [ 0.00 0.00 ] +Key: VCMPPDZrribk: [ 0.00 0.00 ] +Key: VCMPPDZrrik: [ 0.00 0.00 ] +Key: VCMPPDrmi: [ 0.00 0.00 ] +Key: VCMPPDrri: [ 0.00 0.00 ] +Key: VCMPPHZ: [ 0.00 0.00 ] +Key: VCMPPHZrmbi: [ 0.00 0.00 ] +Key: VCMPPHZrmbik: [ 0.00 0.00 ] +Key: VCMPPHZrmi: [ 0.00 0.00 ] +Key: VCMPPHZrmik: [ 0.00 0.00 ] +Key: VCMPPHZrri: [ 0.00 0.00 ] +Key: VCMPPHZrrib: [ 0.00 0.00 ] +Key: VCMPPHZrribk: [ 0.00 0.00 ] +Key: VCMPPHZrrik: [ 0.00 0.00 ] +Key: VCMPPSYrmi: [ 0.00 0.00 ] +Key: VCMPPSYrri: [ 0.00 0.00 ] +Key: VCMPPSZ: [ 0.00 0.00 ] +Key: VCMPPSZrmbi: [ 0.00 0.00 ] +Key: VCMPPSZrmbik: [ 0.00 0.00 ] +Key: VCMPPSZrmi: [ 0.00 0.00 ] +Key: VCMPPSZrmik: [ 0.00 0.00 ] +Key: VCMPPSZrri: [ 0.00 0.00 ] +Key: VCMPPSZrrib: [ 0.00 0.00 ] +Key: VCMPPSZrribk: [ 0.00 0.00 ] +Key: VCMPPSZrrik: [ 0.00 0.00 ] +Key: VCMPPSrmi: [ 0.00 0.00 ] +Key: VCMPPSrri: [ 0.00 0.00 ] +Key: VCMPSDZrmi: [ 0.00 0.00 ] +Key: VCMPSDZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSDZrri: [ 0.00 0.00 ] +Key: VCMPSDZrri_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSDZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSDrmi: [ 0.00 0.00 ] +Key: VCMPSDrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDrri: [ 0.00 0.00 ] +Key: VCMPSDrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmi: [ 0.00 0.00 ] +Key: VCMPSHZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSHZrri: [ 0.00 0.00 ] +Key: VCMPSHZrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSHZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmi: [ 0.00 0.00 ] +Key: VCMPSSZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrri: [ 0.00 0.00 ] +Key: VCMPSSZrri_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSSZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSrmi: [ 0.00 0.00 ] +Key: VCMPSSrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSrri: [ 0.00 0.00 ] +Key: VCMPSSrri_Int: [ 0.00 0.00 ] +Key: VCOMISBF: [ 0.00 0.00 ] +Key: VCOMISDZrm: [ 0.00 0.00 ] +Key: VCOMISDZrm_Int: [ 0.00 0.00 ] +Key: VCOMISDZrr: [ 0.00 0.00 ] +Key: VCOMISDZrr_Int: [ 0.00 0.00 ] +Key: VCOMISDZrrb: [ 0.00 0.00 ] +Key: VCOMISDrm: [ 0.00 0.00 ] +Key: VCOMISDrm_Int: [ 0.00 0.00 ] +Key: VCOMISDrr: [ 0.00 0.00 ] +Key: VCOMISDrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrm: [ 0.00 0.00 ] +Key: VCOMISHZrm_Int: [ 0.00 0.00 ] +Key: VCOMISHZrr: [ 0.00 0.00 ] +Key: VCOMISHZrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrrb: [ 0.00 0.00 ] +Key: VCOMISSZrm: [ 0.00 0.00 ] +Key: VCOMISSZrm_Int: [ 0.00 0.00 ] +Key: VCOMISSZrr: [ 0.00 0.00 ] +Key: VCOMISSZrr_Int: [ 0.00 0.00 ] +Key: VCOMISSZrrb: [ 0.00 0.00 ] +Key: VCOMISSrm: [ 0.00 0.00 ] +Key: VCOMISSrm_Int: [ 0.00 0.00 ] +Key: VCOMISSrr: [ 0.00 0.00 ] +Key: VCOMISSrr_Int: [ 0.00 0.00 ] +Key: VCOMPRESSPDZ: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrkz: [ 0.00 0.00 ] +Key: VCOMPRESSPSZ: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrkz: [ 0.00 0.00 ] +Key: VCOMXSDZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrrb_Int: [ 0.00 0.00 ] +Key: VCVT: [ 0.00 0.00 ] +Key: VCVTBF: [ 0.00 0.00 ] +Key: VCVTBIASPH: [ 0.00 0.00 ] +Key: VCVTDQ: [ 0.00 0.00 ] +Key: VCVTHF: [ 0.00 0.00 ] +Key: VCVTNE: [ 0.00 0.00 ] +Key: VCVTNEEBF: [ 0.00 0.00 ] +Key: VCVTNEEPH: [ 0.00 0.00 ] +Key: VCVTNEOBF: [ 0.00 0.00 ] +Key: VCVTNEOPH: [ 0.00 0.00 ] +Key: VCVTNEPS: [ 0.00 0.00 ] +Key: VCVTPD: [ 0.00 0.00 ] +Key: VCVTPH: [ 0.00 0.00 ] +Key: VCVTPS: [ 0.00 0.00 ] +Key: VCVTQQ: [ 0.00 0.00 ] +Key: VCVTSD: [ 0.00 0.00 ] +Key: VCVTSH: [ 0.00 0.00 ] +Key: VCVTSI: [ 0.00 0.00 ] +Key: VCVTSS: [ 0.00 0.00 ] +Key: VCVTTBF: [ 0.00 0.00 ] +Key: VCVTTPD: [ 0.00 0.00 ] +Key: VCVTTPH: [ 0.00 0.00 ] +Key: VCVTTPS: [ 0.00 0.00 ] +Key: VCVTTSD: [ 0.00 0.00 ] +Key: VCVTTSH: [ 0.00 0.00 ] +Key: VCVTTSS: [ 0.00 0.00 ] +Key: VCVTUDQ: [ 0.00 0.00 ] +Key: VCVTUQQ: [ 0.00 0.00 ] +Key: VCVTUSI: [ 0.00 0.00 ] +Key: VCVTUW: [ 0.00 0.00 ] +Key: VCVTW: [ 0.00 0.00 ] +Key: VDBPSADBWZ: [ 0.00 0.00 ] +Key: VDBPSADBWZrmi: [ 0.00 0.00 ] +Key: VDBPSADBWZrmik: [ 0.00 0.00 ] +Key: VDBPSADBWZrmikz: [ 0.00 0.00 ] +Key: VDBPSADBWZrri: [ 0.00 0.00 ] +Key: VDBPSADBWZrrik: [ 0.00 0.00 ] +Key: VDBPSADBWZrrikz: [ 0.00 0.00 ] +Key: VDIVBF: [ 0.00 0.00 ] +Key: VDIVPDYrm: [ 0.00 0.00 ] +Key: VDIVPDYrr: [ 0.00 0.00 ] +Key: VDIVPDZ: [ 0.00 0.00 ] +Key: VDIVPDZrm: [ 0.00 0.00 ] +Key: VDIVPDZrmb: [ 0.00 0.00 ] +Key: VDIVPDZrmbk: [ 0.00 0.00 ] +Key: VDIVPDZrmbkz: [ 0.00 0.00 ] +Key: VDIVPDZrmk: [ 0.00 0.00 ] +Key: VDIVPDZrmkz: [ 0.00 0.00 ] +Key: VDIVPDZrr: [ 0.00 0.00 ] +Key: VDIVPDZrrb: [ 0.00 0.00 ] +Key: VDIVPDZrrbk: [ 0.00 0.00 ] +Key: VDIVPDZrrbkz: [ 0.00 0.00 ] +Key: VDIVPDZrrk: [ 0.00 0.00 ] +Key: VDIVPDZrrkz: [ 0.00 0.00 ] +Key: VDIVPDrm: [ 0.00 0.00 ] +Key: VDIVPDrr: [ 0.00 0.00 ] +Key: VDIVPHZ: [ 0.00 0.00 ] +Key: VDIVPHZrm: [ 0.00 0.00 ] +Key: VDIVPHZrmb: [ 0.00 0.00 ] +Key: VDIVPHZrmbk: [ 0.00 0.00 ] +Key: VDIVPHZrmbkz: [ 0.00 0.00 ] +Key: VDIVPHZrmk: [ 0.00 0.00 ] +Key: VDIVPHZrmkz: [ 0.00 0.00 ] +Key: VDIVPHZrr: [ 0.00 0.00 ] +Key: VDIVPHZrrb: [ 0.00 0.00 ] +Key: VDIVPHZrrbk: [ 0.00 0.00 ] +Key: VDIVPHZrrbkz: [ 0.00 0.00 ] +Key: VDIVPHZrrk: [ 0.00 0.00 ] +Key: VDIVPHZrrkz: [ 0.00 0.00 ] +Key: VDIVPSYrm: [ 0.00 0.00 ] +Key: VDIVPSYrr: [ 0.00 0.00 ] +Key: VDIVPSZ: [ 0.00 0.00 ] +Key: VDIVPSZrm: [ 0.00 0.00 ] +Key: VDIVPSZrmb: [ 0.00 0.00 ] +Key: VDIVPSZrmbk: [ 0.00 0.00 ] +Key: VDIVPSZrmbkz: [ 0.00 0.00 ] +Key: VDIVPSZrmk: [ 0.00 0.00 ] +Key: VDIVPSZrmkz: [ 0.00 0.00 ] +Key: VDIVPSZrr: [ 0.00 0.00 ] +Key: VDIVPSZrrb: [ 0.00 0.00 ] +Key: VDIVPSZrrbk: [ 0.00 0.00 ] +Key: VDIVPSZrrbkz: [ 0.00 0.00 ] +Key: VDIVPSZrrk: [ 0.00 0.00 ] +Key: VDIVPSZrrkz: [ 0.00 0.00 ] +Key: VDIVPSrm: [ 0.00 0.00 ] +Key: VDIVPSrr: [ 0.00 0.00 ] +Key: VDIVSDZrm: [ 0.00 0.00 ] +Key: VDIVSDZrm_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrr: [ 0.00 0.00 ] +Key: VDIVSDZrr_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSDrm: [ 0.00 0.00 ] +Key: VDIVSDrm_Int: [ 0.00 0.00 ] +Key: VDIVSDrr: [ 0.00 0.00 ] +Key: VDIVSDrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrm: [ 0.00 0.00 ] +Key: VDIVSHZrm_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrr: [ 0.00 0.00 ] +Key: VDIVSHZrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrm: [ 0.00 0.00 ] +Key: VDIVSSZrm_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrr: [ 0.00 0.00 ] +Key: VDIVSSZrr_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSrm: [ 0.00 0.00 ] +Key: VDIVSSrm_Int: [ 0.00 0.00 ] +Key: VDIVSSrr: [ 0.00 0.00 ] +Key: VDIVSSrr_Int: [ 0.00 0.00 ] +Key: VDPBF: [ 0.00 0.00 ] +Key: VDPPDrmi: [ 0.00 0.00 ] +Key: VDPPDrri: [ 0.00 0.00 ] +Key: VDPPHPSZ: [ 0.00 0.00 ] +Key: VDPPHPSZm: [ 0.00 0.00 ] +Key: VDPPHPSZmb: [ 0.00 0.00 ] +Key: VDPPHPSZmbk: [ 0.00 0.00 ] +Key: VDPPHPSZmbkz: [ 0.00 0.00 ] +Key: VDPPHPSZmk: [ 0.00 0.00 ] +Key: VDPPHPSZmkz: [ 0.00 0.00 ] +Key: VDPPHPSZr: [ 0.00 0.00 ] +Key: VDPPHPSZrk: [ 0.00 0.00 ] +Key: VDPPHPSZrkz: [ 0.00 0.00 ] +Key: VDPPSYrmi: [ 0.00 0.00 ] +Key: VDPPSYrri: [ 0.00 0.00 ] +Key: VDPPSrmi: [ 0.00 0.00 ] +Key: VDPPSrri: [ 0.00 0.00 ] +Key: VERRm: [ 0.00 0.00 ] +Key: VERRr: [ 0.00 0.00 ] +Key: VERWm: [ 0.00 0.00 ] +Key: VERWr: [ 0.00 0.00 ] +Key: VEXP: [ 0.00 0.00 ] +Key: VEXPANDPDZ: [ 0.00 0.00 ] +Key: VEXPANDPDZrm: [ 0.00 0.00 ] +Key: VEXPANDPDZrmk: [ 0.00 0.00 ] +Key: VEXPANDPDZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPDZrr: [ 0.00 0.00 ] +Key: VEXPANDPDZrrk: [ 0.00 0.00 ] +Key: VEXPANDPDZrrkz: [ 0.00 0.00 ] +Key: VEXPANDPSZ: [ 0.00 0.00 ] +Key: VEXPANDPSZrm: [ 0.00 0.00 ] +Key: VEXPANDPSZrmk: [ 0.00 0.00 ] +Key: VEXPANDPSZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPSZrr: [ 0.00 0.00 ] +Key: VEXPANDPSZrrk: [ 0.00 0.00 ] +Key: VEXPANDPSZrrkz: [ 0.00 0.00 ] +Key: VEXTRACTF: [ 0.00 0.00 ] +Key: VEXTRACTI: [ 0.00 0.00 ] +Key: VEXTRACTPSZmri: [ 0.00 0.00 ] +Key: VEXTRACTPSZrri: [ 0.00 0.00 ] +Key: VEXTRACTPSmri: [ 0.00 0.00 ] +Key: VEXTRACTPSrri: [ 0.00 0.00 ] +Key: VFCMADDCPHZ: [ 0.00 0.00 ] +Key: VFCMADDCPHZm: [ 0.00 0.00 ] +Key: VFCMADDCPHZmb: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZmk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZr: [ 0.00 0.00 ] +Key: VFCMADDCPHZrb: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZrk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZm: [ 0.00 0.00 ] +Key: VFCMADDCSHZmk: [ 0.00 0.00 ] +Key: VFCMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZr: [ 0.00 0.00 ] +Key: VFCMADDCSHZrb: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZrk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFCMULCPHZ: [ 0.00 0.00 ] +Key: VFCMULCPHZrm: [ 0.00 0.00 ] +Key: VFCMULCPHZrmb: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrmk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrr: [ 0.00 0.00 ] +Key: VFCMULCPHZrrb: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrrk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrm: [ 0.00 0.00 ] +Key: VFCMULCSHZrmk: [ 0.00 0.00 ] +Key: VFCMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrr: [ 0.00 0.00 ] +Key: VFCMULCSHZrrb: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrrk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrikz: [ 0.00 0.00 ] +Key: VFMADD: [ 0.00 0.00 ] +Key: VFMADDCPHZ: [ 0.00 0.00 ] +Key: VFMADDCPHZm: [ 0.00 0.00 ] +Key: VFMADDCPHZmb: [ 0.00 0.00 ] +Key: VFMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZmk: [ 0.00 0.00 ] +Key: VFMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFMADDCPHZr: [ 0.00 0.00 ] +Key: VFMADDCPHZrb: [ 0.00 0.00 ] +Key: VFMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZrk: [ 0.00 0.00 ] +Key: VFMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFMADDCSHZm: [ 0.00 0.00 ] +Key: VFMADDCSHZmk: [ 0.00 0.00 ] +Key: VFMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFMADDCSHZr: [ 0.00 0.00 ] +Key: VFMADDCSHZrb: [ 0.00 0.00 ] +Key: VFMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCSHZrk: [ 0.00 0.00 ] +Key: VFMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFMADDPD: [ 0.00 0.00 ] +Key: VFMADDPS: [ 0.00 0.00 ] +Key: VFMADDSD: [ 0.00 0.00 ] +Key: VFMADDSS: [ 0.00 0.00 ] +Key: VFMADDSUB: [ 0.00 0.00 ] +Key: VFMADDSUBPD: [ 0.00 0.00 ] +Key: VFMADDSUBPS: [ 0.00 0.00 ] +Key: VFMSUB: [ 0.00 0.00 ] +Key: VFMSUBADD: [ 0.00 0.00 ] +Key: VFMSUBADDPD: [ 0.00 0.00 ] +Key: VFMSUBADDPS: [ 0.00 0.00 ] +Key: VFMSUBPD: [ 0.00 0.00 ] +Key: VFMSUBPS: [ 0.00 0.00 ] +Key: VFMSUBSD: [ 0.00 0.00 ] +Key: VFMSUBSS: [ 0.00 0.00 ] +Key: VFMULCPHZ: [ 0.00 0.00 ] +Key: VFMULCPHZrm: [ 0.00 0.00 ] +Key: VFMULCPHZrmb: [ 0.00 0.00 ] +Key: VFMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrmk: [ 0.00 0.00 ] +Key: VFMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFMULCPHZrr: [ 0.00 0.00 ] +Key: VFMULCPHZrrb: [ 0.00 0.00 ] +Key: VFMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrrk: [ 0.00 0.00 ] +Key: VFMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFMULCSHZrm: [ 0.00 0.00 ] +Key: VFMULCSHZrmk: [ 0.00 0.00 ] +Key: VFMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFMULCSHZrr: [ 0.00 0.00 ] +Key: VFMULCSHZrrb: [ 0.00 0.00 ] +Key: VFMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCSHZrrk: [ 0.00 0.00 ] +Key: VFMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFNMADD: [ 0.00 0.00 ] +Key: VFNMADDPD: [ 0.00 0.00 ] +Key: VFNMADDPS: [ 0.00 0.00 ] +Key: VFNMADDSD: [ 0.00 0.00 ] +Key: VFNMADDSS: [ 0.00 0.00 ] +Key: VFNMSUB: [ 0.00 0.00 ] +Key: VFNMSUBPD: [ 0.00 0.00 ] +Key: VFNMSUBPS: [ 0.00 0.00 ] +Key: VFNMSUBSD: [ 0.00 0.00 ] +Key: VFNMSUBSS: [ 0.00 0.00 ] +Key: VFPCLASSBF: [ 0.00 0.00 ] +Key: VFPCLASSPDZ: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPDZmi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmik: [ 0.00 0.00 ] +Key: VFPCLASSPDZri: [ 0.00 0.00 ] +Key: VFPCLASSPDZrik: [ 0.00 0.00 ] +Key: VFPCLASSPHZ: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPHZmi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmik: [ 0.00 0.00 ] +Key: VFPCLASSPHZri: [ 0.00 0.00 ] +Key: VFPCLASSPHZrik: [ 0.00 0.00 ] +Key: VFPCLASSPSZ: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPSZmi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmik: [ 0.00 0.00 ] +Key: VFPCLASSPSZri: [ 0.00 0.00 ] +Key: VFPCLASSPSZrik: [ 0.00 0.00 ] +Key: VFPCLASSSDZmi: [ 0.00 0.00 ] +Key: VFPCLASSSDZmik: [ 0.00 0.00 ] +Key: VFPCLASSSDZri: [ 0.00 0.00 ] +Key: VFPCLASSSDZrik: [ 0.00 0.00 ] +Key: VFPCLASSSHZmi: [ 0.00 0.00 ] +Key: VFPCLASSSHZmik: [ 0.00 0.00 ] +Key: VFPCLASSSHZri: [ 0.00 0.00 ] +Key: VFPCLASSSHZrik: [ 0.00 0.00 ] +Key: VFPCLASSSSZmi: [ 0.00 0.00 ] +Key: VFPCLASSSSZmik: [ 0.00 0.00 ] +Key: VFPCLASSSSZri: [ 0.00 0.00 ] +Key: VFPCLASSSSZrik: [ 0.00 0.00 ] +Key: VFRCZPDYrm: [ 0.00 0.00 ] +Key: VFRCZPDYrr: [ 0.00 0.00 ] +Key: VFRCZPDrm: [ 0.00 0.00 ] +Key: VFRCZPDrr: [ 0.00 0.00 ] +Key: VFRCZPSYrm: [ 0.00 0.00 ] +Key: VFRCZPSYrr: [ 0.00 0.00 ] +Key: VFRCZPSrm: [ 0.00 0.00 ] +Key: VFRCZPSrr: [ 0.00 0.00 ] +Key: VFRCZSDrm: [ 0.00 0.00 ] +Key: VFRCZSDrr: [ 0.00 0.00 ] +Key: VFRCZSSrm: [ 0.00 0.00 ] +Key: VFRCZSSrr: [ 0.00 0.00 ] +Key: VGATHERDPDYrm: [ 0.00 0.00 ] +Key: VGATHERDPDZ: [ 0.00 0.00 ] +Key: VGATHERDPDZrm: [ 0.00 0.00 ] +Key: VGATHERDPDrm: [ 0.00 0.00 ] +Key: VGATHERDPSYrm: [ 0.00 0.00 ] +Key: VGATHERDPSZ: [ 0.00 0.00 ] +Key: VGATHERDPSZrm: [ 0.00 0.00 ] +Key: VGATHERDPSrm: [ 0.00 0.00 ] +Key: VGATHERPF: [ 0.00 0.00 ] +Key: VGATHERQPDYrm: [ 0.00 0.00 ] +Key: VGATHERQPDZ: [ 0.00 0.00 ] +Key: VGATHERQPDZrm: [ 0.00 0.00 ] +Key: VGATHERQPDrm: [ 0.00 0.00 ] +Key: VGATHERQPSYrm: [ 0.00 0.00 ] +Key: VGATHERQPSZ: [ 0.00 0.00 ] +Key: VGATHERQPSZrm: [ 0.00 0.00 ] +Key: VGATHERQPSrm: [ 0.00 0.00 ] +Key: VGETEXPBF: [ 0.00 0.00 ] +Key: VGETEXPPDZ: [ 0.00 0.00 ] +Key: VGETEXPPDZm: [ 0.00 0.00 ] +Key: VGETEXPPDZmb: [ 0.00 0.00 ] +Key: VGETEXPPDZmbk: [ 0.00 0.00 ] +Key: VGETEXPPDZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPDZmk: [ 0.00 0.00 ] +Key: VGETEXPPDZmkz: [ 0.00 0.00 ] +Key: VGETEXPPDZr: [ 0.00 0.00 ] +Key: VGETEXPPDZrb: [ 0.00 0.00 ] +Key: VGETEXPPDZrbk: [ 0.00 0.00 ] +Key: VGETEXPPDZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPDZrk: [ 0.00 0.00 ] +Key: VGETEXPPDZrkz: [ 0.00 0.00 ] +Key: VGETEXPPHZ: [ 0.00 0.00 ] +Key: VGETEXPPHZm: [ 0.00 0.00 ] +Key: VGETEXPPHZmb: [ 0.00 0.00 ] +Key: VGETEXPPHZmbk: [ 0.00 0.00 ] +Key: VGETEXPPHZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZmk: [ 0.00 0.00 ] +Key: VGETEXPPHZmkz: [ 0.00 0.00 ] +Key: VGETEXPPHZr: [ 0.00 0.00 ] +Key: VGETEXPPHZrb: [ 0.00 0.00 ] +Key: VGETEXPPHZrbk: [ 0.00 0.00 ] +Key: VGETEXPPHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZrk: [ 0.00 0.00 ] +Key: VGETEXPPHZrkz: [ 0.00 0.00 ] +Key: VGETEXPPSZ: [ 0.00 0.00 ] +Key: VGETEXPPSZm: [ 0.00 0.00 ] +Key: VGETEXPPSZmb: [ 0.00 0.00 ] +Key: VGETEXPPSZmbk: [ 0.00 0.00 ] +Key: VGETEXPPSZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZmk: [ 0.00 0.00 ] +Key: VGETEXPPSZmkz: [ 0.00 0.00 ] +Key: VGETEXPPSZr: [ 0.00 0.00 ] +Key: VGETEXPPSZrb: [ 0.00 0.00 ] +Key: VGETEXPPSZrbk: [ 0.00 0.00 ] +Key: VGETEXPPSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZrk: [ 0.00 0.00 ] +Key: VGETEXPPSZrkz: [ 0.00 0.00 ] +Key: VGETEXPSDZm: [ 0.00 0.00 ] +Key: VGETEXPSDZmk: [ 0.00 0.00 ] +Key: VGETEXPSDZmkz: [ 0.00 0.00 ] +Key: VGETEXPSDZr: [ 0.00 0.00 ] +Key: VGETEXPSDZrb: [ 0.00 0.00 ] +Key: VGETEXPSDZrbk: [ 0.00 0.00 ] +Key: VGETEXPSDZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSDZrk: [ 0.00 0.00 ] +Key: VGETEXPSDZrkz: [ 0.00 0.00 ] +Key: VGETEXPSHZm: [ 0.00 0.00 ] +Key: VGETEXPSHZmk: [ 0.00 0.00 ] +Key: VGETEXPSHZmkz: [ 0.00 0.00 ] +Key: VGETEXPSHZr: [ 0.00 0.00 ] +Key: VGETEXPSHZrb: [ 0.00 0.00 ] +Key: VGETEXPSHZrbk: [ 0.00 0.00 ] +Key: VGETEXPSHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSHZrk: [ 0.00 0.00 ] +Key: VGETEXPSHZrkz: [ 0.00 0.00 ] +Key: VGETEXPSSZm: [ 0.00 0.00 ] +Key: VGETEXPSSZmk: [ 0.00 0.00 ] +Key: VGETEXPSSZmkz: [ 0.00 0.00 ] +Key: VGETEXPSSZr: [ 0.00 0.00 ] +Key: VGETEXPSSZrb: [ 0.00 0.00 ] +Key: VGETEXPSSZrbk: [ 0.00 0.00 ] +Key: VGETEXPSSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSSZrk: [ 0.00 0.00 ] +Key: VGETEXPSSZrkz: [ 0.00 0.00 ] +Key: VGETMANTBF: [ 0.00 0.00 ] +Key: VGETMANTPDZ: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrmi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrri: [ 0.00 0.00 ] +Key: VGETMANTPDZrrib: [ 0.00 0.00 ] +Key: VGETMANTPDZrribk: [ 0.00 0.00 ] +Key: VGETMANTPDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPDZrrik: [ 0.00 0.00 ] +Key: VGETMANTPDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPHZ: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrmi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrri: [ 0.00 0.00 ] +Key: VGETMANTPHZrrib: [ 0.00 0.00 ] +Key: VGETMANTPHZrribk: [ 0.00 0.00 ] +Key: VGETMANTPHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPHZrrik: [ 0.00 0.00 ] +Key: VGETMANTPHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPSZ: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrmi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrri: [ 0.00 0.00 ] +Key: VGETMANTPSZrrib: [ 0.00 0.00 ] +Key: VGETMANTPSZrribk: [ 0.00 0.00 ] +Key: VGETMANTPSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPSZrrik: [ 0.00 0.00 ] +Key: VGETMANTPSZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrmi: [ 0.00 0.00 ] +Key: VGETMANTSDZrmik: [ 0.00 0.00 ] +Key: VGETMANTSDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrri: [ 0.00 0.00 ] +Key: VGETMANTSDZrrib: [ 0.00 0.00 ] +Key: VGETMANTSDZrribk: [ 0.00 0.00 ] +Key: VGETMANTSDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSDZrrik: [ 0.00 0.00 ] +Key: VGETMANTSDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrmi: [ 0.00 0.00 ] +Key: VGETMANTSHZrmik: [ 0.00 0.00 ] +Key: VGETMANTSHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrri: [ 0.00 0.00 ] +Key: VGETMANTSHZrrib: [ 0.00 0.00 ] +Key: VGETMANTSHZrribk: [ 0.00 0.00 ] +Key: VGETMANTSHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSHZrrik: [ 0.00 0.00 ] +Key: VGETMANTSHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrmi: [ 0.00 0.00 ] +Key: VGETMANTSSZrmik: [ 0.00 0.00 ] +Key: VGETMANTSSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrri: [ 0.00 0.00 ] +Key: VGETMANTSSZrrib: [ 0.00 0.00 ] +Key: VGETMANTSSZrribk: [ 0.00 0.00 ] +Key: VGETMANTSSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSSZrrik: [ 0.00 0.00 ] +Key: VGETMANTSSZrrikz: [ 0.00 0.00 ] +Key: VGF: [ 0.00 0.00 ] +Key: VHADDPDYrm: [ 0.00 0.00 ] +Key: VHADDPDYrr: [ 0.00 0.00 ] +Key: VHADDPDrm: [ 0.00 0.00 ] +Key: VHADDPDrr: [ 0.00 0.00 ] +Key: VHADDPSYrm: [ 0.00 0.00 ] +Key: VHADDPSYrr: [ 0.00 0.00 ] +Key: VHADDPSrm: [ 0.00 0.00 ] +Key: VHADDPSrr: [ 0.00 0.00 ] +Key: VHSUBPDYrm: [ 0.00 0.00 ] +Key: VHSUBPDYrr: [ 0.00 0.00 ] +Key: VHSUBPDrm: [ 0.00 0.00 ] +Key: VHSUBPDrr: [ 0.00 0.00 ] +Key: VHSUBPSYrm: [ 0.00 0.00 ] +Key: VHSUBPSYrr: [ 0.00 0.00 ] +Key: VHSUBPSrm: [ 0.00 0.00 ] +Key: VHSUBPSrr: [ 0.00 0.00 ] +Key: VINSERTF: [ 0.00 0.00 ] +Key: VINSERTI: [ 0.00 0.00 ] +Key: VINSERTPSZrmi: [ 0.00 0.00 ] +Key: VINSERTPSZrri: [ 0.00 0.00 ] +Key: VINSERTPSrmi: [ 0.00 0.00 ] +Key: VINSERTPSrri: [ 0.00 0.00 ] +Key: VLDDQUYrm: [ 0.00 0.00 ] +Key: VLDDQUrm: [ 0.00 0.00 ] +Key: VLDMXCSR: [ 0.00 0.00 ] +Key: VMASKMOVDQU: [ 0.00 0.00 ] +Key: VMASKMOVPDYmr: [ 0.00 0.00 ] +Key: VMASKMOVPDYrm: [ 0.00 0.00 ] +Key: VMASKMOVPDmr: [ 0.00 0.00 ] +Key: VMASKMOVPDrm: [ 0.00 0.00 ] +Key: VMASKMOVPSYmr: [ 0.00 0.00 ] +Key: VMASKMOVPSYrm: [ 0.00 0.00 ] +Key: VMASKMOVPSmr: [ 0.00 0.00 ] +Key: VMASKMOVPSrm: [ 0.00 0.00 ] +Key: VMAXBF: [ 0.00 0.00 ] +Key: VMAXCPDYrm: [ 0.00 0.00 ] +Key: VMAXCPDYrr: [ 0.00 0.00 ] +Key: VMAXCPDZ: [ 0.00 0.00 ] +Key: VMAXCPDZrm: [ 0.00 0.00 ] +Key: VMAXCPDZrmb: [ 0.00 0.00 ] +Key: VMAXCPDZrmbk: [ 0.00 0.00 ] +Key: VMAXCPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPDZrmk: [ 0.00 0.00 ] +Key: VMAXCPDZrmkz: [ 0.00 0.00 ] +Key: VMAXCPDZrr: [ 0.00 0.00 ] +Key: VMAXCPDZrrk: [ 0.00 0.00 ] +Key: VMAXCPDZrrkz: [ 0.00 0.00 ] +Key: VMAXCPDrm: [ 0.00 0.00 ] +Key: VMAXCPDrr: [ 0.00 0.00 ] +Key: VMAXCPHZ: [ 0.00 0.00 ] +Key: VMAXCPHZrm: [ 0.00 0.00 ] +Key: VMAXCPHZrmb: [ 0.00 0.00 ] +Key: VMAXCPHZrmbk: [ 0.00 0.00 ] +Key: VMAXCPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPHZrmk: [ 0.00 0.00 ] +Key: VMAXCPHZrmkz: [ 0.00 0.00 ] +Key: VMAXCPHZrr: [ 0.00 0.00 ] +Key: VMAXCPHZrrk: [ 0.00 0.00 ] +Key: VMAXCPHZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSYrm: [ 0.00 0.00 ] +Key: VMAXCPSYrr: [ 0.00 0.00 ] +Key: VMAXCPSZ: [ 0.00 0.00 ] +Key: VMAXCPSZrm: [ 0.00 0.00 ] +Key: VMAXCPSZrmb: [ 0.00 0.00 ] +Key: VMAXCPSZrmbk: [ 0.00 0.00 ] +Key: VMAXCPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPSZrmk: [ 0.00 0.00 ] +Key: VMAXCPSZrmkz: [ 0.00 0.00 ] +Key: VMAXCPSZrr: [ 0.00 0.00 ] +Key: VMAXCPSZrrk: [ 0.00 0.00 ] +Key: VMAXCPSZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSrm: [ 0.00 0.00 ] +Key: VMAXCPSrr: [ 0.00 0.00 ] +Key: VMAXCSDZrm: [ 0.00 0.00 ] +Key: VMAXCSDZrr: [ 0.00 0.00 ] +Key: VMAXCSDrm: [ 0.00 0.00 ] +Key: VMAXCSDrr: [ 0.00 0.00 ] +Key: VMAXCSHZrm: [ 0.00 0.00 ] +Key: VMAXCSHZrr: [ 0.00 0.00 ] +Key: VMAXCSSZrm: [ 0.00 0.00 ] +Key: VMAXCSSZrr: [ 0.00 0.00 ] +Key: VMAXCSSrm: [ 0.00 0.00 ] +Key: VMAXCSSrr: [ 0.00 0.00 ] +Key: VMAXPDYrm: [ 0.00 0.00 ] +Key: VMAXPDYrr: [ 0.00 0.00 ] +Key: VMAXPDZ: [ 0.00 0.00 ] +Key: VMAXPDZrm: [ 0.00 0.00 ] +Key: VMAXPDZrmb: [ 0.00 0.00 ] +Key: VMAXPDZrmbk: [ 0.00 0.00 ] +Key: VMAXPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXPDZrmk: [ 0.00 0.00 ] +Key: VMAXPDZrmkz: [ 0.00 0.00 ] +Key: VMAXPDZrr: [ 0.00 0.00 ] +Key: VMAXPDZrrb: [ 0.00 0.00 ] +Key: VMAXPDZrrbk: [ 0.00 0.00 ] +Key: VMAXPDZrrbkz: [ 0.00 0.00 ] +Key: VMAXPDZrrk: [ 0.00 0.00 ] +Key: VMAXPDZrrkz: [ 0.00 0.00 ] +Key: VMAXPDrm: [ 0.00 0.00 ] +Key: VMAXPDrr: [ 0.00 0.00 ] +Key: VMAXPHZ: [ 0.00 0.00 ] +Key: VMAXPHZrm: [ 0.00 0.00 ] +Key: VMAXPHZrmb: [ 0.00 0.00 ] +Key: VMAXPHZrmbk: [ 0.00 0.00 ] +Key: VMAXPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXPHZrmk: [ 0.00 0.00 ] +Key: VMAXPHZrmkz: [ 0.00 0.00 ] +Key: VMAXPHZrr: [ 0.00 0.00 ] +Key: VMAXPHZrrb: [ 0.00 0.00 ] +Key: VMAXPHZrrbk: [ 0.00 0.00 ] +Key: VMAXPHZrrbkz: [ 0.00 0.00 ] +Key: VMAXPHZrrk: [ 0.00 0.00 ] +Key: VMAXPHZrrkz: [ 0.00 0.00 ] +Key: VMAXPSYrm: [ 0.00 0.00 ] +Key: VMAXPSYrr: [ 0.00 0.00 ] +Key: VMAXPSZ: [ 0.00 0.00 ] +Key: VMAXPSZrm: [ 0.00 0.00 ] +Key: VMAXPSZrmb: [ 0.00 0.00 ] +Key: VMAXPSZrmbk: [ 0.00 0.00 ] +Key: VMAXPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXPSZrmk: [ 0.00 0.00 ] +Key: VMAXPSZrmkz: [ 0.00 0.00 ] +Key: VMAXPSZrr: [ 0.00 0.00 ] +Key: VMAXPSZrrb: [ 0.00 0.00 ] +Key: VMAXPSZrrbk: [ 0.00 0.00 ] +Key: VMAXPSZrrbkz: [ 0.00 0.00 ] +Key: VMAXPSZrrk: [ 0.00 0.00 ] +Key: VMAXPSZrrkz: [ 0.00 0.00 ] +Key: VMAXPSrm: [ 0.00 0.00 ] +Key: VMAXPSrr: [ 0.00 0.00 ] +Key: VMAXSDZrm: [ 0.00 0.00 ] +Key: VMAXSDZrm_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrr: [ 0.00 0.00 ] +Key: VMAXSDZrr_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSDrm: [ 0.00 0.00 ] +Key: VMAXSDrm_Int: [ 0.00 0.00 ] +Key: VMAXSDrr: [ 0.00 0.00 ] +Key: VMAXSDrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrm: [ 0.00 0.00 ] +Key: VMAXSHZrm_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrr: [ 0.00 0.00 ] +Key: VMAXSHZrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrm: [ 0.00 0.00 ] +Key: VMAXSSZrm_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrr: [ 0.00 0.00 ] +Key: VMAXSSZrr_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSrm: [ 0.00 0.00 ] +Key: VMAXSSrm_Int: [ 0.00 0.00 ] +Key: VMAXSSrr: [ 0.00 0.00 ] +Key: VMAXSSrr_Int: [ 0.00 0.00 ] +Key: VMCALL: [ 0.00 0.00 ] +Key: VMCLEARm: [ 0.00 0.00 ] +Key: VMFUNC: [ 0.00 0.00 ] +Key: VMINBF: [ 0.00 0.00 ] +Key: VMINCPDYrm: [ 0.00 0.00 ] +Key: VMINCPDYrr: [ 0.00 0.00 ] +Key: VMINCPDZ: [ 0.00 0.00 ] +Key: VMINCPDZrm: [ 0.00 0.00 ] +Key: VMINCPDZrmb: [ 0.00 0.00 ] +Key: VMINCPDZrmbk: [ 0.00 0.00 ] +Key: VMINCPDZrmbkz: [ 0.00 0.00 ] +Key: VMINCPDZrmk: [ 0.00 0.00 ] +Key: VMINCPDZrmkz: [ 0.00 0.00 ] +Key: VMINCPDZrr: [ 0.00 0.00 ] +Key: VMINCPDZrrk: [ 0.00 0.00 ] +Key: VMINCPDZrrkz: [ 0.00 0.00 ] +Key: VMINCPDrm: [ 0.00 0.00 ] +Key: VMINCPDrr: [ 0.00 0.00 ] +Key: VMINCPHZ: [ 0.00 0.00 ] +Key: VMINCPHZrm: [ 0.00 0.00 ] +Key: VMINCPHZrmb: [ 0.00 0.00 ] +Key: VMINCPHZrmbk: [ 0.00 0.00 ] +Key: VMINCPHZrmbkz: [ 0.00 0.00 ] +Key: VMINCPHZrmk: [ 0.00 0.00 ] +Key: VMINCPHZrmkz: [ 0.00 0.00 ] +Key: VMINCPHZrr: [ 0.00 0.00 ] +Key: VMINCPHZrrk: [ 0.00 0.00 ] +Key: VMINCPHZrrkz: [ 0.00 0.00 ] +Key: VMINCPSYrm: [ 0.00 0.00 ] +Key: VMINCPSYrr: [ 0.00 0.00 ] +Key: VMINCPSZ: [ 0.00 0.00 ] +Key: VMINCPSZrm: [ 0.00 0.00 ] +Key: VMINCPSZrmb: [ 0.00 0.00 ] +Key: VMINCPSZrmbk: [ 0.00 0.00 ] +Key: VMINCPSZrmbkz: [ 0.00 0.00 ] +Key: VMINCPSZrmk: [ 0.00 0.00 ] +Key: VMINCPSZrmkz: [ 0.00 0.00 ] +Key: VMINCPSZrr: [ 0.00 0.00 ] +Key: VMINCPSZrrk: [ 0.00 0.00 ] +Key: VMINCPSZrrkz: [ 0.00 0.00 ] +Key: VMINCPSrm: [ 0.00 0.00 ] +Key: VMINCPSrr: [ 0.00 0.00 ] +Key: VMINCSDZrm: [ 0.00 0.00 ] +Key: VMINCSDZrr: [ 0.00 0.00 ] +Key: VMINCSDrm: [ 0.00 0.00 ] +Key: VMINCSDrr: [ 0.00 0.00 ] +Key: VMINCSHZrm: [ 0.00 0.00 ] +Key: VMINCSHZrr: [ 0.00 0.00 ] +Key: VMINCSSZrm: [ 0.00 0.00 ] +Key: VMINCSSZrr: [ 0.00 0.00 ] +Key: VMINCSSrm: [ 0.00 0.00 ] +Key: VMINCSSrr: [ 0.00 0.00 ] +Key: VMINMAXBF: [ 0.00 0.00 ] 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0.00 ] +Key: VMINMAXPSZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrmi: [ 0.00 0.00 ] +Key: VMINMAXPSZrmik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrri: [ 0.00 0.00 ] +Key: VMINMAXPSZrrib: [ 0.00 0.00 ] +Key: VMINMAXPSZrribk: [ 0.00 0.00 ] +Key: VMINMAXPSZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPSZrrik: [ 0.00 0.00 ] +Key: VMINMAXPSZrrikz: [ 0.00 0.00 ] +Key: VMINMAXSDrmi: [ 0.00 0.00 ] +Key: VMINMAXSDrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrri: [ 0.00 0.00 ] +Key: VMINMAXSDrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmi: [ 0.00 0.00 ] +Key: VMINMAXSHrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrri: [ 0.00 0.00 ] +Key: VMINMAXSHrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmi: [ 0.00 0.00 ] +Key: VMINMAXSSrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrri: [ 0.00 0.00 ] +Key: VMINMAXSSrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrikz_Int: [ 0.00 0.00 ] +Key: VMINPDYrm: [ 0.00 0.00 ] +Key: VMINPDYrr: [ 0.00 0.00 ] +Key: VMINPDZ: [ 0.00 0.00 ] +Key: VMINPDZrm: [ 0.00 0.00 ] +Key: VMINPDZrmb: [ 0.00 0.00 ] +Key: VMINPDZrmbk: [ 0.00 0.00 ] +Key: VMINPDZrmbkz: [ 0.00 0.00 ] +Key: VMINPDZrmk: [ 0.00 0.00 ] +Key: VMINPDZrmkz: [ 0.00 0.00 ] +Key: VMINPDZrr: [ 0.00 0.00 ] +Key: VMINPDZrrb: [ 0.00 0.00 ] +Key: VMINPDZrrbk: [ 0.00 0.00 ] +Key: VMINPDZrrbkz: [ 0.00 0.00 ] +Key: VMINPDZrrk: [ 0.00 0.00 ] +Key: VMINPDZrrkz: [ 0.00 0.00 ] +Key: VMINPDrm: [ 0.00 0.00 ] +Key: VMINPDrr: [ 0.00 0.00 ] +Key: VMINPHZ: [ 0.00 0.00 ] +Key: VMINPHZrm: [ 0.00 0.00 ] +Key: VMINPHZrmb: [ 0.00 0.00 ] +Key: VMINPHZrmbk: [ 0.00 0.00 ] +Key: VMINPHZrmbkz: [ 0.00 0.00 ] +Key: VMINPHZrmk: [ 0.00 0.00 ] +Key: VMINPHZrmkz: [ 0.00 0.00 ] +Key: VMINPHZrr: [ 0.00 0.00 ] +Key: VMINPHZrrb: [ 0.00 0.00 ] +Key: VMINPHZrrbk: [ 0.00 0.00 ] +Key: VMINPHZrrbkz: [ 0.00 0.00 ] +Key: VMINPHZrrk: [ 0.00 0.00 ] +Key: VMINPHZrrkz: [ 0.00 0.00 ] +Key: VMINPSYrm: [ 0.00 0.00 ] +Key: VMINPSYrr: [ 0.00 0.00 ] +Key: VMINPSZ: [ 0.00 0.00 ] +Key: VMINPSZrm: [ 0.00 0.00 ] +Key: VMINPSZrmb: [ 0.00 0.00 ] +Key: VMINPSZrmbk: [ 0.00 0.00 ] +Key: VMINPSZrmbkz: [ 0.00 0.00 ] +Key: VMINPSZrmk: [ 0.00 0.00 ] +Key: VMINPSZrmkz: [ 0.00 0.00 ] +Key: VMINPSZrr: [ 0.00 0.00 ] +Key: VMINPSZrrb: [ 0.00 0.00 ] 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VMINSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSHZrrk_Int: [ 0.00 0.00 ] +Key: VMINSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrm: [ 0.00 0.00 ] +Key: VMINSSZrm_Int: [ 0.00 0.00 ] +Key: VMINSSZrmk_Int: [ 0.00 0.00 ] +Key: VMINSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrr: [ 0.00 0.00 ] +Key: VMINSSZrr_Int: [ 0.00 0.00 ] +Key: VMINSSZrrb_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrrk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSrm: [ 0.00 0.00 ] +Key: VMINSSrm_Int: [ 0.00 0.00 ] +Key: VMINSSrr: [ 0.00 0.00 ] +Key: VMINSSrr_Int: [ 0.00 0.00 ] +Key: VMLAUNCH: [ 0.00 0.00 ] +Key: VMLOAD: [ 0.00 0.00 ] +Key: VMMCALL: [ 0.00 0.00 ] +Key: VMOV: [ 0.00 0.00 ] +Key: VMOVAPDYmr: [ 0.00 0.00 ] +Key: VMOVAPDYrm: [ 0.00 0.00 ] +Key: VMOVAPDYrr: [ 0.00 0.00 ] +Key: VMOVAPDYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZ: [ 0.00 0.00 ] +Key: VMOVAPDZmr: [ 0.00 0.00 ] +Key: VMOVAPDZmrk: [ 0.00 0.00 ] +Key: VMOVAPDZrm: [ 0.00 0.00 ] +Key: VMOVAPDZrmk: [ 0.00 0.00 ] +Key: VMOVAPDZrmkz: [ 0.00 0.00 ] +Key: VMOVAPDZrr: [ 0.00 0.00 ] +Key: VMOVAPDZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrk: [ 0.00 0.00 ] +Key: VMOVAPDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPDmr: [ 0.00 0.00 ] +Key: VMOVAPDrm: [ 0.00 0.00 ] +Key: VMOVAPDrr: [ 0.00 0.00 ] +Key: VMOVAPDrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSYmr: [ 0.00 0.00 ] +Key: VMOVAPSYrm: [ 0.00 0.00 ] +Key: VMOVAPSYrr: [ 0.00 0.00 ] +Key: VMOVAPSYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZ: [ 0.00 0.00 ] +Key: VMOVAPSZmr: [ 0.00 0.00 ] +Key: VMOVAPSZmrk: [ 0.00 0.00 ] +Key: VMOVAPSZrm: [ 0.00 0.00 ] +Key: VMOVAPSZrmk: [ 0.00 0.00 ] +Key: VMOVAPSZrmkz: [ 0.00 0.00 ] +Key: VMOVAPSZrr: [ 0.00 0.00 ] +Key: VMOVAPSZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrk: [ 0.00 0.00 ] +Key: VMOVAPSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPSmr: [ 0.00 0.00 ] +Key: VMOVAPSrm: [ 0.00 0.00 ] +Key: VMOVAPSrr: [ 0.00 0.00 ] +Key: VMOVAPSrr_REV: [ 0.00 0.00 ] +Key: VMOVDDUPYrm: [ 0.00 0.00 ] +Key: VMOVDDUPYrr: [ 0.00 0.00 ] +Key: VMOVDDUPZ: [ 0.00 0.00 ] +Key: VMOVDDUPZrm: [ 0.00 0.00 ] +Key: VMOVDDUPZrmk: [ 0.00 0.00 ] +Key: VMOVDDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVDDUPZrr: [ 0.00 0.00 ] +Key: VMOVDDUPZrrk: [ 0.00 0.00 ] +Key: VMOVDDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVDDUPrm: [ 0.00 0.00 ] +Key: VMOVDDUPrr: [ 0.00 0.00 ] +Key: VMOVDI: [ 0.00 0.00 ] +Key: VMOVDQA: [ 0.00 0.00 ] +Key: VMOVDQAYmr: [ 0.00 0.00 ] +Key: VMOVDQAYrm: [ 0.00 0.00 ] +Key: VMOVDQAYrr: [ 0.00 0.00 ] +Key: VMOVDQAYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQAmr: [ 0.00 0.00 ] +Key: VMOVDQArm: [ 0.00 0.00 ] +Key: VMOVDQArr: [ 0.00 0.00 ] +Key: VMOVDQArr_REV: [ 0.00 0.00 ] +Key: VMOVDQU: [ 0.00 0.00 ] +Key: VMOVDQUYmr: [ 0.00 0.00 ] +Key: VMOVDQUYrm: [ 0.00 0.00 ] +Key: VMOVDQUYrr: [ 0.00 0.00 ] +Key: VMOVDQUYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQUmr: [ 0.00 0.00 ] +Key: VMOVDQUrm: [ 0.00 0.00 ] +Key: VMOVDQUrr: [ 0.00 0.00 ] +Key: VMOVDQUrr_REV: [ 0.00 0.00 ] +Key: VMOVHLPSZrr: [ 0.00 0.00 ] +Key: VMOVHLPSrr: [ 0.00 0.00 ] +Key: VMOVHPDZ: [ 0.00 0.00 ] +Key: VMOVHPDmr: [ 0.00 0.00 ] +Key: VMOVHPDrm: [ 0.00 0.00 ] +Key: VMOVHPSZ: [ 0.00 0.00 ] +Key: VMOVHPSmr: [ 0.00 0.00 ] +Key: VMOVHPSrm: [ 0.00 0.00 ] +Key: VMOVLHPSZrr: [ 0.00 0.00 ] +Key: VMOVLHPSrr: [ 0.00 0.00 ] +Key: VMOVLPDZ: [ 0.00 0.00 ] +Key: VMOVLPDmr: [ 0.00 0.00 ] +Key: VMOVLPDrm: [ 0.00 0.00 ] +Key: VMOVLPSZ: [ 0.00 0.00 ] +Key: VMOVLPSmr: [ 0.00 0.00 ] +Key: VMOVLPSrm: [ 0.00 0.00 ] +Key: VMOVMSKPDYrr: [ 0.00 0.00 ] +Key: VMOVMSKPDrr: [ 0.00 0.00 ] +Key: VMOVMSKPSYrr: [ 0.00 0.00 ] +Key: VMOVMSKPSrr: [ 0.00 0.00 ] +Key: VMOVNTDQAYrm: [ 0.00 0.00 ] +Key: VMOVNTDQAZ: [ 0.00 0.00 ] +Key: VMOVNTDQAZrm: [ 0.00 0.00 ] +Key: VMOVNTDQArm: [ 0.00 0.00 ] +Key: VMOVNTDQYmr: [ 0.00 0.00 ] +Key: VMOVNTDQZ: [ 0.00 0.00 ] +Key: VMOVNTDQZmr: [ 0.00 0.00 ] +Key: VMOVNTDQmr: [ 0.00 0.00 ] +Key: VMOVNTPDYmr: [ 0.00 0.00 ] +Key: VMOVNTPDZ: [ 0.00 0.00 ] +Key: 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VPERMDYrr: [ 0.00 0.00 ] +Key: VPERMDZ: [ 0.00 0.00 ] +Key: VPERMDZrm: [ 0.00 0.00 ] +Key: VPERMDZrmb: [ 0.00 0.00 ] +Key: VPERMDZrmbk: [ 0.00 0.00 ] +Key: VPERMDZrmbkz: [ 0.00 0.00 ] +Key: VPERMDZrmk: [ 0.00 0.00 ] +Key: VPERMDZrmkz: [ 0.00 0.00 ] +Key: VPERMDZrr: [ 0.00 0.00 ] +Key: VPERMDZrrk: [ 0.00 0.00 ] +Key: VPERMDZrrkz: [ 0.00 0.00 ] +Key: VPERMI: [ 0.00 0.00 ] +Key: VPERMIL: [ 0.00 0.00 ] +Key: VPERMILPDYmi: [ 0.00 0.00 ] +Key: VPERMILPDYri: [ 0.00 0.00 ] +Key: VPERMILPDYrm: [ 0.00 0.00 ] +Key: VPERMILPDYrr: [ 0.00 0.00 ] +Key: VPERMILPDZ: [ 0.00 0.00 ] +Key: VPERMILPDZmbi: [ 0.00 0.00 ] +Key: VPERMILPDZmbik: [ 0.00 0.00 ] +Key: VPERMILPDZmbikz: [ 0.00 0.00 ] +Key: VPERMILPDZmi: [ 0.00 0.00 ] +Key: VPERMILPDZmik: [ 0.00 0.00 ] +Key: VPERMILPDZmikz: [ 0.00 0.00 ] +Key: VPERMILPDZri: [ 0.00 0.00 ] +Key: VPERMILPDZrik: [ 0.00 0.00 ] +Key: VPERMILPDZrikz: [ 0.00 0.00 ] +Key: VPERMILPDZrm: [ 0.00 0.00 ] +Key: VPERMILPDZrmb: [ 0.00 0.00 ] +Key: VPERMILPDZrmbk: [ 0.00 0.00 ] +Key: VPERMILPDZrmbkz: [ 0.00 0.00 ] +Key: VPERMILPDZrmk: [ 0.00 0.00 ] +Key: VPERMILPDZrmkz: [ 0.00 0.00 ] +Key: VPERMILPDZrr: [ 0.00 0.00 ] +Key: VPERMILPDZrrk: [ 0.00 0.00 ] +Key: VPERMILPDZrrkz: [ 0.00 0.00 ] +Key: VPERMILPDmi: [ 0.00 0.00 ] +Key: VPERMILPDri: [ 0.00 0.00 ] +Key: VPERMILPDrm: [ 0.00 0.00 ] +Key: VPERMILPDrr: [ 0.00 0.00 ] +Key: VPERMILPSYmi: [ 0.00 0.00 ] +Key: VPERMILPSYri: [ 0.00 0.00 ] +Key: VPERMILPSYrm: [ 0.00 0.00 ] +Key: VPERMILPSYrr: [ 0.00 0.00 ] +Key: VPERMILPSZ: [ 0.00 0.00 ] +Key: VPERMILPSZmbi: [ 0.00 0.00 ] +Key: VPERMILPSZmbik: [ 0.00 0.00 ] +Key: VPERMILPSZmbikz: [ 0.00 0.00 ] +Key: VPERMILPSZmi: [ 0.00 0.00 ] +Key: VPERMILPSZmik: [ 0.00 0.00 ] +Key: VPERMILPSZmikz: [ 0.00 0.00 ] +Key: VPERMILPSZri: [ 0.00 0.00 ] +Key: VPERMILPSZrik: [ 0.00 0.00 ] +Key: VPERMILPSZrikz: [ 0.00 0.00 ] +Key: VPERMILPSZrm: [ 0.00 0.00 ] +Key: VPERMILPSZrmb: [ 0.00 0.00 ] +Key: VPERMILPSZrmbk: [ 0.00 0.00 ] +Key: VPERMILPSZrmbkz: [ 0.00 0.00 ] +Key: VPERMILPSZrmk: [ 0.00 0.00 ] +Key: VPERMILPSZrmkz: [ 0.00 0.00 ] +Key: VPERMILPSZrr: [ 0.00 0.00 ] +Key: VPERMILPSZrrk: [ 0.00 0.00 ] +Key: VPERMILPSZrrkz: [ 0.00 0.00 ] +Key: VPERMILPSmi: [ 0.00 0.00 ] +Key: VPERMILPSri: [ 0.00 0.00 ] +Key: VPERMILPSrm: [ 0.00 0.00 ] +Key: VPERMILPSrr: [ 0.00 0.00 ] +Key: VPERMPDYmi: [ 0.00 0.00 ] +Key: VPERMPDYri: [ 0.00 0.00 ] +Key: VPERMPDZ: [ 0.00 0.00 ] +Key: VPERMPDZmbi: [ 0.00 0.00 ] +Key: VPERMPDZmbik: [ 0.00 0.00 ] +Key: VPERMPDZmbikz: [ 0.00 0.00 ] +Key: VPERMPDZmi: [ 0.00 0.00 ] +Key: VPERMPDZmik: [ 0.00 0.00 ] +Key: VPERMPDZmikz: [ 0.00 0.00 ] +Key: VPERMPDZri: [ 0.00 0.00 ] +Key: VPERMPDZrik: [ 0.00 0.00 ] +Key: VPERMPDZrikz: [ 0.00 0.00 ] +Key: VPERMPDZrm: [ 0.00 0.00 ] +Key: VPERMPDZrmb: [ 0.00 0.00 ] +Key: VPERMPDZrmbk: [ 0.00 0.00 ] +Key: VPERMPDZrmbkz: [ 0.00 0.00 ] +Key: VPERMPDZrmk: [ 0.00 0.00 ] +Key: VPERMPDZrmkz: [ 0.00 0.00 ] +Key: VPERMPDZrr: [ 0.00 0.00 ] +Key: VPERMPDZrrk: [ 0.00 0.00 ] +Key: VPERMPDZrrkz: [ 0.00 0.00 ] +Key: VPERMPSYrm: [ 0.00 0.00 ] +Key: VPERMPSYrr: [ 0.00 0.00 ] +Key: VPERMPSZ: [ 0.00 0.00 ] +Key: VPERMPSZrm: [ 0.00 0.00 ] +Key: VPERMPSZrmb: [ 0.00 0.00 ] +Key: VPERMPSZrmbk: [ 0.00 0.00 ] +Key: VPERMPSZrmbkz: [ 0.00 0.00 ] +Key: VPERMPSZrmk: [ 0.00 0.00 ] +Key: VPERMPSZrmkz: [ 0.00 0.00 ] +Key: VPERMPSZrr: [ 0.00 0.00 ] +Key: VPERMPSZrrk: [ 0.00 0.00 ] +Key: VPERMPSZrrkz: [ 0.00 0.00 ] +Key: VPERMQYmi: [ 0.00 0.00 ] +Key: VPERMQYri: [ 0.00 0.00 ] +Key: VPERMQZ: [ 0.00 0.00 ] +Key: VPERMQZmbi: [ 0.00 0.00 ] +Key: VPERMQZmbik: [ 0.00 0.00 ] +Key: VPERMQZmbikz: [ 0.00 0.00 ] +Key: VPERMQZmi: [ 0.00 0.00 ] +Key: VPERMQZmik: [ 0.00 0.00 ] +Key: VPERMQZmikz: [ 0.00 0.00 ] +Key: VPERMQZri: [ 0.00 0.00 ] +Key: VPERMQZrik: [ 0.00 0.00 ] +Key: VPERMQZrikz: [ 0.00 0.00 ] +Key: VPERMQZrm: [ 0.00 0.00 ] +Key: VPERMQZrmb: [ 0.00 0.00 ] +Key: VPERMQZrmbk: [ 0.00 0.00 ] +Key: VPERMQZrmbkz: [ 0.00 0.00 ] +Key: VPERMQZrmk: [ 0.00 0.00 ] +Key: VPERMQZrmkz: [ 0.00 0.00 ] +Key: VPERMQZrr: [ 0.00 0.00 ] +Key: VPERMQZrrk: [ 0.00 0.00 ] +Key: VPERMQZrrkz: [ 0.00 0.00 ] +Key: VPERMT: [ 0.00 0.00 ] +Key: VPERMWZ: [ 0.00 0.00 ] +Key: VPERMWZrm: [ 0.00 0.00 ] +Key: VPERMWZrmk: [ 0.00 0.00 ] +Key: VPERMWZrmkz: [ 0.00 0.00 ] +Key: VPERMWZrr: [ 0.00 0.00 ] +Key: VPERMWZrrk: [ 0.00 0.00 ] +Key: VPERMWZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDBZ: [ 0.00 0.00 ] +Key: VPEXPANDBZrm: [ 0.00 0.00 ] +Key: VPEXPANDBZrmk: [ 0.00 0.00 ] +Key: VPEXPANDBZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDBZrr: [ 0.00 0.00 ] +Key: VPEXPANDBZrrk: [ 0.00 0.00 ] +Key: VPEXPANDBZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDDZ: [ 0.00 0.00 ] +Key: VPEXPANDDZrm: [ 0.00 0.00 ] +Key: VPEXPANDDZrmk: [ 0.00 0.00 ] +Key: VPEXPANDDZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDDZrr: [ 0.00 0.00 ] +Key: VPEXPANDDZrrk: [ 0.00 0.00 ] +Key: VPEXPANDDZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDQZ: [ 0.00 0.00 ] +Key: VPEXPANDQZrm: [ 0.00 0.00 ] +Key: VPEXPANDQZrmk: [ 0.00 0.00 ] +Key: VPEXPANDQZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDQZrr: [ 0.00 0.00 ] +Key: VPEXPANDQZrrk: [ 0.00 0.00 ] +Key: VPEXPANDQZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDWZ: [ 0.00 0.00 ] +Key: VPEXPANDWZrm: [ 0.00 0.00 ] +Key: VPEXPANDWZrmk: [ 0.00 0.00 ] +Key: VPEXPANDWZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDWZrr: [ 0.00 0.00 ] +Key: VPEXPANDWZrrk: [ 0.00 0.00 ] +Key: VPEXPANDWZrrkz: [ 0.00 0.00 ] +Key: VPEXTRBZmri: [ 0.00 0.00 ] +Key: VPEXTRBZrri: [ 0.00 0.00 ] +Key: VPEXTRBmri: [ 0.00 0.00 ] +Key: VPEXTRBrri: [ 0.00 0.00 ] +Key: VPEXTRDZmri: [ 0.00 0.00 ] +Key: VPEXTRDZrri: [ 0.00 0.00 ] +Key: VPEXTRDmri: [ 0.00 0.00 ] +Key: VPEXTRDrri: [ 0.00 0.00 ] +Key: VPEXTRQZmri: [ 0.00 0.00 ] +Key: VPEXTRQZrri: [ 0.00 0.00 ] +Key: VPEXTRQmri: [ 0.00 0.00 ] +Key: VPEXTRQrri: [ 0.00 0.00 ] +Key: VPEXTRWZmri: [ 0.00 0.00 ] +Key: VPEXTRWZrri: [ 0.00 0.00 ] +Key: VPEXTRWZrri_REV: [ 0.00 0.00 ] +Key: VPEXTRWmri: [ 0.00 0.00 ] +Key: VPEXTRWrri: [ 0.00 0.00 ] +Key: VPEXTRWrri_REV: [ 0.00 0.00 ] +Key: VPGATHERDDYrm: [ 0.00 0.00 ] +Key: VPGATHERDDZ: [ 0.00 0.00 ] +Key: VPGATHERDDZrm: [ 0.00 0.00 ] +Key: VPGATHERDDrm: [ 0.00 0.00 ] +Key: VPGATHERDQYrm: [ 0.00 0.00 ] +Key: VPGATHERDQZ: [ 0.00 0.00 ] +Key: VPGATHERDQZrm: [ 0.00 0.00 ] +Key: VPGATHERDQrm: [ 0.00 0.00 ] +Key: VPGATHERQDYrm: [ 0.00 0.00 ] +Key: VPGATHERQDZ: [ 0.00 0.00 ] +Key: VPGATHERQDZrm: [ 0.00 0.00 ] +Key: VPGATHERQDrm: [ 0.00 0.00 ] +Key: VPGATHERQQYrm: [ 0.00 0.00 ] +Key: VPGATHERQQZ: [ 0.00 0.00 ] +Key: VPGATHERQQZrm: [ 0.00 0.00 ] +Key: VPGATHERQQrm: [ 0.00 0.00 ] +Key: VPHADDBDrm: [ 0.00 0.00 ] +Key: VPHADDBDrr: [ 0.00 0.00 ] +Key: VPHADDBQrm: [ 0.00 0.00 ] +Key: VPHADDBQrr: [ 0.00 0.00 ] +Key: VPHADDBWrm: [ 0.00 0.00 ] +Key: VPHADDBWrr: [ 0.00 0.00 ] +Key: VPHADDDQrm: [ 0.00 0.00 ] +Key: VPHADDDQrr: [ 0.00 0.00 ] +Key: VPHADDDYrm: [ 0.00 0.00 ] +Key: VPHADDDYrr: [ 0.00 0.00 ] +Key: VPHADDDrm: [ 0.00 0.00 ] +Key: VPHADDDrr: [ 0.00 0.00 ] +Key: VPHADDSWYrm: [ 0.00 0.00 ] +Key: VPHADDSWYrr: [ 0.00 0.00 ] +Key: VPHADDSWrm: [ 0.00 0.00 ] +Key: VPHADDSWrr: [ 0.00 0.00 ] +Key: VPHADDUBDrm: [ 0.00 0.00 ] +Key: VPHADDUBDrr: [ 0.00 0.00 ] +Key: VPHADDUBQrm: [ 0.00 0.00 ] +Key: VPHADDUBQrr: [ 0.00 0.00 ] +Key: VPHADDUBWrm: [ 0.00 0.00 ] +Key: VPHADDUBWrr: [ 0.00 0.00 ] +Key: VPHADDUDQrm: [ 0.00 0.00 ] +Key: VPHADDUDQrr: [ 0.00 0.00 ] +Key: VPHADDUWDrm: [ 0.00 0.00 ] +Key: VPHADDUWDrr: [ 0.00 0.00 ] +Key: VPHADDUWQrm: [ 0.00 0.00 ] +Key: VPHADDUWQrr: [ 0.00 0.00 ] +Key: VPHADDWDrm: [ 0.00 0.00 ] +Key: VPHADDWDrr: [ 0.00 0.00 ] +Key: VPHADDWQrm: [ 0.00 0.00 ] +Key: VPHADDWQrr: [ 0.00 0.00 ] +Key: VPHADDWYrm: [ 0.00 0.00 ] +Key: VPHADDWYrr: [ 0.00 0.00 ] +Key: VPHADDWrm: [ 0.00 0.00 ] +Key: VPHADDWrr: [ 0.00 0.00 ] +Key: VPHMINPOSUWrm: [ 0.00 0.00 ] +Key: VPHMINPOSUWrr: [ 0.00 0.00 ] +Key: VPHSUBBWrm: [ 0.00 0.00 ] +Key: VPHSUBBWrr: [ 0.00 0.00 ] +Key: VPHSUBDQrm: [ 0.00 0.00 ] +Key: VPHSUBDQrr: [ 0.00 0.00 ] +Key: VPHSUBDYrm: [ 0.00 0.00 ] +Key: VPHSUBDYrr: [ 0.00 0.00 ] +Key: VPHSUBDrm: [ 0.00 0.00 ] +Key: VPHSUBDrr: [ 0.00 0.00 ] +Key: VPHSUBSWYrm: [ 0.00 0.00 ] +Key: VPHSUBSWYrr: [ 0.00 0.00 ] +Key: VPHSUBSWrm: [ 0.00 0.00 ] +Key: VPHSUBSWrr: [ 0.00 0.00 ] +Key: VPHSUBWDrm: [ 0.00 0.00 ] +Key: VPHSUBWDrr: [ 0.00 0.00 ] +Key: VPHSUBWYrm: [ 0.00 0.00 ] +Key: VPHSUBWYrr: [ 0.00 0.00 ] +Key: VPHSUBWrm: [ 0.00 0.00 ] +Key: VPHSUBWrr: [ 0.00 0.00 ] +Key: VPINSRBZrmi: [ 0.00 0.00 ] +Key: VPINSRBZrri: [ 0.00 0.00 ] +Key: VPINSRBrmi: [ 0.00 0.00 ] +Key: VPINSRBrri: [ 0.00 0.00 ] +Key: VPINSRDZrmi: [ 0.00 0.00 ] +Key: VPINSRDZrri: [ 0.00 0.00 ] +Key: VPINSRDrmi: [ 0.00 0.00 ] +Key: VPINSRDrri: [ 0.00 0.00 ] +Key: VPINSRQZrmi: [ 0.00 0.00 ] +Key: VPINSRQZrri: [ 0.00 0.00 ] +Key: VPINSRQrmi: [ 0.00 0.00 ] +Key: VPINSRQrri: [ 0.00 0.00 ] +Key: VPINSRWZrmi: [ 0.00 0.00 ] +Key: VPINSRWZrri: [ 0.00 0.00 ] +Key: VPINSRWrmi: [ 0.00 0.00 ] +Key: VPINSRWrri: [ 0.00 0.00 ] +Key: VPLZCNTDZ: [ 0.00 0.00 ] +Key: VPLZCNTDZrm: [ 0.00 0.00 ] +Key: VPLZCNTDZrmb: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrmk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrr: [ 0.00 0.00 ] +Key: VPLZCNTDZrrk: [ 0.00 0.00 ] +Key: VPLZCNTDZrrkz: [ 0.00 0.00 ] +Key: VPLZCNTQZ: [ 0.00 0.00 ] +Key: VPLZCNTQZrm: [ 0.00 0.00 ] +Key: VPLZCNTQZrmb: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrmk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrr: [ 0.00 0.00 ] +Key: VPLZCNTQZrrk: [ 0.00 0.00 ] +Key: VPLZCNTQZrrkz: [ 0.00 0.00 ] +Key: VPMACSDDrm: [ 0.00 0.00 ] +Key: VPMACSDDrr: [ 0.00 0.00 ] +Key: VPMACSDQHrm: [ 0.00 0.00 ] +Key: VPMACSDQHrr: [ 0.00 0.00 ] +Key: VPMACSDQLrm: [ 0.00 0.00 ] +Key: VPMACSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSDDrm: [ 0.00 0.00 ] +Key: VPMACSSDDrr: [ 0.00 0.00 ] +Key: VPMACSSDQHrm: [ 0.00 0.00 ] +Key: VPMACSSDQHrr: [ 0.00 0.00 ] +Key: VPMACSSDQLrm: [ 0.00 0.00 ] +Key: VPMACSSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSWDrm: [ 0.00 0.00 ] +Key: VPMACSSWDrr: [ 0.00 0.00 ] +Key: VPMACSSWWrm: [ 0.00 0.00 ] +Key: VPMACSSWWrr: [ 0.00 0.00 ] +Key: VPMACSWDrm: [ 0.00 0.00 ] +Key: VPMACSWDrr: [ 0.00 0.00 ] +Key: VPMACSWWrm: [ 0.00 0.00 ] +Key: VPMACSWWrr: [ 0.00 0.00 ] +Key: VPMADCSSWDrm: [ 0.00 0.00 ] +Key: VPMADCSSWDrr: [ 0.00 0.00 ] +Key: VPMADCSWDrm: [ 0.00 0.00 ] +Key: VPMADCSWDrr: [ 0.00 0.00 ] +Key: VPMADD: [ 0.00 0.00 ] +Key: VPMADDUBSWYrm: [ 0.00 0.00 ] +Key: VPMADDUBSWYrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZ: [ 0.00 0.00 ] +Key: VPMADDUBSWZrm: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmkz: [ 0.00 0.00 ] +Key: VPMADDUBSWZrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrkz: [ 0.00 0.00 ] +Key: VPMADDUBSWrm: [ 0.00 0.00 ] +Key: VPMADDUBSWrr: [ 0.00 0.00 ] +Key: VPMADDWDYrm: [ 0.00 0.00 ] +Key: VPMADDWDYrr: [ 0.00 0.00 ] +Key: VPMADDWDZ: [ 0.00 0.00 ] +Key: VPMADDWDZrm: [ 0.00 0.00 ] +Key: VPMADDWDZrmk: [ 0.00 0.00 ] +Key: VPMADDWDZrmkz: [ 0.00 0.00 ] +Key: VPMADDWDZrr: [ 0.00 0.00 ] +Key: VPMADDWDZrrk: [ 0.00 0.00 ] +Key: VPMADDWDZrrkz: [ 0.00 0.00 ] +Key: VPMADDWDrm: [ 0.00 0.00 ] +Key: VPMADDWDrr: [ 0.00 0.00 ] +Key: VPMASKMOVDYmr: [ 0.00 0.00 ] +Key: VPMASKMOVDYrm: [ 0.00 0.00 ] +Key: VPMASKMOVDmr: [ 0.00 0.00 ] +Key: VPMASKMOVDrm: [ 0.00 0.00 ] +Key: VPMASKMOVQYmr: [ 0.00 0.00 ] +Key: VPMASKMOVQYrm: [ 0.00 0.00 ] +Key: VPMASKMOVQmr: [ 0.00 0.00 ] +Key: VPMASKMOVQrm: [ 0.00 0.00 ] +Key: VPMAXSBYrm: [ 0.00 0.00 ] +Key: VPMAXSBYrr: [ 0.00 0.00 ] +Key: VPMAXSBZ: [ 0.00 0.00 ] +Key: VPMAXSBZrm: [ 0.00 0.00 ] +Key: VPMAXSBZrmk: [ 0.00 0.00 ] +Key: VPMAXSBZrmkz: [ 0.00 0.00 ] +Key: VPMAXSBZrr: [ 0.00 0.00 ] +Key: VPMAXSBZrrk: [ 0.00 0.00 ] +Key: VPMAXSBZrrkz: [ 0.00 0.00 ] +Key: VPMAXSBrm: [ 0.00 0.00 ] +Key: VPMAXSBrr: [ 0.00 0.00 ] +Key: VPMAXSDYrm: [ 0.00 0.00 ] +Key: VPMAXSDYrr: [ 0.00 0.00 ] +Key: VPMAXSDZ: [ 0.00 0.00 ] +Key: VPMAXSDZrm: [ 0.00 0.00 ] +Key: VPMAXSDZrmb: [ 0.00 0.00 ] +Key: VPMAXSDZrmbk: [ 0.00 0.00 ] +Key: VPMAXSDZrmbkz: [ 0.00 0.00 ] +Key: VPMAXSDZrmk: [ 0.00 0.00 ] +Key: VPMAXSDZrmkz: [ 0.00 0.00 ] +Key: VPMAXSDZrr: [ 0.00 0.00 ] +Key: VPMAXSDZrrk: [ 0.00 0.00 ] +Key: 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VPMOVUSDBZrr: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSDWZ: [ 0.00 0.00 ] +Key: VPMOVUSDWZmr: [ 0.00 0.00 ] +Key: VPMOVUSDWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrr: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQBZ: [ 0.00 0.00 ] +Key: VPMOVUSQBZmr: [ 0.00 0.00 ] +Key: VPMOVUSQBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrr: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQDZ: [ 0.00 0.00 ] +Key: VPMOVUSQDZmr: [ 0.00 0.00 ] +Key: VPMOVUSQDZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrr: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQWZ: [ 0.00 0.00 ] +Key: VPMOVUSQWZmr: [ 0.00 0.00 ] +Key: VPMOVUSQWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrr: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSWBZ: [ 0.00 0.00 ] +Key: VPMOVUSWBZmr: [ 0.00 0.00 ] +Key: VPMOVUSWBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrr: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVW: [ 0.00 0.00 ] +Key: VPMOVWBZ: [ 0.00 0.00 ] +Key: VPMOVWBZmr: [ 0.00 0.00 ] +Key: VPMOVWBZmrk: [ 0.00 0.00 ] +Key: VPMOVWBZrr: [ 0.00 0.00 ] +Key: VPMOVWBZrrk: [ 0.00 0.00 ] +Key: VPMOVWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDYrm: [ 0.00 0.00 ] +Key: VPMOVZXBDYrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZ: [ 0.00 0.00 ] +Key: VPMOVZXBDZrm: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBDZrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDrm: [ 0.00 0.00 ] +Key: VPMOVZXBDrr: [ 0.00 0.00 ] +Key: VPMOVZXBQYrm: [ 0.00 0.00 ] +Key: VPMOVZXBQYrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZ: [ 0.00 0.00 ] +Key: VPMOVZXBQZrm: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBQZrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBQrm: [ 0.00 0.00 ] +Key: VPMOVZXBQrr: [ 0.00 0.00 ] +Key: VPMOVZXBWYrm: [ 0.00 0.00 ] +Key: VPMOVZXBWYrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZ: [ 0.00 0.00 ] +Key: VPMOVZXBWZrm: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBWZrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBWrm: [ 0.00 0.00 ] +Key: VPMOVZXBWrr: [ 0.00 0.00 ] +Key: VPMOVZXDQYrm: [ 0.00 0.00 ] +Key: VPMOVZXDQYrr: [ 0.00 0.00 ] +Key: VPMOVZXDQZ: [ 0.00 0.00 ] +Key: VPMOVZXDQZrm: [ 0.00 0.00 ] +Key: VPMOVZXDQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXDQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXDQZrr: [ 0.00 0.00 ] +Key: VPMOVZXDQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXDQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXDQrm: [ 0.00 0.00 ] +Key: VPMOVZXDQrr: [ 0.00 0.00 ] +Key: VPMOVZXWDYrm: [ 0.00 0.00 ] +Key: VPMOVZXWDYrr: [ 0.00 0.00 ] +Key: VPMOVZXWDZ: [ 0.00 0.00 ] +Key: VPMOVZXWDZrm: [ 0.00 0.00 ] +Key: VPMOVZXWDZrmk: [ 0.00 0.00 ] +Key: VPMOVZXWDZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXWDZrr: [ 0.00 0.00 ] +Key: VPMOVZXWDZrrk: [ 0.00 0.00 ] +Key: VPMOVZXWDZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXWDrm: [ 0.00 0.00 ] +Key: VPMOVZXWDrr: [ 0.00 0.00 ] +Key: VPMOVZXWQYrm: [ 0.00 0.00 ] +Key: VPMOVZXWQYrr: [ 0.00 0.00 ] +Key: VPMOVZXWQZ: [ 0.00 0.00 ] +Key: VPMOVZXWQZrm: [ 0.00 0.00 ] +Key: VPMOVZXWQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXWQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXWQZrr: [ 0.00 0.00 ] +Key: VPMOVZXWQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXWQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXWQrm: [ 0.00 0.00 ] +Key: VPMOVZXWQrr: [ 0.00 0.00 ] +Key: VPMULDQYrm: [ 0.00 0.00 ] +Key: VPMULDQYrr: [ 0.00 0.00 ] +Key: VPMULDQZ: [ 0.00 0.00 ] +Key: VPMULDQZrm: [ 0.00 0.00 ] +Key: VPMULDQZrmb: [ 0.00 0.00 ] +Key: VPMULDQZrmbk: [ 0.00 0.00 ] +Key: VPMULDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULDQZrmk: [ 0.00 0.00 ] +Key: VPMULDQZrmkz: [ 0.00 0.00 ] +Key: VPMULDQZrr: [ 0.00 0.00 ] +Key: VPMULDQZrrk: [ 0.00 0.00 ] +Key: VPMULDQZrrkz: [ 0.00 0.00 ] +Key: VPMULDQrm: [ 0.00 0.00 ] +Key: VPMULDQrr: [ 0.00 0.00 ] +Key: VPMULHRSWYrm: [ 0.00 0.00 ] +Key: VPMULHRSWYrr: [ 0.00 0.00 ] +Key: VPMULHRSWZ: [ 0.00 0.00 ] +Key: VPMULHRSWZrm: [ 0.00 0.00 ] +Key: VPMULHRSWZrmk: [ 0.00 0.00 ] +Key: VPMULHRSWZrmkz: [ 0.00 0.00 ] +Key: VPMULHRSWZrr: [ 0.00 0.00 ] +Key: VPMULHRSWZrrk: [ 0.00 0.00 ] +Key: VPMULHRSWZrrkz: [ 0.00 0.00 ] +Key: VPMULHRSWrm: [ 0.00 0.00 ] +Key: VPMULHRSWrr: [ 0.00 0.00 ] +Key: VPMULHUWYrm: [ 0.00 0.00 ] +Key: VPMULHUWYrr: [ 0.00 0.00 ] +Key: VPMULHUWZ: [ 0.00 0.00 ] +Key: VPMULHUWZrm: [ 0.00 0.00 ] +Key: VPMULHUWZrmk: [ 0.00 0.00 ] +Key: VPMULHUWZrmkz: [ 0.00 0.00 ] +Key: VPMULHUWZrr: [ 0.00 0.00 ] +Key: VPMULHUWZrrk: [ 0.00 0.00 ] +Key: VPMULHUWZrrkz: [ 0.00 0.00 ] +Key: VPMULHUWrm: [ 0.00 0.00 ] +Key: VPMULHUWrr: [ 0.00 0.00 ] +Key: VPMULHWYrm: [ 0.00 0.00 ] +Key: VPMULHWYrr: [ 0.00 0.00 ] +Key: VPMULHWZ: [ 0.00 0.00 ] +Key: VPMULHWZrm: [ 0.00 0.00 ] +Key: VPMULHWZrmk: [ 0.00 0.00 ] +Key: VPMULHWZrmkz: [ 0.00 0.00 ] +Key: VPMULHWZrr: [ 0.00 0.00 ] +Key: VPMULHWZrrk: [ 0.00 0.00 ] +Key: VPMULHWZrrkz: [ 0.00 0.00 ] +Key: VPMULHWrm: [ 0.00 0.00 ] +Key: VPMULHWrr: [ 0.00 0.00 ] +Key: VPMULLDYrm: [ 0.00 0.00 ] +Key: VPMULLDYrr: [ 0.00 0.00 ] +Key: VPMULLDZ: [ 0.00 0.00 ] +Key: VPMULLDZrm: [ 0.00 0.00 ] +Key: VPMULLDZrmb: [ 0.00 0.00 ] +Key: VPMULLDZrmbk: [ 0.00 0.00 ] +Key: VPMULLDZrmbkz: [ 0.00 0.00 ] +Key: VPMULLDZrmk: [ 0.00 0.00 ] +Key: VPMULLDZrmkz: [ 0.00 0.00 ] +Key: VPMULLDZrr: [ 0.00 0.00 ] +Key: VPMULLDZrrk: [ 0.00 0.00 ] +Key: VPMULLDZrrkz: [ 0.00 0.00 ] +Key: VPMULLDrm: [ 0.00 0.00 ] +Key: VPMULLDrr: [ 0.00 0.00 ] +Key: VPMULLQZ: [ 0.00 0.00 ] +Key: VPMULLQZrm: [ 0.00 0.00 ] +Key: VPMULLQZrmb: [ 0.00 0.00 ] +Key: VPMULLQZrmbk: [ 0.00 0.00 ] +Key: VPMULLQZrmbkz: [ 0.00 0.00 ] +Key: VPMULLQZrmk: [ 0.00 0.00 ] +Key: VPMULLQZrmkz: [ 0.00 0.00 ] +Key: VPMULLQZrr: [ 0.00 0.00 ] +Key: VPMULLQZrrk: [ 0.00 0.00 ] +Key: VPMULLQZrrkz: [ 0.00 0.00 ] +Key: VPMULLWYrm: [ 0.00 0.00 ] +Key: VPMULLWYrr: [ 0.00 0.00 ] +Key: VPMULLWZ: [ 0.00 0.00 ] +Key: VPMULLWZrm: [ 0.00 0.00 ] +Key: VPMULLWZrmk: [ 0.00 0.00 ] +Key: VPMULLWZrmkz: [ 0.00 0.00 ] +Key: VPMULLWZrr: [ 0.00 0.00 ] +Key: VPMULLWZrrk: [ 0.00 0.00 ] +Key: VPMULLWZrrkz: [ 0.00 0.00 ] +Key: VPMULLWrm: [ 0.00 0.00 ] +Key: VPMULLWrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZ: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrm: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmb: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQYrm: [ 0.00 0.00 ] +Key: VPMULUDQYrr: [ 0.00 0.00 ] +Key: VPMULUDQZ: [ 0.00 0.00 ] +Key: VPMULUDQZrm: [ 0.00 0.00 ] +Key: VPMULUDQZrmb: [ 0.00 0.00 ] +Key: VPMULUDQZrmbk: [ 0.00 0.00 ] +Key: VPMULUDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULUDQZrmk: [ 0.00 0.00 ] +Key: VPMULUDQZrmkz: [ 0.00 0.00 ] +Key: VPMULUDQZrr: [ 0.00 0.00 ] +Key: VPMULUDQZrrk: [ 0.00 0.00 ] +Key: VPMULUDQZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQrm: [ 0.00 0.00 ] +Key: VPMULUDQrr: [ 0.00 0.00 ] +Key: VPOPCNTBZ: [ 0.00 0.00 ] +Key: VPOPCNTBZrm: [ 0.00 0.00 ] +Key: VPOPCNTBZrmk: [ 0.00 0.00 ] +Key: VPOPCNTBZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTBZrr: [ 0.00 0.00 ] +Key: VPOPCNTBZrrk: [ 0.00 0.00 ] +Key: VPOPCNTBZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTDZ: [ 0.00 0.00 ] +Key: VPOPCNTDZrm: [ 0.00 0.00 ] +Key: VPOPCNTDZrmb: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrmk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrr: [ 0.00 0.00 ] +Key: VPOPCNTDZrrk: [ 0.00 0.00 ] +Key: VPOPCNTDZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTQZ: [ 0.00 0.00 ] +Key: VPOPCNTQZrm: [ 0.00 0.00 ] +Key: VPOPCNTQZrmb: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrmk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrr: [ 0.00 0.00 ] +Key: VPOPCNTQZrrk: [ 0.00 0.00 ] +Key: VPOPCNTQZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTWZ: [ 0.00 0.00 ] +Key: VPOPCNTWZrm: [ 0.00 0.00 ] +Key: VPOPCNTWZrmk: [ 0.00 0.00 ] +Key: VPOPCNTWZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTWZrr: [ 0.00 0.00 ] +Key: VPOPCNTWZrrk: [ 0.00 0.00 ] +Key: VPOPCNTWZrrkz: [ 0.00 0.00 ] +Key: VPORDZ: [ 0.00 0.00 ] +Key: VPORDZrm: [ 0.00 0.00 ] +Key: VPORDZrmb: [ 0.00 0.00 ] +Key: VPORDZrmbk: [ 0.00 0.00 ] +Key: VPORDZrmbkz: [ 0.00 0.00 ] +Key: VPORDZrmk: [ 0.00 0.00 ] +Key: VPORDZrmkz: [ 0.00 0.00 ] +Key: VPORDZrr: [ 0.00 0.00 ] +Key: VPORDZrrk: [ 0.00 0.00 ] +Key: VPORDZrrkz: [ 0.00 0.00 ] +Key: VPORQZ: [ 0.00 0.00 ] +Key: VPORQZrm: [ 0.00 0.00 ] +Key: VPORQZrmb: [ 0.00 0.00 ] +Key: VPORQZrmbk: [ 0.00 0.00 ] +Key: VPORQZrmbkz: [ 0.00 0.00 ] +Key: VPORQZrmk: [ 0.00 0.00 ] +Key: VPORQZrmkz: [ 0.00 0.00 ] +Key: VPORQZrr: [ 0.00 0.00 ] +Key: VPORQZrrk: [ 0.00 0.00 ] +Key: VPORQZrrkz: [ 0.00 0.00 ] +Key: VPORYrm: [ 0.00 0.00 ] +Key: VPORYrr: [ 0.00 0.00 ] +Key: VPORrm: [ 0.00 0.00 ] +Key: VPORrr: [ 0.00 0.00 ] +Key: VPPERMrmr: [ 0.00 0.00 ] +Key: VPPERMrrm: [ 0.00 0.00 ] +Key: VPPERMrrr: [ 0.00 0.00 ] +Key: VPPERMrrr_REV: [ 0.00 0.00 ] +Key: VPROLDZ: [ 0.00 0.00 ] +Key: VPROLDZmbi: [ 0.00 0.00 ] +Key: VPROLDZmbik: [ 0.00 0.00 ] +Key: VPROLDZmbikz: [ 0.00 0.00 ] +Key: VPROLDZmi: [ 0.00 0.00 ] +Key: VPROLDZmik: [ 0.00 0.00 ] +Key: VPROLDZmikz: [ 0.00 0.00 ] +Key: VPROLDZri: [ 0.00 0.00 ] +Key: VPROLDZrik: [ 0.00 0.00 ] +Key: VPROLDZrikz: [ 0.00 0.00 ] +Key: VPROLQZ: [ 0.00 0.00 ] +Key: VPROLQZmbi: [ 0.00 0.00 ] +Key: VPROLQZmbik: [ 0.00 0.00 ] +Key: VPROLQZmbikz: [ 0.00 0.00 ] +Key: VPROLQZmi: [ 0.00 0.00 ] +Key: VPROLQZmik: [ 0.00 0.00 ] +Key: VPROLQZmikz: [ 0.00 0.00 ] +Key: VPROLQZri: [ 0.00 0.00 ] +Key: VPROLQZrik: [ 0.00 0.00 ] +Key: VPROLQZrikz: [ 0.00 0.00 ] +Key: VPROLVDZ: [ 0.00 0.00 ] +Key: VPROLVDZrm: [ 0.00 0.00 ] +Key: VPROLVDZrmb: [ 0.00 0.00 ] +Key: VPROLVDZrmbk: [ 0.00 0.00 ] +Key: VPROLVDZrmbkz: [ 0.00 0.00 ] +Key: VPROLVDZrmk: [ 0.00 0.00 ] +Key: VPROLVDZrmkz: [ 0.00 0.00 ] +Key: VPROLVDZrr: [ 0.00 0.00 ] +Key: VPROLVDZrrk: [ 0.00 0.00 ] +Key: VPROLVDZrrkz: [ 0.00 0.00 ] +Key: VPROLVQZ: [ 0.00 0.00 ] +Key: VPROLVQZrm: [ 0.00 0.00 ] +Key: VPROLVQZrmb: [ 0.00 0.00 ] +Key: VPROLVQZrmbk: [ 0.00 0.00 ] +Key: VPROLVQZrmbkz: [ 0.00 0.00 ] +Key: VPROLVQZrmk: [ 0.00 0.00 ] +Key: VPROLVQZrmkz: [ 0.00 0.00 ] +Key: VPROLVQZrr: [ 0.00 0.00 ] +Key: VPROLVQZrrk: [ 0.00 0.00 ] +Key: VPROLVQZrrkz: [ 0.00 0.00 ] +Key: VPRORDZ: [ 0.00 0.00 ] +Key: VPRORDZmbi: [ 0.00 0.00 ] +Key: VPRORDZmbik: [ 0.00 0.00 ] +Key: VPRORDZmbikz: [ 0.00 0.00 ] +Key: VPRORDZmi: [ 0.00 0.00 ] +Key: VPRORDZmik: [ 0.00 0.00 ] +Key: VPRORDZmikz: [ 0.00 0.00 ] +Key: VPRORDZri: [ 0.00 0.00 ] +Key: VPRORDZrik: [ 0.00 0.00 ] +Key: VPRORDZrikz: [ 0.00 0.00 ] +Key: VPRORQZ: [ 0.00 0.00 ] +Key: VPRORQZmbi: [ 0.00 0.00 ] +Key: VPRORQZmbik: [ 0.00 0.00 ] +Key: VPRORQZmbikz: [ 0.00 0.00 ] +Key: VPRORQZmi: [ 0.00 0.00 ] +Key: VPRORQZmik: [ 0.00 0.00 ] +Key: VPRORQZmikz: [ 0.00 0.00 ] +Key: VPRORQZri: [ 0.00 0.00 ] +Key: VPRORQZrik: [ 0.00 0.00 ] +Key: VPRORQZrikz: [ 0.00 0.00 ] +Key: VPRORVDZ: [ 0.00 0.00 ] +Key: VPRORVDZrm: [ 0.00 0.00 ] +Key: VPRORVDZrmb: [ 0.00 0.00 ] +Key: VPRORVDZrmbk: [ 0.00 0.00 ] +Key: VPRORVDZrmbkz: [ 0.00 0.00 ] +Key: VPRORVDZrmk: [ 0.00 0.00 ] +Key: VPRORVDZrmkz: [ 0.00 0.00 ] +Key: VPRORVDZrr: [ 0.00 0.00 ] +Key: VPRORVDZrrk: [ 0.00 0.00 ] +Key: VPRORVDZrrkz: [ 0.00 0.00 ] +Key: VPRORVQZ: [ 0.00 0.00 ] +Key: VPRORVQZrm: [ 0.00 0.00 ] +Key: VPRORVQZrmb: [ 0.00 0.00 ] +Key: VPRORVQZrmbk: [ 0.00 0.00 ] +Key: VPRORVQZrmbkz: [ 0.00 0.00 ] +Key: VPRORVQZrmk: [ 0.00 0.00 ] +Key: VPRORVQZrmkz: [ 0.00 0.00 ] +Key: VPRORVQZrr: [ 0.00 0.00 ] +Key: VPRORVQZrrk: [ 0.00 0.00 ] +Key: VPRORVQZrrkz: [ 0.00 0.00 ] +Key: VPROTBmi: [ 0.00 0.00 ] +Key: VPROTBmr: [ 0.00 0.00 ] +Key: VPROTBri: [ 0.00 0.00 ] +Key: VPROTBrm: [ 0.00 0.00 ] +Key: VPROTBrr: [ 0.00 0.00 ] +Key: VPROTBrr_REV: [ 0.00 0.00 ] +Key: VPROTDmi: [ 0.00 0.00 ] +Key: VPROTDmr: [ 0.00 0.00 ] +Key: VPROTDri: [ 0.00 0.00 ] +Key: VPROTDrm: [ 0.00 0.00 ] +Key: VPROTDrr: [ 0.00 0.00 ] +Key: VPROTDrr_REV: [ 0.00 0.00 ] +Key: VPROTQmi: [ 0.00 0.00 ] +Key: VPROTQmr: [ 0.00 0.00 ] +Key: VPROTQri: [ 0.00 0.00 ] +Key: VPROTQrm: [ 0.00 0.00 ] +Key: VPROTQrr: [ 0.00 0.00 ] +Key: VPROTQrr_REV: [ 0.00 0.00 ] +Key: VPROTWmi: [ 0.00 0.00 ] +Key: VPROTWmr: [ 0.00 0.00 ] +Key: VPROTWri: [ 0.00 0.00 ] +Key: VPROTWrm: [ 0.00 0.00 ] +Key: VPROTWrr: [ 0.00 0.00 ] +Key: VPROTWrr_REV: [ 0.00 0.00 ] +Key: VPSADBWYrm: [ 0.00 0.00 ] +Key: VPSADBWYrr: [ 0.00 0.00 ] +Key: VPSADBWZ: [ 0.00 0.00 ] +Key: VPSADBWZrm: [ 0.00 0.00 ] +Key: VPSADBWZrr: [ 0.00 0.00 ] +Key: VPSADBWrm: [ 0.00 0.00 ] +Key: VPSADBWrr: [ 0.00 0.00 ] +Key: VPSCATTERDDZ: [ 0.00 0.00 ] +Key: VPSCATTERDDZmr: [ 0.00 0.00 ] +Key: VPSCATTERDQZ: [ 0.00 0.00 ] +Key: VPSCATTERDQZmr: [ 0.00 0.00 ] +Key: VPSCATTERQDZ: [ 0.00 0.00 ] +Key: VPSCATTERQDZmr: [ 0.00 0.00 ] +Key: VPSCATTERQQZ: [ 0.00 0.00 ] +Key: VPSCATTERQQZmr: [ 0.00 0.00 ] +Key: VPSHABmr: [ 0.00 0.00 ] +Key: VPSHABrm: [ 0.00 0.00 ] +Key: VPSHABrr: [ 0.00 0.00 ] +Key: VPSHABrr_REV: [ 0.00 0.00 ] +Key: VPSHADmr: [ 0.00 0.00 ] +Key: VPSHADrm: [ 0.00 0.00 ] +Key: VPSHADrr: [ 0.00 0.00 ] +Key: VPSHADrr_REV: [ 0.00 0.00 ] +Key: VPSHAQmr: [ 0.00 0.00 ] +Key: VPSHAQrm: [ 0.00 0.00 ] +Key: VPSHAQrr: [ 0.00 0.00 ] +Key: VPSHAQrr_REV: [ 0.00 0.00 ] +Key: VPSHAWmr: [ 0.00 0.00 ] +Key: VPSHAWrm: [ 0.00 0.00 ] +Key: VPSHAWrr: [ 0.00 0.00 ] +Key: VPSHAWrr_REV: [ 0.00 0.00 ] +Key: VPSHLBmr: [ 0.00 0.00 ] +Key: VPSHLBrm: [ 0.00 0.00 ] +Key: VPSHLBrr: [ 0.00 0.00 ] +Key: VPSHLBrr_REV: [ 0.00 0.00 ] +Key: VPSHLDDZ: [ 0.00 0.00 ] +Key: VPSHLDDZrmbi: [ 0.00 0.00 ] +Key: VPSHLDDZrmbik: [ 0.00 0.00 ] +Key: VPSHLDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDDZrmi: [ 0.00 0.00 ] +Key: VPSHLDDZrmik: [ 0.00 0.00 ] +Key: VPSHLDDZrmikz: [ 0.00 0.00 ] +Key: VPSHLDDZrri: [ 0.00 0.00 ] +Key: VPSHLDDZrrik: [ 0.00 0.00 ] +Key: VPSHLDDZrrikz: [ 0.00 0.00 ] +Key: VPSHLDQZ: [ 0.00 0.00 ] +Key: VPSHLDQZrmbi: [ 0.00 0.00 ] +Key: VPSHLDQZrmbik: [ 0.00 0.00 ] +Key: VPSHLDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDQZrmi: [ 0.00 0.00 ] +Key: VPSHLDQZrmik: [ 0.00 0.00 ] +Key: VPSHLDQZrmikz: [ 0.00 0.00 ] +Key: VPSHLDQZrri: [ 0.00 0.00 ] +Key: VPSHLDQZrrik: [ 0.00 0.00 ] +Key: VPSHLDQZrrikz: [ 0.00 0.00 ] +Key: VPSHLDVDZ: [ 0.00 0.00 ] +Key: VPSHLDVDZm: [ 0.00 0.00 ] +Key: VPSHLDVDZmb: [ 0.00 0.00 ] +Key: VPSHLDVDZmbk: [ 0.00 0.00 ] +Key: VPSHLDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVDZmk: [ 0.00 0.00 ] +Key: VPSHLDVDZmkz: [ 0.00 0.00 ] +Key: VPSHLDVDZr: [ 0.00 0.00 ] +Key: VPSHLDVDZrk: [ 0.00 0.00 ] +Key: VPSHLDVDZrkz: [ 0.00 0.00 ] +Key: VPSHLDVQZ: [ 0.00 0.00 ] +Key: VPSHLDVQZm: [ 0.00 0.00 ] +Key: VPSHLDVQZmb: [ 0.00 0.00 ] +Key: VPSHLDVQZmbk: [ 0.00 0.00 ] +Key: VPSHLDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVQZmk: [ 0.00 0.00 ] +Key: VPSHLDVQZmkz: [ 0.00 0.00 ] +Key: VPSHLDVQZr: [ 0.00 0.00 ] +Key: VPSHLDVQZrk: [ 0.00 0.00 ] +Key: VPSHLDVQZrkz: [ 0.00 0.00 ] +Key: VPSHLDVWZ: [ 0.00 0.00 ] +Key: VPSHLDVWZm: [ 0.00 0.00 ] +Key: VPSHLDVWZmk: [ 0.00 0.00 ] +Key: VPSHLDVWZmkz: [ 0.00 0.00 ] +Key: VPSHLDVWZr: [ 0.00 0.00 ] +Key: VPSHLDVWZrk: [ 0.00 0.00 ] +Key: VPSHLDVWZrkz: [ 0.00 0.00 ] +Key: VPSHLDWZ: [ 0.00 0.00 ] +Key: VPSHLDWZrmi: [ 0.00 0.00 ] +Key: VPSHLDWZrmik: [ 0.00 0.00 ] +Key: VPSHLDWZrmikz: [ 0.00 0.00 ] +Key: VPSHLDWZrri: [ 0.00 0.00 ] +Key: VPSHLDWZrrik: [ 0.00 0.00 ] +Key: VPSHLDWZrrikz: [ 0.00 0.00 ] +Key: VPSHLDmr: [ 0.00 0.00 ] +Key: VPSHLDrm: [ 0.00 0.00 ] +Key: VPSHLDrr: [ 0.00 0.00 ] +Key: VPSHLDrr_REV: [ 0.00 0.00 ] +Key: VPSHLQmr: [ 0.00 0.00 ] +Key: VPSHLQrm: [ 0.00 0.00 ] +Key: VPSHLQrr: [ 0.00 0.00 ] +Key: VPSHLQrr_REV: [ 0.00 0.00 ] +Key: VPSHLWmr: [ 0.00 0.00 ] +Key: VPSHLWrm: [ 0.00 0.00 ] +Key: VPSHLWrr: [ 0.00 0.00 ] +Key: VPSHLWrr_REV: [ 0.00 0.00 ] +Key: VPSHRDDZ: [ 0.00 0.00 ] +Key: VPSHRDDZrmbi: [ 0.00 0.00 ] +Key: VPSHRDDZrmbik: [ 0.00 0.00 ] +Key: VPSHRDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDDZrmi: [ 0.00 0.00 ] +Key: VPSHRDDZrmik: [ 0.00 0.00 ] +Key: VPSHRDDZrmikz: [ 0.00 0.00 ] +Key: VPSHRDDZrri: [ 0.00 0.00 ] +Key: VPSHRDDZrrik: [ 0.00 0.00 ] +Key: VPSHRDDZrrikz: [ 0.00 0.00 ] +Key: VPSHRDQZ: [ 0.00 0.00 ] +Key: VPSHRDQZrmbi: [ 0.00 0.00 ] +Key: VPSHRDQZrmbik: [ 0.00 0.00 ] +Key: VPSHRDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDQZrmi: [ 0.00 0.00 ] +Key: VPSHRDQZrmik: [ 0.00 0.00 ] +Key: VPSHRDQZrmikz: [ 0.00 0.00 ] +Key: VPSHRDQZrri: [ 0.00 0.00 ] +Key: VPSHRDQZrrik: [ 0.00 0.00 ] +Key: VPSHRDQZrrikz: [ 0.00 0.00 ] +Key: VPSHRDVDZ: [ 0.00 0.00 ] +Key: VPSHRDVDZm: [ 0.00 0.00 ] +Key: VPSHRDVDZmb: [ 0.00 0.00 ] +Key: VPSHRDVDZmbk: [ 0.00 0.00 ] +Key: VPSHRDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVDZmk: [ 0.00 0.00 ] +Key: VPSHRDVDZmkz: [ 0.00 0.00 ] +Key: VPSHRDVDZr: [ 0.00 0.00 ] +Key: VPSHRDVDZrk: [ 0.00 0.00 ] +Key: VPSHRDVDZrkz: [ 0.00 0.00 ] +Key: VPSHRDVQZ: [ 0.00 0.00 ] +Key: VPSHRDVQZm: [ 0.00 0.00 ] +Key: VPSHRDVQZmb: [ 0.00 0.00 ] +Key: VPSHRDVQZmbk: [ 0.00 0.00 ] +Key: VPSHRDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVQZmk: [ 0.00 0.00 ] +Key: VPSHRDVQZmkz: [ 0.00 0.00 ] +Key: VPSHRDVQZr: [ 0.00 0.00 ] +Key: VPSHRDVQZrk: [ 0.00 0.00 ] +Key: VPSHRDVQZrkz: [ 0.00 0.00 ] +Key: VPSHRDVWZ: [ 0.00 0.00 ] +Key: VPSHRDVWZm: [ 0.00 0.00 ] +Key: VPSHRDVWZmk: [ 0.00 0.00 ] +Key: VPSHRDVWZmkz: [ 0.00 0.00 ] +Key: VPSHRDVWZr: [ 0.00 0.00 ] +Key: VPSHRDVWZrk: [ 0.00 0.00 ] +Key: VPSHRDVWZrkz: [ 0.00 0.00 ] +Key: VPSHRDWZ: [ 0.00 0.00 ] +Key: VPSHRDWZrmi: [ 0.00 0.00 ] +Key: VPSHRDWZrmik: [ 0.00 0.00 ] +Key: VPSHRDWZrmikz: [ 0.00 0.00 ] +Key: VPSHRDWZrri: [ 0.00 0.00 ] +Key: VPSHRDWZrrik: [ 0.00 0.00 ] +Key: VPSHRDWZrrikz: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZ: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrm: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrr: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBYrm: [ 0.00 0.00 ] +Key: VPSHUFBYrr: [ 0.00 0.00 ] +Key: VPSHUFBZ: [ 0.00 0.00 ] +Key: VPSHUFBZrm: [ 0.00 0.00 ] +Key: VPSHUFBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBZrmkz: [ 0.00 0.00 ] +Key: VPSHUFBZrr: [ 0.00 0.00 ] +Key: VPSHUFBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBZrrkz: [ 0.00 0.00 ] +Key: VPSHUFBrm: [ 0.00 0.00 ] +Key: VPSHUFBrr: [ 0.00 0.00 ] +Key: VPSHUFDYmi: [ 0.00 0.00 ] +Key: VPSHUFDYri: [ 0.00 0.00 ] +Key: VPSHUFDZ: [ 0.00 0.00 ] +Key: VPSHUFDZmbi: [ 0.00 0.00 ] +Key: VPSHUFDZmbik: [ 0.00 0.00 ] +Key: VPSHUFDZmbikz: [ 0.00 0.00 ] +Key: VPSHUFDZmi: [ 0.00 0.00 ] +Key: VPSHUFDZmik: [ 0.00 0.00 ] +Key: VPSHUFDZmikz: [ 0.00 0.00 ] +Key: VPSHUFDZri: [ 0.00 0.00 ] +Key: VPSHUFDZrik: [ 0.00 0.00 ] +Key: VPSHUFDZrikz: [ 0.00 0.00 ] +Key: VPSHUFDmi: [ 0.00 0.00 ] +Key: VPSHUFDri: [ 0.00 0.00 ] +Key: VPSHUFHWYmi: [ 0.00 0.00 ] +Key: VPSHUFHWYri: [ 0.00 0.00 ] +Key: VPSHUFHWZ: [ 0.00 0.00 ] +Key: VPSHUFHWZmi: [ 0.00 0.00 ] +Key: VPSHUFHWZmik: [ 0.00 0.00 ] +Key: VPSHUFHWZmikz: [ 0.00 0.00 ] +Key: VPSHUFHWZri: [ 0.00 0.00 ] +Key: VPSHUFHWZrik: [ 0.00 0.00 ] +Key: VPSHUFHWZrikz: [ 0.00 0.00 ] +Key: VPSHUFHWmi: [ 0.00 0.00 ] +Key: VPSHUFHWri: [ 0.00 0.00 ] +Key: VPSHUFLWYmi: [ 0.00 0.00 ] +Key: VPSHUFLWYri: [ 0.00 0.00 ] +Key: VPSHUFLWZ: [ 0.00 0.00 ] +Key: VPSHUFLWZmi: [ 0.00 0.00 ] +Key: VPSHUFLWZmik: [ 0.00 0.00 ] +Key: VPSHUFLWZmikz: [ 0.00 0.00 ] +Key: VPSHUFLWZri: [ 0.00 0.00 ] +Key: VPSHUFLWZrik: [ 0.00 0.00 ] +Key: VPSHUFLWZrikz: [ 0.00 0.00 ] +Key: VPSHUFLWmi: [ 0.00 0.00 ] +Key: VPSHUFLWri: [ 0.00 0.00 ] +Key: VPSIGNBYrm: [ 0.00 0.00 ] +Key: VPSIGNBYrr: [ 0.00 0.00 ] +Key: VPSIGNBrm: [ 0.00 0.00 ] +Key: VPSIGNBrr: [ 0.00 0.00 ] +Key: VPSIGNDYrm: [ 0.00 0.00 ] +Key: VPSIGNDYrr: [ 0.00 0.00 ] +Key: VPSIGNDrm: [ 0.00 0.00 ] +Key: VPSIGNDrr: [ 0.00 0.00 ] +Key: VPSIGNWYrm: [ 0.00 0.00 ] +Key: VPSIGNWYrr: [ 0.00 0.00 ] +Key: VPSIGNWrm: [ 0.00 0.00 ] +Key: VPSIGNWrr: [ 0.00 0.00 ] +Key: VPSLLDQYri: [ 0.00 0.00 ] +Key: VPSLLDQZ: [ 0.00 0.00 ] +Key: VPSLLDQZmi: [ 0.00 0.00 ] +Key: VPSLLDQZri: [ 0.00 0.00 ] +Key: VPSLLDQri: [ 0.00 0.00 ] +Key: VPSLLDYri: [ 0.00 0.00 ] +Key: VPSLLDYrm: [ 0.00 0.00 ] +Key: VPSLLDYrr: [ 0.00 0.00 ] +Key: VPSLLDZ: [ 0.00 0.00 ] +Key: VPSLLDZmbi: [ 0.00 0.00 ] +Key: VPSLLDZmbik: [ 0.00 0.00 ] +Key: VPSLLDZmbikz: [ 0.00 0.00 ] +Key: VPSLLDZmi: [ 0.00 0.00 ] +Key: VPSLLDZmik: [ 0.00 0.00 ] +Key: VPSLLDZmikz: [ 0.00 0.00 ] +Key: VPSLLDZri: [ 0.00 0.00 ] +Key: VPSLLDZrik: [ 0.00 0.00 ] +Key: VPSLLDZrikz: [ 0.00 0.00 ] +Key: VPSLLDZrm: [ 0.00 0.00 ] +Key: VPSLLDZrmk: [ 0.00 0.00 ] +Key: VPSLLDZrmkz: [ 0.00 0.00 ] +Key: VPSLLDZrr: [ 0.00 0.00 ] +Key: VPSLLDZrrk: [ 0.00 0.00 ] +Key: VPSLLDZrrkz: [ 0.00 0.00 ] +Key: VPSLLDri: [ 0.00 0.00 ] +Key: VPSLLDrm: [ 0.00 0.00 ] +Key: VPSLLDrr: [ 0.00 0.00 ] +Key: VPSLLQYri: [ 0.00 0.00 ] +Key: VPSLLQYrm: [ 0.00 0.00 ] +Key: VPSLLQYrr: [ 0.00 0.00 ] +Key: VPSLLQZ: [ 0.00 0.00 ] +Key: VPSLLQZmbi: [ 0.00 0.00 ] +Key: VPSLLQZmbik: [ 0.00 0.00 ] +Key: VPSLLQZmbikz: [ 0.00 0.00 ] +Key: VPSLLQZmi: [ 0.00 0.00 ] +Key: VPSLLQZmik: [ 0.00 0.00 ] +Key: VPSLLQZmikz: [ 0.00 0.00 ] +Key: VPSLLQZri: [ 0.00 0.00 ] +Key: VPSLLQZrik: [ 0.00 0.00 ] +Key: VPSLLQZrikz: [ 0.00 0.00 ] +Key: VPSLLQZrm: [ 0.00 0.00 ] +Key: VPSLLQZrmk: [ 0.00 0.00 ] +Key: VPSLLQZrmkz: [ 0.00 0.00 ] +Key: VPSLLQZrr: [ 0.00 0.00 ] +Key: VPSLLQZrrk: [ 0.00 0.00 ] +Key: VPSLLQZrrkz: [ 0.00 0.00 ] +Key: VPSLLQri: [ 0.00 0.00 ] +Key: VPSLLQrm: [ 0.00 0.00 ] +Key: VPSLLQrr: [ 0.00 0.00 ] +Key: VPSLLVDYrm: [ 0.00 0.00 ] +Key: VPSLLVDYrr: [ 0.00 0.00 ] +Key: VPSLLVDZ: [ 0.00 0.00 ] +Key: VPSLLVDZrm: [ 0.00 0.00 ] +Key: VPSLLVDZrmb: [ 0.00 0.00 ] +Key: VPSLLVDZrmbk: [ 0.00 0.00 ] +Key: VPSLLVDZrmbkz: [ 0.00 0.00 ] +Key: VPSLLVDZrmk: [ 0.00 0.00 ] +Key: VPSLLVDZrmkz: [ 0.00 0.00 ] +Key: VPSLLVDZrr: [ 0.00 0.00 ] +Key: VPSLLVDZrrk: [ 0.00 0.00 ] +Key: VPSLLVDZrrkz: [ 0.00 0.00 ] +Key: VPSLLVDrm: [ 0.00 0.00 ] +Key: VPSLLVDrr: [ 0.00 0.00 ] +Key: VPSLLVQYrm: [ 0.00 0.00 ] +Key: VPSLLVQYrr: [ 0.00 0.00 ] +Key: VPSLLVQZ: [ 0.00 0.00 ] +Key: VPSLLVQZrm: [ 0.00 0.00 ] +Key: VPSLLVQZrmb: [ 0.00 0.00 ] +Key: VPSLLVQZrmbk: [ 0.00 0.00 ] +Key: VPSLLVQZrmbkz: [ 0.00 0.00 ] +Key: VPSLLVQZrmk: [ 0.00 0.00 ] +Key: VPSLLVQZrmkz: [ 0.00 0.00 ] +Key: VPSLLVQZrr: [ 0.00 0.00 ] +Key: VPSLLVQZrrk: [ 0.00 0.00 ] +Key: VPSLLVQZrrkz: [ 0.00 0.00 ] +Key: VPSLLVQrm: [ 0.00 0.00 ] +Key: VPSLLVQrr: [ 0.00 0.00 ] +Key: VPSLLVWZ: [ 0.00 0.00 ] +Key: VPSLLVWZrm: [ 0.00 0.00 ] +Key: VPSLLVWZrmk: [ 0.00 0.00 ] +Key: VPSLLVWZrmkz: [ 0.00 0.00 ] +Key: VPSLLVWZrr: [ 0.00 0.00 ] +Key: VPSLLVWZrrk: [ 0.00 0.00 ] +Key: VPSLLVWZrrkz: [ 0.00 0.00 ] +Key: VPSLLWYri: [ 0.00 0.00 ] +Key: VPSLLWYrm: [ 0.00 0.00 ] +Key: VPSLLWYrr: [ 0.00 0.00 ] +Key: VPSLLWZ: [ 0.00 0.00 ] +Key: VPSLLWZmi: [ 0.00 0.00 ] +Key: VPSLLWZmik: [ 0.00 0.00 ] +Key: VPSLLWZmikz: [ 0.00 0.00 ] +Key: VPSLLWZri: [ 0.00 0.00 ] +Key: VPSLLWZrik: [ 0.00 0.00 ] +Key: VPSLLWZrikz: [ 0.00 0.00 ] +Key: VPSLLWZrm: [ 0.00 0.00 ] +Key: VPSLLWZrmk: [ 0.00 0.00 ] +Key: VPSLLWZrmkz: [ 0.00 0.00 ] +Key: VPSLLWZrr: [ 0.00 0.00 ] +Key: VPSLLWZrrk: [ 0.00 0.00 ] +Key: VPSLLWZrrkz: [ 0.00 0.00 ] +Key: VPSLLWri: [ 0.00 0.00 ] +Key: VPSLLWrm: [ 0.00 0.00 ] +Key: VPSLLWrr: [ 0.00 0.00 ] +Key: VPSRADYri: [ 0.00 0.00 ] +Key: VPSRADYrm: [ 0.00 0.00 ] +Key: VPSRADYrr: [ 0.00 0.00 ] +Key: VPSRADZ: [ 0.00 0.00 ] +Key: VPSRADZmbi: [ 0.00 0.00 ] +Key: VPSRADZmbik: [ 0.00 0.00 ] +Key: VPSRADZmbikz: [ 0.00 0.00 ] +Key: VPSRADZmi: [ 0.00 0.00 ] +Key: VPSRADZmik: [ 0.00 0.00 ] +Key: VPSRADZmikz: [ 0.00 0.00 ] +Key: VPSRADZri: [ 0.00 0.00 ] +Key: VPSRADZrik: [ 0.00 0.00 ] +Key: VPSRADZrikz: [ 0.00 0.00 ] +Key: VPSRADZrm: [ 0.00 0.00 ] +Key: VPSRADZrmk: [ 0.00 0.00 ] +Key: VPSRADZrmkz: [ 0.00 0.00 ] +Key: VPSRADZrr: [ 0.00 0.00 ] +Key: VPSRADZrrk: [ 0.00 0.00 ] +Key: VPSRADZrrkz: [ 0.00 0.00 ] +Key: VPSRADri: [ 0.00 0.00 ] +Key: VPSRADrm: [ 0.00 0.00 ] +Key: VPSRADrr: [ 0.00 0.00 ] +Key: VPSRAQZ: [ 0.00 0.00 ] +Key: VPSRAQZmbi: [ 0.00 0.00 ] +Key: VPSRAQZmbik: [ 0.00 0.00 ] +Key: VPSRAQZmbikz: [ 0.00 0.00 ] +Key: VPSRAQZmi: [ 0.00 0.00 ] +Key: VPSRAQZmik: [ 0.00 0.00 ] +Key: VPSRAQZmikz: [ 0.00 0.00 ] +Key: VPSRAQZri: [ 0.00 0.00 ] +Key: VPSRAQZrik: [ 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VREDUCESDZrribkz: [ 0.00 0.00 ] +Key: VREDUCESDZrrik: [ 0.00 0.00 ] +Key: VREDUCESDZrrikz: [ 0.00 0.00 ] +Key: VREDUCESHZrmi: [ 0.00 0.00 ] +Key: VREDUCESHZrmik: [ 0.00 0.00 ] +Key: VREDUCESHZrmikz: [ 0.00 0.00 ] +Key: VREDUCESHZrri: [ 0.00 0.00 ] +Key: VREDUCESHZrrib: [ 0.00 0.00 ] +Key: VREDUCESHZrribk: [ 0.00 0.00 ] +Key: VREDUCESHZrribkz: [ 0.00 0.00 ] +Key: VREDUCESHZrrik: [ 0.00 0.00 ] +Key: VREDUCESHZrrikz: [ 0.00 0.00 ] +Key: VREDUCESSZrmi: [ 0.00 0.00 ] +Key: VREDUCESSZrmik: [ 0.00 0.00 ] +Key: VREDUCESSZrmikz: [ 0.00 0.00 ] +Key: VREDUCESSZrri: [ 0.00 0.00 ] +Key: VREDUCESSZrrib: [ 0.00 0.00 ] +Key: VREDUCESSZrribk: [ 0.00 0.00 ] +Key: VREDUCESSZrribkz: [ 0.00 0.00 ] +Key: VREDUCESSZrrik: [ 0.00 0.00 ] +Key: VREDUCESSZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALEBF: [ 0.00 0.00 ] +Key: VRNDSCALEPDZ: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmbi: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmbik: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmbikz: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmi: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmik: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmikz: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrri: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrrib: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrribk: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrribkz: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrrik: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZ: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmbi: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmbik: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmbikz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmi: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmik: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmikz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrri: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrrib: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrribk: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrribkz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrrik: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZ: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmbi: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmbik: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmbikz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmi: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmik: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmikz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrri: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrrib: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrribk: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrribkz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrrik: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmi: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmi_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmik_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmikz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrri: [ 0.00 0.00 ] +Key: VRNDSCALESDZrri_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrrib_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrribk_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrribkz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrrik_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrrikz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmi: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmi_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmik_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmikz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrri: [ 0.00 0.00 ] +Key: VRNDSCALESHZrri_Int: [ 0.00 0.00 ] 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0.00 ] +Key: VXORPSZrmkz: [ 0.00 0.00 ] +Key: VXORPSZrr: [ 0.00 0.00 ] +Key: VXORPSZrrk: [ 0.00 0.00 ] +Key: VXORPSZrrkz: [ 0.00 0.00 ] +Key: VXORPSrm: [ 0.00 0.00 ] +Key: VXORPSrr: [ 0.00 0.00 ] +Key: VZEROALL: [ 0.00 0.00 ] +Key: VZEROUPPER: [ 0.00 0.00 ] +Key: V_SET: [ 0.00 0.00 ] +Key: V_SETALLONES: [ 0.00 0.00 ] +Key: WAIT: [ 0.00 0.00 ] +Key: WBINVD: [ 0.00 0.00 ] +Key: WBNOINVD: [ 0.00 0.00 ] +Key: WRFLAGS: [ 0.00 0.00 ] +Key: WRFSBASE: [ 0.00 0.00 ] +Key: WRGSBASE: [ 0.00 0.00 ] +Key: WRMSR: [ 0.00 0.00 ] +Key: WRMSRLIST: [ 0.00 0.00 ] +Key: WRMSRNS: [ 0.00 0.00 ] +Key: WRMSRNSir: [ 0.00 0.00 ] +Key: WRMSRNSir_EVEX: [ 0.00 0.00 ] +Key: WRPKRUr: [ 0.00 0.00 ] +Key: WRSSD: [ 0.00 0.00 ] +Key: WRSSD_EVEX: [ 0.00 0.00 ] +Key: WRSSQ: [ 0.00 0.00 ] +Key: WRSSQ_EVEX: [ 0.00 0.00 ] +Key: WRUSSD: [ 0.00 0.00 ] +Key: WRUSSD_EVEX: [ 0.00 0.00 ] +Key: WRUSSQ: [ 0.00 0.00 ] +Key: WRUSSQ_EVEX: [ 0.00 0.00 ] +Key: XABORT: [ 0.00 0.00 ] +Key: XABORT_DEF: [ 0.00 0.00 ] +Key: XACQUIRE_PREFIX: [ 0.00 0.00 ] +Key: XADD: [ 0.00 0.00 ] +Key: XAM_F: [ 0.00 0.00 ] +Key: XAM_Fp: [ 0.00 0.00 ] +Key: XBEGIN: [ 0.00 0.00 ] +Key: XCHG: [ 0.00 0.00 ] +Key: XCH_F: [ 0.00 0.00 ] +Key: XCRYPTCBC: [ 0.00 0.00 ] +Key: XCRYPTCFB: [ 0.00 0.00 ] +Key: XCRYPTCTR: [ 0.00 0.00 ] +Key: XCRYPTECB: [ 0.00 0.00 ] +Key: XCRYPTOFB: [ 0.00 0.00 ] +Key: XEND: [ 0.00 0.00 ] +Key: XGETBV: [ 0.00 0.00 ] +Key: XLAT: [ 0.00 0.00 ] +Key: XOR: [ 0.00 0.00 ] +Key: XORPDrm: [ 0.00 0.00 ] +Key: XORPDrr: [ 0.00 0.00 ] +Key: XORPSrm: [ 0.00 0.00 ] +Key: XORPSrr: [ 0.00 0.00 ] +Key: XRELEASE_PREFIX: [ 0.00 0.00 ] +Key: XRESLDTRK: [ 0.00 0.00 ] +Key: XRSTOR: [ 0.00 0.00 ] +Key: XRSTORS: [ 0.00 0.00 ] +Key: XSAVE: [ 0.00 0.00 ] +Key: XSAVEC: [ 0.00 0.00 ] +Key: XSAVEOPT: [ 0.00 0.00 ] +Key: XSAVES: [ 0.00 0.00 ] +Key: XSETBV: [ 0.00 0.00 ] +Key: XSHA: [ 0.00 0.00 ] +Key: XSTORE: [ 0.00 0.00 ] +Key: XSUSLDTRK: [ 0.00 0.00 ] +Key: XTEST: [ 0.00 0.00 ] diff --git a/llvm/test/CodeGen/MIR2Vec/vocab-basic.ll b/llvm/test/CodeGen/MIR2Vec/vocab-basic.ll new file mode 100644 index 0000000..a57dd0b --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/vocab-basic.ll @@ -0,0 +1,14 @@ +; REQUIRES: x86_64-linux +; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_2D_vocab.json %s 2> %t1.log +; RUN: diff %S/Inputs/reference_x86_vocab_print.txt %t1.log + +; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-opc-weight=1 -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_2D_vocab.json %s 2> %t1.log +; RUN: diff %S/Inputs/reference_x86_vocab_print.txt %t1.log + +; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-opc-weight=0.5 -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_2D_vocab.json %s 2> %t1.log +; RUN: diff %S/Inputs/reference_x86_vocab_wo=0.5_print.txt %t1.log + +define dso_local void @test() { + entry: + ret void +} diff --git a/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll b/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll new file mode 100644 index 0000000..1da516a --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll @@ -0,0 +1,15 @@ +; REQUIRES: x86_64-linux +; RUN: not llc -o /dev/null -print-mir2vec-vocab %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID +; RUN: not llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_zero_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-ZERO-DIM +; RUN: not llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_invalid_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ENTITIES +; RUN: not llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_inconsistent_dims.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-INCONSISTENT-DIMS + +define dso_local void @test() { + entry: + ret void +} + +; CHECK-INVALID: error: MIR2Vec vocabulary file path not specified; set it using --mir2vec-vocab-path +; CHECK-ZERO-DIM: error: Dimension of 'entities' section of the vocabulary is zero +; CHECK-NO-ENTITIES: error: Missing 'entities' section in vocabulary file +; CHECK-INCONSISTENT-DIMS: error: All vectors in the 'entities' section of the vocabulary are not of the same dimension diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll index 4ad2d2c..4914357 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll @@ -23,6 +23,16 @@ ; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s +; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+experimental-zalasr -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s +; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s + +; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+experimental-zalasr -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s +; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s + define float @atomic_load_f32_unordered(ptr %a) nounwind { ; RV32I-LABEL: atomic_load_f32_unordered: @@ -171,6 +181,30 @@ define float @atomic_load_f32_acquire(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: lw a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.w.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-WMO-LABEL: atomic_load_f32_acquire: +; RV32IA-ZALASR-WMO: # %bb.0: +; RV32IA-ZALASR-WMO-NEXT: lw.aq a0, (a0) +; RV32IA-ZALASR-WMO-NEXT: fmv.w.x fa0, a0 +; RV32IA-ZALASR-WMO-NEXT: ret +; +; RV32IA-ZALASR-TSO-LABEL: atomic_load_f32_acquire: +; RV32IA-ZALASR-TSO: # %bb.0: +; RV32IA-ZALASR-TSO-NEXT: lw a0, 0(a0) +; RV32IA-ZALASR-TSO-NEXT: fmv.w.x fa0, a0 +; RV32IA-ZALASR-TSO-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_load_f32_acquire: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: lw.aq a0, (a0) +; RV64IA-ZALASR-WMO-NEXT: fmv.w.x fa0, a0 +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_load_f32_acquire: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: lw a0, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: fmv.w.x fa0, a0 +; RV64IA-ZALASR-TSO-NEXT: ret %1 = load atomic float, ptr %a acquire, align 4 ret float %1 } @@ -256,6 +290,18 @@ define float @atomic_load_f32_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: lw a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.w.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-LABEL: atomic_load_f32_seq_cst: +; RV32IA-ZALASR: # %bb.0: +; RV32IA-ZALASR-NEXT: lw.aq a0, (a0) +; RV32IA-ZALASR-NEXT: fmv.w.x fa0, a0 +; RV32IA-ZALASR-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_load_f32_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: lw.aq a0, (a0) +; RV64IA-ZALASR-NEXT: fmv.w.x fa0, a0 +; RV64IA-ZALASR-NEXT: ret %1 = load atomic float, ptr %a seq_cst, align 4 ret float %1 } @@ -414,6 +460,18 @@ define double @atomic_load_f64_acquire(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: ld a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.d.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_load_f64_acquire: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: ld.aq a0, (a0) +; RV64IA-ZALASR-WMO-NEXT: fmv.d.x fa0, a0 +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_load_f64_acquire: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: ld a0, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: fmv.d.x fa0, a0 +; RV64IA-ZALASR-TSO-NEXT: ret %1 = load atomic double, ptr %a acquire, align 8 ret double %1 } @@ -484,6 +542,12 @@ define double @atomic_load_f64_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: ld a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.d.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_load_f64_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: ld.aq a0, (a0) +; RV64IA-ZALASR-NEXT: fmv.d.x fa0, a0 +; RV64IA-ZALASR-NEXT: ret %1 = load atomic double, ptr %a seq_cst, align 8 ret double %1 } @@ -635,6 +699,30 @@ define void @atomic_store_f32_release(ptr %a, float %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.x.w a1, fa0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: sw a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-WMO-LABEL: atomic_store_f32_release: +; RV32IA-ZALASR-WMO: # %bb.0: +; RV32IA-ZALASR-WMO-NEXT: fmv.x.w a1, fa0 +; RV32IA-ZALASR-WMO-NEXT: sw.rl a1, (a0) +; RV32IA-ZALASR-WMO-NEXT: ret +; +; RV32IA-ZALASR-TSO-LABEL: atomic_store_f32_release: +; RV32IA-ZALASR-TSO: # %bb.0: +; RV32IA-ZALASR-TSO-NEXT: fmv.x.w a1, fa0 +; RV32IA-ZALASR-TSO-NEXT: sw a1, 0(a0) +; RV32IA-ZALASR-TSO-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_store_f32_release: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: fmv.x.w a1, fa0 +; RV64IA-ZALASR-WMO-NEXT: sw.rl a1, (a0) +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_store_f32_release: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: fmv.x.w a1, fa0 +; RV64IA-ZALASR-TSO-NEXT: sw a1, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: ret store atomic float %b, ptr %a release, align 4 ret void } @@ -718,6 +806,18 @@ define void @atomic_store_f32_seq_cst(ptr %a, float %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: sw a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-LABEL: atomic_store_f32_seq_cst: +; RV32IA-ZALASR: # %bb.0: +; RV32IA-ZALASR-NEXT: fmv.x.w a1, fa0 +; RV32IA-ZALASR-NEXT: sw.rl a1, (a0) +; RV32IA-ZALASR-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_store_f32_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: fmv.x.w a1, fa0 +; RV64IA-ZALASR-NEXT: sw.rl a1, (a0) +; RV64IA-ZALASR-NEXT: ret store atomic float %b, ptr %a seq_cst, align 4 ret void } @@ -876,6 +976,18 @@ define void @atomic_store_f64_release(ptr %a, double %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.x.d a1, fa0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: sd a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_store_f64_release: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: fmv.x.d a1, fa0 +; RV64IA-ZALASR-WMO-NEXT: sd.rl a1, (a0) +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_store_f64_release: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: fmv.x.d a1, fa0 +; RV64IA-ZALASR-TSO-NEXT: sd a1, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: ret store atomic double %b, ptr %a release, align 8 ret void } @@ -945,6 +1057,12 @@ define void @atomic_store_f64_seq_cst(ptr %a, double %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: sd a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_store_f64_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: fmv.x.d a1, fa0 +; RV64IA-ZALASR-NEXT: sd.rl a1, (a0) +; RV64IA-ZALASR-NEXT: ret store atomic double %b, ptr %a seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir index 74249c1..e2d3bff 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir @@ -17,7 +17,7 @@ body: | ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV32IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s8)) + ; RV32IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8)) ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]] ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -42,7 +42,7 @@ body: | ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV32IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s16)) + ; RV32IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16)) ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]] ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -67,7 +67,7 @@ body: | ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32)) ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]] ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -92,7 +92,7 @@ body: | ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32)) ; RV32IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_W]], 1 ; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir index a2f7e30..ab537ea 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir @@ -17,7 +17,7 @@ body: | ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV64IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s8)) + ; RV64IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8)) ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]] ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -42,7 +42,7 @@ body: | ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV64IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s16)) + ; RV64IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16)) ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]] ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -67,7 +67,7 @@ body: | ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV64IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s32)) + ; RV64IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32)) ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]] ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -92,7 +92,7 @@ body: | ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s64)) + ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64)) ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]] ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 %0:gpr(p0) = COPY $x10 @@ -116,7 +116,7 @@ body: | ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 - ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s64)) + ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64)) ; RV64IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_D_RV64_]], 1 ; RV64IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir index f7fdc33..e547972 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir @@ -15,7 +15,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[COPY1]] :: (load store monotonic (s8)) + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY1]], [[COPY]] :: (load store monotonic (s8)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -38,7 +38,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY]], [[COPY1]] :: (load store monotonic (s16)) + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY1]], [[COPY]] :: (load store monotonic (s16)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY]], [[COPY1]] :: (load store monotonic (s32)) + ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY1]], [[COPY]] :: (load store monotonic (s32)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_W]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -86,7 +86,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[SUB]] :: (load store monotonic (s8)) + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -113,7 +113,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY]], [[SUB]] :: (load store monotonic (s16)) + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[SUB]], [[COPY]] :: (load store monotonic (s16)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -140,7 +140,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[SUB]] :: (load store monotonic (s8)) + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir index 178586c..f34826c 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir @@ -15,7 +15,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[COPY1]] :: (load store monotonic (s8)) + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY1]], [[COPY]] :: (load store monotonic (s8)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -38,7 +38,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY]], [[COPY1]] :: (load store monotonic (s16)) + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY1]], [[COPY]] :: (load store monotonic (s16)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY]], [[COPY1]] :: (load store monotonic (s32)) + ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY1]], [[COPY]] :: (load store monotonic (s32)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_W]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -84,7 +84,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 - ; CHECK-NEXT: [[AMOADD_D:%[0-9]+]]:gpr = AMOADD_D [[COPY]], [[COPY1]] :: (load store monotonic (s64)) + ; CHECK-NEXT: [[AMOADD_D:%[0-9]+]]:gpr = AMOADD_D [[COPY1]], [[COPY]] :: (load store monotonic (s64)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_D]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -109,7 +109,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[SUB]] :: (load store monotonic (s8)) + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -136,7 +136,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY]], [[SUB]] :: (load store monotonic (s16)) + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[SUB]], [[COPY]] :: (load store monotonic (s16)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -163,7 +163,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY]], [[SUB]] :: (load store monotonic (s32)) + ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[SUB]], [[COPY]] :: (load store monotonic (s32)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_W]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 @@ -190,7 +190,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[SUB]] :: (load store monotonic (s8)) + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(p0) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index ead255b..f3529b1 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -443,7 +443,7 @@ ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0" -; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1" +; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p9" ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0" ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0" ; RV32ZABHA: .attribute 5, "rv32i2p1_zaamo1p0_zabha1p0" @@ -590,8 +590,8 @@ ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0" -; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1" -; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p1_zalrsc1p0" +; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p9" +; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p9_zalrsc1p0" ; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0" ; RV64ZABHA: .attribute 5, "rv64i2p1_zaamo1p0_zabha1p0" ; RV64ZVBC32E: .attribute 5, "rv64i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0" diff --git a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll index 380a4a0..d1f1c46 100644 --- a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll @@ -5,7 +5,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; CHECK-LABEL: atomicrmw_uinc_wrap_i8: ; CHECK: .cfi_startproc ; CHECK-NEXT: ! %bb.0: -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadStore | #StoreStore ; CHECK-NEXT: and %o0, -4, %o2 ; CHECK-NEXT: mov 3, %o3 ; CHECK-NEXT: andn %o3, %o0, %o0 @@ -36,7 +36,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; CHECK-NEXT: nop ; CHECK-NEXT: ! %bb.2: ! %atomicrmw.end ; CHECK-NEXT: srl %o4, %o0, %o0 -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadLoad | #LoadStore ; CHECK-NEXT: retl ; CHECK-NEXT: nop %result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst @@ -47,7 +47,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; CHECK-LABEL: atomicrmw_uinc_wrap_i16: ; CHECK: .cfi_startproc ; CHECK-NEXT: ! %bb.0: -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadStore | #StoreStore ; CHECK-NEXT: and %o0, -4, %o2 ; CHECK-NEXT: and %o0, 3, %o0 ; CHECK-NEXT: xor %o0, 2, %o0 @@ -79,7 +79,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; CHECK-NEXT: nop ; CHECK-NEXT: ! %bb.2: ! %atomicrmw.end ; CHECK-NEXT: srl %o5, %o0, %o0 -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadLoad | #LoadStore ; CHECK-NEXT: retl ; CHECK-NEXT: nop %result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst @@ -90,7 +90,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; CHECK-LABEL: atomicrmw_uinc_wrap_i32: ; CHECK: .cfi_startproc ; CHECK-NEXT: ! %bb.0: -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadStore | #StoreStore ; CHECK-NEXT: ld [%o0], %o2 ; CHECK-NEXT: .LBB2_1: ! %atomicrmw.start ; CHECK-NEXT: ! =>This Inner Loop Header: Depth=1 @@ -106,7 +106,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; CHECK-NEXT: bne %icc, .LBB2_1 ; CHECK-NEXT: nop ; CHECK-NEXT: ! %bb.2: ! %atomicrmw.end -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadLoad | #LoadStore ; CHECK-NEXT: retl ; CHECK-NEXT: mov %o2, %o0 %result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst @@ -160,7 +160,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; CHECK-LABEL: atomicrmw_udec_wrap_i8: ; CHECK: .cfi_startproc ; CHECK-NEXT: ! %bb.0: -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadStore | #StoreStore ; CHECK-NEXT: and %o0, -4, %o2 ; CHECK-NEXT: mov 3, %o3 ; CHECK-NEXT: andn %o3, %o0, %o0 @@ -193,7 +193,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; CHECK-NEXT: nop ; CHECK-NEXT: ! %bb.2: ! %atomicrmw.end ; CHECK-NEXT: srl %o5, %o0, %o0 -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadLoad | #LoadStore ; CHECK-NEXT: retl ; CHECK-NEXT: nop %result = atomicrmw udec_wrap ptr %ptr, i8 %val seq_cst @@ -204,7 +204,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; CHECK-LABEL: atomicrmw_udec_wrap_i16: ; CHECK: .cfi_startproc ; CHECK-NEXT: ! %bb.0: -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadStore | #StoreStore ; CHECK-NEXT: and %o0, -4, %o2 ; CHECK-NEXT: and %o0, 3, %o0 ; CHECK-NEXT: xor %o0, 2, %o0 @@ -238,7 +238,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; CHECK-NEXT: nop ; CHECK-NEXT: ! %bb.2: ! %atomicrmw.end ; CHECK-NEXT: srl %g2, %o0, %o0 -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadLoad | #LoadStore ; CHECK-NEXT: retl ; CHECK-NEXT: nop %result = atomicrmw udec_wrap ptr %ptr, i16 %val seq_cst @@ -249,7 +249,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; CHECK-LABEL: atomicrmw_udec_wrap_i32: ; CHECK: .cfi_startproc ; CHECK-NEXT: ! %bb.0: -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadStore | #StoreStore ; CHECK-NEXT: ld [%o0], %o2 ; CHECK-NEXT: .LBB6_1: ! %atomicrmw.start ; CHECK-NEXT: ! =>This Inner Loop Header: Depth=1 @@ -267,7 +267,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; CHECK-NEXT: bne %icc, .LBB6_1 ; CHECK-NEXT: nop ; CHECK-NEXT: ! %bb.2: ! %atomicrmw.end -; CHECK-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; CHECK-NEXT: membar #LoadLoad | #LoadStore ; CHECK-NEXT: retl ; CHECK-NEXT: mov %o2, %o0 %result = atomicrmw udec_wrap ptr %ptr, i32 %val seq_cst diff --git a/llvm/test/CodeGen/SPARC/atomics-ordering.ll b/llvm/test/CodeGen/SPARC/atomics-ordering.ll new file mode 100644 index 0000000..7c13ac2 --- /dev/null +++ b/llvm/test/CodeGen/SPARC/atomics-ordering.ll @@ -0,0 +1,446 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=sparc -verify-machineinstrs | FileCheck %s --check-prefixes=SPARC32 +; RUN: llc < %s -mtriple=sparc -mcpu=leon4 -verify-machineinstrs | FileCheck %s --check-prefixes=SPARC32-LEON4 +; RUN: llc < %s -mtriple=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s --check-prefixes=SPARC32-V9 +; RUN: llc < %s -mtriple=sparcv9 -verify-machineinstrs | FileCheck %s --check-prefixes=SPARC64 + +define i32 @load_acq(ptr %0) nounwind { +; SPARC32-LABEL: load_acq: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_load_4 +; SPARC32-NEXT: mov 2, %o1 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore %g0, %o0, %o0 +; +; SPARC32-LEON4-LABEL: load_acq: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: ld [%o0], %o0 +; +; SPARC32-V9-LABEL: load_acq: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: ld [%o0], %o0 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: nop +; +; SPARC64-LABEL: load_acq: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: ld [%o0], %o0 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: nop + %2 = load atomic i32, ptr %0 acquire, align 4 + ret i32 %2 +} + +define i32 @load_sc(ptr %0) nounwind { +; SPARC32-LABEL: load_sc: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_load_4 +; SPARC32-NEXT: mov 5, %o1 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore %g0, %o0, %o0 +; +; SPARC32-LEON4-LABEL: load_sc: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: ld [%o0], %o0 +; +; SPARC32-V9-LABEL: load_sc: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: ld [%o0], %o0 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: nop +; +; SPARC64-LABEL: load_sc: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: ld [%o0], %o0 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: nop + %2 = load atomic i32, ptr %0 seq_cst, align 4 + ret i32 %2 +} + +define void @store_rel(ptr %0, i32 %1) nounwind { +; SPARC32-LABEL: store_rel: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i1, %o1 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_store_4 +; SPARC32-NEXT: mov 3, %o2 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore +; +; SPARC32-LEON4-LABEL: store_rel: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: st %o1, [%o0] +; +; SPARC32-V9-LABEL: store_rel: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: st %o1, [%o0] +; +; SPARC64-LABEL: store_rel: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: st %o1, [%o0] + store atomic i32 %1, ptr %0 release, align 4 + ret void +} + +define void @store_sc(ptr %0, i32 %1) nounwind { +; SPARC32-LABEL: store_sc: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i1, %o1 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_store_4 +; SPARC32-NEXT: mov 5, %o2 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore +; +; SPARC32-LEON4-LABEL: store_sc: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: st %o1, [%o0] +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: ldstub [%sp+-1], %g0 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: nop +; +; SPARC32-V9-LABEL: store_sc: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: st %o1, [%o0] +; SPARC32-V9-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: nop +; +; SPARC64-LABEL: store_sc: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: st %o1, [%o0] +; SPARC64-NEXT: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: nop + store atomic i32 %1, ptr %0 seq_cst, align 4 + ret void +} + +define i32 @rmw_acq(ptr %0, i32 %1) nounwind { +; SPARC32-LABEL: rmw_acq: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i1, %o1 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_exchange_4 +; SPARC32-NEXT: mov 2, %o2 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore %g0, %o0, %o0 +; +; SPARC32-LEON4-LABEL: rmw_acq: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: swap [%o0], %o1 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o1, %o0 +; +; SPARC32-V9-LABEL: rmw_acq: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: swap [%o0], %o1 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o1, %o0 +; +; SPARC64-LABEL: rmw_acq: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: swap [%o0], %o1 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o1, %o0 + %3 = atomicrmw xchg ptr %0, i32 %1 acquire, align 4 + ret i32 %3 +} + +define i32 @rmw_rel(ptr %0, i32 %1) nounwind { +; SPARC32-LABEL: rmw_rel: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i1, %o1 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_exchange_4 +; SPARC32-NEXT: mov 3, %o2 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore %g0, %o0, %o0 +; +; SPARC32-LEON4-LABEL: rmw_rel: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: swap [%o0], %o1 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o1, %o0 +; +; SPARC32-V9-LABEL: rmw_rel: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: swap [%o0], %o1 +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o1, %o0 +; +; SPARC64-LABEL: rmw_rel: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: swap [%o0], %o1 +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o1, %o0 + %3 = atomicrmw xchg ptr %0, i32 %1 release, align 4 + ret i32 %3 +} + +define i32 @rmw_acq_rel(ptr %0, i32 %1) nounwind { +; SPARC32-LABEL: rmw_acq_rel: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i1, %o1 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_exchange_4 +; SPARC32-NEXT: mov 4, %o2 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore %g0, %o0, %o0 +; +; SPARC32-LEON4-LABEL: rmw_acq_rel: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: swap [%o0], %o1 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o1, %o0 +; +; SPARC32-V9-LABEL: rmw_acq_rel: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: swap [%o0], %o1 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o1, %o0 +; +; SPARC64-LABEL: rmw_acq_rel: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: swap [%o0], %o1 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o1, %o0 + %3 = atomicrmw xchg ptr %0, i32 %1 acq_rel, align 4 + ret i32 %3 +} + +define i32 @rmw_sc(ptr %0, i32 %1) nounwind { +; SPARC32-LABEL: rmw_sc: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i1, %o1 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: call __atomic_exchange_4 +; SPARC32-NEXT: mov 5, %o2 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore %g0, %o0, %o0 +; +; SPARC32-LEON4-LABEL: rmw_sc: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: swap [%o0], %o1 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o1, %o0 +; +; SPARC32-V9-LABEL: rmw_sc: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: swap [%o0], %o1 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o1, %o0 +; +; SPARC64-LABEL: rmw_sc: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: swap [%o0], %o1 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o1, %o0 + %3 = atomicrmw xchg ptr %0, i32 %1 seq_cst, align 4 + ret i32 %3 +} + +define i32 @cas_acq(ptr %0, i32 %1, i32 %2) nounwind { +; SPARC32-LABEL: cas_acq: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i2, %o2 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: st %i1, [%fp+-4] +; SPARC32-NEXT: add %fp, -4, %o1 +; SPARC32-NEXT: mov 2, %o3 +; SPARC32-NEXT: call __atomic_compare_exchange_4 +; SPARC32-NEXT: mov %o3, %o4 +; SPARC32-NEXT: ld [%fp+-4], %i0 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore +; +; SPARC32-LEON4-LABEL: cas_acq: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: casa [%o0] 10, %o1, %o2 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o2, %o0 +; +; SPARC32-V9-LABEL: cas_acq: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: cas [%o0], %o1, %o2 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o2, %o0 +; +; SPARC64-LABEL: cas_acq: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: cas [%o0], %o1, %o2 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o2, %o0 + %4 = cmpxchg ptr %0, i32 %1, i32 %2 acquire acquire, align 4 + %5 = extractvalue { i32, i1 } %4, 0 + ret i32 %5 +} + +define i32 @cas_rel(ptr %0, i32 %1, i32 %2) nounwind { +; SPARC32-LABEL: cas_rel: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i2, %o2 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: st %i1, [%fp+-4] +; SPARC32-NEXT: add %fp, -4, %o1 +; SPARC32-NEXT: mov 3, %o3 +; SPARC32-NEXT: call __atomic_compare_exchange_4 +; SPARC32-NEXT: mov %g0, %o4 +; SPARC32-NEXT: ld [%fp+-4], %i0 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore +; +; SPARC32-LEON4-LABEL: cas_rel: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: casa [%o0] 10, %o1, %o2 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o2, %o0 +; +; SPARC32-V9-LABEL: cas_rel: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: cas [%o0], %o1, %o2 +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o2, %o0 +; +; SPARC64-LABEL: cas_rel: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: cas [%o0], %o1, %o2 +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o2, %o0 + %4 = cmpxchg ptr %0, i32 %1, i32 %2 release monotonic, align 4 + %5 = extractvalue { i32, i1 } %4, 0 + ret i32 %5 +} + +define i32 @cas_acq_rel(ptr %0, i32 %1, i32 %2) nounwind { +; SPARC32-LABEL: cas_acq_rel: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i2, %o2 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: st %i1, [%fp+-4] +; SPARC32-NEXT: add %fp, -4, %o1 +; SPARC32-NEXT: mov 4, %o3 +; SPARC32-NEXT: call __atomic_compare_exchange_4 +; SPARC32-NEXT: mov 2, %o4 +; SPARC32-NEXT: ld [%fp+-4], %i0 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore +; +; SPARC32-LEON4-LABEL: cas_acq_rel: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: casa [%o0] 10, %o1, %o2 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o2, %o0 +; +; SPARC32-V9-LABEL: cas_acq_rel: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: cas [%o0], %o1, %o2 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o2, %o0 +; +; SPARC64-LABEL: cas_acq_rel: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: cas [%o0], %o1, %o2 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o2, %o0 + %4 = cmpxchg ptr %0, i32 %1, i32 %2 acq_rel acquire, align 4 + %5 = extractvalue { i32, i1 } %4, 0 + ret i32 %5 +} + +define i32 @cas_sc(ptr %0, i32 %1, i32 %2) nounwind { +; SPARC32-LABEL: cas_sc: +; SPARC32: ! %bb.0: +; SPARC32-NEXT: save %sp, -96, %sp +; SPARC32-NEXT: mov %i2, %o2 +; SPARC32-NEXT: mov %i0, %o0 +; SPARC32-NEXT: st %i1, [%fp+-4] +; SPARC32-NEXT: add %fp, -4, %o1 +; SPARC32-NEXT: mov 5, %o3 +; SPARC32-NEXT: call __atomic_compare_exchange_4 +; SPARC32-NEXT: mov %o3, %o4 +; SPARC32-NEXT: ld [%fp+-4], %i0 +; SPARC32-NEXT: ret +; SPARC32-NEXT: restore +; +; SPARC32-LEON4-LABEL: cas_sc: +; SPARC32-LEON4: ! %bb.0: +; SPARC32-LEON4-NEXT: stbar +; SPARC32-LEON4-NEXT: casa [%o0] 10, %o1, %o2 +; SPARC32-LEON4-NEXT: retl +; SPARC32-LEON4-NEXT: mov %o2, %o0 +; +; SPARC32-V9-LABEL: cas_sc: +; SPARC32-V9: ! %bb.0: +; SPARC32-V9-NEXT: membar #LoadStore | #StoreStore +; SPARC32-V9-NEXT: cas [%o0], %o1, %o2 +; SPARC32-V9-NEXT: membar #LoadLoad | #LoadStore +; SPARC32-V9-NEXT: retl +; SPARC32-V9-NEXT: mov %o2, %o0 +; +; SPARC64-LABEL: cas_sc: +; SPARC64: ! %bb.0: +; SPARC64-NEXT: membar #LoadStore | #StoreStore +; SPARC64-NEXT: cas [%o0], %o1, %o2 +; SPARC64-NEXT: membar #LoadLoad | #LoadStore +; SPARC64-NEXT: retl +; SPARC64-NEXT: mov %o2, %o0 + %4 = cmpxchg ptr %0, i32 %1, i32 %2 seq_cst seq_cst, align 4 + %5 = extractvalue { i32, i1 } %4, 0 + ret i32 %5 +} diff --git a/llvm/test/CodeGen/SPIRV/llc-pipeline.ll b/llvm/test/CodeGen/SPIRV/llc-pipeline.ll new file mode 100644 index 0000000..3fff2a8 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/llc-pipeline.ll @@ -0,0 +1,214 @@ +; UNSUPPORTED:expensive_checks +; RUN:llc -O0 -mtriple=spirv-- -disable-verify -debug-pass=Structure < %s 2>&1 \ +; RUN: | FileCheck -match-full-lines -strict-whitespace -check-prefix=SPIRV-O0 %s +; RUN:llc -O1 -mtriple=spirv-- -disable-verify -debug-pass=Structure < %s 2>&1 \ +; RUN: | FileCheck -match-full-lines -strict-whitespace -check-prefix=SPIRV-Opt %s +; RUN:llc -O2 -mtriple=spirv-- -disable-verify -debug-pass=Structure < %s 2>&1 \ +; RUN: | FileCheck -match-full-lines -strict-whitespace -check-prefix=SPIRV-Opt %s +; RUN:llc -O3 -mtriple=spirv-- -disable-verify -debug-pass=Structure < %s 2>&1 \ +; RUN: | FileCheck -match-full-lines -strict-whitespace -check-prefix=SPIRV-Opt %s +; +; REQUIRES:asserts + +; SPIRV-O0:Target Library Information +; SPIRV-O0-NEXT:Target Pass Configuration +; SPIRV-O0-NEXT:Machine Module Information +; SPIRV-O0-NEXT:Target Transform Information +; SPIRV-O0-NEXT:Create Garbage Collector Module Metadata +; SPIRV-O0-NEXT:Assumption Cache Tracker +; SPIRV-O0-NEXT:Profile summary info +; SPIRV-O0-NEXT:Machine Branch Probability Analysis +; SPIRV-O0-NEXT: ModulePass Manager +; SPIRV-O0-NEXT: Pre-ISel Intrinsic Lowering +; SPIRV-O0-NEXT: FunctionPass Manager +; SPIRV-O0-NEXT: Expand large div/rem +; SPIRV-O0-NEXT: Expand fp +; SPIRV-O0-NEXT: Lower Garbage Collection Instructions +; SPIRV-O0-NEXT: Shadow Stack GC Lowering +; SPIRV-O0-NEXT: Remove unreachable blocks from the CFG +; SPIRV-O0-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining) +; SPIRV-O0-NEXT: Scalarize Masked Memory Intrinsics +; SPIRV-O0-NEXT: Expand reduction intrinsics +; SPIRV-O0-NEXT: SPIR-V Regularizer +; SPIRV-O0-NEXT: SPIRV prepare functions +; SPIRV-O0-NEXT: FunctionPass Manager +; SPIRV-O0-NEXT: Lower invoke and unwind, for unwindless code generators +; SPIRV-O0-NEXT: Remove unreachable blocks from the CFG +; SPIRV-O0-NEXT: SPIRV strip convergent intrinsics +; SPIRV-O0-NEXT: SPIRV Legalize Implicit Binding +; SPIRV-O0-NEXT: SPIRV CBuffer Access +; SPIRV-O0-NEXT: SPIRV emit intrinsics +; SPIRV-O0-NEXT: FunctionPass Manager +; SPIRV-O0-NEXT: SPIRV legalize bitcast pass +; SPIRV-O0-NEXT: Prepare callbr +; SPIRV-O0-NEXT: Safe Stack instrumentation pass +; SPIRV-O0-NEXT: Insert stack protectors +; SPIRV-O0-NEXT: Analysis containing CSE Info +; SPIRV-O0-NEXT: IRTranslator +; SPIRV-O0-NEXT: Analysis for ComputingKnownBits +; SPIRV-O0-NEXT: MachineDominator Tree Construction +; SPIRV-O0-NEXT: SPIRVPreLegalizerCombiner +; SPIRV-O0-NEXT: SPIRV pre legalizer +; SPIRV-O0-NEXT: Analysis containing CSE Info +; SPIRV-O0-NEXT: Legalizer +; SPIRV-O0-NEXT: SPIRV post legalizer +; SPIRV-O0-NEXT: Analysis for ComputingKnownBits +; SPIRV-O0-NEXT: Dominator Tree Construction +; SPIRV-O0-NEXT: Natural Loop Information +; SPIRV-O0-NEXT: Lazy Branch Probability Analysis +; SPIRV-O0-NEXT: Lazy Block Frequency Analysis +; SPIRV-O0-NEXT: InstructionSelect +; SPIRV-O0-NEXT: ResetMachineFunction +; SPIRV-O0-NEXT: Finalize ISel and expand pseudo-instructions +; SPIRV-O0-NEXT: Local Stack Slot Allocation +; SPIRV-O0-NEXT: Remove Redundant DEBUG_VALUE analysis +; SPIRV-O0-NEXT: Fixup Statepoint Caller Saved +; SPIRV-O0-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-O0-NEXT: Machine Optimization Remark Emitter +; SPIRV-O0-NEXT: Prologue/Epilogue Insertion & Frame Finalization +; SPIRV-O0-NEXT: Post-RA pseudo instruction expansion pass +; SPIRV-O0-NEXT: Analyze Machine Code For Garbage Collection +; SPIRV-O0-NEXT: Insert fentry calls +; SPIRV-O0-NEXT: Insert XRay ops +; SPIRV-O0-NEXT: Machine Sanitizer Binary Metadata +; SPIRV-O0-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-O0-NEXT: Machine Optimization Remark Emitter +; SPIRV-O0-NEXT: Stack Frame Layout Analysis +; SPIRV-O0-NEXT: SPIRV module analysis +; SPIRV-O0-NEXT: FunctionPass Manager +; SPIRV-O0-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-O0-NEXT: Machine Optimization Remark Emitter +; SPIRV-O0-NEXT: SPIRV Assembly Printer +; SPIRV-O0-NEXT: Free MachineFunction + +; SPIRV-Opt:Target Library Information +; SPIRV-Opt-NEXT:Target Pass Configuration +; SPIRV-Opt-NEXT:Machine Module Information +; SPIRV-Opt-NEXT:Target Transform Information +; SPIRV-Opt-NEXT:Assumption Cache Tracker +; SPIRV-Opt-NEXT:Type-Based Alias Analysis +; SPIRV-Opt-NEXT:Scoped NoAlias Alias Analysis +; SPIRV-Opt-NEXT:Profile summary info +; SPIRV-Opt-NEXT:Create Garbage Collector Module Metadata +; SPIRV-Opt-NEXT:Machine Branch Probability Analysis +; SPIRV-Opt-NEXT: ModulePass Manager +; SPIRV-Opt-NEXT: Pre-ISel Intrinsic Lowering +; SPIRV-Opt-NEXT: FunctionPass Manager +; SPIRV-Opt-NEXT: Expand large div/rem +; SPIRV-Opt-NEXT: Expand fp +; SPIRV-Opt-NEXT: Dominator Tree Construction +; SPIRV-Opt-NEXT: Basic Alias Analysis (stateless AA impl) +; SPIRV-Opt-NEXT: Natural Loop Information +; SPIRV-Opt-NEXT: Canonicalize natural loops +; SPIRV-Opt-NEXT: Scalar Evolution Analysis +; SPIRV-Opt-NEXT: Loop Pass Manager +; SPIRV-Opt-NEXT: Canonicalize Freeze Instructions in Loops +; SPIRV-Opt-NEXT: Induction Variable Users +; SPIRV-Opt-NEXT: Loop Strength Reduction +; SPIRV-Opt-NEXT: Basic Alias Analysis (stateless AA impl) +; SPIRV-Opt-NEXT: Function Alias Analysis Results +; SPIRV-Opt-NEXT: Merge contiguous icmps into a memcmp +; SPIRV-Opt-NEXT: Natural Loop Information +; SPIRV-Opt-NEXT: Lazy Branch Probability Analysis +; SPIRV-Opt-NEXT: Lazy Block Frequency Analysis +; SPIRV-Opt-NEXT: Expand memcmp() to load/stores +; SPIRV-Opt-NEXT: Lower Garbage Collection Instructions +; SPIRV-Opt-NEXT: Shadow Stack GC Lowering +; SPIRV-Opt-NEXT: Remove unreachable blocks from the CFG +; SPIRV-Opt-NEXT: Natural Loop Information +; SPIRV-Opt-NEXT: Post-Dominator Tree Construction +; SPIRV-Opt-NEXT: Branch Probability Analysis +; SPIRV-Opt-NEXT: Block Frequency Analysis +; SPIRV-Opt-NEXT: Constant Hoisting +; SPIRV-Opt-NEXT: Replace intrinsics with calls to vector library +; SPIRV-Opt-NEXT: Lazy Branch Probability Analysis +; SPIRV-Opt-NEXT: Lazy Block Frequency Analysis +; SPIRV-Opt-NEXT: Optimization Remark Emitter +; SPIRV-Opt-NEXT: Partially inline calls to library functions +; SPIRV-Opt-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining) +; SPIRV-Opt-NEXT: Scalarize Masked Memory Intrinsics +; SPIRV-Opt-NEXT: Expand reduction intrinsics +; SPIRV-Opt-NEXT: SPIR-V Regularizer +; SPIRV-Opt-NEXT: SPIRV prepare functions +; SPIRV-Opt-NEXT: FunctionPass Manager +; SPIRV-Opt-NEXT: Dominator Tree Construction +; SPIRV-Opt-NEXT: Natural Loop Information +; SPIRV-Opt-NEXT: CodeGen Prepare +; SPIRV-Opt-NEXT: Lower invoke and unwind, for unwindless code generators +; SPIRV-Opt-NEXT: Remove unreachable blocks from the CFG +; SPIRV-Opt-NEXT: SPIRV strip convergent intrinsics +; SPIRV-Opt-NEXT: SPIRV Legalize Implicit Binding +; SPIRV-Opt-NEXT: SPIRV CBuffer Access +; SPIRV-Opt-NEXT: SPIRV emit intrinsics +; SPIRV-Opt-NEXT: FunctionPass Manager +; SPIRV-Opt-NEXT: SPIRV legalize bitcast pass +; SPIRV-Opt-NEXT: Dominator Tree Construction +; SPIRV-Opt-NEXT: Basic Alias Analysis (stateless AA impl) +; SPIRV-Opt-NEXT: Function Alias Analysis Results +; SPIRV-Opt-NEXT: ObjC ARC contraction +; SPIRV-Opt-NEXT: Prepare callbr +; SPIRV-Opt-NEXT: Safe Stack instrumentation pass +; SPIRV-Opt-NEXT: Insert stack protectors +; SPIRV-Opt-NEXT: Analysis containing CSE Info +; SPIRV-Opt-NEXT: Natural Loop Information +; SPIRV-Opt-NEXT: Post-Dominator Tree Construction +; SPIRV-Opt-NEXT: Branch Probability Analysis +; SPIRV-Opt-NEXT: Basic Alias Analysis (stateless AA impl) +; SPIRV-Opt-NEXT: Function Alias Analysis Results +; SPIRV-Opt-NEXT: IRTranslator +; SPIRV-Opt-NEXT: Analysis for ComputingKnownBits +; SPIRV-Opt-NEXT: MachineDominator Tree Construction +; SPIRV-Opt-NEXT: SPIRVPreLegalizerCombiner +; SPIRV-Opt-NEXT: SPIRV pre legalizer +; SPIRV-Opt-NEXT: Analysis containing CSE Info +; SPIRV-Opt-NEXT: Legalizer +; SPIRV-Opt-NEXT: SPIRV post legalizer +; SPIRV-Opt-NEXT: Analysis for ComputingKnownBits +; SPIRV-Opt-NEXT: Lazy Branch Probability Analysis +; SPIRV-Opt-NEXT: Lazy Block Frequency Analysis +; SPIRV-Opt-NEXT: InstructionSelect +; SPIRV-Opt-NEXT: ResetMachineFunction +; SPIRV-Opt-NEXT: Finalize ISel and expand pseudo-instructions +; SPIRV-Opt-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-Opt-NEXT: Early Tail Duplication +; SPIRV-Opt-NEXT: Optimize machine instruction PHIs +; SPIRV-Opt-NEXT: Slot index numbering +; SPIRV-Opt-NEXT: Merge disjoint stack slots +; SPIRV-Opt-NEXT: Local Stack Slot Allocation +; SPIRV-Opt-NEXT: Remove dead machine instructions +; SPIRV-Opt-NEXT: MachineDominator Tree Construction +; SPIRV-Opt-NEXT: Machine Natural Loop Construction +; SPIRV-Opt-NEXT: Machine Block Frequency Analysis +; SPIRV-Opt-NEXT: Early Machine Loop Invariant Code Motion +; SPIRV-Opt-NEXT: MachineDominator Tree Construction +; SPIRV-Opt-NEXT: Machine Block Frequency Analysis +; SPIRV-Opt-NEXT: Machine Common Subexpression Elimination +; SPIRV-Opt-NEXT: MachinePostDominator Tree Construction +; SPIRV-Opt-NEXT: Machine Cycle Info Analysis +; SPIRV-Opt-NEXT: Machine code sinking +; SPIRV-Opt-NEXT: Peephole Optimizations +; SPIRV-Opt-NEXT: Remove dead machine instructions +; SPIRV-Opt-NEXT: Remove Redundant DEBUG_VALUE analysis +; SPIRV-Opt-NEXT: Fixup Statepoint Caller Saved +; SPIRV-Opt-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-Opt-NEXT: Machine Optimization Remark Emitter +; SPIRV-Opt-NEXT: Prologue/Epilogue Insertion & Frame Finalization +; SPIRV-Opt-NEXT: Tail Duplication +; SPIRV-Opt-NEXT: Post-RA pseudo instruction expansion pass +; SPIRV-Opt-NEXT: Analyze Machine Code For Garbage Collection +; SPIRV-Opt-NEXT: Insert fentry calls +; SPIRV-Opt-NEXT: Insert XRay ops +; SPIRV-Opt-NEXT: Machine Sanitizer Binary Metadata +; SPIRV-Opt-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-Opt-NEXT: Machine Optimization Remark Emitter +; SPIRV-Opt-NEXT: Stack Frame Layout Analysis +; SPIRV-Opt-NEXT: SPIRV module analysis +; SPIRV-Opt-NEXT: FunctionPass Manager +; SPIRV-Opt-NEXT: Lazy Machine Block Frequency Analysis +; SPIRV-Opt-NEXT: Machine Optimization Remark Emitter +; SPIRV-Opt-NEXT: SPIRV Assembly Printer +; SPIRV-Opt-NEXT: Free MachineFunction + +define void @empty() { + ret void +} diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir index 021cb4c..8abe5c5 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir @@ -8,7 +8,7 @@ --- | %struct.DCT_InstanceTypeDef = type { ptr, i32, i32 } - + ; Function Attrs: nofree nounwind define hidden arm_aapcs_vfpcc void @test(ptr nocapture readonly %S, ptr %pIn, ptr nocapture %pOut) { entry: @@ -41,7 +41,7 @@ %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %8, i32 1) %14 = icmp ne i32 %13, 0 br i1 %14, label %do.body, label %do.end - + do.end: ; preds = %do.body %15 = extractelement <4 x float> %11, i32 0 %16 = extractelement <4 x float> %11, i32 1 @@ -56,7 +56,7 @@ %sub4 = add i32 %1, -4 %cmp5201 = icmp ugt i32 %sub4, 1 br i1 %cmp5201, label %for.body.lr.ph, label %for.cond54.preheader - + for.body.lr.ph: ; preds = %do.end %scevgep = getelementptr float, ptr %pIn, i32 4 %20 = add i32 %0, 4 @@ -161,7 +161,7 @@ %63 = call i32 @llvm.loop.decrement.reg.i32(i32 %53, i32 1) %64 = icmp ne i32 %63, 0 br i1 %64, label %do.body24, label %do.end33 - + do.end33: ; preds = %do.body24 %65 = bitcast ptr %lsr.iv27 to ptr %66 = bitcast ptr %lsr.iv20 to ptr @@ -254,7 +254,7 @@ %inc = add nuw i32 %k.1200, 1 %exitcond.not = icmp eq i32 %inc, %1 br i1 %exitcond.not, label %for.end72, label %for.body56 - + for.end72: ; preds = %do.end66, %for.cond54.preheader ret void } @@ -428,28 +428,28 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14 /* CC::al */, $noreg - + bb.2.do.end: successors: %bb.3(0x40000000), %bb.7(0x40000000) liveins: $q0, $r2, $r3, $r4, $r5, $r11 - - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r0, dead $cpsr = tSUBi3 renamable $r3, 4, 14 /* CC::al */, $noreg tSTRspi killed renamable $r3, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.8) - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm tSTRspi renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm renamable $s2 = VLDRS renamable $r11, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.2) tCMPi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VMULS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VMULS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm VSTRS killed renamable $s0, renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pOut) t2Bcc %bb.7, 3 /* CC::lo */, killed $cpsr - + bb.3.for.body.lr.ph: successors: %bb.4(0x80000000) liveins: $r0, $r2, $r4, $r5, $r11 - + renamable $r6 = t2ADDri renamable $r5, 16, 14 /* CC::al */, $noreg, $noreg renamable $r1, dead $cpsr = tSUBi3 renamable $r4, 4, 14 /* CC::al */, $noreg tSTRspi killed renamable $r6, $sp, 4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.5) @@ -523,26 +523,26 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr tB %bb.6, 14 /* CC::al */, $noreg - + bb.6.do.end33: successors: %bb.4(0x7c000000), %bb.7(0x04000000) liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r6, $r8, $r9, $r10, $r12 - - renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s12, renamable $s13, 14 /* CC::al */, $noreg - renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s8, renamable $s9, 14 /* CC::al */, $noreg - renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, renamable $s14, 14 /* CC::al */, $noreg - renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, renamable $s10, 14 /* CC::al */, $noreg - renamable $s12 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, killed renamable $s15, 14 /* CC::al */, $noreg, implicit $q3 - renamable $s8 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, killed renamable $s11, 14 /* CC::al */, $noreg, implicit $q2 - renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s4, renamable $s5, 14 /* CC::al */, $noreg - renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + + renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s12, renamable $s13, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s8, renamable $s9, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, renamable $s14, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, renamable $s10, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s12 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, killed renamable $s15, 14 /* CC::al */, $noreg, implicit $q3, implicit $fpscr_rm + renamable $s8 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, killed renamable $s11, 14 /* CC::al */, $noreg, implicit $q2, implicit $fpscr_rm + renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s4, renamable $s5, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r7 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, renamable $s6, 14 /* CC::al */, $noreg - renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, renamable $s2, 14 /* CC::al */, $noreg + renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, renamable $s6, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r3 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg renamable $r7 = t2ADDrs renamable $r2, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, killed renamable $s7, 14 /* CC::al */, $noreg, implicit $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, killed renamable $s7, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm VSTRS killed renamable $s12, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx37) VSTRS killed renamable $s8, killed renamable $r7, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx42) renamable $r3 = t2ADDrs renamable $r2, killed renamable $r8, 18, 14 /* CC::al */, $noreg, $noreg @@ -597,7 +597,7 @@ body: | bb.13: successors: %bb.10(0x80000000) liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 - + bb.10.do.body59 (align 4): successors: %bb.10(0x7c000000), %bb.11(0x04000000) liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 @@ -611,20 +611,20 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr tB %bb.11, 14 /* CC::al */, $noreg - + bb.11.do.end66: successors: %bb.12(0x04000000), %bb.9(0x7c000000) liveins: $q0, $r0, $r2, $r3, $r4, $r5, $r11, $r12 - - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r1 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm tCMPhir renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr VSTRS killed renamable $s0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx70) tBcc %bb.9, 1 /* CC::ne */, killed $cpsr - + bb.12.for.end72: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir index 31e88ea..85b826a 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir @@ -185,15 +185,15 @@ body: | successors: %bb.5(0x80000000) liveins: $q0, $r0, $r1, $r2, $r4 - renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg + renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg, implicit $fpscr_rm $lr = tMOVr $r4, 14, $noreg $r3 = tMOVr $r1, 14, $noreg - renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg - renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0 + renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0, implicit $fpscr_rm $s2 = VMOVSR $r1, 14, $noreg renamable $s2 = VUITOS killed renamable $s2, 14, $noreg $lr = t2DoLoopStart killed $r4 - renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg + renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg, implicit $fpscr_rm renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 bb.5: @@ -215,13 +215,13 @@ body: | bb.6: liveins: $q0, $r1, $r2 - renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg + renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg, implicit $fpscr_rm renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14, $noreg - renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg - renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0 + renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0, implicit $fpscr_rm $s2 = VMOVSR killed $r0, 14, $noreg renamable $s2 = VUITOS killed renamable $s2, 14, $noreg - renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg + renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg, implicit $fpscr_rm VSTRS killed renamable $s0, killed renamable $r2, 0, 14, $noreg tPOP_RET 14, $noreg, def $r4, def $pc diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir index f5da7ac..780831c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir @@ -232,9 +232,9 @@ body: | bb.3.middle.block: liveins: $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg - renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 @@ -376,9 +376,9 @@ body: | bb.3.middle.block: liveins: $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg - renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir index c331612..5dcd0a1 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir @@ -240,10 +240,10 @@ body: | $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm $lr = t2DoLoopStart killed $r4 renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 @@ -267,10 +267,10 @@ body: | liveins: $q0, $r1, $r2 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult) frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc diff --git a/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir b/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir index 5221205..d9d2f25 100644 --- a/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir +++ b/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir @@ -96,7 +96,7 @@ body: | ; CHECK-NEXT: bb.6.for.body: ; CHECK-NEXT: successors: %bb.7(0x80000000), %bb.8(0x00000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], %30, 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], %30, 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[COPY7]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg @@ -119,13 +119,13 @@ body: | ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VLDRS5]], %bb.6, %47, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI %40, %bb.6, %55, %bb.7 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %45, %bb.7 - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI4]], [[PHI5]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI4]], [[PHI5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri4:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[t2ADDri5:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]] ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]] ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]] @@ -140,7 +140,7 @@ body: | ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS5]], %bb.6, [[VLDRS6]], %bb.7 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI %40, %bb.6, %55, %bb.7 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI7]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) @@ -148,8 +148,8 @@ body: | ; CHECK-NEXT: [[PHI11:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS3]], %bb.5, [[PHI8]], %bb.8 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:spr = PHI %30, %bb.5, [[PHI9]], %bb.8 - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI12]], [[PHI13]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI11]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI12]], [[PHI13]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI11]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -194,8 +194,8 @@ body: | %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) INLINEASM &nop, 0 /* attdialect */, 196618 /* regdef:SPR */, def %25, 2147483657 /* reguse tiedto:$0 */, %19(tied-def 3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %25, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %25, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/Thumb2/scavenge-lr.mir b/llvm/test/CodeGen/Thumb2/scavenge-lr.mir index 5513bed..bfe55a5 100644 --- a/llvm/test/CodeGen/Thumb2/scavenge-lr.mir +++ b/llvm/test/CodeGen/Thumb2/scavenge-lr.mir @@ -147,10 +147,10 @@ body: | $q5 = VLD1q64 $r3, 16, 14 /* CC::al */, $noreg :: (load (s128) from %ir.zzz..sroa_cast241, align 32) $q1 = VMLAfq killed $q1, $q5, killed $q8, 14 /* CC::al */, $noreg $s8 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) - $s3 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q0 - $s2 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 - $s1 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 - $s0 = VDIVS $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q0, implicit-def $q0 + $s3 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q0, implicit $fpscr_rm + $s2 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0, implicit $fpscr_rm + $s1 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0, implicit $fpscr_rm + $s0 = VDIVS $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q0, implicit-def $q0, implicit $fpscr_rm $r7 = t2SUBri $r0, 64, 14 /* CC::al */, $noreg, $noreg $q8 = VLD1q64 $r7, 16, 14 /* CC::al */, $noreg :: (load (s128) from %ir.yyy..sroa_cast244, align 32) VSTMQIA $q8, %stack.1, 14 /* CC::al */, $noreg :: (store (s128) into %stack.1) @@ -185,10 +185,10 @@ body: | $r3 = VST1q32wb_fixed killed $r3, 16, killed $q10, 14 /* CC::al */, $noreg :: (store (s128) into %ir.zzz..sroa_cast241, align 32) $q10 = VLD1q64 $r3, 16, 14 /* CC::al */, $noreg :: (load (s128) from %ir.zzz..sroa_cast241 + 16, basealign 32) $q1 = VMLAfq killed $q1, $q10, killed $q8, 14 /* CC::al */, $noreg - $s23 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q5 - $s22 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5 - $s21 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5 - $s20 = VDIVS killed $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q5, implicit-def $q5 + $s23 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q5, implicit $fpscr_rm + $s22 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5, implicit $fpscr_rm + $s21 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5, implicit $fpscr_rm + $s20 = VDIVS killed $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q5, implicit-def $q5, implicit $fpscr_rm VST1q64 killed $r5, 16, $q5, 14 /* CC::al */, $noreg :: (store (s128) into %ir.xxx..sroa_cast248 + 16, basealign 32) VST1q64 killed $r6, 16, $q5, 14 /* CC::al */, $noreg :: (store (s128) into %ir.vvv..sroa_cast230 + 16, basealign 32) $q8 = VLDMQIA %stack.0, 14 /* CC::al */, $noreg :: (load (s128) from %stack.0) diff --git a/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir b/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir index ba10045..20f044a 100644 --- a/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir +++ b/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir @@ -83,7 +83,7 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprnopc = COPY [[t2ADDri1]] @@ -98,7 +98,7 @@ body: | ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[COPY6]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2SUBri3]] ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2ADDri3]] @@ -115,7 +115,7 @@ body: | ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %43, %bb.7 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, %52, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) @@ -124,7 +124,7 @@ body: | ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]] ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]] ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]] - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} @@ -134,14 +134,14 @@ body: | ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, [[VMULS2]], %bb.7 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[PHI7]], %bb.8 - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -185,8 +185,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir b/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir index 854c5b8..177c94e 100644 --- a/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir +++ b/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir @@ -84,7 +84,7 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprlr = COPY [[t2DoLoopStart]] ; CHECK-NEXT: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[COPY5]], 1 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2LoopDec]] @@ -110,8 +110,8 @@ body: | ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr = COPY [[t2ADDri2]] ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri3]] - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI4]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI4]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2LoopDec1]] ; CHECK-NEXT: t2LoopEnd [[t2LoopDec1]], %bb.6, implicit-def $cpsr ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg @@ -121,7 +121,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS]], %bb.6 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[VMULS1]], %bb.6 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI5]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -166,8 +166,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %42:gprlr = COPY %4 %23:gprlr = t2LoopDec %42:gprlr, 1 %7:gpr = COPY %23 diff --git a/llvm/test/CodeGen/Thumb2/swp-fixedii.mir b/llvm/test/CodeGen/Thumb2/swp-fixedii.mir index dd02703..7939717 100644 --- a/llvm/test/CodeGen/Thumb2/swp-fixedii.mir +++ b/llvm/test/CodeGen/Thumb2/swp-fixedii.mir @@ -83,7 +83,7 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprnopc = COPY [[t2ADDri1]] @@ -98,7 +98,7 @@ body: | ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[COPY6]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2SUBri3]] ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2ADDri3]] @@ -115,7 +115,7 @@ body: | ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %43, %bb.7 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, %52, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) @@ -124,7 +124,7 @@ body: | ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]] ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]] ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]] - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr ; CHECK-NEXT: t2B %bb.8, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} @@ -134,14 +134,14 @@ body: | ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, [[VMULS2]], %bb.7 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[PHI7]], %bb.8 - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -185,8 +185,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/Thumb2/swp-regpressure.mir b/llvm/test/CodeGen/Thumb2/swp-regpressure.mir index 2bcb0c9..955b53df 100644 --- a/llvm/test/CodeGen/Thumb2/swp-regpressure.mir +++ b/llvm/test/CodeGen/Thumb2/swp-regpressure.mir @@ -148,8 +148,8 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2ADDri1]] @@ -236,8 +236,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 @@ -314,24 +314,24 @@ body: | ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %66:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %67:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %68:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %69:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %70:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %71:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %72:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %73:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %74:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %75:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %76:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %77:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %78:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %79:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %80:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %81:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %82:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %83:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY7:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY8:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY9:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY10:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY11:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY12:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY13:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY14:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY15:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY16:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY17:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY18:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY19:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY20:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY21:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY22:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY23:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY24:%[0-9]+]]:rgpr = COPY [[COPY4]] ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} @@ -342,82 +342,82 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2ADDri1]] - ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2ADDri]] + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[COPY25:%[0-9]+]]:gpr = COPY [[t2ADDri1]] + ; CHECK-NEXT: [[COPY26:%[0-9]+]]:gpr = COPY [[t2ADDri]] ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2SUBri3]] - ; CHECK-NEXT: [[COPY10:%[0-9]+]]:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %94:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %95:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %96:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %97:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %98:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %99:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %100:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %101:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %102:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %103:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %104:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %105:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %106:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %107:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %108:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %109:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %110:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %111:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: [[COPY27:%[0-9]+]]:gpr = COPY [[t2SUBri3]] + ; CHECK-NEXT: [[COPY28:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY29:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY30:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY31:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY32:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY33:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY34:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY35:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY36:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY37:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY38:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY39:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY40:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY41:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY42:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY43:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY44:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY45:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY46:%[0-9]+]]:rgpr = COPY [[COPY6]] ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7.for.body: ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.7(0x7c000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, %116, %bb.7 - ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.6, %117, %bb.7 - ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY9]], %bb.6, %140, %bb.7 + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY26]], %bb.6, %116, %bb.7 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY25]], %bb.6, %117, %bb.7 + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY27]], %bb.6, %140, %bb.7 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %137, %bb.7 - ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY10]], %bb.6, %139, %bb.7 + ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY28]], %bb.6, %139, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %118, %bb.7 ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri2]] - ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri3]] - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: dead %119:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %120:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %121:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %122:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %123:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %124:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %125:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %126:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %127:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %128:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %129:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %130:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %131:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %132:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %133:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %134:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %135:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %136:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY47:%[0-9]+]]:gpr = COPY [[t2ADDri2]] + ; CHECK-NEXT: [[COPY48:%[0-9]+]]:gpr = COPY [[t2ADDri3]] + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: dead [[COPY49:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY50:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY51:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY52:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY53:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY54:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY55:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY56:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY57:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY58:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY59:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY60:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY61:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY62:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY63:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY64:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY65:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY66:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK-NEXT: [[COPY13:%[0-9]+]]:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: [[COPY14:%[0-9]+]]:gpr = COPY [[t2SUBri4]] + ; CHECK-NEXT: [[COPY67:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: [[COPY68:%[0-9]+]]:gpr = COPY [[t2SUBri4]] ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr ; CHECK-NEXT: t2B %bb.8, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: ; CHECK-NEXT: successors: %bb.9(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, [[COPY11]], %bb.7 - ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.6, [[COPY12]], %bb.7 + ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY26]], %bb.6, [[COPY47]], %bb.7 + ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY25]], %bb.6, [[COPY48]], %bb.7 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI9]], [[PHI8]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI9]], [[PHI8]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) @@ -427,8 +427,8 @@ body: | ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI10]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI11]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS7]], [[VLDRS6]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI12]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS7]], [[VLDRS6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI12]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -491,8 +491,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll index 172ff53..e562c4a 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll @@ -132,4 +132,17 @@ define i32 @all_true_2_4_i32(<4 x i32> %v) { ret i32 %conv3 } +; Regression test for the intrinsic pattern matcher with nullary intrinsics +define i64 @other_intrinsic() #0 { +; CHECK-LABEL: other_intrinsic: +; CHECK: .functype other_intrinsic () -> (i64) +; CHECK-NEXT: # %bb.0: # %entry +; CHECK-NEXT: global.get $push0=, __tls_align +; CHECK-NEXT: return $pop0 +entry: + %0 = call i64 @llvm.wasm.tls.align.i64() + ret i64 %0 +} + +attributes #0 = { "target-features"="+atomics" } diff --git a/llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll b/llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll new file mode 100644 index 0000000..c302d41 --- /dev/null +++ b/llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll @@ -0,0 +1,11 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-linux-gnu -fast-isel -fast-isel-abort=1 < %s -o - | FileCheck %s + +define i64 @ptrtoaddr(ptr %p) { +; CHECK-LABEL: ptrtoaddr: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq + %addr = ptrtoaddr ptr %p to i64 + ret i64 %addr +} diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s b/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s index a21f762..73653d0 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s @@ -1,64 +1,71 @@ -// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefixes=GFX1250,GFX1250-ASM %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250,GFX1250-DIS %s s_mov_b64 s[2:3], 0x10abcdef12345678 -// GFX1250: s_mov_b64 s[2:3], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_mov_b64 s[2:3], 0x10abcdef12345678 ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_add_nc_u64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5] -// GFX1250: s_mul_u64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5] -// GFX1250: s_and_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_or_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5] -// GFX1250: s_xor_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678 -// GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), lit64(0x10abcdef12345678) ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678 ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_andn2_b64 s[2:3], 0x10abcdef12345678, s[4:5] -// GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_orn2_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_nand_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_nor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_xnor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_lshl_b64 s[2:3], 0x10abcdef12345678, s4 -// GFX1250: s_lshl_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_lshl_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_lshr_b64 s[2:3], 0x10abcdef12345678, s4 -// GFX1250: s_lshr_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_lshr_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_ashr_i64 s[2:3], 0x10abcdef12345678, s4 -// GFX1250: s_ashr_i64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_ashr_i64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_bfe_u64 s[2:3], 0x10abcdef12345678, 5 -// GFX1250: s_bfe_u64 s[2:3], lit64(0x10abcdef12345678), 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_bfe_u64 s[2:3], 0x10abcdef12345678, 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_bfe_i64 s[2:3], 0x80abcdef12345678, 5 -// GFX1250: s_bfe_i64 s[2:3], lit64(0x80abcdef12345678), 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80] +// GFX1250: s_bfe_i64 s[2:3], 0x80abcdef12345678, 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80] s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678 -// GFX1250: s_cselect_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] s_mov_b64 s[2:3], 0xffffffff01234567 -// GFX1250: s_mov_b64 s[2:3], lit64(0xffffffff01234567) ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff] +// GFX1250: s_mov_b64 s[2:3], 0xffffffff01234567 ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff] +// TODO: disasm s_mov_b64 s[2:3], lit64(0x777) -// GFX1250: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00] +// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xfe,0x01,0x82,0xbe,0x77,0x07,0x00,0x00,0x00,0x00,0x00,0x00] +// GFX1250-DIS: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00] + +s_mov_b64 s[2:3], 0x777 +// GFX1250: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s index 5cf484f..cc351af 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s @@ -1,61 +1,63 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR --implicit-check-not=error: --strict-whitespace %s s_add_pc_i64 s[2:3] // GFX1250: s_add_pc_i64 s[2:3] ; encoding: [0x02,0x4b,0x80,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_add_pc_i64 4 // GFX1250: s_add_pc_i64 4 ; encoding: [0x84,0x4b,0x80,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_add_pc_i64 100 // GFX1250: s_add_pc_i64 0x64 ; encoding: [0xff,0x4b,0x80,0xbe,0x64,0x00,0x00,0x00] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_add_pc_i64 0x12345678abcd0 -// GFX1250: s_add_pc_i64 lit64(0x12345678abcd0) ; encoding: [0xfe,0x4b,0x80,0xbe,0xd0,0xbc,0x8a,0x67,0x45,0x23,0x01,0x00] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX1250: s_add_pc_i64 0x12345678abcd0 ; encoding: [0xfe,0x4b,0x80,0xbe,0xd0,0xbc,0x8a,0x67,0x45,0x23,0x01,0x00] +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_get_pc_i64 s[2:3] // GFX1250: s_get_pc_i64 s[2:3] ; encoding: [0x00,0x47,0x82,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_getpc_b64 s[2:3] // GFX1250: s_get_pc_i64 s[2:3] ; encoding: [0x00,0x47,0x82,0xbe] s_set_pc_i64 s[2:3] // GFX1250: s_set_pc_i64 s[2:3] ; encoding: [0x02,0x48,0x80,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_setpc_b64 s[2:3] // GFX1250: s_set_pc_i64 s[2:3] ; encoding: [0x02,0x48,0x80,0xbe] s_swap_pc_i64 s[2:3], 10 // GFX1250: s_swap_pc_i64 s[2:3], 10 ; encoding: [0x8a,0x49,0x82,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_swappc_b64 s[2:3], 10 // GFX1250: s_swap_pc_i64 s[2:3], 10 ; encoding: [0x8a,0x49,0x82,0xbe] s_rfe_i64 s[2:3] // GFX1250: s_rfe_i64 s[2:3] ; encoding: [0x02,0x4a,0x80,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_rfe_b64 s[2:3] // GFX1250: s_rfe_i64 s[2:3] ; encoding: [0x02,0x4a,0x80,0xbe] s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) // GFX1250: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) ; encoding: [0x88,0x4c,0x82,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:31: error: specified message id is not supported on this GPU s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) // GFX1250: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) ; encoding: [0x88,0x4d,0x82,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:35: error: specified message id is not supported on this GPU s_get_shader_cycles_u64 s[2:3] // GFX1250: s_get_shader_cycles_u64 s[2:3] ; encoding: [0x00,0x06,0x82,0xbe] -// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU +// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU s_barrier_signal -3 // GFX1250: s_barrier_signal -3 ; encoding: [0xc3,0x4e,0x80,0xbe] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s b/llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s index 7395a51..58da119 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s @@ -1,211 +1,213 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s v_ceil_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x30,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_ceil_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x30,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cvt_f32_f64 v255, 0x10abcdef12345678 -// GFX1250: v_cvt_f32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x1e,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cvt_f32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x1e,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cvt_i32_f64 v255, 0x10abcdef12345678 -// GFX1250: v_cvt_i32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x06,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cvt_i32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x06,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cvt_u32_f64 v255, 0x10abcdef12345678 -// GFX1250: v_cvt_u32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x2a,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cvt_u32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x2a,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_floor_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_floor_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x34,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_floor_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x34,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_fract_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_fract_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x7c,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_fract_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x7c,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_frexp_exp_i32_f64 v255, 0x10abcdef12345678 -// GFX1250: v_frexp_exp_i32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x78,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_frexp_exp_i32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x78,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_frexp_mant_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_frexp_mant_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x7a,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_frexp_mant_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x7a,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_rcp_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_rcp_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x5e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_rcp_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x5e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_rndne_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_rndne_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x32,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_rndne_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x32,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_rsq_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_rsq_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x62,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_rsq_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x62,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_sqrt_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_sqrt_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x68,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_sqrt_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x68,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_trunc_f64 v[254:255], 0x10abcdef12345678 -// GFX1250: v_trunc_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x2e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_trunc_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x2e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_add_f64 v[254:255], 0x10abcdef12345678, v[254:255] -// GFX1250: v_add_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x05,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_add_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x05,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_max_num_f64 v[254:255], 0x10abcdef12345678, v[254:255] -// GFX1250: v_max_num_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_max_num_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_min_num_f64 v[254:255], 0x10abcdef12345678, v[254:255] -// GFX1250: v_min_num_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_min_num_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_mul_f64 v[254:255], 0x10abcdef12345678, v[254:255] -// GFX1250: v_mul_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x0d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_mul_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x0d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_class_f64 vcc_lo, 0x10abcdef12345678, v255 -// GFX1250: v_cmp_class_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v255 ; encoding: [0xfe,0xfe,0xff,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_class_f64_e32 vcc_lo, 0x10abcdef12345678, v255 ; encoding: [0xfe,0xfe,0xff,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_eq_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_eq_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_eq_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_ge_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_ge_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_ge_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_gt_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_gt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_gt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_gt_i64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_gt_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_gt_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_gt_u64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_gt_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_gt_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_le_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_le_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_le_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_le_i64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_le_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_le_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_le_u64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_le_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_le_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_lg_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_lg_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_lg_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_lt_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_lt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_lt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_lt_i64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_lt_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_lt_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_lt_u64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_lt_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_lt_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_ne_i64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_ne_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_ne_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_ne_u64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_ne_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_ne_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_neq_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_neq_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_neq_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_nge_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_nge_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_nge_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_ngt_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_ngt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_ngt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_nle_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_nle_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_nle_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_nlg_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_nlg_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_nlg_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_nlt_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_nlt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_nlt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_o_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_o_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_o_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmp_u_f64 vcc_lo, 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmp_u_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmp_u_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_class_f64 0x10abcdef12345678, v255 -// GFX1250: v_cmpx_class_f64_e32 lit64(0x10abcdef12345678), v255 ; encoding: [0xfe,0xfe,0xff,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_class_f64_e32 0x10abcdef12345678, v255 ; encoding: [0xfe,0xfe,0xff,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_eq_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_eq_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_eq_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_eq_i64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_eq_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_eq_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_eq_u64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_eq_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_eq_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_ge_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_ge_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_ge_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_ge_i64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_ge_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xad,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_ge_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xad,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_ge_u64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_ge_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xbd,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_ge_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xbd,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_gt_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_gt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_gt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_gt_i64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_gt_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_gt_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_gt_u64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_gt_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_gt_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_le_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_le_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_le_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_le_i64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_le_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_le_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_le_u64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_le_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_le_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_lg_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_lg_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_lg_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_lt_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_lt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_lt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_lt_i64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_lt_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_lt_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_lt_u64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_lt_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_lt_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_ne_i64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_ne_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_ne_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_ne_u64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_ne_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_ne_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_neq_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_neq_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_neq_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_nge_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_nge_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_nge_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_ngt_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_ngt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_ngt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_nle_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_nle_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_nle_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_nlg_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_nlg_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_nlg_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_nlt_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_nlt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_nlt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_o_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_o_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_o_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_cmpx_u_f64 0x10abcdef12345678, v[254:255] -// GFX1250: v_cmpx_u_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +// GFX1250: v_cmpx_u_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] v_ceil_f64 v[254:255], 153.1 -// GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x4063233333333333) ; encoding: [0xfe,0x30,0xfc,0x7f,0x33,0x33,0x33,0x33,0x33,0x23,0x63,0x40] +// GFX1250: v_ceil_f64_e32 v[254:255], 0x4063233333333333 ; encoding: [0xfe,0x30,0xfc,0x7f,0x33,0x33,0x33,0x33,0x33,0x23,0x63,0x40] v_ceil_f64 v[254:255], 1.5e22 -// GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x448969368974c05b) ; encoding: [0xfe,0x30,0xfc,0x7f,0x5b,0xc0,0x74,0x89,0x36,0x69,0x89,0x44] +// GFX1250: v_ceil_f64_e32 v[254:255], 0x448969368974c05b ; encoding: [0xfe,0x30,0xfc,0x7f,0x5b,0xc0,0x74,0x89,0x36,0x69,0x89,0x44] // These 64-bit literals can be represented as 32-bit with encoding 255. HW behavior: // 64 bit float: the lower 32-bit are padded with zero diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s index 2a761d9..16cec8b 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s @@ -1,7 +1,7 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX1250-ERR --implicit-check-not=error: --strict-whitespace %s global_load_b96 v[1:3], v[0:1], off -// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_b32 v5, v[2:3] scale_offset // GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: scale_offset is not supported for this instruction diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s index 811c6eb..6950c72 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s @@ -26,7 +26,7 @@ v_mov_b64 v[4:5], 0.5 // GFX1250: v_mov_b64_e32 v[4:5], 0.5 ; encoding: [0xf0,0x3a,0x08,0x7e] v_mov_b64 v[254:255], 0xaf123456 -// GFX1250: v_mov_b64_e32 v[254:255], lit64(0xaf123456) ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: v_mov_b64_e32 v[254:255], 0xaf123456 ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] v_tanh_f32 v5, v1 // GFX1250: v_tanh_f32_e32 v5, v1 ; encoding: [0x01,0x3d,0x0a,0x7e] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s index 40fcd6f..0d61c1f 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s @@ -1,5 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s v_mov_b64_e32 v[4:5], v[2:3] // GFX1250: v_mov_b64_e32 v[4:5], v[2:3] ; encoding: [0x02,0x3b,0x08,0x7e] @@ -26,7 +27,7 @@ v_mov_b64 v[4:5], 0.5 // GFX1250: v_mov_b64_e32 v[4:5], 0.5 ; encoding: [0xf0,0x3a,0x08,0x7e] v_mov_b64 v[254:255], 0xaf123456 -// GFX1250: v_mov_b64_e32 v[254:255], lit64(0xaf123456) ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: v_mov_b64_e32 v[254:255], 0xaf123456 ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] v_tanh_f32 v5, v1 // GFX1250: v_tanh_f32_e32 v5, v1 ; encoding: [0x01,0x3d,0x0a,0x7e] @@ -628,8 +629,8 @@ v_cvt_f16_fp8 v1.l, 0x1234 v_cvt_f16_fp8 v1.h, v2 // GFX1250: v_cvt_f16_fp8_e32 v1.h, v2 ; encoding: [0x02,0xef,0x02,0x7f] -v_cvt_pk_f16_bf8 v1, v2 -// GFX1250: v_cvt_pk_f16_bf8 v1, v2 ; encoding: [0x02,0xed,0x02,0x7e] +v_cvt_pk_f16_bf8 v1, v2.l +// GFX1250: v_cvt_pk_f16_bf8 v1, v2.l ; encoding: [0x02,0xed,0x02,0x7e] v_cvt_pk_f16_bf8 v1, s2 // GFX1250: v_cvt_pk_f16_bf8 v1, s2 ; encoding: [0x02,0xec,0x02,0x7e] @@ -637,8 +638,8 @@ v_cvt_pk_f16_bf8 v1, s2 v_cvt_pk_f16_bf8 v1, 100 // GFX1250: v_cvt_pk_f16_bf8 v1, 0x64 ; encoding: [0xff,0xec,0x02,0x7e,0x64,0x00,0x00,0x00] -v_cvt_pk_f16_fp8 v1, v2 -// GFX1250: v_cvt_pk_f16_fp8 v1, v2 ; encoding: [0x02,0xeb,0x02,0x7e] +v_cvt_pk_f16_fp8 v1, v2.l +// GFX1250: v_cvt_pk_f16_fp8 v1, v2.l ; encoding: [0x02,0xeb,0x02,0x7e] v_cvt_pk_f16_fp8 v1, s2 // GFX1250: v_cvt_pk_f16_fp8 v1, s2 ; encoding: [0x02,0xea,0x02,0x7e] @@ -694,8 +695,8 @@ v_cvt_pk_f32_fp8_e32 v[2:3], s3 v_cvt_pk_f32_fp8_e32 v[2:3], 3 // GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], 3 ; encoding: [0x83,0xdc,0x04,0x7e] -v_cvt_pk_f32_fp8_e32 v[2:3], v3 -// GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], v3 ; encoding: [0x03,0xdd,0x04,0x7e] +v_cvt_pk_f32_fp8_e32 v[2:3], v3.l +// GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], v3.l ; encoding: [0x03,0xdd,0x04,0x7e] v_cvt_pk_f32_fp8_e32 v[4:5], v127.h // GFX1250: v_cvt_pk_f32_fp8_e32 v[4:5], v127.h ; encoding: [0xff,0xdd,0x08,0x7e] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s index 0a1d3bf..02872b0 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s @@ -1,5 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | FileCheck --check-prefixes=GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | FileCheck --check-prefixes=GFX1250,GFX1250-ASM %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250,GFX1250-DIS %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck --check-prefix=GFX1200-ERR --implicit-check-not=error: %s v_fmac_f64 v[4:5], v[2:3], v[4:5] @@ -195,7 +196,7 @@ v_add_nc_u64 v[4:5], -4.0, v[4:5] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_add_nc_u64 v[4:5], 0xaf123456, v[4:5] -// GFX1250: v_add_nc_u64_e32 v[4:5], lit64(0xaf123456), v[4:5] ; encoding: [0xfe,0x08,0x08,0x50,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: v_add_nc_u64_e32 v[4:5], 0xaf123456, v[4:5] ; encoding: [0xfe,0x08,0x08,0x50,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_add_nc_u64 v[4:5], 0x3f717273, v[4:5] @@ -315,7 +316,7 @@ v_sub_nc_u64 v[4:5], -4.0, v[4:5] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_sub_nc_u64 v[4:5], 0xaf123456, v[4:5] -// GFX1250: v_sub_nc_u64_e32 v[4:5], lit64(0xaf123456), v[4:5] ; encoding: [0xfe,0x08,0x08,0x52,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: v_sub_nc_u64_e32 v[4:5], 0xaf123456, v[4:5] ; encoding: [0xfe,0x08,0x08,0x52,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_sub_nc_u64 v[4:5], 0x3f717273, v[4:5] @@ -435,7 +436,7 @@ v_mul_u64 v[4:5], -4.0, v[4:5] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_mul_u64 v[4:5], 0xaf123456, v[4:5] -// GFX1250: v_mul_u64_e32 v[4:5], lit64(0xaf123456), v[4:5] ; encoding: [0xfe,0x08,0x08,0x54,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: v_mul_u64_e32 v[4:5], 0xaf123456, v[4:5] ; encoding: [0xfe,0x08,0x08,0x54,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_mul_u64 v[4:5], 0x3f717273, v[4:5] @@ -519,7 +520,7 @@ v_fmamk_f64 v[6:7], v[254:255], 0x405ec00000000000, v[2:3] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[6:7], s[2:3], 0x405ec00012345678, v[2:3] -// GFX1250: v_fmamk_f64 v[6:7], s[2:3], lit64(0x405ec00012345678), v[2:3] ; encoding: [0x02,0x04,0x0c,0x46,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +// GFX1250: v_fmamk_f64 v[6:7], s[2:3], 0x405ec00012345678, v[2:3] ; encoding: [0x02,0x04,0x0c,0x46,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[6:7], vcc, 0x405ec000, v[2:3] @@ -551,7 +552,7 @@ v_fmamk_f64 v[254:255], 0x405ec000, 0x405ec000, v[254:255] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[254:255], 0x405ec00012345678, 0x405ec00012345678, v[254:255] -// GFX1250: v_fmamk_f64 v[254:255], lit64(0x405ec00012345678), lit64(0x405ec00012345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x47,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +// GFX1250: v_fmamk_f64 v[254:255], 0x405ec00012345678, 0x405ec00012345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x47,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[254:255], 123.0, 0x405ec000, v[2:3] @@ -559,15 +560,15 @@ v_fmamk_f64 v[254:255], 123.0, 0x405ec000, v[2:3] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[4:5], v[2:3], 123.1, v[6:7] -// GFX1250: v_fmamk_f64 v[4:5], v[2:3], lit64(0x405ec66666666666), v[6:7] ; encoding: [0x02,0x0d,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +// GFX1250: v_fmamk_f64 v[4:5], v[2:3], 0x405ec66666666666, v[6:7] ; encoding: [0x02,0x0d,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[4:5], 0x405ec66666666666, 123.1, v[6:7] -// GFX1250: v_fmamk_f64 v[4:5], lit64(0x405ec66666666666), lit64(0x405ec66666666666), v[6:7] ; encoding: [0xfe,0x0c,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +// GFX1250: v_fmamk_f64 v[4:5], 0x405ec66666666666, 0x405ec66666666666, v[6:7] ; encoding: [0xfe,0x0c,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[4:5], 123.1, 123.1, v[8:9] -// GFX1250: v_fmamk_f64 v[4:5], lit64(0x405ec66666666666), lit64(0x405ec66666666666), v[8:9] ; encoding: [0xfe,0x10,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +// GFX1250: v_fmamk_f64 v[4:5], 0x405ec66666666666, 0x405ec66666666666, v[8:9] ; encoding: [0xfe,0x10,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmamk_f64 v[4:5], 1.0, 1.0, v[6:7] @@ -595,7 +596,7 @@ v_fmaak_f64 v[6:7], v[254:255], v[8:9], 0x405ec00000000000 // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[6:7], s[2:3], v[8:9], 0x405ec00012345678 -// GFX1250: v_fmaak_f64 v[6:7], s[2:3], v[8:9], lit64(0x405ec00012345678) ; encoding: [0x02,0x10,0x0c,0x48,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +// GFX1250: v_fmaak_f64 v[6:7], s[2:3], v[8:9], 0x405ec00012345678 ; encoding: [0x02,0x10,0x0c,0x48,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[6:7], vcc, v[8:9], 0x405ec000 @@ -631,27 +632,28 @@ v_fmaak_f64 v[254:255], 0x405ec00000000000, v[254:255], 0x405ec00000000000 // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[254:255], 0x405ec00012345678, v[254:255], 0x405ec00012345678 -// GFX1250: v_fmaak_f64 v[254:255], lit64(0x405ec00012345678), v[254:255], lit64(0x405ec00012345678) ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +// GFX1250: v_fmaak_f64 v[254:255], 0x405ec00012345678, v[254:255], 0x405ec00012345678 ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[254:255], lit64(0x405ec00012345678), v[254:255], lit(0x405ec00012345678) -// GFX1250: v_fmaak_f64 v[254:255], lit64(0x405ec00012345678), v[254:255], lit64(0x405ec00012345678) ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] -// GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250-ASM: v_fmaak_f64 v[254:255], lit64(0x405ec00012345678), v[254:255], lit(0x405ec00012345678) ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +// GFX1250-DIS: v_fmaak_f64 v[254:255], 0x405ec00012345678, v[254:255], 0x405ec00012345678 ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +// GFX1200-ERR: :[[@LINE-3]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[254:255], 123.0, v[2:3], 0x405ec000 // GFX1250: v_fmaak_f64 v[254:255], 0x405ec000, v[2:3], 0x405ec000 ; encoding: [0xfe,0x04,0xfc,0x49,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[4:5], v[2:3], v[2:3], 123.1 -// GFX1250: v_fmaak_f64 v[4:5], v[2:3], v[2:3], lit64(0x405ec66666666666) ; encoding: [0x02,0x05,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +// GFX1250: v_fmaak_f64 v[4:5], v[2:3], v[2:3], 0x405ec66666666666 ; encoding: [0x02,0x05,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[4:5], 0x405ec66666666666, v[6:7], 123.1 -// GFX1250: v_fmaak_f64 v[4:5], lit64(0x405ec66666666666), v[6:7], lit64(0x405ec66666666666) ; encoding: [0xfe,0x0c,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +// GFX1250: v_fmaak_f64 v[4:5], 0x405ec66666666666, v[6:7], 0x405ec66666666666 ; encoding: [0xfe,0x0c,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[4:5], 123.1, v[8:9], 123.1 -// GFX1250: v_fmaak_f64 v[4:5], lit64(0x405ec66666666666), v[8:9], lit64(0x405ec66666666666) ; encoding: [0xfe,0x10,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +// GFX1250: v_fmaak_f64 v[4:5], 0x405ec66666666666, v[8:9], 0x405ec66666666666 ; encoding: [0xfe,0x10,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] // GFX1200-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU v_fmaak_f64 v[4:5], 1.0, v[8:9], 1.0 diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s index 9f50361..a83d84f 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s @@ -1,7 +1,7 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX1250-ERR --implicit-check-not=error: --strict-whitespace %s v_add_f64 v[1:2], v[1:2], v[1:2] -// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction v_fmaak_f32 v4, v2, v6, 3 row_share:1 // GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s index 949847e..ad5771b 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s @@ -1,6 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefixes=GFX12,GFX1200 %s // RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefixes=GFX12,GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s s_alloc_vgpr 0x1235 // GFX12: s_alloc_vgpr 0x1235 ; encoding: [0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00] @@ -859,7 +860,7 @@ s_mov_b64 s[0:1], 0x3f717273 s_mov_b64 s[0:1], 0xaf123456 // GFX1200: s_mov_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_mov_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_mov_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_mov_b64 s[0:1], null // GFX12: s_mov_b64 s[0:1], null ; encoding: [0x7c,0x01,0x80,0xbe] @@ -968,7 +969,7 @@ s_cmov_b64 s[0:1], 0x3f717273 s_cmov_b64 s[0:1], 0xaf123456 // GFX1200: s_cmov_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_cmov_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cmov_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_not_b32 s0, s1 // GFX12: s_not_b32 s0, s1 ; encoding: [0x01,0x1e,0x80,0xbe] @@ -1071,7 +1072,7 @@ s_not_b64 s[0:1], 0x3f717273 s_not_b64 s[0:1], 0xaf123456 // GFX1200: s_not_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_not_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_not_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_wqm_b32 s0, s1 // GFX12: s_wqm_b32 s0, s1 ; encoding: [0x01,0x1c,0x80,0xbe] @@ -1174,7 +1175,7 @@ s_wqm_b64 s[0:1], 0x3f717273 s_wqm_b64 s[0:1], 0xaf123456 // GFX1200: s_wqm_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_wqm_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_wqm_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_brev_b32 s0, s1 // GFX12: s_brev_b32 s0, s1 ; encoding: [0x01,0x04,0x80,0xbe] @@ -1277,7 +1278,7 @@ s_brev_b64 s[0:1], 0x3f717273 s_brev_b64 s[0:1], 0xaf123456 // GFX1200: s_brev_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_brev_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_brev_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_bcnt0_i32_b32 s0, s1 // GFX12: s_bcnt0_i32_b32 s0, s1 ; encoding: [0x01,0x16,0x80,0xbe] @@ -1389,7 +1390,7 @@ s_bcnt0_i32_b64 s0, 0x3f717273 s_bcnt0_i32_b64 s0, 0xaf123456 // GFX1200: s_bcnt0_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_bcnt0_i32_b64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_bcnt0_i32_b64 s0, 0xaf123456 ; encoding: [0xfe,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_bcnt1_i32_b32 s0, s1 // GFX12: s_bcnt1_i32_b32 s0, s1 ; encoding: [0x01,0x18,0x80,0xbe] @@ -1501,7 +1502,7 @@ s_bcnt1_i32_b64 s0, 0x3f717273 s_bcnt1_i32_b64 s0, 0xaf123456 // GFX1200: s_bcnt1_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_bcnt1_i32_b64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_bcnt1_i32_b64 s0, 0xaf123456 ; encoding: [0xfe,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_ff1_i32_b32 s0, s1 // GFX12: s_ctz_i32_b32 s0, s1 ; encoding: [0x01,0x08,0x80,0xbe] @@ -1613,7 +1614,7 @@ s_ff1_i32_b64 s0, 0x3f717273 s_ff1_i32_b64 s0, 0xaf123456 // GFX1200: s_ctz_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_ctz_i32_b64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_ctz_i32_b64 s0, 0xaf123456 ; encoding: [0xfe,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_flbit_i32_b32 s0, s1 // GFX12: s_clz_i32_u32 s0, s1 ; encoding: [0x01,0x0a,0x80,0xbe] @@ -1725,7 +1726,7 @@ s_flbit_i32_b64 s0, 0x3f717273 s_flbit_i32_b64 s0, 0xaf123456 // GFX1200: s_clz_i32_u64 s0, 0xaf123456 ; encoding: [0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_clz_i32_u64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_clz_i32_u64 s0, 0xaf123456 ; encoding: [0xfe,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_flbit_i32 s0, s1 // GFX12: s_cls_i32 s0, s1 ; encoding: [0x01,0x0c,0x80,0xbe] @@ -1837,7 +1838,7 @@ s_flbit_i32_i64 s0, 0x3f717273 s_flbit_i32_i64 s0, 0xaf123456 // GFX1200: s_cls_i32_i64 s0, 0xaf123456 ; encoding: [0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_cls_i32_i64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cls_i32_i64 s0, 0xaf123456 ; encoding: [0xfe,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_sext_i32_i8 s0, s1 // GFX12: s_sext_i32_i8 s0, s1 ; encoding: [0x01,0x0e,0x80,0xbe] @@ -2283,7 +2284,7 @@ s_and_saveexec_b64 s[0:1], 0x3f717273 s_and_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_and_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_saveexec_b64 s[0:1], s[2:3] // GFX12: s_or_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x23,0x80,0xbe] @@ -2323,7 +2324,7 @@ s_or_saveexec_b64 s[0:1], 0x3f717273 s_or_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_or_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_xor_saveexec_b64 s[0:1], s[2:3] // GFX12: s_xor_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x25,0x80,0xbe] @@ -2363,7 +2364,7 @@ s_xor_saveexec_b64 s[0:1], 0x3f717273 s_xor_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_xor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_xor_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_xor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_andn2_saveexec_b64 s[0:1], s[2:3] // GFX12: s_and_not1_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x31,0x80,0xbe] @@ -2403,7 +2404,7 @@ s_andn2_saveexec_b64 s[0:1], 0x3f717273 s_andn2_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_and_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_orn2_saveexec_b64 s[0:1], s[2:3] // GFX12: s_or_not1_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x33,0x80,0xbe] @@ -2443,7 +2444,7 @@ s_orn2_saveexec_b64 s[0:1], 0x3f717273 s_orn2_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_or_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not1_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_nand_saveexec_b64 s[0:1], s[2:3] // GFX12: s_nand_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x27,0x80,0xbe] @@ -2483,7 +2484,7 @@ s_nand_saveexec_b64 s[0:1], 0x3f717273 s_nand_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_nand_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_nand_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_nand_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_nor_saveexec_b64 s[0:1], s[2:3] // GFX12: s_nor_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x29,0x80,0xbe] @@ -2523,7 +2524,7 @@ s_nor_saveexec_b64 s[0:1], 0x3f717273 s_nor_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_nor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_nor_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_nor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_xnor_saveexec_b64 s[0:1], s[2:3] // GFX12: s_xnor_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x2b,0x80,0xbe] @@ -2563,7 +2564,7 @@ s_xnor_saveexec_b64 s[0:1], 0x3f717273 s_xnor_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_xnor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_xnor_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_xnor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_quadmask_b32 s0, s1 // GFX12: s_quadmask_b32 s0, s1 ; encoding: [0x01,0x1a,0x80,0xbe] @@ -2666,7 +2667,7 @@ s_quadmask_b64 s[0:1], 0x3f717273 s_quadmask_b64 s[0:1], 0xaf123456 // GFX1200: s_quadmask_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_quadmask_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_quadmask_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_movrels_b32 s0, s1 // GFX12: s_movrels_b32 s0, s1 ; encoding: [0x01,0x40,0x80,0xbe] @@ -2811,7 +2812,7 @@ s_movreld_b64 s[0:1], 0x3f717273 s_movreld_b64 s[0:1], 0xaf123456 // GFX1200: s_movreld_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_movreld_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_movreld_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_abs_i32 s0, s1 // GFX12: s_abs_i32 s0, s1 ; encoding: [0x01,0x15,0x80,0xbe] @@ -2911,7 +2912,7 @@ s_andn1_saveexec_b64 s[0:1], 0x3f717273 s_andn1_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_and_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not0_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_orn1_saveexec_b64 s[0:1], s[2:3] // GFX12: s_or_not0_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x2f,0x80,0xbe] @@ -2951,7 +2952,7 @@ s_orn1_saveexec_b64 s[0:1], 0x3f717273 s_orn1_saveexec_b64 s[0:1], 0xaf123456 // GFX1200: s_or_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not0_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_andn1_wrexec_b64 s[0:1], s[2:3] // GFX12: s_and_not0_wrexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x35,0x80,0xbe] @@ -2991,7 +2992,7 @@ s_andn1_wrexec_b64 s[0:1], 0x3f717273 s_andn1_wrexec_b64 s[0:1], 0xaf123456 // GFX1200: s_and_not0_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not0_wrexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not0_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_andn2_wrexec_b64 s[0:1], s[2:3] // GFX12: s_and_not1_wrexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x37,0x80,0xbe] @@ -3031,7 +3032,7 @@ s_andn2_wrexec_b64 s[0:1], 0x3f717273 s_andn2_wrexec_b64 s[0:1], 0xaf123456 // GFX1200: s_and_not1_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_wrexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_bitreplicate_b64_b32 s[0:1], s2 // GFX12: s_bitreplicate_b64_b32 s[0:1], s2 ; encoding: [0x02,0x14,0x80,0xbe] @@ -3830,7 +3831,7 @@ s_ctz_i32_b64 exec_hi, src_scc s_ctz_i32_b64 null, 0xaf123456 // GFX1200: s_ctz_i32_b64 null, 0xaf123456 ; encoding: [0xff,0x09,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_ctz_i32_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x09,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_ctz_i32_b64 null, 0xaf123456 ; encoding: [0xfe,0x09,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_not1_saveexec_b64 s[10:11], s[2:3] // GFX12: s_and_not1_saveexec_b64 s[10:11], s[2:3] ; encoding: [0x02,0x31,0x8a,0xbe] @@ -3858,7 +3859,7 @@ s_and_not1_saveexec_b64 ttmp[14:15], src_scc s_and_not1_saveexec_b64 null, 0xaf123456 // GFX1200: s_and_not1_saveexec_b64 null, 0xaf123456 ; encoding: [0xff,0x31,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_saveexec_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x31,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_saveexec_b64 null, 0xaf123456 ; encoding: [0xfe,0x31,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_not0_saveexec_b32 s5, s1 // GFX12: s_and_not0_saveexec_b32 s5, s1 ; encoding: [0x01,0x2c,0x85,0xbe] @@ -3919,7 +3920,7 @@ s_and_not0_saveexec_b64 ttmp[14:15], src_scc s_and_not0_saveexec_b64 null, 0xaf123456 // GFX1200: s_and_not0_saveexec_b64 null, 0xaf123456 ; encoding: [0xff,0x2d,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not0_saveexec_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x2d,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not0_saveexec_b64 null, 0xaf123456 ; encoding: [0xfe,0x2d,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_not0_wrexec_b32 s5, s1 // GFX12: s_and_not0_wrexec_b32 s5, s1 ; encoding: [0x01,0x34,0x85,0xbe] @@ -3980,7 +3981,7 @@ s_and_not0_wrexec_b64 ttmp[14:15], src_scc s_and_not0_wrexec_b64 null, 0xaf123456 // GFX1200: s_and_not0_wrexec_b64 null, 0xaf123456 ; encoding: [0xff,0x35,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not0_wrexec_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x35,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not0_wrexec_b64 null, 0xaf123456 ; encoding: [0xfe,0x35,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_not1_saveexec_b32 s5, s1 // GFX12: s_and_not1_saveexec_b32 s5, s1 ; encoding: [0x01,0x30,0x85,0xbe] @@ -4074,7 +4075,7 @@ s_and_not1_wrexec_b64 ttmp[14:15], src_scc s_and_not1_wrexec_b64 null, 0xaf123456 // GFX1200: s_and_not1_wrexec_b64 null, 0xaf123456 ; encoding: [0xff,0x37,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_wrexec_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x37,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_wrexec_b64 null, 0xaf123456 ; encoding: [0xfe,0x37,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_cls_i32 s5, s1 // GFX12: s_cls_i32 s5, s1 ; encoding: [0x01,0x0c,0x85,0xbe] @@ -4144,7 +4145,7 @@ s_cls_i32_i64 exec_hi, src_scc s_cls_i32_i64 null, 0xaf123456 // GFX1200: s_cls_i32_i64 null, 0xaf123456 ; encoding: [0xff,0x0d,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_cls_i32_i64 null, lit64(0xaf123456) ; encoding: [0xfe,0x0d,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cls_i32_i64 null, 0xaf123456 ; encoding: [0xfe,0x0d,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_clz_i32_u32 s5, s1 // GFX12: s_clz_i32_u32 s5, s1 ; encoding: [0x01,0x0a,0x85,0xbe] @@ -4214,7 +4215,7 @@ s_clz_i32_u64 exec_hi, src_scc s_clz_i32_u64 null, 0xaf123456 // GFX1200: s_clz_i32_u64 null, 0xaf123456 ; encoding: [0xff,0x0b,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_clz_i32_u64 null, lit64(0xaf123456) ; encoding: [0xfe,0x0b,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_clz_i32_u64 null, 0xaf123456 ; encoding: [0xfe,0x0b,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_not0_saveexec_b32 s5, s1 // GFX12: s_or_not0_saveexec_b32 s5, s1 ; encoding: [0x01,0x2e,0x85,0xbe] @@ -4275,7 +4276,7 @@ s_or_not0_saveexec_b64 ttmp[14:15], src_scc s_or_not0_saveexec_b64 null, 0xaf123456 // GFX1200: s_or_not0_saveexec_b64 null, 0xaf123456 ; encoding: [0xff,0x2f,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not0_saveexec_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x2f,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not0_saveexec_b64 null, 0xaf123456 ; encoding: [0xfe,0x2f,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_not1_saveexec_b32 s5, s1 // GFX12: s_or_not1_saveexec_b32 s5, s1 ; encoding: [0x01,0x32,0x85,0xbe] @@ -4336,4 +4337,4 @@ s_or_not1_saveexec_b64 ttmp[14:15], src_scc s_or_not1_saveexec_b64 null, 0xaf123456 // GFX1200: s_or_not1_saveexec_b64 null, 0xaf123456 ; encoding: [0xff,0x33,0xfc,0xbe,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not1_saveexec_b64 null, lit64(0xaf123456) ; encoding: [0xfe,0x33,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not1_saveexec_b64 null, 0xaf123456 ; encoding: [0xfe,0x33,0xfc,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s index 2ecec4c..9c83879 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s @@ -1,6 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefixes=GFX12,GFX1200 %s // RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefixes=GFX12,GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s s_add_nc_u64 s[0:1], s[2:3], s[4:5] // GFX12: s_add_nc_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0xa9] @@ -55,7 +56,7 @@ s_add_nc_u64 s[0:1], 0x3f717273, s[2:3] s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] // GFX1200: s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf] -// GFX1250: s_add_nc_u64 s[0:1], lit64(0xaf123456), s[2:3] ; encoding: [0xfe,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xfe,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_add_nc_u64 s[0:1], s[2:3], exec // GFX12: s_add_nc_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0xa9] @@ -80,7 +81,7 @@ s_add_nc_u64 s[0:1], s[2:3], 0x3f717273 s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0xa9,0x56,0x34,0x12,0xaf] -// GFX1250: s_add_nc_u64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_sub_nc_u64 s[0:1], s[2:3], s[4:5] // GFX12: s_sub_nc_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x00,0xaa] @@ -135,7 +136,7 @@ s_sub_nc_u64 s[0:1], 0x3f717273, s[2:3] s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] // GFX1200: s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf] -// GFX1250: s_sub_nc_u64 s[0:1], lit64(0xaf123456), s[2:3] ; encoding: [0xfe,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xfe,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_sub_nc_u64 s[0:1], s[2:3], exec // GFX12: s_sub_nc_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x00,0xaa] @@ -160,7 +161,7 @@ s_sub_nc_u64 s[0:1], s[2:3], 0x3f717273 s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x00,0xaa,0x56,0x34,0x12,0xaf] -// GFX1250: s_sub_nc_u64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_mul_u64 s[0:1], s[2:3], s[4:5] // GFX12: s_mul_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0xaa] @@ -215,7 +216,7 @@ s_mul_u64 s[0:1], 0x3f717273, s[2:3] s_mul_u64 s[0:1], 0xaf123456, s[2:3] // GFX1200: s_mul_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf] -// GFX1250: s_mul_u64 s[0:1], lit64(0xaf123456), s[2:3] ; encoding: [0xfe,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_mul_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xfe,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_mul_u64 s[0:1], s[2:3], exec // GFX12: s_mul_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0xaa] @@ -240,7 +241,7 @@ s_mul_u64 s[0:1], s[2:3], 0x3f717273 s_mul_u64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_mul_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0xaa,0x56,0x34,0x12,0xaf] -// GFX1250: s_mul_u64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_mul_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_add_f32 s5, s1, s2 // GFX12: s_add_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa0] @@ -2358,7 +2359,7 @@ s_cselect_b64 s[0:1], 0x3f717273, s[4:5] s_cselect_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_cselect_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x98,0x56,0x34,0x12,0xaf] -// GFX1250: s_cselect_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cselect_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_cselect_b64 s[0:1], s[2:3], exec // GFX12: s_cselect_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x98] @@ -2383,7 +2384,7 @@ s_cselect_b64 s[0:1], s[2:3], 0x3f717273 s_cselect_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_cselect_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x98,0x56,0x34,0x12,0xaf] -// GFX1250: s_cselect_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cselect_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_b32 s0, s1, s2 // GFX12: s_and_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8b] @@ -2552,7 +2553,7 @@ s_and_b64 s[0:1], 0x3f717273, s[4:5] s_and_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_and_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_b64 s[0:1], s[2:3], exec // GFX12: s_and_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8b] @@ -2577,7 +2578,7 @@ s_and_b64 s[0:1], s[2:3], 0x3f717273 s_and_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_and_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_b32 s0, s1, s2 // GFX12: s_or_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8c] @@ -2737,7 +2738,7 @@ s_or_b64 s[0:1], 0x3f717273, s[4:5] s_or_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_or_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_b64 s[0:1], s[2:3], exec // GFX12: s_or_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8c] @@ -2762,7 +2763,7 @@ s_or_b64 s[0:1], s[2:3], 0x3f717273 s_or_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_or_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_xor_b32 s0, s1, s2 // GFX12: s_xor_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8d] @@ -2922,7 +2923,7 @@ s_xor_b64 s[0:1], 0x3f717273, s[4:5] s_xor_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_xor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf] -// GFX1250: s_xor_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_xor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_xor_b64 s[0:1], s[2:3], exec // GFX12: s_xor_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8d] @@ -2947,7 +2948,7 @@ s_xor_b64 s[0:1], s[2:3], 0x3f717273 s_xor_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_xor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf] -// GFX1250: s_xor_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_xor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_andn2_b32 s0, s1, s2 // GFX12: s_and_not1_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x91] @@ -3107,7 +3108,7 @@ s_andn2_b64 s[0:1], 0x3f717273, s[4:5] s_andn2_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_and_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_andn2_b64 s[0:1], s[2:3], exec // GFX12: s_and_not1_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x91] @@ -3132,7 +3133,7 @@ s_andn2_b64 s[0:1], s[2:3], 0x3f717273 s_andn2_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_and_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_orn2_b32 s0, s1, s2 // GFX12: s_or_not1_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x92] @@ -3292,7 +3293,7 @@ s_orn2_b64 s[0:1], 0x3f717273, s[4:5] s_orn2_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_or_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x92,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not1_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_orn2_b64 s[0:1], s[2:3], exec // GFX12: s_or_not1_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x92] @@ -3317,7 +3318,7 @@ s_orn2_b64 s[0:1], s[2:3], 0x3f717273 s_orn2_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_or_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not1_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_nand_b32 s0, s1, s2 // GFX12: s_nand_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8e] @@ -3477,7 +3478,7 @@ s_nand_b64 s[0:1], 0x3f717273, s[4:5] s_nand_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_nand_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf] -// GFX1250: s_nand_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_nand_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_nand_b64 s[0:1], s[2:3], exec // GFX12: s_nand_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8e] @@ -3502,7 +3503,7 @@ s_nand_b64 s[0:1], s[2:3], 0x3f717273 s_nand_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_nand_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf] -// GFX1250: s_nand_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_nand_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_nor_b32 s0, s1, s2 // GFX12: s_nor_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8f] @@ -3662,7 +3663,7 @@ s_nor_b64 s[0:1], 0x3f717273, s[4:5] s_nor_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_nor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf] -// GFX1250: s_nor_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_nor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_nor_b64 s[0:1], s[2:3], exec // GFX12: s_nor_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8f] @@ -3687,7 +3688,7 @@ s_nor_b64 s[0:1], s[2:3], 0x3f717273 s_nor_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_nor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf] -// GFX1250: s_nor_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_nor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_xnor_b32 s0, s1, s2 // GFX12: s_xnor_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x90] @@ -3847,7 +3848,7 @@ s_xnor_b64 s[0:1], 0x3f717273, s[4:5] s_xnor_b64 s[0:1], 0xaf123456, s[4:5] // GFX1200: s_xnor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf] -// GFX1250: s_xnor_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_xnor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_xnor_b64 s[0:1], s[2:3], exec // GFX12: s_xnor_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x90] @@ -3872,7 +3873,7 @@ s_xnor_b64 s[0:1], s[2:3], 0x3f717273 s_xnor_b64 s[0:1], s[2:3], 0xaf123456 // GFX1200: s_xnor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf] -// GFX1250: s_xnor_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_xnor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_lshl_b32 s0, s1, s2 // GFX12: s_lshl_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x84] @@ -4032,7 +4033,7 @@ s_lshl_b64 s[0:1], 0x3f717273, s4 s_lshl_b64 s[0:1], 0xaf123456, s4 // GFX1200: s_lshl_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x84,0x56,0x34,0x12,0xaf] -// GFX1250: s_lshl_b64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x84,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_lshl_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x84,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_lshl_b64 s[0:1], s[2:3], exec_lo // GFX12: s_lshl_b64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x84] @@ -4216,7 +4217,7 @@ s_lshr_b64 s[0:1], 0x3f717273, s4 s_lshr_b64 s[0:1], 0xaf123456, s4 // GFX1200: s_lshr_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf] -// GFX1250: s_lshr_b64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x85,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_lshr_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x85,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_lshr_b64 s[0:1], s[2:3], exec_lo // GFX12: s_lshr_b64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x85] @@ -4400,7 +4401,7 @@ s_ashr_i64 s[0:1], 0x3f717273, s4 s_ashr_i64 s[0:1], 0xaf123456, s4 // GFX1200: s_ashr_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x86,0x56,0x34,0x12,0xaf] -// GFX1250: s_ashr_i64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x86,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_ashr_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x86,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_ashr_i64 s[0:1], s[2:3], exec_lo // GFX12: s_ashr_i64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x86] @@ -4995,7 +4996,7 @@ s_bfe_u64 s[0:1], 0x3f717273, s4 s_bfe_u64 s[0:1], 0xaf123456, s4 // GFX1200: s_bfe_u64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x00,0x94,0x56,0x34,0x12,0xaf] -// GFX1250: s_bfe_u64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x00,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_bfe_u64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x00,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_bfe_u64 s[0:1], s[2:3], exec_lo // GFX12: s_bfe_u64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x00,0x94] @@ -5074,7 +5075,7 @@ s_bfe_i64 s[0:1], 0x3f717273, s4 s_bfe_i64 s[0:1], 0xaf123456, s4 // GFX1200: s_bfe_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf] -// GFX1250: s_bfe_i64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_bfe_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_bfe_i64 s[0:1], s[2:3], exec_lo // GFX12: s_bfe_i64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x94] @@ -6278,7 +6279,7 @@ s_and_not1_b64 s[10:11], vcc, ttmp[14:15] s_and_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 // GFX1200: s_and_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x7a,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_b64 s[10:11], ttmp[14:15], lit64(0xaf123456) ; encoding: [0x7a,0xfe,0x8a,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x7a,0xfe,0x8a,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_and_not1_b64 s[10:11], exec, src_scc // GFX12: s_and_not1_b64 s[10:11], exec, src_scc ; encoding: [0x7e,0xfd,0x8a,0x91] @@ -6297,7 +6298,7 @@ s_and_not1_b64 exec, src_scc, exec s_and_not1_b64 null, 0xaf123456, vcc // GFX1200: s_and_not1_b64 null, 0xaf123456, vcc ; encoding: [0xff,0x6a,0xfc,0x91,0x56,0x34,0x12,0xaf] -// GFX1250: s_and_not1_b64 null, lit64(0xaf123456), vcc ; encoding: [0xfe,0x6a,0xfc,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_and_not1_b64 null, 0xaf123456, vcc ; encoding: [0xfe,0x6a,0xfc,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_not1_b64 s[10:11], s[2:3], s[4:5] // GFX12: s_or_not1_b64 s[10:11], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x8a,0x92] @@ -6310,7 +6311,7 @@ s_or_not1_b64 s[10:11], vcc, ttmp[14:15] s_or_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 // GFX1200: s_or_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x7a,0xff,0x8a,0x92,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not1_b64 s[10:11], ttmp[14:15], lit64(0xaf123456) ; encoding: [0x7a,0xfe,0x8a,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x7a,0xfe,0x8a,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_or_not1_b64 s[10:11], exec, src_scc // GFX12: s_or_not1_b64 s[10:11], exec, src_scc ; encoding: [0x7e,0xfd,0x8a,0x92] @@ -6329,4 +6330,4 @@ s_or_not1_b64 exec, src_scc, exec s_or_not1_b64 null, 0xaf123456, vcc // GFX1200: s_or_not1_b64 null, 0xaf123456, vcc ; encoding: [0xff,0x6a,0xfc,0x92,0x56,0x34,0x12,0xaf] -// GFX1250: s_or_not1_b64 null, lit64(0xaf123456), vcc ; encoding: [0xfe,0x6a,0xfc,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_or_not1_b64 null, 0xaf123456, vcc ; encoding: [0xfe,0x6a,0xfc,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s index cedba66d..98bb3c3 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s @@ -1,6 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck --check-prefixes=GFX12,GFX1200 %s // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | FileCheck --check-prefixes=GFX12,GFX1250 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s s_cmp_lt_f32 s1, s2 // GFX12: s_cmp_lt_f32 s1, s2 ; encoding: [0x01,0x02,0x41,0xbf] @@ -2119,7 +2120,7 @@ s_cmp_eq_u64 s[0:1], 0x3f717273 s_cmp_eq_u64 s[0:1], 0xaf123456 // GFX1200: s_cmp_eq_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf] -// GFX1250: s_cmp_eq_u64 s[0:1], lit64(0xaf123456) ; encoding: [0x00,0xfe,0x10,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cmp_eq_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xfe,0x10,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] s_cmp_lg_u64 s[0:1], s[2:3] // GFX12: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x11,0xbf] @@ -2162,4 +2163,4 @@ s_cmp_lg_u64 s[0:1], 0x3f717273 s_cmp_lg_u64 s[0:1], 0xaf123456 // GFX1200: s_cmp_lg_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x11,0xbf,0x56,0x34,0x12,0xaf] -// GFX1250: s_cmp_lg_u64 s[0:1], lit64(0xaf123456) ; encoding: [0x00,0xfe,0x11,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +// GFX1250: s_cmp_lg_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xfe,0x11,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s index 43673d1..c96a72d 100644 --- a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s +++ b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s @@ -2,707 +2,707 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s // GFX90A: flat_load_ubyte a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[2:3] offset:4095 // GFX90A: flat_load_ubyte a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a255, v[2:3] offset:4095 // GFX90A: flat_load_ubyte a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[254:255] offset:4095 // GFX90A: flat_load_ubyte a5, v[2:3] ; encoding: [0x00,0x00,0x40,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[2:3] // GFX90A: flat_load_ubyte a5, v[2:3] ; encoding: [0x00,0x00,0x40,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[2:3] // GFX90A: flat_load_ubyte a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x40,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[2:3] offset:7 // GFX90A: flat_load_ubyte a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x41,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[2:3] offset:4095 glc // GFX90A: flat_load_ubyte a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x42,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte a5, v[2:3] offset:4095 slc // GFX90A: flat_load_sbyte a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x44,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[2:3] offset:4095 // GFX90A: flat_load_sbyte a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x44,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a255, v[2:3] offset:4095 // GFX90A: flat_load_sbyte a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x44,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[254:255] offset:4095 // GFX90A: flat_load_sbyte a5, v[2:3] ; encoding: [0x00,0x00,0x44,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[2:3] // GFX90A: flat_load_sbyte a5, v[2:3] ; encoding: [0x00,0x00,0x44,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[2:3] // GFX90A: flat_load_sbyte a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x44,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[2:3] offset:7 // GFX90A: flat_load_sbyte a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x45,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[2:3] offset:4095 glc // GFX90A: flat_load_sbyte a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x46,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte a5, v[2:3] offset:4095 slc // GFX90A: flat_load_ushort a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x48,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[2:3] offset:4095 // GFX90A: flat_load_ushort a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x48,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a255, v[2:3] offset:4095 // GFX90A: flat_load_ushort a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x48,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[254:255] offset:4095 // GFX90A: flat_load_ushort a5, v[2:3] ; encoding: [0x00,0x00,0x48,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[2:3] // GFX90A: flat_load_ushort a5, v[2:3] ; encoding: [0x00,0x00,0x48,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[2:3] // GFX90A: flat_load_ushort a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x48,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[2:3] offset:7 // GFX90A: flat_load_ushort a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x49,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[2:3] offset:4095 glc // GFX90A: flat_load_ushort a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x4a,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ushort a5, v[2:3] offset:4095 slc // GFX90A: flat_load_sshort a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x4c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[2:3] offset:4095 // GFX90A: flat_load_sshort a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x4c,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a255, v[2:3] offset:4095 // GFX90A: flat_load_sshort a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x4c,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[254:255] offset:4095 // GFX90A: flat_load_sshort a5, v[2:3] ; encoding: [0x00,0x00,0x4c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[2:3] // GFX90A: flat_load_sshort a5, v[2:3] ; encoding: [0x00,0x00,0x4c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[2:3] // GFX90A: flat_load_sshort a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x4c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[2:3] offset:7 // GFX90A: flat_load_sshort a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x4d,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[2:3] offset:4095 glc // GFX90A: flat_load_sshort a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x4e,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sshort a5, v[2:3] offset:4095 slc // GFX90A: flat_load_dword a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[2:3] offset:4095 // GFX90A: flat_load_dword a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a255, v[2:3] offset:4095 // GFX90A: flat_load_dword a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[254:255] offset:4095 // GFX90A: flat_load_dword a5, v[2:3] ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[2:3] // GFX90A: flat_load_dword a5, v[2:3] ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[2:3] // GFX90A: flat_load_dword a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x50,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[2:3] offset:7 // GFX90A: flat_load_dword a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x51,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[2:3] offset:4095 glc // GFX90A: flat_load_dword a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x52,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dword a5, v[2:3] offset:4095 slc // GFX90A: flat_load_dwordx2 a[6:7], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x54,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[2:3] offset:4095 // GFX90A: flat_load_dwordx2 a[254:255], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x54,0xdc,0x02,0x00,0x80,0xfe] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[254:255], v[2:3] offset:4095 // GFX90A: flat_load_dwordx2 a[6:7], v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x54,0xdc,0xfe,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[254:255] offset:4095 // GFX90A: flat_load_dwordx2 a[6:7], v[2:3] ; encoding: [0x00,0x00,0x54,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[2:3] // GFX90A: flat_load_dwordx2 a[6:7], v[2:3] ; encoding: [0x00,0x00,0x54,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[2:3] // GFX90A: flat_load_dwordx2 a[6:7], v[2:3] offset:7 ; encoding: [0x07,0x00,0x54,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[2:3] offset:7 // GFX90A: flat_load_dwordx2 a[6:7], v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x55,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[2:3] offset:4095 glc // GFX90A: flat_load_dwordx2 a[6:7], v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x56,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx2 a[6:7], v[2:3] offset:4095 slc // GFX90A: flat_load_dwordx3 a[6:8], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x58,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[2:3] offset:4095 // GFX90A: flat_load_dwordx3 a[252:254], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x58,0xdc,0x02,0x00,0x80,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[252:254], v[2:3] offset:4095 // GFX90A: flat_load_dwordx3 a[6:8], v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x58,0xdc,0xfe,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[254:255] offset:4095 // GFX90A: flat_load_dwordx3 a[6:8], v[2:3] ; encoding: [0x00,0x00,0x58,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[2:3] // GFX90A: flat_load_dwordx3 a[6:8], v[2:3] ; encoding: [0x00,0x00,0x58,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[2:3] // GFX90A: flat_load_dwordx3 a[6:8], v[2:3] offset:7 ; encoding: [0x07,0x00,0x58,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[2:3] offset:7 // GFX90A: flat_load_dwordx3 a[6:8], v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x59,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[2:3] offset:4095 glc // GFX90A: flat_load_dwordx3 a[6:8], v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x5a,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx3 a[6:8], v[2:3] offset:4095 slc // GFX90A: flat_load_dwordx4 a[6:9], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x5c,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[2:3] offset:4095 // GFX90A: flat_load_dwordx4 a[252:255], v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x5c,0xdc,0x02,0x00,0x80,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[252:255], v[2:3] offset:4095 // GFX90A: flat_load_dwordx4 a[6:9], v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x5c,0xdc,0xfe,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[254:255] offset:4095 // GFX90A: flat_load_dwordx4 a[6:9], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[2:3] // GFX90A: flat_load_dwordx4 a[6:9], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[2:3] // GFX90A: flat_load_dwordx4 a[6:9], v[2:3] offset:7 ; encoding: [0x07,0x00,0x5c,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[2:3] offset:7 // GFX90A: flat_load_dwordx4 a[6:9], v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x5d,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[2:3] offset:4095 glc // GFX90A: flat_load_dwordx4 a[6:9], v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x5e,0xdc,0x02,0x00,0x80,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_dwordx4 a[6:9], v[2:3] offset:4095 slc // GFX90A: flat_store_byte v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x60,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a2 offset:4095 // GFX90A: flat_store_byte v[254:255], a2 offset:4095 ; encoding: [0xff,0x0f,0x60,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[254:255], a2 offset:4095 // GFX90A: flat_store_byte v[2:3], a255 offset:4095 ; encoding: [0xff,0x0f,0x60,0xdc,0x02,0xff,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a255 offset:4095 // GFX90A: flat_store_byte v[2:3], a2 ; encoding: [0x00,0x00,0x60,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a2 // GFX90A: flat_store_byte v[2:3], a2 ; encoding: [0x00,0x00,0x60,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a2 // GFX90A: flat_store_byte v[2:3], a2 offset:7 ; encoding: [0x07,0x00,0x60,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a2 offset:7 // GFX90A: flat_store_byte v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x61,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a2 offset:4095 glc // GFX90A: flat_store_byte v[2:3], a2 offset:4095 slc ; encoding: [0xff,0x0f,0x62,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte v[2:3], a2 offset:4095 slc // GFX90A: flat_store_byte_d16_hi v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x64,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a2 offset:4095 // GFX90A: flat_store_byte_d16_hi v[254:255], a2 offset:4095 ; encoding: [0xff,0x0f,0x64,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[254:255], a2 offset:4095 // GFX90A: flat_store_byte_d16_hi v[2:3], a255 offset:4095 ; encoding: [0xff,0x0f,0x64,0xdc,0x02,0xff,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a255 offset:4095 // GFX90A: flat_store_byte_d16_hi v[2:3], a2 ; encoding: [0x00,0x00,0x64,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a2 // GFX90A: flat_store_byte_d16_hi v[2:3], a2 ; encoding: [0x00,0x00,0x64,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a2 // GFX90A: flat_store_byte_d16_hi v[2:3], a2 offset:7 ; encoding: [0x07,0x00,0x64,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a2 offset:7 // GFX90A: flat_store_byte_d16_hi v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x65,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a2 offset:4095 glc // GFX90A: flat_store_byte_d16_hi v[2:3], a2 offset:4095 slc ; encoding: [0xff,0x0f,0x66,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_byte_d16_hi v[2:3], a2 offset:4095 slc // GFX90A: flat_store_short v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x68,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a2 offset:4095 // GFX90A: flat_store_short v[254:255], a2 offset:4095 ; encoding: [0xff,0x0f,0x68,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[254:255], a2 offset:4095 // GFX90A: flat_store_short v[2:3], a255 offset:4095 ; encoding: [0xff,0x0f,0x68,0xdc,0x02,0xff,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a255 offset:4095 // GFX90A: flat_store_short v[2:3], a2 ; encoding: [0x00,0x00,0x68,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a2 // GFX90A: flat_store_short v[2:3], a2 ; encoding: [0x00,0x00,0x68,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a2 // GFX90A: flat_store_short v[2:3], a2 offset:7 ; encoding: [0x07,0x00,0x68,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a2 offset:7 // GFX90A: flat_store_short v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x69,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a2 offset:4095 glc // GFX90A: flat_store_short v[2:3], a2 offset:4095 slc ; encoding: [0xff,0x0f,0x6a,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short v[2:3], a2 offset:4095 slc // GFX90A: flat_store_short_d16_hi v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a2 offset:4095 // GFX90A: flat_store_short_d16_hi v[254:255], a2 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[254:255], a2 offset:4095 // GFX90A: flat_store_short_d16_hi v[2:3], a255 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xdc,0x02,0xff,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a255 offset:4095 // GFX90A: flat_store_short_d16_hi v[2:3], a2 ; encoding: [0x00,0x00,0x6c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a2 // GFX90A: flat_store_short_d16_hi v[2:3], a2 ; encoding: [0x00,0x00,0x6c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a2 // GFX90A: flat_store_short_d16_hi v[2:3], a2 offset:7 ; encoding: [0x07,0x00,0x6c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a2 offset:7 // GFX90A: flat_store_short_d16_hi v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x6d,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a2 offset:4095 glc // GFX90A: flat_store_short_d16_hi v[2:3], a2 offset:4095 slc ; encoding: [0xff,0x0f,0x6e,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_short_d16_hi v[2:3], a2 offset:4095 slc // GFX90A: flat_store_dword v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x70,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a2 offset:4095 // GFX90A: flat_store_dword v[254:255], a2 offset:4095 ; encoding: [0xff,0x0f,0x70,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[254:255], a2 offset:4095 // GFX90A: flat_store_dword v[2:3], a255 offset:4095 ; encoding: [0xff,0x0f,0x70,0xdc,0x02,0xff,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a255 offset:4095 // GFX90A: flat_store_dword v[2:3], a2 ; encoding: [0x00,0x00,0x70,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a2 // GFX90A: flat_store_dword v[2:3], a2 ; encoding: [0x00,0x00,0x70,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a2 // GFX90A: flat_store_dword v[2:3], a2 offset:7 ; encoding: [0x07,0x00,0x70,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a2 offset:7 // GFX90A: flat_store_dword v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x71,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a2 offset:4095 glc // GFX90A: flat_store_dword v[2:3], a2 offset:4095 slc ; encoding: [0xff,0x0f,0x72,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dword v[2:3], a2 offset:4095 slc // GFX90A: flat_store_dwordx2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x74,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_store_dwordx2 v[254:255], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x74,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[254:255], a[2:3] offset:4095 // GFX90A: flat_store_dwordx2 v[2:3], a[254:255] offset:4095 ; encoding: [0xff,0x0f,0x74,0xdc,0x02,0xfe,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[254:255] offset:4095 // GFX90A: flat_store_dwordx2 v[2:3], a[2:3] ; encoding: [0x00,0x00,0x74,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[2:3] // GFX90A: flat_store_dwordx2 v[2:3], a[2:3] ; encoding: [0x00,0x00,0x74,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[2:3] // GFX90A: flat_store_dwordx2 v[2:3], a[2:3] offset:7 ; encoding: [0x07,0x00,0x74,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[2:3] offset:7 // GFX90A: flat_store_dwordx2 v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x75,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[2:3] offset:4095 glc // GFX90A: flat_store_dwordx2 v[2:3], a[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x76,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx2 v[2:3], a[2:3] offset:4095 slc // GFX90A: flat_store_dwordx3 v[2:3], a[2:4] offset:4095 ; encoding: [0xff,0x0f,0x78,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[2:4] offset:4095 // GFX90A: flat_store_dwordx3 v[254:255], a[2:4] offset:4095 ; encoding: [0xff,0x0f,0x78,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[254:255], a[2:4] offset:4095 // GFX90A: flat_store_dwordx3 v[2:3], a[252:254] offset:4095 ; encoding: [0xff,0x0f,0x78,0xdc,0x02,0xfc,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[252:254] offset:4095 // GFX90A: flat_store_dwordx3 v[2:3], a[2:4] ; encoding: [0x00,0x00,0x78,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[2:4] // GFX90A: flat_store_dwordx3 v[2:3], a[2:4] ; encoding: [0x00,0x00,0x78,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[2:4] // GFX90A: flat_store_dwordx3 v[2:3], a[2:4] offset:7 ; encoding: [0x07,0x00,0x78,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[2:4] offset:7 // GFX90A: flat_store_dwordx3 v[2:3], a[2:4] offset:4095 glc ; encoding: [0xff,0x0f,0x79,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[2:4] offset:4095 glc // GFX90A: flat_store_dwordx3 v[2:3], a[2:4] offset:4095 slc ; encoding: [0xff,0x0f,0x7a,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx3 v[2:3], a[2:4] offset:4095 slc // GFX90A: flat_store_dwordx4 v[2:3], a[2:5] offset:4095 ; encoding: [0xff,0x0f,0x7c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[2:5] offset:4095 // GFX90A: flat_store_dwordx4 v[254:255], a[2:5] offset:4095 ; encoding: [0xff,0x0f,0x7c,0xdc,0xfe,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[254:255], a[2:5] offset:4095 // GFX90A: flat_store_dwordx4 v[2:3], a[252:255] offset:4095 ; encoding: [0xff,0x0f,0x7c,0xdc,0x02,0xfc,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[252:255] offset:4095 // GFX90A: flat_store_dwordx4 v[2:3], a[2:5] ; encoding: [0x00,0x00,0x7c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[2:5] // GFX90A: flat_store_dwordx4 v[2:3], a[2:5] ; encoding: [0x00,0x00,0x7c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[2:5] // GFX90A: flat_store_dwordx4 v[2:3], a[2:5] offset:7 ; encoding: [0x07,0x00,0x7c,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[2:5] offset:7 // GFX90A: flat_store_dwordx4 v[2:3], a[2:5] offset:4095 glc ; encoding: [0xff,0x0f,0x7d,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[2:5] offset:4095 glc // GFX90A: flat_store_dwordx4 v[2:3], a[2:5] offset:4095 slc ; encoding: [0xff,0x0f,0x7e,0xdc,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_store_dwordx4 v[2:3], a[2:5] offset:4095 slc // GFX90A: flat_load_ubyte_d16 a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x80,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[2:3] offset:4095 // GFX90A: flat_load_ubyte_d16 a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x80,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a255, v[2:3] offset:4095 // GFX90A: flat_load_ubyte_d16 a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x80,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[254:255] offset:4095 // GFX90A: flat_load_ubyte_d16 a5, v[2:3] ; encoding: [0x00,0x00,0x80,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[2:3] // GFX90A: flat_load_ubyte_d16 a5, v[2:3] ; encoding: [0x00,0x00,0x80,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[2:3] // GFX90A: flat_load_ubyte_d16 a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x80,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[2:3] offset:7 // GFX90A: flat_load_ubyte_d16 a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x81,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[2:3] offset:4095 glc // GFX90A: flat_load_ubyte_d16 a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x82,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16 a5, v[2:3] offset:4095 slc // GFX90A: flat_load_ubyte_d16_hi a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x84,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[2:3] offset:4095 // GFX90A: flat_load_ubyte_d16_hi a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x84,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a255, v[2:3] offset:4095 // GFX90A: flat_load_ubyte_d16_hi a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x84,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[254:255] offset:4095 // GFX90A: flat_load_ubyte_d16_hi a5, v[2:3] ; encoding: [0x00,0x00,0x84,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[2:3] // GFX90A: flat_load_ubyte_d16_hi a5, v[2:3] ; encoding: [0x00,0x00,0x84,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[2:3] // GFX90A: flat_load_ubyte_d16_hi a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x84,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[2:3] offset:7 // GFX90A: flat_load_ubyte_d16_hi a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x85,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[2:3] offset:4095 glc // GFX90A: flat_load_ubyte_d16_hi a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x86,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_ubyte_d16_hi a5, v[2:3] offset:4095 slc // GFX90A: flat_load_sbyte_d16 a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x88,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[2:3] offset:4095 // GFX90A: flat_load_sbyte_d16 a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x88,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a255, v[2:3] offset:4095 // GFX90A: flat_load_sbyte_d16 a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x88,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[254:255] offset:4095 // GFX90A: flat_load_sbyte_d16 a5, v[2:3] ; encoding: [0x00,0x00,0x88,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[2:3] // GFX90A: flat_load_sbyte_d16 a5, v[2:3] ; encoding: [0x00,0x00,0x88,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[2:3] // GFX90A: flat_load_sbyte_d16 a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x88,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[2:3] offset:7 // GFX90A: flat_load_sbyte_d16 a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x89,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[2:3] offset:4095 glc // GFX90A: flat_load_sbyte_d16 a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x8a,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16 a5, v[2:3] offset:4095 slc // GFX90A: flat_load_sbyte_d16_hi a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x8c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[2:3] offset:4095 // GFX90A: flat_load_sbyte_d16_hi a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x8c,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a255, v[2:3] offset:4095 // GFX90A: flat_load_sbyte_d16_hi a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x8c,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[254:255] offset:4095 // GFX90A: flat_load_sbyte_d16_hi a5, v[2:3] ; encoding: [0x00,0x00,0x8c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[2:3] // GFX90A: flat_load_sbyte_d16_hi a5, v[2:3] ; encoding: [0x00,0x00,0x8c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[2:3] // GFX90A: flat_load_sbyte_d16_hi a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x8c,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[2:3] offset:7 // GFX90A: flat_load_sbyte_d16_hi a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x8d,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[2:3] offset:4095 glc // GFX90A: flat_load_sbyte_d16_hi a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x8e,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_sbyte_d16_hi a5, v[2:3] offset:4095 slc // GFX90A: flat_load_short_d16 a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x90,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[2:3] offset:4095 // GFX90A: flat_load_short_d16 a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x90,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a255, v[2:3] offset:4095 // GFX90A: flat_load_short_d16 a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x90,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[254:255] offset:4095 // GFX90A: flat_load_short_d16 a5, v[2:3] ; encoding: [0x00,0x00,0x90,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[2:3] // GFX90A: flat_load_short_d16 a5, v[2:3] ; encoding: [0x00,0x00,0x90,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[2:3] // GFX90A: flat_load_short_d16 a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x90,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[2:3] offset:7 // GFX90A: flat_load_short_d16 a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x91,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[2:3] offset:4095 glc // GFX90A: flat_load_short_d16 a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x92,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16 a5, v[2:3] offset:4095 slc // GFX90A: flat_load_short_d16_hi a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x94,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[2:3] offset:4095 // GFX90A: flat_load_short_d16_hi a255, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x94,0xdc,0x02,0x00,0x80,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a255, v[2:3] offset:4095 // GFX90A: flat_load_short_d16_hi a5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x94,0xdc,0xfe,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[254:255] offset:4095 // GFX90A: flat_load_short_d16_hi a5, v[2:3] ; encoding: [0x00,0x00,0x94,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[2:3] // GFX90A: flat_load_short_d16_hi a5, v[2:3] ; encoding: [0x00,0x00,0x94,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[2:3] // GFX90A: flat_load_short_d16_hi a5, v[2:3] offset:7 ; encoding: [0x07,0x00,0x94,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[2:3] offset:7 // GFX90A: flat_load_short_d16_hi a5, v[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x95,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[2:3] offset:4095 glc // GFX90A: flat_load_short_d16_hi a5, v[2:3] offset:4095 slc ; encoding: [0xff,0x0f,0x96,0xdc,0x02,0x00,0x80,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_load_short_d16_hi a5, v[2:3] offset:4095 slc // GFX90A: flat_atomic_swap a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x01,0xdd,0x02,0x02,0x80,0x00] @@ -810,371 +810,371 @@ flat_atomic_inc_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc flat_atomic_dec_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc // GFX90A: flat_atomic_swap v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x00,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_swap v[2:3], a2 offset:4095 // GFX90A: flat_atomic_cmpswap v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x04,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_cmpswap v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_add v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x08,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_add v[2:3], a2 offset:4095 // GFX90A: flat_atomic_sub v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_sub v[2:3], a2 offset:4095 // GFX90A: flat_atomic_smin v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x10,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_smin v[2:3], a2 offset:4095 // GFX90A: flat_atomic_umin v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x14,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_umin v[2:3], a2 offset:4095 // GFX90A: flat_atomic_smax v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x18,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_smax v[2:3], a2 offset:4095 // GFX90A: flat_atomic_umax v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_umax v[2:3], a2 offset:4095 // GFX90A: flat_atomic_and v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x20,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_and v[2:3], a2 offset:4095 // GFX90A: flat_atomic_or v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x24,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_or v[2:3], a2 offset:4095 // GFX90A: flat_atomic_xor v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x28,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_xor v[2:3], a2 offset:4095 // GFX90A: flat_atomic_inc v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_inc v[2:3], a2 offset:4095 // GFX90A: flat_atomic_dec v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x30,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_dec v[2:3], a2 offset:4095 // GFX90A: flat_atomic_swap_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x80,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_swap_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_cmpswap_x2 v[2:3], a[2:5] offset:4095 ; encoding: [0xff,0x0f,0x84,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_cmpswap_x2 v[2:3], a[2:5] offset:4095 // GFX90A: flat_atomic_add_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x88,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_add_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_sub_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x8c,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_sub_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_smin_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x90,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_smin_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_umin_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x94,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_umin_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_smax_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x98,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_smax_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_umax_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0x9c,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_umax_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_and_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0xa0,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_and_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_or_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0xa4,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_or_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_xor_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0xa8,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_xor_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_inc_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0xac,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_inc_x2 v[2:3], a[2:3] offset:4095 // GFX90A: flat_atomic_dec_x2 v[2:3], a[2:3] offset:4095 ; encoding: [0xff,0x0f,0xb0,0xdd,0x02,0x02,0x80,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction flat_atomic_dec_x2 v[2:3], a[2:3] offset:4095 // GFX90A: global_load_ubyte a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x40,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte a5, v[2:3], off offset:-1 // GFX90A: global_load_ubyte a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x40,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte a255, v[2:3], off offset:-1 // GFX90A: global_load_ubyte a5, v[2:3], off ; encoding: [0x00,0x80,0x40,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte a5, v[2:3], off // GFX90A: global_load_sbyte a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x44,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte a5, v[2:3], off offset:-1 // GFX90A: global_load_sbyte a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x44,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte a255, v[2:3], off offset:-1 // GFX90A: global_load_sbyte a5, v[2:3], off ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte a5, v[2:3], off // GFX90A: global_load_ushort a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x48,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ushort a5, v[2:3], off offset:-1 // GFX90A: global_load_ushort a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x48,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ushort a255, v[2:3], off offset:-1 // GFX90A: global_load_ushort a5, v[2:3], off ; encoding: [0x00,0x80,0x48,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ushort a5, v[2:3], off // GFX90A: global_load_sshort a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x4c,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sshort a5, v[2:3], off offset:-1 // GFX90A: global_load_sshort a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x4c,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sshort a255, v[2:3], off offset:-1 // GFX90A: global_load_sshort a5, v[2:3], off ; encoding: [0x00,0x80,0x4c,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sshort a5, v[2:3], off // GFX90A: global_load_dword a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x50,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dword a5, v[2:3], off offset:-1 // GFX90A: global_load_dword a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x50,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dword a255, v[2:3], off offset:-1 // GFX90A: global_load_dword a5, v[2:3], off ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dword a5, v[2:3], off // GFX90A: global_load_dwordx2 a[6:7], v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x54,0xdc,0x02,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx2 a[6:7], v[2:3], off offset:-1 // GFX90A: global_load_dwordx2 a[254:255], v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x54,0xdc,0x02,0x00,0xff,0xfe] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx2 a[254:255], v[2:3], off offset:-1 // GFX90A: global_load_dwordx2 a[6:7], v[2:3], off ; encoding: [0x00,0x80,0x54,0xdc,0x02,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx2 a[6:7], v[2:3], off // GFX90A: global_load_dwordx3 a[6:8], v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x58,0xdc,0x02,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx3 a[6:8], v[2:3], off offset:-1 // GFX90A: global_load_dwordx3 a[252:254], v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x58,0xdc,0x02,0x00,0xff,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx3 a[252:254], v[2:3], off offset:-1 // GFX90A: global_load_dwordx3 a[6:8], v[2:3], off ; encoding: [0x00,0x80,0x58,0xdc,0x02,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx3 a[6:8], v[2:3], off // GFX90A: global_load_dwordx4 a[6:9], v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x5c,0xdc,0x02,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx4 a[6:9], v[2:3], off offset:-1 // GFX90A: global_load_dwordx4 a[252:255], v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x5c,0xdc,0x02,0x00,0xff,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx4 a[252:255], v[2:3], off offset:-1 // GFX90A: global_load_dwordx4 a[6:9], v[2:3], off ; encoding: [0x00,0x80,0x5c,0xdc,0x02,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx4 a[6:9], v[2:3], off // GFX90A: global_store_byte v[2:3], a2, off offset:-1 ; encoding: [0xff,0x9f,0x60,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_byte v[2:3], a2, off offset:-1 // GFX90A: global_store_byte v[2:3], a255, off offset:-1 ; encoding: [0xff,0x9f,0x60,0xdc,0x02,0xff,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_byte v[2:3], a255, off offset:-1 // GFX90A: global_store_byte v[2:3], a2, off ; encoding: [0x00,0x80,0x60,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_byte v[2:3], a2, off // GFX90A: global_store_byte_d16_hi v[2:3], a2, off offset:-1 ; encoding: [0xff,0x9f,0x64,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_byte_d16_hi v[2:3], a2, off offset:-1 // GFX90A: global_store_byte_d16_hi v[2:3], a255, off offset:-1 ; encoding: [0xff,0x9f,0x64,0xdc,0x02,0xff,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_byte_d16_hi v[2:3], a255, off offset:-1 // GFX90A: global_store_byte_d16_hi v[2:3], a2, off ; encoding: [0x00,0x80,0x64,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_byte_d16_hi v[2:3], a2, off // GFX90A: global_store_short v[2:3], a2, off offset:-1 ; encoding: [0xff,0x9f,0x68,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_short v[2:3], a2, off offset:-1 // GFX90A: global_store_short v[2:3], a255, off offset:-1 ; encoding: [0xff,0x9f,0x68,0xdc,0x02,0xff,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_short v[2:3], a255, off offset:-1 // GFX90A: global_store_short v[2:3], a2, off ; encoding: [0x00,0x80,0x68,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_short v[2:3], a2, off // GFX90A: global_store_short_d16_hi v[2:3], a2, off offset:-1 ; encoding: [0xff,0x9f,0x6c,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_short_d16_hi v[2:3], a2, off offset:-1 // GFX90A: global_store_short_d16_hi v[2:3], a255, off offset:-1 ; encoding: [0xff,0x9f,0x6c,0xdc,0x02,0xff,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_short_d16_hi v[2:3], a255, off offset:-1 // GFX90A: global_store_short_d16_hi v[2:3], a2, off ; encoding: [0x00,0x80,0x6c,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_short_d16_hi v[2:3], a2, off // GFX90A: global_store_dword v[2:3], a2, off offset:-1 ; encoding: [0xff,0x9f,0x70,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dword v[2:3], a2, off offset:-1 // GFX90A: global_store_dword v[2:3], a255, off offset:-1 ; encoding: [0xff,0x9f,0x70,0xdc,0x02,0xff,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dword v[2:3], a255, off offset:-1 // GFX90A: global_store_dword v[2:3], a2, off ; encoding: [0x00,0x80,0x70,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dword v[2:3], a2, off // GFX90A: global_store_dwordx2 v[2:3], a[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x74,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx2 v[2:3], a[2:3], off offset:-1 // GFX90A: global_store_dwordx2 v[2:3], a[254:255], off offset:-1 ; encoding: [0xff,0x9f,0x74,0xdc,0x02,0xfe,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx2 v[2:3], a[254:255], off offset:-1 // GFX90A: global_store_dwordx2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx2 v[2:3], a[2:3], off // GFX90A: global_store_dwordx3 v[2:3], a[2:4], off offset:-1 ; encoding: [0xff,0x9f,0x78,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx3 v[2:3], a[2:4], off offset:-1 // GFX90A: global_store_dwordx3 v[2:3], a[252:254], off offset:-1 ; encoding: [0xff,0x9f,0x78,0xdc,0x02,0xfc,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx3 v[2:3], a[252:254], off offset:-1 // GFX90A: global_store_dwordx3 v[2:3], a[2:4], off ; encoding: [0x00,0x80,0x78,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx3 v[2:3], a[2:4], off // GFX90A: global_store_dwordx4 v[2:3], a[2:5], off offset:-1 ; encoding: [0xff,0x9f,0x7c,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx4 v[2:3], a[2:5], off offset:-1 // GFX90A: global_store_dwordx4 v[2:3], a[252:255], off offset:-1 ; encoding: [0xff,0x9f,0x7c,0xdc,0x02,0xfc,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx4 v[2:3], a[252:255], off offset:-1 // GFX90A: global_store_dwordx4 v[2:3], a[2:5], off ; encoding: [0x00,0x80,0x7c,0xdc,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_store_dwordx4 v[2:3], a[2:5], off // GFX90A: global_load_ubyte_d16 a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x80,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte_d16 a5, v[2:3], off offset:-1 // GFX90A: global_load_ubyte_d16 a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x80,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte_d16 a255, v[2:3], off offset:-1 // GFX90A: global_load_ubyte_d16 a5, v[2:3], off ; encoding: [0x00,0x80,0x80,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte_d16 a5, v[2:3], off // GFX90A: global_load_ubyte_d16_hi a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x84,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte_d16_hi a5, v[2:3], off offset:-1 // GFX90A: global_load_ubyte_d16_hi a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x84,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte_d16_hi a255, v[2:3], off offset:-1 // GFX90A: global_load_ubyte_d16_hi a5, v[2:3], off ; encoding: [0x00,0x80,0x84,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_ubyte_d16_hi a5, v[2:3], off // GFX90A: global_load_sbyte_d16 a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x88,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte_d16 a5, v[2:3], off offset:-1 // GFX90A: global_load_sbyte_d16 a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x88,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte_d16 a255, v[2:3], off offset:-1 // GFX90A: global_load_sbyte_d16 a5, v[2:3], off ; encoding: [0x00,0x80,0x88,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte_d16 a5, v[2:3], off // GFX90A: global_load_sbyte_d16_hi a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x8c,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte_d16_hi a5, v[2:3], off offset:-1 // GFX90A: global_load_sbyte_d16_hi a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x8c,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte_d16_hi a255, v[2:3], off offset:-1 // GFX90A: global_load_sbyte_d16_hi a5, v[2:3], off ; encoding: [0x00,0x80,0x8c,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_sbyte_d16_hi a5, v[2:3], off // GFX90A: global_load_short_d16 a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x90,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_short_d16 a5, v[2:3], off offset:-1 // GFX90A: global_load_short_d16 a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x90,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_short_d16 a255, v[2:3], off offset:-1 // GFX90A: global_load_short_d16 a5, v[2:3], off ; encoding: [0x00,0x80,0x90,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_short_d16 a5, v[2:3], off // GFX90A: global_load_short_d16_hi a5, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x94,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_short_d16_hi a5, v[2:3], off offset:-1 // GFX90A: global_load_short_d16_hi a255, v[2:3], off offset:-1 ; encoding: [0xff,0x9f,0x94,0xdc,0x02,0x00,0xff,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_short_d16_hi a255, v[2:3], off offset:-1 // GFX90A: global_load_short_d16_hi a5, v[2:3], off ; encoding: [0x00,0x80,0x94,0xdc,0x02,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_short_d16_hi a5, v[2:3], off // GFX90A: global_atomic_swap a1, v[2:3], a2, off glc ; encoding: [0x00,0x80,0x01,0xdd,0x02,0x02,0xff,0x01] @@ -1282,5815 +1282,5815 @@ global_atomic_inc_x2 a[2:3], v[2:3], a[2:3], off glc global_atomic_dec_x2 a[2:3], v[2:3], a[2:3], off glc // GFX90A: global_atomic_swap v[2:3], a2, off ; encoding: [0x00,0x80,0x00,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_swap v[2:3], a2, off // GFX90A: global_atomic_cmpswap v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x04,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_cmpswap v[2:3], a[2:3], off // GFX90A: global_atomic_add v[2:3], a2, off ; encoding: [0x00,0x80,0x08,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_add v[2:3], a2, off // GFX90A: global_atomic_sub v[2:3], a2, off ; encoding: [0x00,0x80,0x0c,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_sub v[2:3], a2, off // GFX90A: global_atomic_smin v[2:3], a2, off ; encoding: [0x00,0x80,0x10,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_smin v[2:3], a2, off // GFX90A: global_atomic_umin v[2:3], a2, off ; encoding: [0x00,0x80,0x14,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_umin v[2:3], a2, off // GFX90A: global_atomic_smax v[2:3], a2, off ; encoding: [0x00,0x80,0x18,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_smax v[2:3], a2, off // GFX90A: global_atomic_umax v[2:3], a2, off ; encoding: [0x00,0x80,0x1c,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_umax v[2:3], a2, off // GFX90A: global_atomic_and v[2:3], a2, off ; encoding: [0x00,0x80,0x20,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_and v[2:3], a2, off // GFX90A: global_atomic_or v[2:3], a2, off ; encoding: [0x00,0x80,0x24,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_or v[2:3], a2, off // GFX90A: global_atomic_xor v[2:3], a2, off ; encoding: [0x00,0x80,0x28,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_xor v[2:3], a2, off // GFX90A: global_atomic_inc v[2:3], a2, off ; encoding: [0x00,0x80,0x2c,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_inc v[2:3], a2, off // GFX90A: global_atomic_dec v[2:3], a2, off ; encoding: [0x00,0x80,0x30,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_dec v[2:3], a2, off // GFX90A: global_atomic_swap_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x80,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_swap_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_cmpswap_x2 v[2:3], a[2:5], off ; encoding: [0x00,0x80,0x84,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_cmpswap_x2 v[2:3], a[2:5], off // GFX90A: global_atomic_add_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x88,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_add_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_sub_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x8c,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_sub_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_smin_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x90,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_smin_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_umin_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x94,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_umin_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_smax_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x98,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_smax_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_umax_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0x9c,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_umax_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_and_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0xa0,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_and_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_or_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0xa4,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_or_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_xor_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0xa8,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_xor_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_inc_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0xac,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_inc_x2 v[2:3], a[2:3], off // GFX90A: global_atomic_dec_x2 v[2:3], a[2:3], off ; encoding: [0x00,0x80,0xb0,0xdd,0x02,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction global_atomic_dec_x2 v[2:3], a[2:3], off // GFX90A: scratch_load_ubyte a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 offset:-1 // GFX90A: scratch_load_ubyte a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a255, off, s2 offset:-1 // GFX90A: scratch_load_ubyte a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s101 offset:-1 // GFX90A: scratch_load_ubyte a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_ubyte a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_ubyte a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_ubyte a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_ubyte a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x40,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, v0, off offset:-1 // GFX90A: scratch_load_ubyte a5, off, s2 ; encoding: [0x00,0x40,0x40,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 // GFX90A: scratch_load_ubyte a5, off, s2 ; encoding: [0x00,0x40,0x40,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 // GFX90A: scratch_load_ubyte a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x40,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 offset:4095 // GFX90A: scratch_load_ubyte a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x40,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 offset:-4096 // GFX90A: scratch_load_ubyte a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x41,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 offset:-1 glc // GFX90A: scratch_load_ubyte a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x42,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte a5, off, s2 offset:-1 slc // GFX90A: scratch_load_sbyte a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 offset:-1 // GFX90A: scratch_load_sbyte a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a255, off, s2 offset:-1 // GFX90A: scratch_load_sbyte a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s101 offset:-1 // GFX90A: scratch_load_sbyte a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_sbyte a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_sbyte a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_sbyte a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_sbyte a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x44,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, v0, off offset:-1 // GFX90A: scratch_load_sbyte a5, off, s2 ; encoding: [0x00,0x40,0x44,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 // GFX90A: scratch_load_sbyte a5, off, s2 ; encoding: [0x00,0x40,0x44,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 // GFX90A: scratch_load_sbyte a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x44,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 offset:4095 // GFX90A: scratch_load_sbyte a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x44,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 offset:-4096 // GFX90A: scratch_load_sbyte a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x45,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 offset:-1 glc // GFX90A: scratch_load_sbyte a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x46,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte a5, off, s2 offset:-1 slc // GFX90A: scratch_load_ushort a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 offset:-1 // GFX90A: scratch_load_ushort a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a255, off, s2 offset:-1 // GFX90A: scratch_load_ushort a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s101 offset:-1 // GFX90A: scratch_load_ushort a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_ushort a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_ushort a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_ushort a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_ushort a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x48,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, v0, off offset:-1 // GFX90A: scratch_load_ushort a5, off, s2 ; encoding: [0x00,0x40,0x48,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 // GFX90A: scratch_load_ushort a5, off, s2 ; encoding: [0x00,0x40,0x48,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 // GFX90A: scratch_load_ushort a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x48,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 offset:4095 // GFX90A: scratch_load_ushort a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x48,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 offset:-4096 // GFX90A: scratch_load_ushort a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x49,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 offset:-1 glc // GFX90A: scratch_load_ushort a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x4a,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ushort a5, off, s2 offset:-1 slc // GFX90A: scratch_load_sshort a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 offset:-1 // GFX90A: scratch_load_sshort a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a255, off, s2 offset:-1 // GFX90A: scratch_load_sshort a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s101 offset:-1 // GFX90A: scratch_load_sshort a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_sshort a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_sshort a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_sshort a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_sshort a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, v0, off offset:-1 // GFX90A: scratch_load_sshort a5, off, s2 ; encoding: [0x00,0x40,0x4c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 // GFX90A: scratch_load_sshort a5, off, s2 ; encoding: [0x00,0x40,0x4c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 // GFX90A: scratch_load_sshort a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x4c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 offset:4095 // GFX90A: scratch_load_sshort a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x4c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 offset:-4096 // GFX90A: scratch_load_sshort a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x4d,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 offset:-1 glc // GFX90A: scratch_load_sshort a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x4e,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sshort a5, off, s2 offset:-1 slc // GFX90A: scratch_load_dword a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 offset:-1 // GFX90A: scratch_load_dword a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a255, off, s2 offset:-1 // GFX90A: scratch_load_dword a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s101 offset:-1 // GFX90A: scratch_load_dword a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_dword a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_dword a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_dword a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_dword a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, v0, off offset:-1 // GFX90A: scratch_load_dword a5, off, s2 ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 // GFX90A: scratch_load_dword a5, off, s2 ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 // GFX90A: scratch_load_dword a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x50,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 offset:4095 // GFX90A: scratch_load_dword a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x50,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 offset:-4096 // GFX90A: scratch_load_dword a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x51,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 offset:-1 glc // GFX90A: scratch_load_dword a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x52,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dword a5, off, s2 offset:-1 slc // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 offset:-1 // GFX90A: scratch_load_dwordx2 a[254:255], off, s2 offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x82,0xfe] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[254:255], off, s2 offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], off, s101 offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0xe5,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s101 offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0xe6,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0xe7,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0xea,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, vcc_lo offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0xeb,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, vcc_hi offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], v0, off offset:-1 ; encoding: [0xff,0x5f,0x54,0xdc,0x00,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], v0, off offset:-1 // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 ; encoding: [0x00,0x40,0x54,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 ; encoding: [0x00,0x40,0x54,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 offset:4095 ; encoding: [0xff,0x4f,0x54,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 offset:4095 // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 offset:-4096 ; encoding: [0x00,0x50,0x54,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 offset:-4096 // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x55,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 offset:-1 glc // GFX90A: scratch_load_dwordx2 a[6:7], off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x56,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx2 a[6:7], off, s2 offset:-1 slc // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 offset:-1 // GFX90A: scratch_load_dwordx3 a[252:254], off, s2 offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x82,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[252:254], off, s2 offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], off, s101 offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0xe5,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s101 offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0xe6,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0xe7,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0xea,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, vcc_lo offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0xeb,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, vcc_hi offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], v0, off offset:-1 ; encoding: [0xff,0x5f,0x58,0xdc,0x00,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], v0, off offset:-1 // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 ; encoding: [0x00,0x40,0x58,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 ; encoding: [0x00,0x40,0x58,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 offset:4095 ; encoding: [0xff,0x4f,0x58,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 offset:4095 // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 offset:-4096 ; encoding: [0x00,0x50,0x58,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 offset:-4096 // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x59,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 offset:-1 glc // GFX90A: scratch_load_dwordx3 a[6:8], off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x5a,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx3 a[6:8], off, s2 offset:-1 slc // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 offset:-1 // GFX90A: scratch_load_dwordx4 a[252:255], off, s2 offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x82,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[252:255], off, s2 offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], off, s101 offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0xe5,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s101 offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0xe6,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0xe7,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0xea,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, vcc_lo offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0xeb,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, vcc_hi offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], v0, off offset:-1 ; encoding: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0xff,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], v0, off offset:-1 // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 ; encoding: [0x00,0x40,0x5c,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 ; encoding: [0x00,0x40,0x5c,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 offset:4095 ; encoding: [0xff,0x4f,0x5c,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 offset:4095 // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 offset:-4096 ; encoding: [0x00,0x50,0x5c,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 offset:-4096 // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x5d,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 offset:-1 glc // GFX90A: scratch_load_dwordx4 a[6:9], off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x5e,0xdc,0x00,0x00,0x82,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_dwordx4 a[6:9], off, s2 offset:-1 slc // GFX90A: scratch_store_byte off, a2, s3 offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 offset:-1 // GFX90A: scratch_store_byte off, a255, s3 offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0xff,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a255, s3 offset:-1 // GFX90A: scratch_store_byte off, a2, s101 offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s101 offset:-1 // GFX90A: scratch_store_byte off, a2, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, flat_scratch_lo offset:-1 // GFX90A: scratch_store_byte off, a2, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, flat_scratch_hi offset:-1 // GFX90A: scratch_store_byte off, a2, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, vcc_lo offset:-1 // GFX90A: scratch_store_byte off, a2, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, vcc_hi offset:-1 // GFX90A: scratch_store_byte v0, a2, off offset:-1 ; encoding: [0xff,0x5f,0x60,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte v0, a2, off offset:-1 // GFX90A: scratch_store_byte off, a2, s3 ; encoding: [0x00,0x40,0x60,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 // GFX90A: scratch_store_byte off, a2, s3 ; encoding: [0x00,0x40,0x60,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 // GFX90A: scratch_store_byte off, a2, s3 offset:4095 ; encoding: [0xff,0x4f,0x60,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 offset:4095 // GFX90A: scratch_store_byte off, a2, s3 offset:-4096 ; encoding: [0x00,0x50,0x60,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 offset:-4096 // GFX90A: scratch_store_byte off, a2, s3 offset:-1 glc ; encoding: [0xff,0x5f,0x61,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 offset:-1 glc // GFX90A: scratch_store_byte off, a2, s3 offset:-1 slc ; encoding: [0xff,0x5f,0x62,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte off, a2, s3 offset:-1 slc // GFX90A: scratch_store_byte_d16_hi off, a2, s3 offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a255, s3 offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0xff,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a255, s3 offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a2, s101 offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s101 offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a2, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, flat_scratch_lo offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a2, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, flat_scratch_hi offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a2, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, vcc_lo offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a2, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, vcc_hi offset:-1 // GFX90A: scratch_store_byte_d16_hi v0, a2, off offset:-1 ; encoding: [0xff,0x5f,0x64,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi v0, a2, off offset:-1 // GFX90A: scratch_store_byte_d16_hi off, a2, s3 ; encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 // GFX90A: scratch_store_byte_d16_hi off, a2, s3 ; encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 // GFX90A: scratch_store_byte_d16_hi off, a2, s3 offset:4095 ; encoding: [0xff,0x4f,0x64,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 offset:4095 // GFX90A: scratch_store_byte_d16_hi off, a2, s3 offset:-4096 ; encoding: [0x00,0x50,0x64,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 offset:-4096 // GFX90A: scratch_store_byte_d16_hi off, a2, s3 offset:-1 glc ; encoding: [0xff,0x5f,0x65,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 offset:-1 glc // GFX90A: scratch_store_byte_d16_hi off, a2, s3 offset:-1 slc ; encoding: [0xff,0x5f,0x66,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_byte_d16_hi off, a2, s3 offset:-1 slc // GFX90A: scratch_store_short off, a2, s3 offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 offset:-1 // GFX90A: scratch_store_short off, a255, s3 offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0xff,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a255, s3 offset:-1 // GFX90A: scratch_store_short off, a2, s101 offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s101 offset:-1 // GFX90A: scratch_store_short off, a2, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, flat_scratch_lo offset:-1 // GFX90A: scratch_store_short off, a2, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, flat_scratch_hi offset:-1 // GFX90A: scratch_store_short off, a2, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, vcc_lo offset:-1 // GFX90A: scratch_store_short off, a2, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, vcc_hi offset:-1 // GFX90A: scratch_store_short v0, a2, off offset:-1 ; encoding: [0xff,0x5f,0x68,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short v0, a2, off offset:-1 // GFX90A: scratch_store_short off, a2, s3 ; encoding: [0x00,0x40,0x68,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 // GFX90A: scratch_store_short off, a2, s3 ; encoding: [0x00,0x40,0x68,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 // GFX90A: scratch_store_short off, a2, s3 offset:4095 ; encoding: [0xff,0x4f,0x68,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 offset:4095 // GFX90A: scratch_store_short off, a2, s3 offset:-4096 ; encoding: [0x00,0x50,0x68,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 offset:-4096 // GFX90A: scratch_store_short off, a2, s3 offset:-1 glc ; encoding: [0xff,0x5f,0x69,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 offset:-1 glc // GFX90A: scratch_store_short off, a2, s3 offset:-1 slc ; encoding: [0xff,0x5f,0x6a,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short off, a2, s3 offset:-1 slc // GFX90A: scratch_store_short_d16_hi off, a2, s3 offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 offset:-1 // GFX90A: scratch_store_short_d16_hi off, a255, s3 offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0xff,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a255, s3 offset:-1 // GFX90A: scratch_store_short_d16_hi off, a2, s101 offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s101 offset:-1 // GFX90A: scratch_store_short_d16_hi off, a2, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, flat_scratch_lo offset:-1 // GFX90A: scratch_store_short_d16_hi off, a2, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, flat_scratch_hi offset:-1 // GFX90A: scratch_store_short_d16_hi off, a2, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, vcc_lo offset:-1 // GFX90A: scratch_store_short_d16_hi off, a2, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, vcc_hi offset:-1 // GFX90A: scratch_store_short_d16_hi v0, a2, off offset:-1 ; encoding: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi v0, a2, off offset:-1 // GFX90A: scratch_store_short_d16_hi off, a2, s3 ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 // GFX90A: scratch_store_short_d16_hi off, a2, s3 ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 // GFX90A: scratch_store_short_d16_hi off, a2, s3 offset:4095 ; encoding: [0xff,0x4f,0x6c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 offset:4095 // GFX90A: scratch_store_short_d16_hi off, a2, s3 offset:-4096 ; encoding: [0x00,0x50,0x6c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 offset:-4096 // GFX90A: scratch_store_short_d16_hi off, a2, s3 offset:-1 glc ; encoding: [0xff,0x5f,0x6d,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 offset:-1 glc // GFX90A: scratch_store_short_d16_hi off, a2, s3 offset:-1 slc ; encoding: [0xff,0x5f,0x6e,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_short_d16_hi off, a2, s3 offset:-1 slc // GFX90A: scratch_store_dword off, a2, s3 offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 offset:-1 // GFX90A: scratch_store_dword off, a255, s3 offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0xff,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a255, s3 offset:-1 // GFX90A: scratch_store_dword off, a2, s101 offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s101 offset:-1 // GFX90A: scratch_store_dword off, a2, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, flat_scratch_lo offset:-1 // GFX90A: scratch_store_dword off, a2, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, flat_scratch_hi offset:-1 // GFX90A: scratch_store_dword off, a2, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, vcc_lo offset:-1 // GFX90A: scratch_store_dword off, a2, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, vcc_hi offset:-1 // GFX90A: scratch_store_dword v0, a2, off offset:-1 ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword v0, a2, off offset:-1 // GFX90A: scratch_store_dword off, a2, s3 ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 // GFX90A: scratch_store_dword off, a2, s3 ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 // GFX90A: scratch_store_dword off, a2, s3 offset:4095 ; encoding: [0xff,0x4f,0x70,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 offset:4095 // GFX90A: scratch_store_dword off, a2, s3 offset:-4096 ; encoding: [0x00,0x50,0x70,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 offset:-4096 // GFX90A: scratch_store_dword off, a2, s3 offset:-1 glc ; encoding: [0xff,0x5f,0x71,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 offset:-1 glc // GFX90A: scratch_store_dword off, a2, s3 offset:-1 slc ; encoding: [0xff,0x5f,0x72,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dword off, a2, s3 offset:-1 slc // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 offset:-1 // GFX90A: scratch_store_dwordx2 off, a[254:255], s3 offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0xfe,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[254:255], s3 offset:-1 // GFX90A: scratch_store_dwordx2 off, a[2:3], s101 offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s101 offset:-1 // GFX90A: scratch_store_dwordx2 off, a[2:3], flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], flat_scratch_lo offset:-1 // GFX90A: scratch_store_dwordx2 off, a[2:3], flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], flat_scratch_hi offset:-1 // GFX90A: scratch_store_dwordx2 off, a[2:3], vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], vcc_lo offset:-1 // GFX90A: scratch_store_dwordx2 off, a[2:3], vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], vcc_hi offset:-1 // GFX90A: scratch_store_dwordx2 v0, a[2:3], off offset:-1 ; encoding: [0xff,0x5f,0x74,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 v0, a[2:3], off offset:-1 // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 ; encoding: [0x00,0x40,0x74,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 ; encoding: [0x00,0x40,0x74,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 offset:4095 ; encoding: [0xff,0x4f,0x74,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 offset:4095 // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 offset:-4096 ; encoding: [0x00,0x50,0x74,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 offset:-4096 // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 offset:-1 glc ; encoding: [0xff,0x5f,0x75,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 offset:-1 glc // GFX90A: scratch_store_dwordx2 off, a[2:3], s3 offset:-1 slc ; encoding: [0xff,0x5f,0x76,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx2 off, a[2:3], s3 offset:-1 slc // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 offset:-1 // GFX90A: scratch_store_dwordx3 off, a[252:254], s3 offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0xfc,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[252:254], s3 offset:-1 // GFX90A: scratch_store_dwordx3 off, a[2:4], s101 offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s101 offset:-1 // GFX90A: scratch_store_dwordx3 off, a[2:4], flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], flat_scratch_lo offset:-1 // GFX90A: scratch_store_dwordx3 off, a[2:4], flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], flat_scratch_hi offset:-1 // GFX90A: scratch_store_dwordx3 off, a[2:4], vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], vcc_lo offset:-1 // GFX90A: scratch_store_dwordx3 off, a[2:4], vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], vcc_hi offset:-1 // GFX90A: scratch_store_dwordx3 v0, a[2:4], off offset:-1 ; encoding: [0xff,0x5f,0x78,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 v0, a[2:4], off offset:-1 // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 ; encoding: [0x00,0x40,0x78,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 ; encoding: [0x00,0x40,0x78,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 offset:4095 ; encoding: [0xff,0x4f,0x78,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 offset:4095 // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 offset:-4096 ; encoding: [0x00,0x50,0x78,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 offset:-4096 // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 offset:-1 glc ; encoding: [0xff,0x5f,0x79,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 offset:-1 glc // GFX90A: scratch_store_dwordx3 off, a[2:4], s3 offset:-1 slc ; encoding: [0xff,0x5f,0x7a,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx3 off, a[2:4], s3 offset:-1 slc // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 offset:-1 // GFX90A: scratch_store_dwordx4 off, a[252:255], s3 offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0xfc,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[252:255], s3 offset:-1 // GFX90A: scratch_store_dwordx4 off, a[2:5], s101 offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0xe5,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s101 offset:-1 // GFX90A: scratch_store_dwordx4 off, a[2:5], flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0xe6,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], flat_scratch_lo offset:-1 // GFX90A: scratch_store_dwordx4 off, a[2:5], flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0xe7,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], flat_scratch_hi offset:-1 // GFX90A: scratch_store_dwordx4 off, a[2:5], vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0xea,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], vcc_lo offset:-1 // GFX90A: scratch_store_dwordx4 off, a[2:5], vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0xeb,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], vcc_hi offset:-1 // GFX90A: scratch_store_dwordx4 v0, a[2:5], off offset:-1 ; encoding: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0xff,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 v0, a[2:5], off offset:-1 // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 ; encoding: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 ; encoding: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 offset:4095 ; encoding: [0xff,0x4f,0x7c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 offset:4095 // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 offset:-4096 ; encoding: [0x00,0x50,0x7c,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 offset:-4096 // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 offset:-1 glc ; encoding: [0xff,0x5f,0x7d,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 offset:-1 glc // GFX90A: scratch_store_dwordx4 off, a[2:5], s3 offset:-1 slc ; encoding: [0xff,0x5f,0x7e,0xdc,0x00,0x02,0x83,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_store_dwordx4 off, a[2:5], s3 offset:-1 slc // GFX90A: scratch_load_ubyte_d16 a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 offset:-1 // GFX90A: scratch_load_ubyte_d16 a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a255, off, s2 offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s101 offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x80,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, v0, off offset:-1 // GFX90A: scratch_load_ubyte_d16 a5, off, s2 ; encoding: [0x00,0x40,0x80,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 // GFX90A: scratch_load_ubyte_d16 a5, off, s2 ; encoding: [0x00,0x40,0x80,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 // GFX90A: scratch_load_ubyte_d16 a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x80,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 offset:4095 // GFX90A: scratch_load_ubyte_d16 a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x80,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 offset:-4096 // GFX90A: scratch_load_ubyte_d16 a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x81,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 offset:-1 glc // GFX90A: scratch_load_ubyte_d16 a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x82,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16 a5, off, s2 offset:-1 slc // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a255, off, s2 offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s101 offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x84,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, v0, off offset:-1 // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 ; encoding: [0x00,0x40,0x84,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 ; encoding: [0x00,0x40,0x84,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x84,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 offset:4095 // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x84,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 offset:-4096 // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x85,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 offset:-1 glc // GFX90A: scratch_load_ubyte_d16_hi a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x86,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_ubyte_d16_hi a5, off, s2 offset:-1 slc // GFX90A: scratch_load_sbyte_d16 a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 offset:-1 // GFX90A: scratch_load_sbyte_d16 a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a255, off, s2 offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s101 offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x88,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, v0, off offset:-1 // GFX90A: scratch_load_sbyte_d16 a5, off, s2 ; encoding: [0x00,0x40,0x88,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 // GFX90A: scratch_load_sbyte_d16 a5, off, s2 ; encoding: [0x00,0x40,0x88,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 // GFX90A: scratch_load_sbyte_d16 a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x88,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 offset:4095 // GFX90A: scratch_load_sbyte_d16 a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x88,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 offset:-4096 // GFX90A: scratch_load_sbyte_d16 a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x89,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 offset:-1 glc // GFX90A: scratch_load_sbyte_d16 a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x8a,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16 a5, off, s2 offset:-1 slc // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a255, off, s2 offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s101 offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, v0, off offset:-1 // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 ; encoding: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 ; encoding: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x8c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 offset:4095 // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x8c,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 offset:-4096 // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x8d,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 offset:-1 glc // GFX90A: scratch_load_sbyte_d16_hi a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x8e,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_sbyte_d16_hi a5, off, s2 offset:-1 slc // GFX90A: scratch_load_short_d16 a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 offset:-1 // GFX90A: scratch_load_short_d16 a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a255, off, s2 offset:-1 // GFX90A: scratch_load_short_d16 a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s101 offset:-1 // GFX90A: scratch_load_short_d16 a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_short_d16 a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_short_d16 a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_short_d16 a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_short_d16 a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x90,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, v0, off offset:-1 // GFX90A: scratch_load_short_d16 a5, off, s2 ; encoding: [0x00,0x40,0x90,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 // GFX90A: scratch_load_short_d16 a5, off, s2 ; encoding: [0x00,0x40,0x90,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 // GFX90A: scratch_load_short_d16 a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x90,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 offset:4095 // GFX90A: scratch_load_short_d16 a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x90,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 offset:-4096 // GFX90A: scratch_load_short_d16 a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x91,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 offset:-1 glc // GFX90A: scratch_load_short_d16 a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x92,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16 a5, off, s2 offset:-1 slc // GFX90A: scratch_load_short_d16_hi a5, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 offset:-1 // GFX90A: scratch_load_short_d16_hi a255, off, s2 offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x82,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a255, off, s2 offset:-1 // GFX90A: scratch_load_short_d16_hi a5, off, s101 offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0xe5,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s101 offset:-1 // GFX90A: scratch_load_short_d16_hi a5, off, flat_scratch_lo offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0xe6,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, flat_scratch_lo offset:-1 // GFX90A: scratch_load_short_d16_hi a5, off, flat_scratch_hi offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0xe7,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, flat_scratch_hi offset:-1 // GFX90A: scratch_load_short_d16_hi a5, off, vcc_lo offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0xea,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, vcc_lo offset:-1 // GFX90A: scratch_load_short_d16_hi a5, off, vcc_hi offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0xeb,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, vcc_hi offset:-1 // GFX90A: scratch_load_short_d16_hi a5, v0, off offset:-1 ; encoding: [0xff,0x5f,0x94,0xdc,0x00,0x00,0xff,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, v0, off offset:-1 // GFX90A: scratch_load_short_d16_hi a5, off, s2 ; encoding: [0x00,0x40,0x94,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 // GFX90A: scratch_load_short_d16_hi a5, off, s2 ; encoding: [0x00,0x40,0x94,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 // GFX90A: scratch_load_short_d16_hi a5, off, s2 offset:4095 ; encoding: [0xff,0x4f,0x94,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 offset:4095 // GFX90A: scratch_load_short_d16_hi a5, off, s2 offset:-4096 ; encoding: [0x00,0x50,0x94,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 offset:-4096 // GFX90A: scratch_load_short_d16_hi a5, off, s2 offset:-1 glc ; encoding: [0xff,0x5f,0x95,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 offset:-1 glc // GFX90A: scratch_load_short_d16_hi a5, off, s2 offset:-1 slc ; encoding: [0xff,0x5f,0x96,0xdc,0x00,0x00,0x82,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction scratch_load_short_d16_hi a5, off, s2 offset:-1 slc // GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_x a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_x a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_x a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_x a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s3 // GFX90A: buffer_load_format_x a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s3 // GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_x a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_xy a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_xy a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_xy a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x04,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x06,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_xyz a[252:254], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0xfc,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[252:254], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s3 ; encoding: [0x00,0x00,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s3 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s3 ; encoding: [0x00,0x00,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s3 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x08,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x0a,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyz a[6:8], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_xyzw a[252:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[252:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s3 ; encoding: [0x00,0x00,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s3 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s3 ; encoding: [0x00,0x00,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s3 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x0c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x0e,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_xyzw a[6:9], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_store_format_x a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_x a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_x a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_x a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_x a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s4 // GFX90A: buffer_store_format_x a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s4 // GFX90A: buffer_store_format_x a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_x a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_x a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x12,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_x a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_xy a[254:255], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[254:255], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_xy a[2:3], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_xy a[2:3], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x14,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x16,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xy a[2:3], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_xyz a[252:254], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0xfc,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[252:254], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s4 ; encoding: [0x00,0x00,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s4 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s4 ; encoding: [0x00,0x00,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s4 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x18,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x1a,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyz a[2:4], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_xyzw a[252:255], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[252:255], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s4 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s4 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s4 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s4 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x1c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x1e,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_xyzw a[2:5], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_x a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_d16_x a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_d16_x a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s3 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s3 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_d16_x a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x22,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_x a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_xy a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_d16_xy a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_d16_xy a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s3 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s3 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x26,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xy a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x28,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x2a,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyz a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x2c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x2e,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_format_d16_xyzw a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_x a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_d16_x a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_d16_x a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s4 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s4 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x30,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_d16_x a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x32,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_x a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_xy a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_d16_xy a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_d16_xy a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s4 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s4 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x34,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x36,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xy a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[254:255], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0xfe,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[254:255], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x38,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x38,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x3a,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyz a[2:3], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[254:255], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0xfe,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[254:255], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x3c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x3e,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_format_d16_xyzw a[2:3], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ubyte a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_ubyte a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_ubyte a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s3 // GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s3 // GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x40,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sbyte a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_sbyte a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_sbyte a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s3 // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s3 // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x44,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ushort a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_ushort a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_ushort a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s3 // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s3 // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x48,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ushort a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sshort a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_sshort a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_sshort a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s3 // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s3 // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x4c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sshort a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dword a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dword a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_dword a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_dword a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_dword a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_dword a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s3 // GFX90A: buffer_load_dword a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s3 // GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dword a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dwordx2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x54,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x56,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dwordx3 a[252:254], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0xfc,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[252:254], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x58,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s3 ; encoding: [0x00,0x00,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s3 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s3 ; encoding: [0x00,0x00,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s3 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x58,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x5a,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx3 a[6:8], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dwordx4 a[252:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0xfc,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[252:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x5c,0xe0,0x00,0x06,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s3 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s3 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s3 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s3 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:7 // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x5c,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x5e,0xe0,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_dwordx4 a[6:9], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_store_byte a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_byte a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_byte a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_byte a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_byte a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_byte a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_byte a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s4 // GFX90A: buffer_store_byte a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s4 // GFX90A: buffer_store_byte a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_byte a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_byte a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x62,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_byte_d16_hi a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s4 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s4 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x64,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x66,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_byte_d16_hi a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_short a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_short a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_short a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_short a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_short a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_short a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_short a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s4 // GFX90A: buffer_store_short a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s4 // GFX90A: buffer_store_short a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_short a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_short a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x6a,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_short_d16_hi a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_short_d16_hi a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_short_d16_hi a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s4 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s4 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x6c,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x6e,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_short_d16_hi a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_dword a1, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dword a255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a255, off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dword a1, off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_dword a1, off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_dword a1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_dword a1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_dword a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s4 // GFX90A: buffer_store_dword a1, off, s[12:15], s4 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s4 // GFX90A: buffer_store_dword a1, off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s4 offset:7 // GFX90A: buffer_store_dword a1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_dword a1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x72,0xe0,0x00,0x01,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dword a1, off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dwordx2 a[254:255], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[254:255], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x74,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s4 ; encoding: [0x00,0x00,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s4 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x74,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x76,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx2 a[2:3], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dwordx3 a[252:254], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0xfc,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[252:254], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x78,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s4 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s4 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s4 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s4 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x78,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x7a,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx3 a[2:4], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dwordx4 a[252:255], off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0xfc,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[252:255], off, s[12:15], s4 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[16:19], s4 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x84,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[16:19], s4 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[96:99], s4 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x98,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[96:99], s4 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s101 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s101 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], m0 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], m0 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], 0 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], 0 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], -1 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], -1 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], 0.5 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x02,0x83,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], -4.0 offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], v0, s[12:15], s4 idxen offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], v0, s[12:15], s4 offen offset:4095 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s4 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s4 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s4 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s4 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:7 ; encoding: [0x07,0x00,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:7 // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x7c,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:4095 glc // GFX90A: buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x7e,0xe0,0x00,0x02,0x83,0x04] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_store_dwordx4 a[2:5], off, s[12:15], s4 offset:4095 slc // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16 a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s3 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s3 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x80,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x82,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16 a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x84,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x86,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_ubyte_d16_hi a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16 a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s3 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s3 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x88,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x8a,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16 a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x8c,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x8e,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_sbyte_d16_hi a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_short_d16 a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_short_d16 a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_short_d16 a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s3 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s3 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x90,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_short_d16 a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x92,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16 a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_short_d16_hi a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], 0.5 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0xf0] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], 0.5 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x82,0xf7] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], -4.0 offset:4095 // GFX90A: buffer_load_short_d16_hi a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_load_short_d16_hi a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s3 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s3 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x94,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x96,0xe0,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_load_short_d16_hi a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_swap a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_swap a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_swap a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_swap a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_swap a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s3 // GFX90A: buffer_atomic_swap a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s3 // GFX90A: buffer_atomic_swap a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_swap a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x00,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_swap a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x02,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x04,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x06,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_add a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_add a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_add a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_add a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_add a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_add a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_add a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_add a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_add a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_add a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_add a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s3 // GFX90A: buffer_atomic_add a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s3 // GFX90A: buffer_atomic_add a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_add a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_add a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x0a,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_sub a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_sub a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_sub a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_sub a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_sub a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s3 // GFX90A: buffer_atomic_sub a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s3 // GFX90A: buffer_atomic_sub a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_sub a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x0c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_sub a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x0e,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_smin a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smin a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_smin a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_smin a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_smin a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s3 // GFX90A: buffer_atomic_smin a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s3 // GFX90A: buffer_atomic_smin a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_smin a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x10,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_smin a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x12,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_umin a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umin a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_umin a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_umin a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_umin a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s3 // GFX90A: buffer_atomic_umin a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s3 // GFX90A: buffer_atomic_umin a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_umin a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x14,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_umin a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x16,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_smax a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smax a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_smax a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_smax a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_smax a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s3 // GFX90A: buffer_atomic_smax a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s3 // GFX90A: buffer_atomic_smax a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_smax a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x18,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_smax a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x1a,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_umax a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umax a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_umax a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_umax a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_umax a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s3 // GFX90A: buffer_atomic_umax a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s3 // GFX90A: buffer_atomic_umax a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_umax a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x1c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_umax a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x1e,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_and a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_and a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_and a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_and a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_and a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_and a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_and a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_and a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_and a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_and a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_and a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s3 // GFX90A: buffer_atomic_and a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s3 // GFX90A: buffer_atomic_and a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_and a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x20,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_and a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x22,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_or a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_or a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_or a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_or a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_or a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_or a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_or a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_or a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_or a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_or a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_or a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s3 // GFX90A: buffer_atomic_or a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s3 // GFX90A: buffer_atomic_or a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_or a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x24,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_or a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x26,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_xor a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_xor a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_xor a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_xor a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_xor a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s3 // GFX90A: buffer_atomic_xor a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s3 // GFX90A: buffer_atomic_xor a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_xor a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x28,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_xor a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x2a,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_inc a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_inc a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_inc a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_inc a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_inc a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s3 // GFX90A: buffer_atomic_inc a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s3 // GFX90A: buffer_atomic_inc a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_inc a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x2c,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_inc a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x2e,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_dec a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_dec a255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0xff,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a255, off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_dec a5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_dec a5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_dec a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s3 // GFX90A: buffer_atomic_dec a5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s3 // GFX90A: buffer_atomic_dec a5, off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_dec a5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x30,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_dec a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x32,0xe1,0x00,0x05,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec a5, off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x80,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x80,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x82,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_swap_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[252:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0xfc,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[252:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x84,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 ; encoding: [0x00,0x00,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 ; encoding: [0x00,0x00,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x84,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x86,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_cmpswap_x2 a[6:9], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_add_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x88,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x88,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x8a,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_add_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x8c,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x8c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x8e,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_sub_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x90,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x90,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x92,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smin_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x94,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x94,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x96,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umin_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x98,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x9a,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_smax_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x9e,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_umax_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_and_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0xa0,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0xa0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0xa2,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_and_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_or_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0xa4,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0xa4,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0xa6,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_or_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0xa8,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0xa8,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0xaa,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_xor_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0xac,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0xac,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0xae,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_inc_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[254:255], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0xfe,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[254:255], off, s[8:11], s3 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x83,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[12:15], s3 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[96:99], s3 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x98,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[96:99], s3 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s101 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x82,0x65] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s101 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], m0 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x82,0x7c] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], m0 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], 0 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x82,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], 0 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], -1 offset:4095 ; encoding: [0xff,0x0f,0xb0,0xe1,0x00,0x06,0x82,0xc1] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], -1 offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], v0, s[8:11], s3 idxen offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], v0, s[8:11], s3 offen offset:4095 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 ; encoding: [0x00,0x00,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:7 ; encoding: [0x07,0x00,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:7 // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0xb0,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:4095 glc // GFX90A: buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0xb2,0xe1,0x00,0x06,0x82,0x03] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction buffer_atomic_dec_x2 a[6:7], off, s[8:11], s3 offset:4095 slc // GFX90A: tbuffer_load_format_x a1, off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x00,0x78,0xe9,0x00,0x01,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_load_format_x a1, off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_load_format_xy a[2:3], off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x78,0xe9,0x00,0x02,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_load_format_xy a[2:3], off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_load_format_xyz a[2:4], off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x00,0x79,0xe9,0x00,0x02,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_load_format_xyz a[2:4], off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_load_format_xyzw a[2:5], off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x79,0xe9,0x00,0x02,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_load_format_xyzw a[2:5], off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_store_format_x a1, off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x00,0x7a,0xe9,0x00,0x01,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_x a1, off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_store_format_xy a[2:3], off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x7a,0xe9,0x00,0x02,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_xy a[2:3], off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_store_format_xyzw a[2:5], off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x7b,0xe9,0x00,0x02,0x81,0x01] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_xyzw a[2:5], off, s[4:7], dfmt:15, nfmt:2, s1 // GFX90A: tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], ttmp1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x7b,0xe9,0x00,0x02,0x9c,0x6d] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], dfmt:15, nfmt:2, ttmp1 // GFX90A: tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], ttmp1 format:[BUF_DATA_FORMAT_RESERVED_15] ; encoding: [0x00,0x80,0x7b,0xe8,0x00,0x02,0x9c,0x6d] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], dfmt:15, nfmt:0, ttmp1 // GFX90A: tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], ttmp1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x03,0xe9,0x00,0x02,0x9c,0x6d] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], dfmt:0, nfmt:2, ttmp1 // GFX90A: tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], ttmp1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x80,0x7b,0xe9,0x00,0x02,0x9c,0x6d] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction tbuffer_store_format_xyzw a[2:5], off, ttmp[4:7], dfmt:15, nfmt:2, ttmp1 // GFX90A: ds_add_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x00,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u32 v1, a2 offset:65535 // GFX90A: ds_add_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x00,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u32 v255, a2 offset:65535 // GFX90A: ds_add_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x00,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u32 v1, a255 offset:65535 // GFX90A: ds_add_u32 v1, a2 ; encoding: [0x00,0x00,0x00,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u32 v1, a2 // GFX90A: ds_add_u32 v1, a2 ; encoding: [0x00,0x00,0x00,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u32 v1, a2 // GFX90A: ds_add_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x00,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u32 v1, a2 offset:4 // GFX90A: ds_sub_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x02,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u32 v1, a2 offset:65535 // GFX90A: ds_sub_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x02,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u32 v255, a2 offset:65535 // GFX90A: ds_sub_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x02,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u32 v1, a255 offset:65535 // GFX90A: ds_sub_u32 v1, a2 ; encoding: [0x00,0x00,0x02,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u32 v1, a2 // GFX90A: ds_sub_u32 v1, a2 ; encoding: [0x00,0x00,0x02,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u32 v1, a2 // GFX90A: ds_sub_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x02,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u32 v1, a2 offset:4 // GFX90A: ds_rsub_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x04,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u32 v1, a2 offset:65535 // GFX90A: ds_rsub_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x04,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u32 v255, a2 offset:65535 // GFX90A: ds_rsub_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x04,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u32 v1, a255 offset:65535 // GFX90A: ds_rsub_u32 v1, a2 ; encoding: [0x00,0x00,0x04,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u32 v1, a2 // GFX90A: ds_rsub_u32 v1, a2 ; encoding: [0x00,0x00,0x04,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u32 v1, a2 // GFX90A: ds_rsub_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x04,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u32 v1, a2 offset:4 // GFX90A: ds_inc_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x06,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u32 v1, a2 offset:65535 // GFX90A: ds_inc_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x06,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u32 v255, a2 offset:65535 // GFX90A: ds_inc_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x06,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u32 v1, a255 offset:65535 // GFX90A: ds_inc_u32 v1, a2 ; encoding: [0x00,0x00,0x06,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u32 v1, a2 // GFX90A: ds_inc_u32 v1, a2 ; encoding: [0x00,0x00,0x06,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u32 v1, a2 // GFX90A: ds_inc_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x06,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u32 v1, a2 offset:4 // GFX90A: ds_dec_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x08,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u32 v1, a2 offset:65535 // GFX90A: ds_dec_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x08,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u32 v255, a2 offset:65535 // GFX90A: ds_dec_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x08,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u32 v1, a255 offset:65535 // GFX90A: ds_dec_u32 v1, a2 ; encoding: [0x00,0x00,0x08,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u32 v1, a2 // GFX90A: ds_dec_u32 v1, a2 ; encoding: [0x00,0x00,0x08,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u32 v1, a2 // GFX90A: ds_dec_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x08,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u32 v1, a2 offset:4 // GFX90A: ds_min_i32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x0a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i32 v1, a2 offset:65535 // GFX90A: ds_min_i32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x0a,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i32 v255, a2 offset:65535 // GFX90A: ds_min_i32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x0a,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i32 v1, a255 offset:65535 // GFX90A: ds_min_i32 v1, a2 ; encoding: [0x00,0x00,0x0a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i32 v1, a2 // GFX90A: ds_min_i32 v1, a2 ; encoding: [0x00,0x00,0x0a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i32 v1, a2 // GFX90A: ds_min_i32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x0a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i32 v1, a2 offset:4 // GFX90A: ds_max_i32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x0c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i32 v1, a2 offset:65535 // GFX90A: ds_max_i32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x0c,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i32 v255, a2 offset:65535 // GFX90A: ds_max_i32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x0c,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i32 v1, a255 offset:65535 // GFX90A: ds_max_i32 v1, a2 ; encoding: [0x00,0x00,0x0c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i32 v1, a2 // GFX90A: ds_max_i32 v1, a2 ; encoding: [0x00,0x00,0x0c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i32 v1, a2 // GFX90A: ds_max_i32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x0c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i32 v1, a2 offset:4 // GFX90A: ds_min_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x0e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u32 v1, a2 offset:65535 // GFX90A: ds_min_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x0e,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u32 v255, a2 offset:65535 // GFX90A: ds_min_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x0e,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u32 v1, a255 offset:65535 // GFX90A: ds_min_u32 v1, a2 ; encoding: [0x00,0x00,0x0e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u32 v1, a2 // GFX90A: ds_min_u32 v1, a2 ; encoding: [0x00,0x00,0x0e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u32 v1, a2 // GFX90A: ds_min_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x0e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u32 v1, a2 offset:4 // GFX90A: ds_max_u32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x10,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u32 v1, a2 offset:65535 // GFX90A: ds_max_u32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x10,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u32 v255, a2 offset:65535 // GFX90A: ds_max_u32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x10,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u32 v1, a255 offset:65535 // GFX90A: ds_max_u32 v1, a2 ; encoding: [0x00,0x00,0x10,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u32 v1, a2 // GFX90A: ds_max_u32 v1, a2 ; encoding: [0x00,0x00,0x10,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u32 v1, a2 // GFX90A: ds_max_u32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x10,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u32 v1, a2 offset:4 // GFX90A: ds_and_b32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x12,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b32 v1, a2 offset:65535 // GFX90A: ds_and_b32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x12,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b32 v255, a2 offset:65535 // GFX90A: ds_and_b32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x12,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b32 v1, a255 offset:65535 // GFX90A: ds_and_b32 v1, a2 ; encoding: [0x00,0x00,0x12,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b32 v1, a2 // GFX90A: ds_and_b32 v1, a2 ; encoding: [0x00,0x00,0x12,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b32 v1, a2 // GFX90A: ds_and_b32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x12,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b32 v1, a2 offset:4 // GFX90A: ds_or_b32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x14,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b32 v1, a2 offset:65535 // GFX90A: ds_or_b32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x14,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b32 v255, a2 offset:65535 // GFX90A: ds_or_b32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x14,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b32 v1, a255 offset:65535 // GFX90A: ds_or_b32 v1, a2 ; encoding: [0x00,0x00,0x14,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b32 v1, a2 // GFX90A: ds_or_b32 v1, a2 ; encoding: [0x00,0x00,0x14,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b32 v1, a2 // GFX90A: ds_or_b32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x14,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b32 v1, a2 offset:4 // GFX90A: ds_xor_b32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x16,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b32 v1, a2 offset:65535 // GFX90A: ds_xor_b32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x16,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b32 v255, a2 offset:65535 // GFX90A: ds_xor_b32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x16,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b32 v1, a255 offset:65535 // GFX90A: ds_xor_b32 v1, a2 ; encoding: [0x00,0x00,0x16,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b32 v1, a2 // GFX90A: ds_xor_b32 v1, a2 ; encoding: [0x00,0x00,0x16,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b32 v1, a2 // GFX90A: ds_xor_b32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x16,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b32 v1, a2 offset:4 // GFX90A: ds_mskor_b32 v1, a2, a3 offset:65535 ; encoding: [0xff,0xff,0x18,0xda,0x01,0x02,0x03,0x00] @@ -7122,27 +7122,27 @@ ds_mskor_b32 v1, a2, a3 ds_mskor_b32 v1, a2, a3 offset:4 // GFX90A: ds_write_b32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x1a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b32 v1, a2 offset:65535 // GFX90A: ds_write_b32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x1a,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b32 v255, a2 offset:65535 // GFX90A: ds_write_b32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x1a,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b32 v1, a255 offset:65535 // GFX90A: ds_write_b32 v1, a2 ; encoding: [0x00,0x00,0x1a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b32 v1, a2 // GFX90A: ds_write_b32 v1, a2 ; encoding: [0x00,0x00,0x1a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b32 v1, a2 // GFX90A: ds_write_b32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x1a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b32 v1, a2 offset:4 // GFX90A: ds_write2_b32 v1, a2, a3 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x1c,0xda,0x01,0x02,0x03,0x00] @@ -7282,123 +7282,123 @@ ds_cmpst_f32 v1, a2, a3 ds_cmpst_f32 v1, a2, a3 offset:4 // GFX90A: ds_min_f32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x24,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f32 v1, a2 offset:65535 // GFX90A: ds_min_f32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x24,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f32 v255, a2 offset:65535 // GFX90A: ds_min_f32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x24,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f32 v1, a255 offset:65535 // GFX90A: ds_min_f32 v1, a2 ; encoding: [0x00,0x00,0x24,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f32 v1, a2 // GFX90A: ds_min_f32 v1, a2 ; encoding: [0x00,0x00,0x24,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f32 v1, a2 // GFX90A: ds_min_f32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x24,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f32 v1, a2 offset:4 // GFX90A: ds_max_f32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x26,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f32 v1, a2 offset:65535 // GFX90A: ds_max_f32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x26,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f32 v255, a2 offset:65535 // GFX90A: ds_max_f32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x26,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f32 v1, a255 offset:65535 // GFX90A: ds_max_f32 v1, a2 ; encoding: [0x00,0x00,0x26,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f32 v1, a2 // GFX90A: ds_max_f32 v1, a2 ; encoding: [0x00,0x00,0x26,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f32 v1, a2 // GFX90A: ds_max_f32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x26,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f32 v1, a2 offset:4 // GFX90A: ds_add_f32 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x2a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_f32 v1, a2 offset:65535 // GFX90A: ds_add_f32 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x2a,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_f32 v255, a2 offset:65535 // GFX90A: ds_add_f32 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x2a,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_f32 v1, a255 offset:65535 // GFX90A: ds_add_f32 v1, a2 ; encoding: [0x00,0x00,0x2a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_f32 v1, a2 // GFX90A: ds_add_f32 v1, a2 ; encoding: [0x00,0x00,0x2a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_f32 v1, a2 // GFX90A: ds_add_f32 v1, a2 offset:4 ; encoding: [0x04,0x00,0x2a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_f32 v1, a2 offset:4 // GFX90A: ds_write_b8 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x3c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8 v1, a2 offset:65535 // GFX90A: ds_write_b8 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x3c,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8 v255, a2 offset:65535 // GFX90A: ds_write_b8 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x3c,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8 v1, a255 offset:65535 // GFX90A: ds_write_b8 v1, a2 ; encoding: [0x00,0x00,0x3c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8 v1, a2 // GFX90A: ds_write_b8 v1, a2 ; encoding: [0x00,0x00,0x3c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8 v1, a2 // GFX90A: ds_write_b8 v1, a2 offset:4 ; encoding: [0x04,0x00,0x3c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8 v1, a2 offset:4 // GFX90A: ds_write_b16 v1, a2 offset:65535 ; encoding: [0xff,0xff,0x3e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16 v1, a2 offset:65535 // GFX90A: ds_write_b16 v255, a2 offset:65535 ; encoding: [0xff,0xff,0x3e,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16 v255, a2 offset:65535 // GFX90A: ds_write_b16 v1, a255 offset:65535 ; encoding: [0xff,0xff,0x3e,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16 v1, a255 offset:65535 // GFX90A: ds_write_b16 v1, a2 ; encoding: [0x00,0x00,0x3e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16 v1, a2 // GFX90A: ds_write_b16 v1, a2 ; encoding: [0x00,0x00,0x3e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16 v1, a2 // GFX90A: ds_write_b16 v1, a2 offset:4 ; encoding: [0x04,0x00,0x3e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16 v1, a2 offset:4 // GFX90A: ds_add_rtn_u32 a5, v1, a2 offset:65535 ; encoding: [0xff,0xff,0x40,0xda,0x01,0x02,0x00,0x05] @@ -8066,219 +8066,219 @@ ds_add_rtn_f32 a5, v1, a2 ds_add_rtn_f32 a5, v1, a2 offset:4 // GFX90A: ds_read_b32 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x6c,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b32 a5, v1 offset:65535 // GFX90A: ds_read_b32 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x6c,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b32 a255, v1 offset:65535 // GFX90A: ds_read_b32 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x6c,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b32 a5, v255 offset:65535 // GFX90A: ds_read_b32 a5, v1 ; encoding: [0x00,0x00,0x6c,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b32 a5, v1 // GFX90A: ds_read_b32 a5, v1 ; encoding: [0x00,0x00,0x6c,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b32 a5, v1 // GFX90A: ds_read_b32 a5, v1 offset:4 ; encoding: [0x04,0x00,0x6c,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b32 a5, v1 offset:4 // GFX90A: ds_read2_b32 a[6:7], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset0:127 offset1:255 // GFX90A: ds_read2_b32 a[254:255], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x6e,0xda,0x01,0x00,0x00,0xfe] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[254:255], v1 offset0:127 offset1:255 // GFX90A: ds_read2_b32 a[6:7], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x6e,0xda,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v255 offset0:127 offset1:255 // GFX90A: ds_read2_b32 a[6:7], v1 offset1:255 ; encoding: [0x00,0xff,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset1:255 // GFX90A: ds_read2_b32 a[6:7], v1 offset1:255 ; encoding: [0x00,0xff,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset1:255 // GFX90A: ds_read2_b32 a[6:7], v1 offset0:16 offset1:255 ; encoding: [0x10,0xff,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset0:16 offset1:255 // GFX90A: ds_read2_b32 a[6:7], v1 offset0:127 ; encoding: [0x7f,0x00,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset0:127 // GFX90A: ds_read2_b32 a[6:7], v1 offset0:127 ; encoding: [0x7f,0x00,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset0:127 // GFX90A: ds_read2_b32 a[6:7], v1 offset0:127 offset1:1 ; encoding: [0x7f,0x01,0x6e,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b32 a[6:7], v1 offset0:127 offset1:1 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset0:127 offset1:255 // GFX90A: ds_read2st64_b32 a[254:255], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x70,0xda,0x01,0x00,0x00,0xfe] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[254:255], v1 offset0:127 offset1:255 // GFX90A: ds_read2st64_b32 a[6:7], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x70,0xda,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v255 offset0:127 offset1:255 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset1:255 ; encoding: [0x00,0xff,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset1:255 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset1:255 ; encoding: [0x00,0xff,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset1:255 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset0:16 offset1:255 ; encoding: [0x10,0xff,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset0:16 offset1:255 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset0:127 ; encoding: [0x7f,0x00,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset0:127 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset0:127 ; encoding: [0x7f,0x00,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset0:127 // GFX90A: ds_read2st64_b32 a[6:7], v1 offset0:127 offset1:1 ; encoding: [0x7f,0x01,0x70,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b32 a[6:7], v1 offset0:127 offset1:1 // GFX90A: ds_read_i8 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x72,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8 a5, v1 offset:65535 // GFX90A: ds_read_i8 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x72,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8 a255, v1 offset:65535 // GFX90A: ds_read_i8 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x72,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8 a5, v255 offset:65535 // GFX90A: ds_read_i8 a5, v1 ; encoding: [0x00,0x00,0x72,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8 a5, v1 // GFX90A: ds_read_i8 a5, v1 ; encoding: [0x00,0x00,0x72,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8 a5, v1 // GFX90A: ds_read_i8 a5, v1 offset:4 ; encoding: [0x04,0x00,0x72,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8 a5, v1 offset:4 // GFX90A: ds_read_u8 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x74,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8 a5, v1 offset:65535 // GFX90A: ds_read_u8 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x74,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8 a255, v1 offset:65535 // GFX90A: ds_read_u8 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x74,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8 a5, v255 offset:65535 // GFX90A: ds_read_u8 a5, v1 ; encoding: [0x00,0x00,0x74,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8 a5, v1 // GFX90A: ds_read_u8 a5, v1 ; encoding: [0x00,0x00,0x74,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8 a5, v1 // GFX90A: ds_read_u8 a5, v1 offset:4 ; encoding: [0x04,0x00,0x74,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8 a5, v1 offset:4 // GFX90A: ds_read_i16 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x76,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i16 a5, v1 offset:65535 // GFX90A: ds_read_i16 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x76,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i16 a255, v1 offset:65535 // GFX90A: ds_read_i16 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x76,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i16 a5, v255 offset:65535 // GFX90A: ds_read_i16 a5, v1 ; encoding: [0x00,0x00,0x76,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i16 a5, v1 // GFX90A: ds_read_i16 a5, v1 ; encoding: [0x00,0x00,0x76,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i16 a5, v1 // GFX90A: ds_read_i16 a5, v1 offset:4 ; encoding: [0x04,0x00,0x76,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i16 a5, v1 offset:4 // GFX90A: ds_read_u16 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x78,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16 a5, v1 offset:65535 // GFX90A: ds_read_u16 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x78,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16 a255, v1 offset:65535 // GFX90A: ds_read_u16 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x78,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16 a5, v255 offset:65535 // GFX90A: ds_read_u16 a5, v1 ; encoding: [0x00,0x00,0x78,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16 a5, v1 // GFX90A: ds_read_u16 a5, v1 ; encoding: [0x00,0x00,0x78,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16 a5, v1 // GFX90A: ds_read_u16 a5, v1 offset:4 ; encoding: [0x04,0x00,0x78,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16 a5, v1 offset:4 // GFX90A: ds_swizzle_b32 a5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_swizzle_b32 a5, v1 offset:65535 // GFX90A: ds_swizzle_b32 a255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_swizzle_b32 a255, v1 offset:65535 // GFX90A: ds_swizzle_b32 a5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_swizzle_b32 a5, v255 offset:65535 // GFX90A: ds_swizzle_b32 a5, v1 ; encoding: [0x00,0x00,0x7a,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_swizzle_b32 a5, v1 // GFX90A: ds_swizzle_b32 a5, v1 ; encoding: [0x00,0x00,0x7a,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_swizzle_b32 a5, v1 // GFX90A: ds_swizzle_b32 a5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0x7a,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_swizzle_b32 a5, v1 offset:swizzle(BITMASK_PERM,"00p00") // GFX90A: ds_permute_b32 a5, v1, a2 offset:65535 ; encoding: [0xff,0xff,0x7c,0xda,0x01,0x02,0x00,0x05] @@ -8338,291 +8338,291 @@ ds_bpermute_b32 a5, v1, a2 ds_bpermute_b32 a5, v1, a2 offset:4 // GFX90A: ds_add_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x80,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u64 v1, a[2:3] offset:65535 // GFX90A: ds_add_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x80,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u64 v255, a[2:3] offset:65535 // GFX90A: ds_add_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x80,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u64 v1, a[254:255] offset:65535 // GFX90A: ds_add_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u64 v1, a[2:3] // GFX90A: ds_add_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u64 v1, a[2:3] // GFX90A: ds_add_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x80,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_add_u64 v1, a[2:3] offset:4 // GFX90A: ds_sub_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x82,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u64 v1, a[2:3] offset:65535 // GFX90A: ds_sub_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x82,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u64 v255, a[2:3] offset:65535 // GFX90A: ds_sub_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x82,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u64 v1, a[254:255] offset:65535 // GFX90A: ds_sub_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x82,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u64 v1, a[2:3] // GFX90A: ds_sub_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x82,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u64 v1, a[2:3] // GFX90A: ds_sub_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x82,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_sub_u64 v1, a[2:3] offset:4 // GFX90A: ds_rsub_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x84,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u64 v1, a[2:3] offset:65535 // GFX90A: ds_rsub_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x84,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u64 v255, a[2:3] offset:65535 // GFX90A: ds_rsub_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x84,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u64 v1, a[254:255] offset:65535 // GFX90A: ds_rsub_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u64 v1, a[2:3] // GFX90A: ds_rsub_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u64 v1, a[2:3] // GFX90A: ds_rsub_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x84,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_rsub_u64 v1, a[2:3] offset:4 // GFX90A: ds_inc_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x86,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u64 v1, a[2:3] offset:65535 // GFX90A: ds_inc_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x86,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u64 v255, a[2:3] offset:65535 // GFX90A: ds_inc_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x86,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u64 v1, a[254:255] offset:65535 // GFX90A: ds_inc_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x86,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u64 v1, a[2:3] // GFX90A: ds_inc_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x86,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u64 v1, a[2:3] // GFX90A: ds_inc_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x86,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_inc_u64 v1, a[2:3] offset:4 // GFX90A: ds_dec_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x88,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u64 v1, a[2:3] offset:65535 // GFX90A: ds_dec_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x88,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u64 v255, a[2:3] offset:65535 // GFX90A: ds_dec_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x88,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u64 v1, a[254:255] offset:65535 // GFX90A: ds_dec_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x88,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u64 v1, a[2:3] // GFX90A: ds_dec_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x88,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u64 v1, a[2:3] // GFX90A: ds_dec_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x88,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_dec_u64 v1, a[2:3] offset:4 // GFX90A: ds_min_i64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x8a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i64 v1, a[2:3] offset:65535 // GFX90A: ds_min_i64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x8a,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i64 v255, a[2:3] offset:65535 // GFX90A: ds_min_i64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x8a,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i64 v1, a[254:255] offset:65535 // GFX90A: ds_min_i64 v1, a[2:3] ; encoding: [0x00,0x00,0x8a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i64 v1, a[2:3] // GFX90A: ds_min_i64 v1, a[2:3] ; encoding: [0x00,0x00,0x8a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i64 v1, a[2:3] // GFX90A: ds_min_i64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x8a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_i64 v1, a[2:3] offset:4 // GFX90A: ds_max_i64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x8c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i64 v1, a[2:3] offset:65535 // GFX90A: ds_max_i64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x8c,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i64 v255, a[2:3] offset:65535 // GFX90A: ds_max_i64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x8c,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i64 v1, a[254:255] offset:65535 // GFX90A: ds_max_i64 v1, a[2:3] ; encoding: [0x00,0x00,0x8c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i64 v1, a[2:3] // GFX90A: ds_max_i64 v1, a[2:3] ; encoding: [0x00,0x00,0x8c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i64 v1, a[2:3] // GFX90A: ds_max_i64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x8c,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_i64 v1, a[2:3] offset:4 // GFX90A: ds_min_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x8e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u64 v1, a[2:3] offset:65535 // GFX90A: ds_min_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x8e,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u64 v255, a[2:3] offset:65535 // GFX90A: ds_min_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x8e,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u64 v1, a[254:255] offset:65535 // GFX90A: ds_min_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x8e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u64 v1, a[2:3] // GFX90A: ds_min_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x8e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u64 v1, a[2:3] // GFX90A: ds_min_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x8e,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_u64 v1, a[2:3] offset:4 // GFX90A: ds_max_u64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x90,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u64 v1, a[2:3] offset:65535 // GFX90A: ds_max_u64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x90,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u64 v255, a[2:3] offset:65535 // GFX90A: ds_max_u64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x90,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u64 v1, a[254:255] offset:65535 // GFX90A: ds_max_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x90,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u64 v1, a[2:3] // GFX90A: ds_max_u64 v1, a[2:3] ; encoding: [0x00,0x00,0x90,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u64 v1, a[2:3] // GFX90A: ds_max_u64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x90,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_u64 v1, a[2:3] offset:4 // GFX90A: ds_and_b64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x92,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b64 v1, a[2:3] offset:65535 // GFX90A: ds_and_b64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x92,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b64 v255, a[2:3] offset:65535 // GFX90A: ds_and_b64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x92,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b64 v1, a[254:255] offset:65535 // GFX90A: ds_and_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x92,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b64 v1, a[2:3] // GFX90A: ds_and_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x92,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b64 v1, a[2:3] // GFX90A: ds_and_b64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x92,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_and_b64 v1, a[2:3] offset:4 // GFX90A: ds_or_b64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x94,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b64 v1, a[2:3] offset:65535 // GFX90A: ds_or_b64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x94,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b64 v255, a[2:3] offset:65535 // GFX90A: ds_or_b64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x94,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b64 v1, a[254:255] offset:65535 // GFX90A: ds_or_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x94,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b64 v1, a[2:3] // GFX90A: ds_or_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x94,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b64 v1, a[2:3] // GFX90A: ds_or_b64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x94,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_or_b64 v1, a[2:3] offset:4 // GFX90A: ds_xor_b64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x96,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b64 v1, a[2:3] offset:65535 // GFX90A: ds_xor_b64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x96,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b64 v255, a[2:3] offset:65535 // GFX90A: ds_xor_b64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x96,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b64 v1, a[254:255] offset:65535 // GFX90A: ds_xor_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x96,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b64 v1, a[2:3] // GFX90A: ds_xor_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x96,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b64 v1, a[2:3] // GFX90A: ds_xor_b64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x96,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_xor_b64 v1, a[2:3] offset:4 // GFX90A: ds_mskor_b64 v1, a[2:3], a[4:5] offset:65535 ; encoding: [0xff,0xff,0x98,0xda,0x01,0x02,0x04,0x00] @@ -8654,27 +8654,27 @@ ds_mskor_b64 v1, a[2:3], a[4:5] ds_mskor_b64 v1, a[2:3], a[4:5] offset:4 // GFX90A: ds_write_b64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x9a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b64 v1, a[2:3] offset:65535 // GFX90A: ds_write_b64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0x9a,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b64 v255, a[2:3] offset:65535 // GFX90A: ds_write_b64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0x9a,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b64 v1, a[254:255] offset:65535 // GFX90A: ds_write_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x9a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b64 v1, a[2:3] // GFX90A: ds_write_b64 v1, a[2:3] ; encoding: [0x00,0x00,0x9a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b64 v1, a[2:3] // GFX90A: ds_write_b64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0x9a,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b64 v1, a[2:3] offset:4 // GFX90A: ds_write2_b64 v1, a[2:3], a[4:5] offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x9c,0xda,0x01,0x02,0x04,0x00] @@ -8814,243 +8814,243 @@ ds_cmpst_f64 v1, a[2:3], a[4:5] ds_cmpst_f64 v1, a[2:3], a[4:5] offset:4 // GFX90A: ds_min_f64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0xa4,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f64 v1, a[2:3] offset:65535 // GFX90A: ds_min_f64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0xa4,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f64 v255, a[2:3] offset:65535 // GFX90A: ds_min_f64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0xa4,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f64 v1, a[254:255] offset:65535 // GFX90A: ds_min_f64 v1, a[2:3] ; encoding: [0x00,0x00,0xa4,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f64 v1, a[2:3] // GFX90A: ds_min_f64 v1, a[2:3] ; encoding: [0x00,0x00,0xa4,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f64 v1, a[2:3] // GFX90A: ds_min_f64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0xa4,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_min_f64 v1, a[2:3] offset:4 // GFX90A: ds_max_f64 v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0xa6,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f64 v1, a[2:3] offset:65535 // GFX90A: ds_max_f64 v255, a[2:3] offset:65535 ; encoding: [0xff,0xff,0xa6,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f64 v255, a[2:3] offset:65535 // GFX90A: ds_max_f64 v1, a[254:255] offset:65535 ; encoding: [0xff,0xff,0xa6,0xda,0x01,0xfe,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f64 v1, a[254:255] offset:65535 // GFX90A: ds_max_f64 v1, a[2:3] ; encoding: [0x00,0x00,0xa6,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f64 v1, a[2:3] // GFX90A: ds_max_f64 v1, a[2:3] ; encoding: [0x00,0x00,0xa6,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f64 v1, a[2:3] // GFX90A: ds_max_f64 v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0xa6,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_max_f64 v1, a[2:3] offset:4 // GFX90A: ds_write_b8_d16_hi v1, a2 offset:65535 ; encoding: [0xff,0xff,0xa8,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8_d16_hi v1, a2 offset:65535 // GFX90A: ds_write_b8_d16_hi v255, a2 offset:65535 ; encoding: [0xff,0xff,0xa8,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8_d16_hi v255, a2 offset:65535 // GFX90A: ds_write_b8_d16_hi v1, a255 offset:65535 ; encoding: [0xff,0xff,0xa8,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8_d16_hi v1, a255 offset:65535 // GFX90A: ds_write_b8_d16_hi v1, a2 ; encoding: [0x00,0x00,0xa8,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8_d16_hi v1, a2 // GFX90A: ds_write_b8_d16_hi v1, a2 ; encoding: [0x00,0x00,0xa8,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8_d16_hi v1, a2 // GFX90A: ds_write_b8_d16_hi v1, a2 offset:4 ; encoding: [0x04,0x00,0xa8,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b8_d16_hi v1, a2 offset:4 // GFX90A: ds_write_b16_d16_hi v1, a2 offset:65535 ; encoding: [0xff,0xff,0xaa,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16_d16_hi v1, a2 offset:65535 // GFX90A: ds_write_b16_d16_hi v255, a2 offset:65535 ; encoding: [0xff,0xff,0xaa,0xda,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16_d16_hi v255, a2 offset:65535 // GFX90A: ds_write_b16_d16_hi v1, a255 offset:65535 ; encoding: [0xff,0xff,0xaa,0xda,0x01,0xff,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16_d16_hi v1, a255 offset:65535 // GFX90A: ds_write_b16_d16_hi v1, a2 ; encoding: [0x00,0x00,0xaa,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16_d16_hi v1, a2 // GFX90A: ds_write_b16_d16_hi v1, a2 ; encoding: [0x00,0x00,0xaa,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16_d16_hi v1, a2 // GFX90A: ds_write_b16_d16_hi v1, a2 offset:4 ; encoding: [0x04,0x00,0xaa,0xda,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b16_d16_hi v1, a2 offset:4 // GFX90A: ds_read_u8_d16 a5, v1 offset:65535 ; encoding: [0xff,0xff,0xac,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16 a5, v1 offset:65535 // GFX90A: ds_read_u8_d16 a255, v1 offset:65535 ; encoding: [0xff,0xff,0xac,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16 a255, v1 offset:65535 // GFX90A: ds_read_u8_d16 a5, v255 offset:65535 ; encoding: [0xff,0xff,0xac,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16 a5, v255 offset:65535 // GFX90A: ds_read_u8_d16 a5, v1 ; encoding: [0x00,0x00,0xac,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16 a5, v1 // GFX90A: ds_read_u8_d16 a5, v1 ; encoding: [0x00,0x00,0xac,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16 a5, v1 // GFX90A: ds_read_u8_d16 a5, v1 offset:4 ; encoding: [0x04,0x00,0xac,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16 a5, v1 offset:4 // GFX90A: ds_read_u8_d16_hi a5, v1 offset:65535 ; encoding: [0xff,0xff,0xae,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16_hi a5, v1 offset:65535 // GFX90A: ds_read_u8_d16_hi a255, v1 offset:65535 ; encoding: [0xff,0xff,0xae,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16_hi a255, v1 offset:65535 // GFX90A: ds_read_u8_d16_hi a5, v255 offset:65535 ; encoding: [0xff,0xff,0xae,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16_hi a5, v255 offset:65535 // GFX90A: ds_read_u8_d16_hi a5, v1 ; encoding: [0x00,0x00,0xae,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16_hi a5, v1 // GFX90A: ds_read_u8_d16_hi a5, v1 ; encoding: [0x00,0x00,0xae,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16_hi a5, v1 // GFX90A: ds_read_u8_d16_hi a5, v1 offset:4 ; encoding: [0x04,0x00,0xae,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u8_d16_hi a5, v1 offset:4 // GFX90A: ds_read_i8_d16 a5, v1 offset:65535 ; encoding: [0xff,0xff,0xb0,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16 a5, v1 offset:65535 // GFX90A: ds_read_i8_d16 a255, v1 offset:65535 ; encoding: [0xff,0xff,0xb0,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16 a255, v1 offset:65535 // GFX90A: ds_read_i8_d16 a5, v255 offset:65535 ; encoding: [0xff,0xff,0xb0,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16 a5, v255 offset:65535 // GFX90A: ds_read_i8_d16 a5, v1 ; encoding: [0x00,0x00,0xb0,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16 a5, v1 // GFX90A: ds_read_i8_d16 a5, v1 ; encoding: [0x00,0x00,0xb0,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16 a5, v1 // GFX90A: ds_read_i8_d16 a5, v1 offset:4 ; encoding: [0x04,0x00,0xb0,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16 a5, v1 offset:4 // GFX90A: ds_read_i8_d16_hi a5, v1 offset:65535 ; encoding: [0xff,0xff,0xb2,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16_hi a5, v1 offset:65535 // GFX90A: ds_read_i8_d16_hi a255, v1 offset:65535 ; encoding: [0xff,0xff,0xb2,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16_hi a255, v1 offset:65535 // GFX90A: ds_read_i8_d16_hi a5, v255 offset:65535 ; encoding: [0xff,0xff,0xb2,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16_hi a5, v255 offset:65535 // GFX90A: ds_read_i8_d16_hi a5, v1 ; encoding: [0x00,0x00,0xb2,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16_hi a5, v1 // GFX90A: ds_read_i8_d16_hi a5, v1 ; encoding: [0x00,0x00,0xb2,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16_hi a5, v1 // GFX90A: ds_read_i8_d16_hi a5, v1 offset:4 ; encoding: [0x04,0x00,0xb2,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_i8_d16_hi a5, v1 offset:4 // GFX90A: ds_read_u16_d16 a5, v1 offset:65535 ; encoding: [0xff,0xff,0xb4,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16 a5, v1 offset:65535 // GFX90A: ds_read_u16_d16 a255, v1 offset:65535 ; encoding: [0xff,0xff,0xb4,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16 a255, v1 offset:65535 // GFX90A: ds_read_u16_d16 a5, v255 offset:65535 ; encoding: [0xff,0xff,0xb4,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16 a5, v255 offset:65535 // GFX90A: ds_read_u16_d16 a5, v1 ; encoding: [0x00,0x00,0xb4,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16 a5, v1 // GFX90A: ds_read_u16_d16 a5, v1 ; encoding: [0x00,0x00,0xb4,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16 a5, v1 // GFX90A: ds_read_u16_d16 a5, v1 offset:4 ; encoding: [0x04,0x00,0xb4,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16 a5, v1 offset:4 // GFX90A: ds_read_u16_d16_hi a5, v1 offset:65535 ; encoding: [0xff,0xff,0xb6,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16_hi a5, v1 offset:65535 // GFX90A: ds_read_u16_d16_hi a255, v1 offset:65535 ; encoding: [0xff,0xff,0xb6,0xda,0x01,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16_hi a255, v1 offset:65535 // GFX90A: ds_read_u16_d16_hi a5, v255 offset:65535 ; encoding: [0xff,0xff,0xb6,0xda,0xff,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16_hi a5, v255 offset:65535 // GFX90A: ds_read_u16_d16_hi a5, v1 ; encoding: [0x00,0x00,0xb6,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16_hi a5, v1 // GFX90A: ds_read_u16_d16_hi a5, v1 ; encoding: [0x00,0x00,0xb6,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16_hi a5, v1 // GFX90A: ds_read_u16_d16_hi a5, v1 offset:4 ; encoding: [0x04,0x00,0xb6,0xda,0x01,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_u16_d16_hi a5, v1 offset:4 // GFX90A: ds_add_rtn_u64 a[6:7], v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x01,0x02,0x00,0x06] @@ -9658,99 +9658,99 @@ ds_max_rtn_f64 a[6:7], v1, a[2:3] ds_max_rtn_f64 a[6:7], v1, a[2:3] offset:4 // GFX90A: ds_read_b64 a[6:7], v1 offset:65535 ; encoding: [0xff,0xff,0xec,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b64 a[6:7], v1 offset:65535 // GFX90A: ds_read_b64 a[254:255], v1 offset:65535 ; encoding: [0xff,0xff,0xec,0xda,0x01,0x00,0x00,0xfe] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b64 a[254:255], v1 offset:65535 // GFX90A: ds_read_b64 a[6:7], v255 offset:65535 ; encoding: [0xff,0xff,0xec,0xda,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b64 a[6:7], v255 offset:65535 // GFX90A: ds_read_b64 a[6:7], v1 ; encoding: [0x00,0x00,0xec,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b64 a[6:7], v1 // GFX90A: ds_read_b64 a[6:7], v1 ; encoding: [0x00,0x00,0xec,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b64 a[6:7], v1 // GFX90A: ds_read_b64 a[6:7], v1 offset:4 ; encoding: [0x04,0x00,0xec,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b64 a[6:7], v1 offset:4 // GFX90A: ds_read2_b64 a[6:9], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset0:127 offset1:255 // GFX90A: ds_read2_b64 a[252:255], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xee,0xda,0x01,0x00,0x00,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[252:255], v1 offset0:127 offset1:255 // GFX90A: ds_read2_b64 a[6:9], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xee,0xda,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v255 offset0:127 offset1:255 // GFX90A: ds_read2_b64 a[6:9], v1 offset1:255 ; encoding: [0x00,0xff,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset1:255 // GFX90A: ds_read2_b64 a[6:9], v1 offset1:255 ; encoding: [0x00,0xff,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset1:255 // GFX90A: ds_read2_b64 a[6:9], v1 offset0:16 offset1:255 ; encoding: [0x10,0xff,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset0:16 offset1:255 // GFX90A: ds_read2_b64 a[6:9], v1 offset0:127 ; encoding: [0x7f,0x00,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset0:127 // GFX90A: ds_read2_b64 a[6:9], v1 offset0:127 ; encoding: [0x7f,0x00,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset0:127 // GFX90A: ds_read2_b64 a[6:9], v1 offset0:127 offset1:1 ; encoding: [0x7f,0x01,0xee,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2_b64 a[6:9], v1 offset0:127 offset1:1 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset0:127 offset1:255 // GFX90A: ds_read2st64_b64 a[252:255], v1 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xf0,0xda,0x01,0x00,0x00,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[252:255], v1 offset0:127 offset1:255 // GFX90A: ds_read2st64_b64 a[6:9], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xf0,0xda,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v255 offset0:127 offset1:255 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset1:255 ; encoding: [0x00,0xff,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset1:255 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset1:255 ; encoding: [0x00,0xff,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset1:255 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset0:16 offset1:255 ; encoding: [0x10,0xff,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset0:16 offset1:255 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset0:127 ; encoding: [0x7f,0x00,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset0:127 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset0:127 ; encoding: [0x7f,0x00,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset0:127 // GFX90A: ds_read2st64_b64 a[6:9], v1 offset0:127 offset1:1 ; encoding: [0x7f,0x01,0xf0,0xda,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read2st64_b64 a[6:9], v1 offset0:127 offset1:1 // GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 ; encoding: [0xff,0xff,0xfc,0xda,0x01,0x02,0x00,0x06] @@ -9782,921 +9782,921 @@ ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4 // GFX90A: ds_gws_init a0 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_init a0 offset:65535 gds // GFX90A: ds_gws_init a254 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0xfe,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_init a254 offset:65535 gds // GFX90A: ds_gws_init a2 gds ; encoding: [0x00,0x00,0x33,0xdb,0x02,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_init a2 gds // GFX90A: ds_gws_init a0 gds ; encoding: [0x00,0x00,0x33,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_init a0 gds // GFX90A: ds_gws_init a0 offset:4 gds ; encoding: [0x04,0x00,0x33,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_init a0 offset:4 gds // GFX90A: ds_gws_sema_br a2 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0x02,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_sema_br a2 offset:65535 gds // GFX90A: ds_gws_sema_br a254 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0xfe,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_sema_br a254 offset:65535 gds // GFX90A: ds_gws_sema_br a0 gds ; encoding: [0x00,0x00,0x37,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_sema_br a0 gds // GFX90A: ds_gws_sema_br a2 gds ; encoding: [0x00,0x00,0x37,0xdb,0x02,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_sema_br a2 gds // GFX90A: ds_gws_sema_br a0 offset:4 gds ; encoding: [0x04,0x00,0x37,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_sema_br a0 offset:4 gds // GFX90A: ds_gws_barrier a2 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0x02,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_barrier a2 offset:65535 gds // GFX90A: ds_gws_barrier a254 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0xfe,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_barrier a254 offset:65535 gds // GFX90A: ds_gws_barrier a0 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_barrier a0 gds // GFX90A: ds_gws_barrier a2 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x02,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_barrier a2 gds // GFX90A: ds_gws_barrier a0 offset:4 gds ; encoding: [0x04,0x00,0x3b,0xdb,0x00,0x00,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_gws_barrier a0 offset:4 gds // GFX90A: ds_consume a5 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_consume a5 offset:65535 // GFX90A: ds_consume a255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_consume a255 offset:65535 // GFX90A: ds_consume a5 ; encoding: [0x00,0x00,0x7a,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_consume a5 // GFX90A: ds_consume a5 ; encoding: [0x00,0x00,0x7a,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_consume a5 // GFX90A: ds_consume a5 offset:4 ; encoding: [0x04,0x00,0x7a,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_consume a5 offset:4 // GFX90A: ds_append a5 offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_append a5 offset:65535 // GFX90A: ds_append a255 offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0x00,0x00,0x00,0xff] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_append a255 offset:65535 // GFX90A: ds_append a5 ; encoding: [0x00,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_append a5 // GFX90A: ds_append a5 ; encoding: [0x00,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_append a5 // GFX90A: ds_append a5 offset:4 ; encoding: [0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_append a5 offset:4 // GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b96 v1, a[2:4] offset:65535 // GFX90A: ds_write_b96 v255, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b96 v255, a[2:4] offset:65535 // GFX90A: ds_write_b96 v1, a[252:254] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0xfc,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b96 v1, a[252:254] offset:65535 // GFX90A: ds_write_b96 v1, a[2:4] ; encoding: [0x00,0x00,0xbc,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b96 v1, a[2:4] // GFX90A: ds_write_b96 v1, a[2:4] ; encoding: [0x00,0x00,0xbc,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b96 v1, a[2:4] // GFX90A: ds_write_b96 v1, a[2:4] offset:4 ; encoding: [0x04,0x00,0xbc,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b96 v1, a[2:4] offset:4 // GFX90A: ds_write_b128 v1, a[2:5] offset:65535 ; encoding: [0xff,0xff,0xbe,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b128 v1, a[2:5] offset:65535 // GFX90A: ds_write_b128 v255, a[2:5] offset:65535 ; encoding: [0xff,0xff,0xbe,0xdb,0xff,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b128 v255, a[2:5] offset:65535 // GFX90A: ds_write_b128 v1, a[252:255] offset:65535 ; encoding: [0xff,0xff,0xbe,0xdb,0x01,0xfc,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b128 v1, a[252:255] offset:65535 // GFX90A: ds_write_b128 v1, a[2:5] ; encoding: [0x00,0x00,0xbe,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b128 v1, a[2:5] // GFX90A: ds_write_b128 v1, a[2:5] ; encoding: [0x00,0x00,0xbe,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b128 v1, a[2:5] // GFX90A: ds_write_b128 v1, a[2:5] offset:4 ; encoding: [0x04,0x00,0xbe,0xdb,0x01,0x02,0x00,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_write_b128 v1, a[2:5] offset:4 // GFX90A: ds_read_b96 a[6:8], v1 offset:65535 ; encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b96 a[6:8], v1 offset:65535 // GFX90A: ds_read_b96 a[252:254], v1 offset:65535 ; encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b96 a[252:254], v1 offset:65535 // GFX90A: ds_read_b96 a[6:8], v255 offset:65535 ; encoding: [0xff,0xff,0xfc,0xdb,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b96 a[6:8], v255 offset:65535 // GFX90A: ds_read_b96 a[6:8], v1 ; encoding: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b96 a[6:8], v1 // GFX90A: ds_read_b96 a[6:8], v1 ; encoding: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b96 a[6:8], v1 // GFX90A: ds_read_b96 a[6:8], v1 offset:4 ; encoding: [0x04,0x00,0xfc,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b96 a[6:8], v1 offset:4 // GFX90A: ds_read_b128 a[6:9], v1 offset:65535 ; encoding: [0xff,0xff,0xfe,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b128 a[6:9], v1 offset:65535 // GFX90A: ds_read_b128 a[252:255], v1 offset:65535 ; encoding: [0xff,0xff,0xfe,0xdb,0x01,0x00,0x00,0xfc] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b128 a[252:255], v1 offset:65535 // GFX90A: ds_read_b128 a[6:9], v255 offset:65535 ; encoding: [0xff,0xff,0xfe,0xdb,0xff,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b128 a[6:9], v255 offset:65535 // GFX90A: ds_read_b128 a[6:9], v1 ; encoding: [0x00,0x00,0xfe,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b128 a[6:9], v1 // GFX90A: ds_read_b128 a[6:9], v1 ; encoding: [0x00,0x00,0xfe,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b128 a[6:9], v1 // GFX90A: ds_read_b128 a[6:9], v1 offset:4 ; encoding: [0x04,0x00,0xfe,0xdb,0x01,0x00,0x00,0x06] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction ds_read_b128 a[6:9], v1 offset:4 // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 // GFX90A: image_load a252, v[2:5], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x01,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a252, v[2:5], s[8:15] dmask:0x1 // GFX90A: image_load a5, v[252:255], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x01,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[252:255], s[8:15] dmask:0x1 // GFX90A: image_load a5, v[2:5], s[12:19] dmask:0x1 ; encoding: [0x00,0x01,0x01,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[12:19] dmask:0x1 // GFX90A: image_load a5, v[2:5], s[92:99] dmask:0x1 ; encoding: [0x00,0x01,0x01,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[92:99] dmask:0x1 // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x2 ; encoding: [0x00,0x02,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x2 // GFX90A: image_load a[6:7], v[2:5], s[8:15] dmask:0x3 ; encoding: [0x00,0x03,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:7], v[2:5], s[8:15] dmask:0x3 // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x4 ; encoding: [0x00,0x04,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x4 // GFX90A: image_load a[6:7], v[2:5], s[8:15] dmask:0x5 ; encoding: [0x00,0x05,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:7], v[2:5], s[8:15] dmask:0x5 // GFX90A: image_load a[6:7], v[2:5], s[8:15] dmask:0x6 ; encoding: [0x00,0x06,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:7], v[2:5], s[8:15] dmask:0x6 // GFX90A: image_load a[6:8], v[2:5], s[8:15] dmask:0x7 ; encoding: [0x00,0x07,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:8], v[2:5], s[8:15] dmask:0x7 // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x8 ; encoding: [0x00,0x08,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x8 // GFX90A: image_load a[6:7], v[2:5], s[8:15] dmask:0x9 ; encoding: [0x00,0x09,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:7], v[2:5], s[8:15] dmask:0x9 // GFX90A: image_load a[6:7], v[2:5], s[8:15] dmask:0xa ; encoding: [0x00,0x0a,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:7], v[2:5], s[8:15] dmask:0xa // GFX90A: image_load a[6:8], v[2:5], s[8:15] dmask:0xb ; encoding: [0x00,0x0b,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:8], v[2:5], s[8:15] dmask:0xb // GFX90A: image_load a[6:7], v[2:5], s[8:15] dmask:0xc ; encoding: [0x00,0x0c,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:7], v[2:5], s[8:15] dmask:0xc // GFX90A: image_load a[6:8], v[2:5], s[8:15] dmask:0xd ; encoding: [0x00,0x0d,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:8], v[2:5], s[8:15] dmask:0xd // GFX90A: image_load a[6:8], v[2:5], s[8:15] dmask:0xe ; encoding: [0x00,0x0e,0x01,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[6:8], v[2:5], s[8:15] dmask:0xe // GFX90A: image_load a5, v[2:5], s[8:15] ; encoding: [0x00,0x00,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 glc ; encoding: [0x00,0x21,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 glc // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x01,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 slc // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x03,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 lwe // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 da ; encoding: [0x00,0x41,0x01,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 da // GFX90A: image_load a5, v[2:5], s[8:15] dmask:0x1 d16 ; encoding: [0x00,0x01,0x01,0xf0,0x02,0x05,0x02,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a5, v[2:5], s[8:15] dmask:0x1 d16 // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_store a252, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x21,0xf0,0x02,0xfc,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a252, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_store a1, v[252:255], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x21,0xf0,0xfc,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[252:255], s[12:19] dmask:0x1 unorm // GFX90A: image_store a1, v[2:5], s[16:23] dmask:0x1 unorm ; encoding: [0x00,0x11,0x21,0xf0,0x02,0x01,0x04,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[16:23] dmask:0x1 unorm // GFX90A: image_store a1, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x21,0xf0,0x02,0x01,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x2 unorm ; encoding: [0x00,0x12,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x2 unorm // GFX90A: image_store a[2:3], v[2:5], s[12:19] dmask:0x3 unorm ; encoding: [0x00,0x13,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:3], v[2:5], s[12:19] dmask:0x3 unorm // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x4 unorm ; encoding: [0x00,0x14,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x4 unorm // GFX90A: image_store a[2:3], v[2:5], s[12:19] dmask:0x5 unorm ; encoding: [0x00,0x15,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:3], v[2:5], s[12:19] dmask:0x5 unorm // GFX90A: image_store a[2:3], v[2:5], s[12:19] dmask:0x6 unorm ; encoding: [0x00,0x16,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:3], v[2:5], s[12:19] dmask:0x6 unorm // GFX90A: image_store a[2:4], v[2:5], s[12:19] dmask:0x7 unorm ; encoding: [0x00,0x17,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:4], v[2:5], s[12:19] dmask:0x7 unorm // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x8 unorm ; encoding: [0x00,0x18,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x8 unorm // GFX90A: image_store a[2:3], v[2:5], s[12:19] dmask:0x9 unorm ; encoding: [0x00,0x19,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:3], v[2:5], s[12:19] dmask:0x9 unorm // GFX90A: image_store a[2:3], v[2:5], s[12:19] dmask:0xa unorm ; encoding: [0x00,0x1a,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:3], v[2:5], s[12:19] dmask:0xa unorm // GFX90A: image_store a[2:4], v[2:5], s[12:19] dmask:0xb unorm ; encoding: [0x00,0x1b,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:4], v[2:5], s[12:19] dmask:0xb unorm // GFX90A: image_store a[2:3], v[2:5], s[12:19] dmask:0xc unorm ; encoding: [0x00,0x1c,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:3], v[2:5], s[12:19] dmask:0xc unorm // GFX90A: image_store a[2:4], v[2:5], s[12:19] dmask:0xd unorm ; encoding: [0x00,0x1d,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:4], v[2:5], s[12:19] dmask:0xd unorm // GFX90A: image_store a[2:4], v[2:5], s[12:19] dmask:0xe unorm ; encoding: [0x00,0x1e,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:4], v[2:5], s[12:19] dmask:0xe unorm // GFX90A: image_store a[2:5], v[2:5], s[12:19] dmask:0xf unorm ; encoding: [0x00,0x1f,0x21,0xf0,0x02,0x02,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[2:5], v[2:5], s[12:19] dmask:0xf unorm // GFX90A: image_store a1, v[2:5], s[12:19] unorm ; encoding: [0x00,0x10,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] unorm // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x1 unorm glc // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x21,0xf2,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x1 unorm slc // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x23,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x1 unorm lwe // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x21,0xf0,0x02,0x01,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x1 unorm da // GFX90A: image_store a1, v[2:5], s[12:19] dmask:0x1 unorm d16 ; encoding: [0x00,0x11,0x21,0xf0,0x02,0x01,0x03,0x80] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a1, v[2:5], s[12:19] dmask:0x1 unorm d16 // GFX90A: image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x41,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_swap a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x41,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_swap a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x41,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_swap a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x41,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_swap a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x41,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_swap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x41,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x41,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x41,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x43,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x41,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x45,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_cmpswap a[252:253], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x45,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[252:253], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_cmpswap a[6:7], v[252:255], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x45,0xf0,0xfc,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[252:255], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[12:19] dmask:0x3 unorm ; encoding: [0x00,0x13,0x45,0xf0,0x02,0x06,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[12:19] dmask:0x3 unorm // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[92:99] dmask:0x3 unorm ; encoding: [0x00,0x13,0x45,0xf0,0x02,0x06,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[92:99] dmask:0x3 unorm // GFX90A: image_atomic_cmpswap a[6:9], v[2:5], s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x45,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:9], v[2:5], s[8:15] dmask:0xf unorm // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x45,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm glc // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm slc ; encoding: [0x00,0x13,0x45,0xf2,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm slc // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm lwe ; encoding: [0x00,0x13,0x47,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm lwe // GFX90A: image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm da ; encoding: [0x00,0x53,0x45,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[6:7], v[2:5], s[8:15] dmask:0x3 unorm da // GFX90A: image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x49,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_add a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x49,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_add a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x49,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_add a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x49,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_add a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x49,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_add a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x49,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x49,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x49,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x4b,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x49,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_add a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x4d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_sub a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x4d,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_sub a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x4d,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_sub a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x4d,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_sub a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x4d,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_sub a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x4d,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x4d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x4d,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x4f,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x4d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_sub a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x51,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_smin a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x51,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_smin a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x51,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_smin a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x51,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_smin a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x51,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_smin a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x51,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x51,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x51,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x53,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x51,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smin a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x55,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_umin a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x55,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_umin a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x55,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_umin a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x55,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_umin a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x55,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_umin a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x55,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x55,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x55,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x57,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x55,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umin a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x59,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_smax a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x59,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_smax a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x59,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_smax a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x59,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_smax a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x59,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_smax a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x59,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x59,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x59,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x5b,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x59,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_smax a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x5d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_umax a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x5d,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_umax a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x5d,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_umax a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x5d,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_umax a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x5d,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_umax a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x5d,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x5d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x5d,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x5f,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x5d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_umax a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x61,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_and a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x61,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_and a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x61,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_and a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x61,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_and a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x61,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_and a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x61,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x61,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x61,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x63,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x61,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_and a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x65,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_or a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x65,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_or a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x65,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_or a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x65,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_or a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x65,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_or a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x65,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x65,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x65,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x67,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x65,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_or a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x69,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_xor a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x69,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_xor a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x69,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_xor a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x69,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_xor a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x69,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_xor a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x69,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x69,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x69,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x6b,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x69,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_xor a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x6d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_inc a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x6d,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_inc a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x6d,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_inc a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x6d,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_inc a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x6d,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_inc a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x6d,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x6d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x6d,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x6f,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x6d,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_inc a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x71,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_dec a252, v[2:5], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x71,0xf0,0x02,0xfc,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a252, v[2:5], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_dec a5, v[252:255], s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x71,0xf0,0xfc,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[252:255], s[8:15] dmask:0x1 unorm // GFX90A: image_atomic_dec a5, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x71,0xf0,0x02,0x05,0x03,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[12:19] dmask:0x1 unorm // GFX90A: image_atomic_dec a5, v[2:5], s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x71,0xf0,0x02,0x05,0x17,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[92:99] dmask:0x1 unorm // GFX90A: image_atomic_dec a[6:7], v[2:5], s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x71,0xf0,0x02,0x06,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a[6:7], v[2:5], s[8:15] dmask:0x3 unorm // GFX90A: image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x71,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm glc // GFX90A: image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x71,0xf2,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm slc // GFX90A: image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x73,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm lwe // GFX90A: image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x71,0xf0,0x02,0x05,0x02,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_dec a5, v[2:5], s[8:15] dmask:0x1 unorm da // GFX90A: image_sample a5, v[0:3], s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x81,0xf0,0x00,0x05,0x62,0x00] -// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU +// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction image_sample a5, v[0:3], s[8:15], s[12:15] dmask:0x1 diff --git a/llvm/test/MC/AMDGPU/gfx950-unsupported.s b/llvm/test/MC/AMDGPU/gfx950-unsupported.s index 8bdab2d..cea81b2 100644 --- a/llvm/test/MC/AMDGPU/gfx950-unsupported.s +++ b/llvm/test/MC/AMDGPU/gfx950-unsupported.s @@ -183,7 +183,7 @@ v_mfma_f32_16x16x8_xf32 v[0:3], a[0:3], a[0:3], v[4:7] // ds_read_b64_tr_b4 //===----------------------------------------------------------------------===// ds_read_b64_tr_b4 v[1:2], v0 -// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU ds_read_b64_tr_b4 v1, v0 @@ -202,7 +202,7 @@ ds_read_b64_tr_b4 v[2:3], v2 offset:-64 //ds_read_b64_tr_b8 //===----------------------------------------------------------------------===// ds_read_b64_tr_b8 v[1:2], v0 -// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU ds_read_b64_tr_b8 v1, v0 @@ -221,7 +221,7 @@ ds_read_b64_tr_b8 v[2:3], v2 offset:-64 // ds_read_b64_tr_b16 //===----------------------------------------------------------------------===// ds_read_b64_tr_b16 v[1:2], v0 -// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU ds_read_b64_tr_b16 v1, v0 diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s index 7839475..78aa8f2 100644 --- a/llvm/test/MC/AMDGPU/literals.s +++ b/llvm/test/MC/AMDGPU/literals.s @@ -1,935 +1,1849 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 // RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI // RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=SICI,CI -// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GFX89 -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX89,GFX9 - -// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSI,NOSICI,NOSICIVI --implicit-check-not=error: -// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOCIVI,NOSICIVI --implicit-check-not=error: -// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICIVI,NOVI,NOGFX89 --implicit-check-not=error: -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX89,NOGFX9 --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX89 +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX89,GFX9 +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX11 +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX12XX,GFX12 +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX12XX,GFX1250 + +// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOSI --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOCI --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX89,NOVI --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX89,NOGFX9 --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX11 --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX12 --implicit-check-not=error: +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 %s -mattr=+real-true16 -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX1250 --implicit-check-not=error: //---------------------------------------------------------------------------// // fp literal, expected fp operand //---------------------------------------------------------------------------// -// SICI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x64,0x00,0x7e] v_fract_f64 v[0:1], 0.5 +// SICI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e] -// SICI: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x68,0x00,0x7e] -// GFX89: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x50,0x00,0x7e] v_sqrt_f64 v[0:1], -4.0 +// SICI: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x68,0x00,0x7e] +// GFX89: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x50,0x00,0x7e] +// GFX12XX: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x68,0x00,0x7e] +// GFX11: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x68,0x00,0x7e] -// SICI: v_log_clamp_f32_e32 v1, 0.5 ; encoding: [0xf0,0x4c,0x02,0x7e] -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU v_log_clamp_f32 v1, 0.5 +// NOGFX8PLUS: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// SICI: v_log_clamp_f32_e32 v1, 0.5 ; encoding: [0xf0,0x4c,0x02,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x64,0x00,0x7e] -v_fract_f64 v[0:1], 0.5 - -// SICI: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x38,0x00,0x7e] v_trunc_f32 v0, 0.5 +// SICI: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x64,0x00,0x7e] v_fract_f64 v[0:1], -1.0 +// SICI: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x7c,0x00,0x7e] -// SICI: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x38,0x00,0x7e] v_trunc_f32 v0, -1.0 +// SICI: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x64,0x00,0x7e] v_fract_f64 v[0:1], 4.0 +// SICI: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x7c,0x00,0x7e] -// SICI: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x38,0x00,0x7e] v_trunc_f32 v0, 4.0 +// SICI: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x64,0x00,0x7e] v_fract_f64 v[0:1], 0.0 +// SICI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e] -// SICI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x38,0x00,0x7e] v_trunc_f32 v0, 0.0 +// SICI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf8,0x3f] -// GFX89: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x64,0x00,0x7e,0x00,0x00,0xf8,0x3f] v_fract_f64 v[0:1], 1.5 +// SICI: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf8,0x3f] +// GFX89: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x64,0x00,0x7e,0x00,0x00,0xf8,0x3f] +// GFX12XX: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf8,0x3f] +// GFX11: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf8,0x3f] -// SICI: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0xc0,0x3f] -// GFX89: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x00,0xc0,0x3f] v_trunc_f32 v0, 1.5 +// SICI: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0xc0,0x3f] +// GFX89: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x00,0xc0,0x3f] +// GFX12XX: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0xc0,0x3f] +// GFX11: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0xc0,0x3f] -// SICI: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x7c,0x00,0x7e,0xca,0x21,0x09,0xc0] -// GFX89: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x64,0x00,0x7e,0xca,0x21,0x09,0xc0] v_fract_f64 v[0:1], -3.1415 +// SICI: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x7c,0x00,0x7e,0xca,0x21,0x09,0xc0] +// GFX89: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x64,0x00,0x7e,0xca,0x21,0x09,0xc0] +// NOSICI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX89: :[[@LINE-4]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// GFX11: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x7c,0x00,0x7e,0xca,0x21,0x09,0xc0] +// GFX12: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x7c,0x00,0x7e,0xca,0x21,0x09,0xc0] +// GFX1250: v_fract_f64_e32 v[0:1], 0xc00921cac083126f ; encoding: [0xfe,0x7c,0x00,0x7e,0x6f,0x12,0x83,0xc0,0xca,0x21,0x09,0xc0] +// NOGFX11: :[[@LINE-8]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX12: :[[@LINE-9]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOSICIVI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero -// SICI: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x42,0x00,0x7e,0x56,0x0e,0x49,0xc0] -// GFX89: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x38,0x00,0x7e,0x56,0x0e,0x49,0xc0] v_trunc_f32 v0, -3.1415 +// SICI: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x42,0x00,0x7e,0x56,0x0e,0x49,0xc0] +// GFX89: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x38,0x00,0x7e,0x56,0x0e,0x49,0xc0] +// GFX12XX: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x42,0x00,0x7e,0x56,0x0e,0x49,0xc0] +// GFX11: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x42,0x00,0x7e,0x56,0x0e,0x49,0xc0] -// SICI: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x7c,0x00,0x7e,0x02,0x2d,0xb5,0x44] -// GFX89: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x64,0x00,0x7e,0x02,0x2d,0xb5,0x44] v_fract_f64 v[0:1], 100000000000000000000000.0 +// SICI: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x7c,0x00,0x7e,0x02,0x2d,0xb5,0x44] +// GFX89: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x64,0x00,0x7e,0x02,0x2d,0xb5,0x44] +// NOSICI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX89: :[[@LINE-4]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// GFX11: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x7c,0x00,0x7e,0x02,0x2d,0xb5,0x44] +// GFX12: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x7c,0x00,0x7e,0x02,0x2d,0xb5,0x44] +// GFX1250: v_fract_f64_e32 v[0:1], 0x44b52d02c7e14af6 ; encoding: [0xfe,0x7c,0x00,0x7e,0xf6,0x4a,0xe1,0xc7,0x02,0x2d,0xb5,0x44] +// NOGFX11: :[[@LINE-8]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX12: :[[@LINE-9]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOSICIVI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero -// SICI: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x42,0x00,0x7e,0x16,0x68,0xa9,0x65] -// GFX89: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x38,0x00,0x7e,0x16,0x68,0xa9,0x65] v_trunc_f32 v0, 100000000000000000000000.0 +// SICI: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x42,0x00,0x7e,0x16,0x68,0xa9,0x65] +// GFX89: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x38,0x00,0x7e,0x16,0x68,0xa9,0x65] +// GFX12XX: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x42,0x00,0x7e,0x16,0x68,0xa9,0x65] +// GFX11: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x42,0x00,0x7e,0x16,0x68,0xa9,0x65] -// SICI: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x7c,0x00,0x7e,0xd0,0x12,0x63,0x41] -// GFX89: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x64,0x00,0x7e,0xd0,0x12,0x63,0x41] v_fract_f64 v[0:1], 10000000.0 +// SICI: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x7c,0x00,0x7e,0xd0,0x12,0x63,0x41] +// GFX89: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x64,0x00,0x7e,0xd0,0x12,0x63,0x41] +// GFX12XX: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x7c,0x00,0x7e,0xd0,0x12,0x63,0x41] +// GFX11: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x7c,0x00,0x7e,0xd0,0x12,0x63,0x41] -// SICI: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x42,0x00,0x7e,0x80,0x96,0x18,0x4b] -// GFX89: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x38,0x00,0x7e,0x80,0x96,0x18,0x4b] v_trunc_f32 v0, 10000000.0 +// SICI: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x42,0x00,0x7e,0x80,0x96,0x18,0x4b] +// GFX89: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x38,0x00,0x7e,0x80,0x96,0x18,0x4b] +// GFX12XX: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x42,0x00,0x7e,0x80,0x96,0x18,0x4b] +// GFX11: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x42,0x00,0x7e,0x80,0x96,0x18,0x4b] -// SICI: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xef,0x47] -// GFX89: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0xef,0x47] v_fract_f64 v[0:1], 3.402823e+38 +// SICI: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xef,0x47] +// GFX89: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0xef,0x47] +// NOSICI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX89: :[[@LINE-4]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// GFX11: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xef,0x47] +// GFX12: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xef,0x47] +// GFX1250: v_fract_f64_e32 v[0:1], 0x47efffff966ad924 ; encoding: [0xfe,0x7c,0x00,0x7e,0x24,0xd9,0x6a,0x96,0xff,0xff,0xef,0x47] +// NOGFX11: :[[@LINE-8]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX12: :[[@LINE-9]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOSICIVI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero -// SICI: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x42,0x00,0x7e,0xfd,0xff,0x7f,0x7f] -// GFX89: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x38,0x00,0x7e,0xfd,0xff,0x7f,0x7f] v_trunc_f32 v0, 3.402823e+38 +// SICI: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x42,0x00,0x7e,0xfd,0xff,0x7f,0x7f] +// GFX89: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x38,0x00,0x7e,0xfd,0xff,0x7f,0x7f] +// GFX12XX: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x42,0x00,0x7e,0xfd,0xff,0x7f,0x7f] +// GFX11: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x42,0x00,0x7e,0xfd,0xff,0x7f,0x7f] -// SICI: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0x1f,0x38] -// GFX89: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0x1f,0x38] v_fract_f64 v[0:1], 2.3509886e-38 +// SICI: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0x1f,0x38] +// GFX89: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0x1f,0x38] +// NOSICI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX89: :[[@LINE-4]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// GFX11: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0x1f,0x38] +// GFX12: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0x1f,0x38] +// GFX1250: v_fract_f64_e32 v[0:1], 0x381fffffe8c9d9fb ; encoding: [0xfe,0x7c,0x00,0x7e,0xfb,0xd9,0xc9,0xe8,0xff,0xff,0x1f,0x38] +// NOGFX11: :[[@LINE-8]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX12: :[[@LINE-9]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOSICIVI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero -// SICI: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x42,0x00,0x7e,0xff,0xff,0xff,0x00] -// GFX89: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x38,0x00,0x7e,0xff,0xff,0xff,0x00] v_trunc_f32 v0, 2.3509886e-38 +// SICI: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x42,0x00,0x7e,0xff,0xff,0xff,0x00] +// GFX89: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x38,0x00,0x7e,0xff,0xff,0xff,0x00] +// GFX12XX: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x42,0x00,0x7e,0xff,0xff,0xff,0x00] +// GFX11: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x42,0x00,0x7e,0xff,0xff,0xff,0x00] -// SICI: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x7c,0x00,0x7e,0x23,0xf6,0x79,0x31] -// GFX89: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x64,0x00,0x7e,0x23,0xf6,0x79,0x31] v_fract_f64 v[0:1], 2.3509886e-70 +// SICI: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x7c,0x00,0x7e,0x23,0xf6,0x79,0x31] +// GFX89: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x64,0x00,0x7e,0x23,0xf6,0x79,0x31] +// NOSICI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX89: :[[@LINE-4]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// GFX11: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x7c,0x00,0x7e,0x23,0xf6,0x79,0x31] +// GFX12: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x7c,0x00,0x7e,0x23,0xf6,0x79,0x31] +// GFX1250: v_fract_f64_e32 v[0:1], 0x3179f623c2d3cf3c ; encoding: [0xfe,0x7c,0x00,0x7e,0x3c,0xcf,0xd3,0xc2,0x23,0xf6,0x79,0x31] +// NOGFX11: :[[@LINE-8]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOGFX12: :[[@LINE-9]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// NOSICIVI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32 v0, 2.3509886e-70 +// NOGCN: :[[@LINE-1]]:17: error: invalid operand for instruction + +v_fract_f64_e32 v[0:1], 1.0 +// SICI: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e] + +v_fract_f64_e32 v[0:1], lit(1.0) +// SICI: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f] +// GFX89: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x64,0x00,0x7e,0x00,0x00,0xf0,0x3f] +// GFX11: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f] +// GFX12: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f] +// GFX1250: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xfe,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f,0x00,0x00,0x00,0x00] + +v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], 1.0 ; encoding: [0x08,0x40,0x44,0xcc,0x00,0x09,0xca,0x1b] +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-3]]:54: error: invalid operand for instruction +// NOGFX12: :[[@LINE-4]]:54: error: invalid operand for instruction +// NOGFX1250: :[[@LINE-5]]:54: error: invalid operand for instruction + +v_cos_f16_e32 v5.l, 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +// GFX11: v_cos_f16_e32 v5.l, 1.0 ; encoding: [0xf2,0xc2,0x0a,0x7e] +// GFX1250: v_cos_f16_e32 v5.l, 1.0 ; encoding: [0xf2,0xc2,0x0a,0x7e] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_cos_f16_e32 v5.l, lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +// GFX11: v_cos_f16_e32 v5.l, lit(0x3c00) ; encoding: [0xff,0xc2,0x0a,0x7e,0x00,0x3c,0x00,0x00] +// GFX1250: v_cos_f16_e32 v5.l, lit(0x3c00) ; encoding: [0xff,0xc2,0x0a,0x7e,0x00,0x3c,0x00,0x00] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_tanh_bf16 v5, 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_tanh_bf16_e32 v5, 1.0 ; encoding: [0xf2,0x94,0x0a,0x7e] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_tanh_bf16 v5, lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_tanh_bf16_e32 v5, lit(0x3f80) ; encoding: [0xff,0x94,0x0a,0x7e,0x80,0x3f,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_trunc_f32_e32 v0, 1.0 +// SICI: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e] + +v_trunc_f32_e32 v0, lit(1.0) +// SICI: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f] +// GFX89: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x00,0x80,0x3f] +// GFX12XX: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f] +// GFX11: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f] + +v_dot2_bf16_bf16 v5.l, v1, v2, 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_bf16_bf16 v5.l, v1, v2, 1.0 ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xca,0x03] +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_dot2_bf16_bf16 v5.l, v1, v2, lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_bf16_bf16 v5.l, v1, v2, lit(0x3f80) ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xfe,0x03,0x80,0x3f,0x00,0x00] +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_dot2_f32_f16 v5, v1, 1.0, v2 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_f32_f16 v5, v1, 1.0, v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xe5,0x09,0x1c] +// GFX12: v_dot2_f32_f16 v5, v1, 1.0, v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xe5,0x09,0x1c] +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_dot2_f32_f16 v5, v1, lit(1.0), v2 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_f32_f16 v5, v1, lit(0x3c00), v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xff,0x09,0x1c,0x00,0x3c,0x00,0x00] +// GFX12: v_dot2_f32_f16 v5, v1, lit(0x3c00), v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xff,0x09,0x1c,0x00,0x3c,0x00,0x00] +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_cvt_pk_fp8_f16 v1.l, 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_cvt_pk_fp8_f16 v1.l, 0x3c00 ; encoding: [0x01,0x00,0x72,0xd7,0xff,0x00,0x00,0x00,0x00,0x3c,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_cvt_pk_fp8_f16 v1.l, lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_cvt_pk_fp8_f16 v1.l, lit(0x3c00) ; encoding: [0x01,0x00,0x72,0xd7,0xff,0x00,0x00,0x00,0x00,0x3c,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU //---------------------------------------------------------------------------// // fp literal, expected int operand //---------------------------------------------------------------------------// -// SICI: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 0.5 +// GFX8PLUS: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x04,0x80,0xbe] + +s_mov_b64 s[0:1], lit(0.5) +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x26] v_and_b32_e32 v0, 0.5, v1 +// SICI: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf0,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf0,0x02,0x02,0x00] v_and_b32_e64 v0, 0.5, v1 +// SICI: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf0,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf0,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf0,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf0,0x02,0x02,0x00] -// SICI: s_mov_b64 s[0:1], -1.0 ; encoding: [0xf3,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], -1.0 ; encoding: [0xf3,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], -1.0 +// GFX8PLUS: s_mov_b64 s[0:1], -1.0 ; encoding: [0xf3,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], -1.0 ; encoding: [0xf3,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x26] v_and_b32_e32 v0, -1.0, v1 +// SICI: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf3,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf3,0x02,0x02,0x00] v_and_b32_e64 v0, -1.0, v1 +// SICI: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf3,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf3,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf3,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf3,0x02,0x02,0x00] -// SICI: s_mov_b64 s[0:1], 4.0 ; encoding: [0xf6,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], 4.0 ; encoding: [0xf6,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 4.0 +// GFX8PLUS: s_mov_b64 s[0:1], 4.0 ; encoding: [0xf6,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], 4.0 ; encoding: [0xf6,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x26] v_and_b32_e32 v0, 4.0, v1 +// SICI: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf6,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf6,0x02,0x02,0x00] v_and_b32_e64 v0, 4.0, v1 +// SICI: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf6,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf6,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf6,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf6,0x02,0x02,0x00] -// SICI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 0.0 +// GFX8PLUS: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x26] v_and_b32_e32 v0, 0.0, v1 +// SICI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0x80,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0x80,0x02,0x02,0x00] v_and_b32_e64 v0, 0.0, v1 +// SICI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0x80,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0x80,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0x80,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0x80,0x02,0x02,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 1.5 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0xc0,0x3f] -// GFX89: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x26,0x00,0x00,0xc0,0x3f] v_and_b32_e32 v0, 1.5, v1 +// SICI: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0xc0,0x3f] +// GFX89: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x26,0x00,0x00,0xc0,0x3f] +// GFX12XX: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0xc0,0x3f] +// GFX11: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0xc0,0x3f] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], -3.1415 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x36,0x56,0x0e,0x49,0xc0] -// GFX89: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x26,0x56,0x0e,0x49,0xc0] v_and_b32_e32 v0, -3.1415, v1 +// SICI: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x36,0x56,0x0e,0x49,0xc0] +// GFX89: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x26,0x56,0x0e,0x49,0xc0] +// GFX12XX: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x36,0x56,0x0e,0x49,0xc0] +// GFX11: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x36,0x56,0x0e,0x49,0xc0] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 100000000000000000000000.0 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x36,0x16,0x68,0xa9,0x65] -// GFX89: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x26,0x16,0x68,0xa9,0x65] v_and_b32_e32 v0, 100000000000000000000000.0, v1 +// SICI: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x36,0x16,0x68,0xa9,0x65] +// GFX89: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x26,0x16,0x68,0xa9,0x65] +// GFX12XX: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x36,0x16,0x68,0xa9,0x65] +// GFX11: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x36,0x16,0x68,0xa9,0x65] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 10000000.0 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x36,0x80,0x96,0x18,0x4b] -// GFX89: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x26,0x80,0x96,0x18,0x4b] v_and_b32_e32 v0, 10000000.0, v1 +// SICI: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x36,0x80,0x96,0x18,0x4b] +// GFX89: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x26,0x80,0x96,0x18,0x4b] +// GFX12XX: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x36,0x80,0x96,0x18,0x4b] +// GFX11: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x36,0x80,0x96,0x18,0x4b] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 3.402823e+38 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x36,0xfd,0xff,0x7f,0x7f] -// GFX89: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x26,0xfd,0xff,0x7f,0x7f] v_and_b32_e32 v0, 3.402823e+38, v1 +// SICI: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x36,0xfd,0xff,0x7f,0x7f] +// GFX89: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x26,0xfd,0xff,0x7f,0x7f] +// GFX12XX: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x36,0xfd,0xff,0x7f,0x7f] +// GFX11: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x36,0xfd,0xff,0x7f,0x7f] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 2.3509886e-38 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x36,0xff,0xff,0xff,0x00] -// GFX89: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x26,0xff,0xff,0xff,0x00] v_and_b32_e32 v0, 2.3509886e-38, v1 +// SICI: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x36,0xff,0xff,0xff,0x00] +// GFX89: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x26,0xff,0xff,0xff,0x00] +// GFX12XX: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x36,0xff,0xff,0xff,0x00] +// GFX11: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x36,0xff,0xff,0xff,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 2.3509886e-70 +// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_and_b32_e32 v0, 2.3509886e-70, v1 +// NOGCN: :[[@LINE-1]]:19: error: invalid operand for instruction + +v_not_b16 v5.l, 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_not_b16_e32 v5.l, 1.0 ; encoding: [0xf2,0xd2,0x0a,0x7e] +// GFX1250: v_not_b16_e32 v5.l, 1.0 ; encoding: [0xf2,0xd2,0x0a,0x7e] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_not_b16 v5.l, lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_not_b16_e32 v5.l, lit(0x3f800000) ; encoding: [0xff,0xd2,0x0a,0x7e,0x00,0x00,0x80,0x3f] +// GFX1250: v_not_b16_e32 v5.l, lit(0x3f800000) ; encoding: [0xff,0xd2,0x0a,0x7e,0x00,0x00,0x80,0x3f] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_and_b32_e32 v0, 1.0, v1 +// SICI: v_and_b32_e32 v0, 1.0, v1 ; encoding: [0xf2,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 1.0, v1 ; encoding: [0xf2,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 1.0, v1 ; encoding: [0xf2,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 1.0, v1 ; encoding: [0xf2,0x02,0x00,0x36] + +v_and_b32_e32 v0, lit(1.0), v1 +// SICI: v_and_b32_e32 v0, lit(0x3f800000), v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0x80,0x3f] +// GFX89: v_and_b32_e32 v0, lit(0x3f800000), v1 ; encoding: [0xff,0x02,0x00,0x26,0x00,0x00,0x80,0x3f] +// GFX12XX: v_and_b32_e32 v0, lit(0x3f800000), v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0x80,0x3f] +// GFX11: v_and_b32_e32 v0, lit(0x3f800000), v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0x80,0x3f] + +v_pk_add_u16 v5, exec_lo, 1.0 +// GFX12XX: v_pk_add_u16 v5, exec_lo, 1.0 ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0xe4,0x01,0x18] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_pk_add_u16 v5, exec_lo, 1.0 ; encoding: [0x05,0x40,0x8a,0xd3,0x7e,0xe4,0x01,0x18] +// GFX11: v_pk_add_u16 v5, exec_lo, 1.0 ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0xe4,0x01,0x18] +// NOVI: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_pk_add_u16 v5, exec_lo, lit(1.0) +// GFX12XX: v_pk_add_u16 v5, exec_lo, lit(0x3f800000) ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0xfe,0x01,0x18,0x00,0x00,0x80,0x3f] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_pk_add_u16 v5, exec_lo, lit(0x3f800000) ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0xfe,0x01,0x18,0x00,0x00,0x80,0x3f] +// NOVI: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX9: :[[@LINE-5]]:31: error: invalid operand (violates constant bus restrictions) + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 1.0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 1.0 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0xca,0x03] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], lit(1.0) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], lit(0x3f800000) ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0xfe,0x03,0x00,0x00,0x80,0x3f] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU //---------------------------------------------------------------------------// // int literal, expected fp operand //---------------------------------------------------------------------------// -// SICI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x38,0x00,0x7e] v_trunc_f32_e32 v0, 0 +// SICI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e] + +v_fract_f64_e32 v[0:1], 1 +// SICI: v_fract_f64_e32 v[0:1], 1 ; encoding: [0x81,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], 1 ; encoding: [0x81,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 1 ; encoding: [0x81,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], 1 ; encoding: [0x81,0x7c,0x00,0x7e] + +v_fract_f64_e32 v[0:1], lit(1) +// SICI: v_fract_f64_e32 v[0:1], lit(0x1) ; encoding: [0xff,0x7c,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX89: v_fract_f64_e32 v[0:1], lit(0x1) ; encoding: [0xff,0x64,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX11: v_fract_f64_e32 v[0:1], lit(0x1) ; encoding: [0xff,0x7c,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX12: v_fract_f64_e32 v[0:1], lit(0x1) ; encoding: [0xff,0x7c,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX1250: v_fract_f64_e32 v[0:1], lit(0x1) ; encoding: [0xfe,0x7c,0x00,0x7e,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00] -// SICI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x64,0x00,0x7e] -v_fract_f64_e32 v[0:1], 0 - -// SICI: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0x42,0xd3,0x80,0x00,0x00,0x00] -// GFX89: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00] v_trunc_f32_e64 v0, 0 +// SICI: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0x42,0xd3,0x80,0x00,0x00,0x00] +// GFX89: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00] +// GFX12XX: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0xa1,0xd5,0x80,0x00,0x00,0x00] +// GFX11: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0xa1,0xd5,0x80,0x00,0x00,0x00] -// SICI: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0x7c,0xd3,0x80,0x00,0x00,0x00] -// GFX89: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0x72,0xd1,0x80,0x00,0x00,0x00] v_fract_f64_e64 v[0:1], 0 +// SICI: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0x7c,0xd3,0x80,0x00,0x00,0x00] +// GFX89: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0x72,0xd1,0x80,0x00,0x00,0x00] +// GFX12XX: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0xbe,0xd5,0x80,0x00,0x00,0x00] +// GFX11: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0xbe,0xd5,0x80,0x00,0x00,0x00] -// SICI: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x38,0x00,0x7e] v_trunc_f32_e32 v0, -13 +// SICI: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x64,0x00,0x7e] v_fract_f64_e32 v[0:1], -13 +// SICI: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x7c,0x00,0x7e] -// SICI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x42,0xd3,0xcd,0x00,0x00,0x00] -// GFX89: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x5c,0xd1,0xcd,0x00,0x00,0x00] v_trunc_f32_e64 v0, -13 +// SICI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x42,0xd3,0xcd,0x00,0x00,0x00] +// GFX89: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x5c,0xd1,0xcd,0x00,0x00,0x00] +// GFX12XX: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0xa1,0xd5,0xcd,0x00,0x00,0x00] +// GFX11: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0xa1,0xd5,0xcd,0x00,0x00,0x00] -// SICI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x7c,0xd3,0xcd,0x00,0x00,0x00] -// GFX89: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x72,0xd1,0xcd,0x00,0x00,0x00] v_fract_f64_e64 v[0:1], -13 +// SICI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x7c,0xd3,0xcd,0x00,0x00,0x00] +// GFX89: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x72,0xd1,0xcd,0x00,0x00,0x00] +// GFX12XX: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0xbe,0xd5,0xcd,0x00,0x00,0x00] +// GFX11: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0xbe,0xd5,0xcd,0x00,0x00,0x00] -// SICI: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x38,0x00,0x7e] v_trunc_f32_e32 v0, 35 +// SICI: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x64,0x00,0x7e] v_fract_f64_e32 v[0:1], 35 +// SICI: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x7c,0x00,0x7e] -// SICI: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0x42,0xd3,0xa3,0x00,0x00,0x00] -// GFX89: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0x5c,0xd1,0xa3,0x00,0x00,0x00] v_trunc_f32_e64 v0, 35 +// SICI: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0x42,0xd3,0xa3,0x00,0x00,0x00] +// GFX89: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0x5c,0xd1,0xa3,0x00,0x00,0x00] +// GFX12XX: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0xa1,0xd5,0xa3,0x00,0x00,0x00] +// GFX11: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0xa1,0xd5,0xa3,0x00,0x00,0x00] -// SICI: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0x7c,0xd3,0xa3,0x00,0x00,0x00] -// GFX89: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0x72,0xd1,0xa3,0x00,0x00,0x00] v_fract_f64_e64 v[0:1], 35 +// SICI: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0x7c,0xd3,0xa3,0x00,0x00,0x00] +// GFX89: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0x72,0xd1,0xa3,0x00,0x00,0x00] +// GFX12XX: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0xbe,0xd5,0xa3,0x00,0x00,0x00] +// GFX11: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0xbe,0xd5,0xa3,0x00,0x00,0x00] -// SICI: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x42,0x00,0x7e,0xd2,0x04,0x00,0x00] -// GFX89: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x38,0x00,0x7e,0xd2,0x04,0x00,0x00] v_trunc_f32_e32 v0, 1234 +// SICI: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x42,0x00,0x7e,0xd2,0x04,0x00,0x00] +// GFX89: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x38,0x00,0x7e,0xd2,0x04,0x00,0x00] +// GFX12XX: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x42,0x00,0x7e,0xd2,0x04,0x00,0x00] +// GFX11: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x42,0x00,0x7e,0xd2,0x04,0x00,0x00] -// SICI: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x7c,0x00,0x7e,0xd2,0x04,0x00,0x00] -// GFX89: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x64,0x00,0x7e,0xd2,0x04,0x00,0x00] v_fract_f64_e32 v[0:1], 1234 +// SICI: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x7c,0x00,0x7e,0xd2,0x04,0x00,0x00] +// GFX89: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x64,0x00,0x7e,0xd2,0x04,0x00,0x00] +// GFX12XX: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x7c,0x00,0x7e,0xd2,0x04,0x00,0x00] +// GFX11: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x7c,0x00,0x7e,0xd2,0x04,0x00,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: literal operands are not supported -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: literal operands are not supported v_trunc_f32_e64 v0, 1234 +// GFX12XX: v_trunc_f32_e64 v0, 0x4d2 ; encoding: [0x00,0x00,0xa1,0xd5,0xff,0x00,0x00,0x00,0xd2,0x04,0x00,0x00] +// NOSICI: :[[@LINE-2]]:21: error: literal operands are not supported +// NOGFX89: :[[@LINE-3]]:21: error: literal operands are not supported +// GFX11: v_trunc_f32_e64 v0, 0x4d2 ; encoding: [0x00,0x00,0xa1,0xd5,0xff,0x00,0x00,0x00,0xd2,0x04,0x00,0x00] +// NOSICIVI: :[[@LINE-1]]:21: error: literal operands are not supported -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: literal operands are not supported -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: literal operands are not supported v_fract_f64_e64 v[0:1], 1234 +// GFX12XX: v_fract_f64_e64 v[0:1], 0x4d2 ; encoding: [0x00,0x00,0xbe,0xd5,0xff,0x00,0x00,0x00,0xd2,0x04,0x00,0x00] +// NOSICI: :[[@LINE-2]]:25: error: literal operands are not supported +// NOGFX89: :[[@LINE-3]]:25: error: literal operands are not supported +// GFX11: v_fract_f64_e64 v[0:1], 0x4d2 ; encoding: [0x00,0x00,0xbe,0xd5,0xff,0x00,0x00,0x00,0xd2,0x04,0x00,0x00] +// NOSICIVI: :[[@LINE-1]]:25: error: literal operands are not supported -// SICI: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x42,0x00,0x7e,0xcf,0x2b,0xff,0xff] -// GFX89: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x38,0x00,0x7e,0xcf,0x2b,0xff,0xff] v_trunc_f32_e32 v0, -54321 +// SICI: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x42,0x00,0x7e,0xcf,0x2b,0xff,0xff] +// GFX89: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x38,0x00,0x7e,0xcf,0x2b,0xff,0xff] +// GFX12XX: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x42,0x00,0x7e,0xcf,0x2b,0xff,0xff] +// GFX11: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x42,0x00,0x7e,0xcf,0x2b,0xff,0xff] -// SICI: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x7c,0x00,0x7e,0xcf,0x2b,0xff,0xff] -// GFX89: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x64,0x00,0x7e,0xcf,0x2b,0xff,0xff] v_fract_f64_e32 v[0:1], -54321 +// SICI: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x7c,0x00,0x7e,0xcf,0x2b,0xff,0xff] +// GFX89: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x64,0x00,0x7e,0xcf,0x2b,0xff,0xff] +// GFX12XX: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x7c,0x00,0x7e,0xcf,0x2b,0xff,0xff] +// GFX11: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x7c,0x00,0x7e,0xcf,0x2b,0xff,0xff] -// SICI: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x42,0x00,0x7e,0xef,0xbe,0xad,0xde] -// GFX89: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x38,0x00,0x7e,0xef,0xbe,0xad,0xde] v_trunc_f32_e32 v0, 0xdeadbeef +// SICI: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x42,0x00,0x7e,0xef,0xbe,0xad,0xde] +// GFX89: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x38,0x00,0x7e,0xef,0xbe,0xad,0xde] +// GFX12XX: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x42,0x00,0x7e,0xef,0xbe,0xad,0xde] +// GFX11: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x42,0x00,0x7e,0xef,0xbe,0xad,0xde] -// SICI: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x7c,0x00,0x7e,0xef,0xbe,0xad,0xde] -// GFX89: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x64,0x00,0x7e,0xef,0xbe,0xad,0xde] v_fract_f64_e32 v[0:1], 0xdeadbeef +// SICI: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x7c,0x00,0x7e,0xef,0xbe,0xad,0xde] +// GFX89: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x64,0x00,0x7e,0xef,0xbe,0xad,0xde] +// GFX12XX: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x7c,0x00,0x7e,0xef,0xbe,0xad,0xde] +// GFX11: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x7c,0x00,0x7e,0xef,0xbe,0xad,0xde] -// SICI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x38,0x00,0x7e] v_trunc_f32_e32 v0, 0xffffffff +// SICI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xff,0xff] -// GFX89: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0xff,0xff] v_fract_f64_e32 v[0:1], 0xffffffff +// SICI: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xff,0xff] +// GFX89: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0xff,0xff] +// GFX12XX: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xff,0xff] +// GFX11: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xff,0xff] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32_e32 v0, 0x123456789abcdef0 +// NOGCN: :[[@LINE-1]]:21: error: invalid operand for instruction -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_fract_f64_e32 v[0:1], 0x123456789abcdef0 +// NOSICI: :[[@LINE-1]]:25: error: invalid operand for instruction +// NOGFX89: :[[@LINE-2]]:25: error: invalid operand for instruction +// GFX1250: v_fract_f64_e32 v[0:1], 0x123456789abcdef0 ; encoding: [0xfe,0x7c,0x00,0x7e,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] +// NOGFX11: :[[@LINE-4]]:25: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:25: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:25: error: invalid operand for instruction -// SICI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] -// GFX89: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x38,0x00,0x7e] v_trunc_f32_e32 v0, 0xffffffffffffffff +// SICI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x7c,0x00,0x7e] -// GFX89: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x64,0x00,0x7e] v_fract_f64_e32 v[0:1], 0xffffffffffffffff +// SICI: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x7c,0x00,0x7e] +// GFX89: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x7c,0x00,0x7e] +// GFX11: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x7c,0x00,0x7e] + +v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], 1 ; encoding: [0x08,0x40,0x44,0xcc,0x00,0x09,0x06,0x1a] +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-3]]:54: error: invalid operand for instruction +// NOGFX12: :[[@LINE-4]]:54: error: invalid operand for instruction +// NOGFX1250: :[[@LINE-5]]:54: error: invalid operand for instruction + +v_cos_f16_e32 v5.l, 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +// GFX11: v_cos_f16_e32 v5.l, 1 ; encoding: [0x81,0xc2,0x0a,0x7e] +// GFX1250: v_cos_f16_e32 v5.l, 1 ; encoding: [0x81,0xc2,0x0a,0x7e] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_cos_f16_e32 v5.l, lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +// GFX11: v_cos_f16_e32 v5.l, lit(0x1) ; encoding: [0xff,0xc2,0x0a,0x7e,0x01,0x00,0x00,0x00] +// GFX1250: v_cos_f16_e32 v5.l, lit(0x1) ; encoding: [0xff,0xc2,0x0a,0x7e,0x01,0x00,0x00,0x00] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_tanh_bf16 v5, 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_tanh_bf16_e32 v5, 1 ; encoding: [0x81,0x94,0x0a,0x7e] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_tanh_bf16 v5, lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_tanh_bf16_e32 v5, lit(0x1) ; encoding: [0xff,0x94,0x0a,0x7e,0x01,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_trunc_f32_e32 v0, 1 +// SICI: v_trunc_f32_e32 v0, 1 ; encoding: [0x81,0x42,0x00,0x7e] +// GFX89: v_trunc_f32_e32 v0, 1 ; encoding: [0x81,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 1 ; encoding: [0x81,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 1 ; encoding: [0x81,0x42,0x00,0x7e] + +v_trunc_f32_e32 v0, lit(1) +// SICI: v_trunc_f32_e32 v0, lit(0x1) ; encoding: [0xff,0x42,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX89: v_trunc_f32_e32 v0, lit(0x1) ; encoding: [0xff,0x38,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX12XX: v_trunc_f32_e32 v0, lit(0x1) ; encoding: [0xff,0x42,0x00,0x7e,0x01,0x00,0x00,0x00] +// GFX11: v_trunc_f32_e32 v0, lit(0x1) ; encoding: [0xff,0x42,0x00,0x7e,0x01,0x00,0x00,0x00] + +v_dot2_bf16_bf16 v5.l, v1, v2, 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_bf16_bf16 v5.l, v1, v2, 1 ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0x06,0x02] +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_dot2_bf16_bf16 v5.l, v1, v2, lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_bf16_bf16 v5.l, v1, v2, lit(0x1) ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xfe,0x03,0x01,0x00,0x00,0x00] +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_dot2_f32_f16 v5, v1, 1, v2 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_f32_f16 v5, v1, 1, v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0x03,0x09,0x1c] +// GFX12: v_dot2_f32_f16 v5, v1, 1, v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0x03,0x09,0x1c] +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_dot2_f32_f16 v5, v1, lit(1), v2 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_dot2_f32_f16 v5, v1, lit(0x1), v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xff,0x09,0x1c,0x01,0x00,0x00,0x00] +// GFX12: v_dot2_f32_f16 v5, v1, lit(0x1), v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xff,0x09,0x1c,0x01,0x00,0x00,0x00] +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_cvt_pk_fp8_f16 v1.l, 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_cvt_pk_fp8_f16 v1.l, 1 ; encoding: [0x01,0x00,0x72,0xd7,0xff,0x00,0x00,0x00,0x01,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_cvt_pk_fp8_f16 v1.l, lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_cvt_pk_fp8_f16 v1.l, lit(0x1) ; encoding: [0x01,0x00,0x72,0xd7,0xff,0x00,0x00,0x00,0x01,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU //---------------------------------------------------------------------------// // int literal, expected int operand //---------------------------------------------------------------------------// -// SICI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 0 +// GFX8PLUS: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x26] v_and_b32_e32 v0, 0, v1 +// SICI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0x80,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0x80,0x02,0x02,0x00] v_and_b32_e64 v0, 0, v1 +// SICI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0x80,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0x80,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0x80,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0x80,0x02,0x02,0x00] -// SICI: s_mov_b64 s[0:1], -13 ; encoding: [0xcd,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], -13 ; encoding: [0xcd,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], -13 +// GFX8PLUS: s_mov_b64 s[0:1], -13 ; encoding: [0xcd,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], -13 ; encoding: [0xcd,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x26] v_and_b32_e32 v0, -13, v1 +// SICI: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xcd,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xcd,0x02,0x02,0x00] v_and_b32_e64 v0, -13, v1 +// SICI: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xcd,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xcd,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xcd,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xcd,0x02,0x02,0x00] -// SICI: s_mov_b64 s[0:1], 35 ; encoding: [0xa3,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], 35 ; encoding: [0xa3,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 35 +// GFX8PLUS: s_mov_b64 s[0:1], 35 ; encoding: [0xa3,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], 35 ; encoding: [0xa3,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x26] v_and_b32_e32 v0, 35, v1 +// SICI: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x36] -// SICI: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xa3,0x02,0x02,0x00] -// GFX89: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xa3,0x02,0x02,0x00] v_and_b32_e64 v0, 35, v1 +// SICI: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xa3,0x02,0x02,0x00] +// GFX89: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xa3,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xa3,0x02,0x02,0x00] +// GFX11: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xa3,0x02,0x02,0x00] -// SICI: s_mov_b64 s[0:1], 0x4d2 ; encoding: [0xff,0x04,0x80,0xbe,0xd2,0x04,0x00,0x00] -// GFX89: s_mov_b64 s[0:1], 0x4d2 ; encoding: [0xff,0x01,0x80,0xbe,0xd2,0x04,0x00,0x00] s_mov_b64_e32 s[0:1], 1234 +// GFX8PLUS: s_mov_b64 s[0:1], 0x4d2 ; encoding: [0xff,0x01,0x80,0xbe,0xd2,0x04,0x00,0x00] +// SICI: s_mov_b64 s[0:1], 0x4d2 ; encoding: [0xff,0x04,0x80,0xbe,0xd2,0x04,0x00,0x00] -// SICI: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x36,0xd2,0x04,0x00,0x00] -// GFX89: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x26,0xd2,0x04,0x00,0x00] v_and_b32_e32 v0, 1234, v1 +// SICI: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x36,0xd2,0x04,0x00,0x00] +// GFX89: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x26,0xd2,0x04,0x00,0x00] +// GFX12XX: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x36,0xd2,0x04,0x00,0x00] +// GFX11: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x36,0xd2,0x04,0x00,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: literal operands are not supported -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: literal operands are not supported v_and_b32_e64 v0, 1234, v1 +// GFX12XX: v_and_b32_e64 v0, 0x4d2, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xff,0x02,0x02,0x00,0xd2,0x04,0x00,0x00] +// NOSICI: :[[@LINE-2]]:19: error: literal operands are not supported +// NOGFX89: :[[@LINE-3]]:19: error: literal operands are not supported +// GFX11: v_and_b32_e64 v0, 0x4d2, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xff,0x02,0x02,0x00,0xd2,0x04,0x00,0x00] +// NOSICIVI: :[[@LINE-1]]:19: error: literal operands are not supported -// SICI: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x04,0x80,0xbe,0xcf,0x2b,0xff,0xff] -// GFX89: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x01,0x80,0xbe,0xcf,0x2b,0xff,0xff] s_mov_b64_e32 s[0:1], -54321 +// SICI: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x04,0x80,0xbe,0xcf,0x2b,0xff,0xff] +// GFX89: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x01,0x80,0xbe,0xcf,0x2b,0xff,0xff] +// GFX11: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x01,0x80,0xbe,0xcf,0x2b,0xff,0xff] +// GFX12: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x01,0x80,0xbe,0xcf,0x2b,0xff,0xff] +// GFX1250: s_mov_b64 s[0:1], 0xffffffffffff2bcf ; encoding: [0xfe,0x01,0x80,0xbe,0xcf,0x2b,0xff,0xff,0xff,0xff,0xff,0xff] -// SICI: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x36,0xcf,0x2b,0xff,0xff] -// GFX89: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x26,0xcf,0x2b,0xff,0xff] v_and_b32_e32 v0, -54321, v1 +// SICI: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x36,0xcf,0x2b,0xff,0xff] +// GFX89: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x26,0xcf,0x2b,0xff,0xff] +// GFX12XX: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x36,0xcf,0x2b,0xff,0xff] +// GFX11: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x36,0xcf,0x2b,0xff,0xff] -// SICI: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x04,0x80,0xbe,0xef,0xbe,0xad,0xde] -// GFX89: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x01,0x80,0xbe,0xef,0xbe,0xad,0xde] s_mov_b64_e32 s[0:1], 0xdeadbeef +// SICI: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x04,0x80,0xbe,0xef,0xbe,0xad,0xde] +// GFX89: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x01,0x80,0xbe,0xef,0xbe,0xad,0xde] +// GFX11: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x01,0x80,0xbe,0xef,0xbe,0xad,0xde] +// GFX12: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x01,0x80,0xbe,0xef,0xbe,0xad,0xde] +// GFX1250: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xfe,0x01,0x80,0xbe,0xef,0xbe,0xad,0xde,0x00,0x00,0x00,0x00] -// SICI: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x36,0xef,0xbe,0xad,0xde] -// GFX89: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x26,0xef,0xbe,0xad,0xde] v_and_b32_e32 v0, 0xdeadbeef, v1 +// SICI: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x36,0xef,0xbe,0xad,0xde] +// GFX89: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x26,0xef,0xbe,0xad,0xde] +// GFX12XX: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x36,0xef,0xbe,0xad,0xde] +// GFX11: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x36,0xef,0xbe,0xad,0xde] -// SICI: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x04,0x80,0xbe,0xff,0xff,0xff,0xff] -// GFX89: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x01,0x80,0xbe,0xff,0xff,0xff,0xff] s_mov_b64_e32 s[0:1], 0xffffffff +// SICI: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x04,0x80,0xbe,0xff,0xff,0xff,0xff] +// GFX89: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x01,0x80,0xbe,0xff,0xff,0xff,0xff] +// GFX11: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x01,0x80,0xbe,0xff,0xff,0xff,0xff] +// GFX12: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x01,0x80,0xbe,0xff,0xff,0xff,0xff] +// GFX1250: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xfe,0x01,0x80,0xbe,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00] -// SICI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x26] v_and_b32_e32 v0, 0xffffffff, v1 +// SICI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64_e32 s[0:1], 0x123456789abcdef0 +// NOSICI: :[[@LINE-1]]:23: error: invalid operand for instruction +// NOGFX89: :[[@LINE-2]]:23: error: invalid operand for instruction +// GFX1250: s_mov_b64 s[0:1], 0x123456789abcdef0 ; encoding: [0xfe,0x01,0x80,0xbe,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] +// NOGFX11: :[[@LINE-4]]:23: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:23: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:23: error: invalid operand for instruction -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_and_b32_e32 v0, 0x123456789abcdef0, v1 +// NOGCN: :[[@LINE-1]]:19: error: invalid operand for instruction -// SICI: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x04,0x80,0xbe] -// GFX89: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 0xffffffffffffffff +// GFX8PLUS: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x04,0x80,0xbe] -// SICI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] -// GFX89: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x26] v_and_b32_e32 v0, 0xffffffffffffffff, v1 +// SICI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36] + +v_not_b16 v5.l, 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_not_b16_e32 v5.l, 1 ; encoding: [0x81,0xd2,0x0a,0x7e] +// GFX1250: v_not_b16_e32 v5.l, 1 ; encoding: [0x81,0xd2,0x0a,0x7e] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +v_not_b16 v5.l, lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_not_b16_e32 v5.l, lit(0x1) ; encoding: [0xff,0xd2,0x0a,0x7e,0x01,0x00,0x00,0x00] +// GFX1250: v_not_b16_e32 v5.l, lit(0x1) ; encoding: [0xff,0xd2,0x0a,0x7e,0x01,0x00,0x00,0x00] +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode + +s_mov_b64 s[0:1], 1 +// GFX8PLUS: s_mov_b64 s[0:1], 1 ; encoding: [0x81,0x01,0x80,0xbe] +// SICI: s_mov_b64 s[0:1], 1 ; encoding: [0x81,0x04,0x80,0xbe] + +s_mov_b64 s[0:1], lit(1) +// SICI: s_mov_b64 s[0:1], lit(0x1) ; encoding: [0xff,0x04,0x80,0xbe,0x01,0x00,0x00,0x00] +// GFX89: s_mov_b64 s[0:1], lit(0x1) ; encoding: [0xff,0x01,0x80,0xbe,0x01,0x00,0x00,0x00] +// GFX11: s_mov_b64 s[0:1], lit(0x1) ; encoding: [0xff,0x01,0x80,0xbe,0x01,0x00,0x00,0x00] +// GFX12: s_mov_b64 s[0:1], lit(0x1) ; encoding: [0xff,0x01,0x80,0xbe,0x01,0x00,0x00,0x00] +// GFX1250: s_mov_b64 s[0:1], lit(0x1) ; encoding: [0xfe,0x01,0x80,0xbe,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00] + +v_and_b32_e32 v0, 1, v1 +// SICI: v_and_b32_e32 v0, 1, v1 ; encoding: [0x81,0x02,0x00,0x36] +// GFX89: v_and_b32_e32 v0, 1, v1 ; encoding: [0x81,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 1, v1 ; encoding: [0x81,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 1, v1 ; encoding: [0x81,0x02,0x00,0x36] + +v_and_b32_e32 v0, lit(1), v1 +// SICI: v_and_b32_e32 v0, lit(0x1), v1 ; encoding: [0xff,0x02,0x00,0x36,0x01,0x00,0x00,0x00] +// GFX89: v_and_b32_e32 v0, lit(0x1), v1 ; encoding: [0xff,0x02,0x00,0x26,0x01,0x00,0x00,0x00] +// GFX12XX: v_and_b32_e32 v0, lit(0x1), v1 ; encoding: [0xff,0x02,0x00,0x36,0x01,0x00,0x00,0x00] +// GFX11: v_and_b32_e32 v0, lit(0x1), v1 ; encoding: [0xff,0x02,0x00,0x36,0x01,0x00,0x00,0x00] + +v_pk_add_u16 v5, exec_lo, 1 +// GFX12XX: v_pk_add_u16 v5, exec_lo, 1 ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0x02,0x01,0x18] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_pk_add_u16 v5, exec_lo, 1 ; encoding: [0x05,0x40,0x8a,0xd3,0x7e,0x02,0x01,0x18] +// GFX11: v_pk_add_u16 v5, exec_lo, 1 ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0x02,0x01,0x18] +// NOVI: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_pk_add_u16 v5, exec_lo, lit(1) +// GFX12XX: v_pk_add_u16 v5, exec_lo, lit(0x1) ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0xfe,0x01,0x18,0x01,0x00,0x00,0x00] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_pk_add_u16 v5, exec_lo, lit(0x1) ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0xfe,0x01,0x18,0x01,0x00,0x00,0x00] +// NOVI: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX9: :[[@LINE-5]]:31: error: invalid operand (violates constant bus restrictions) + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 1 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], 1 ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0x06,0x02] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU + +v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], lit(1) +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX1250: v_perm_pk16_b6_u4 v[2:4], v4, v[4:5], lit(0x1) ; encoding: [0x02,0x00,0x42,0xd6,0x04,0x09,0xfe,0x03,0x01,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU //---------------------------------------------------------------------------// // 1/(2*PI) //---------------------------------------------------------------------------// -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32_e32 v0, 0x3fc45f306dc9c882 +// NOGCN: :[[@LINE-1]]:21: error: invalid operand for instruction -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX89: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e] v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882 +// GFX89: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x7c,0x00,0x7e] +// NOSICI: :[[@LINE-3]]:25: error: invalid operand for instruction +// GFX11: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x7c,0x00,0x7e] +// NOSICIVI: :[[@LINE-2]]:25: error: invalid operand for instruction -// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] -// GFX89: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e] v_trunc_f32_e32 v0, 0x3e22f983 +// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX89: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x42,0x00,0x7e] -// SICI: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x7c,0x00,0x7e,0x83,0xf9,0x22,0x3e] -// GFX89: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x64,0x00,0x7e,0x83,0xf9,0x22,0x3e] v_fract_f64_e32 v[0:1], 0x3e22f983 +// SICI: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x7c,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX89: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x64,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX12XX: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x7c,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX11: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x7c,0x00,0x7e,0x83,0xf9,0x22,0x3e] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32_e64 v0, 0x3fc45f306dc9c882 +// NOGCN: :[[@LINE-1]]:21: error: invalid operand for instruction -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX89: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00] v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882 +// GFX89: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00] +// GFX12XX: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0xbe,0xd5,0xf8,0x00,0x00,0x00] +// NOSICI: :[[@LINE-3]]:25: error: invalid operand for instruction +// GFX11: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0xbe,0xd5,0xf8,0x00,0x00,0x00] +// NOSICIVI: :[[@LINE-2]]:25: error: invalid operand for instruction -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: literal operands are not supported -// GFX89: v_trunc_f32_e64 v0, 0.15915494 ; encoding: [0x00,0x00,0x5c,0xd1,0xf8,0x00,0x00,0x00] v_trunc_f32_e64 v0, 0x3e22f983 +// GFX89: v_trunc_f32_e64 v0, 0.15915494 ; encoding: [0x00,0x00,0x5c,0xd1,0xf8,0x00,0x00,0x00] +// GFX12XX: v_trunc_f32_e64 v0, 0.15915494 ; encoding: [0x00,0x00,0xa1,0xd5,0xf8,0x00,0x00,0x00] +// NOSICI: :[[@LINE-3]]:21: error: literal operands are not supported +// GFX11: v_trunc_f32_e64 v0, 0.15915494 ; encoding: [0x00,0x00,0xa1,0xd5,0xf8,0x00,0x00,0x00] +// NOSICIVI: :[[@LINE-2]]:21: error: literal operands are not supported -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: literal operands are not supported -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: literal operands are not supported v_fract_f64_e64 v[0:1], 0x3e22f983 +// GFX12XX: v_fract_f64_e64 v[0:1], 0x3e22f983 ; encoding: [0x00,0x00,0xbe,0xd5,0xff,0x00,0x00,0x00,0x83,0xf9,0x22,0x3e] +// NOSICI: :[[@LINE-2]]:25: error: literal operands are not supported +// NOGFX89: :[[@LINE-3]]:25: error: literal operands are not supported +// GFX11: v_fract_f64_e64 v[0:1], 0x3e22f983 ; encoding: [0x00,0x00,0xbe,0xd5,0xff,0x00,0x00,0x00,0x83,0xf9,0x22,0x3e] +// NOSICIVI: :[[@LINE-1]]:25: error: literal operands are not supported -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX89: s_mov_b64 s[0:1], 0.15915494309189532 ; encoding: [0xf8,0x01,0x80,0xbe] s_mov_b64_e32 s[0:1], 0.159154943091895317852646485335 +// GFX8PLUS: s_mov_b64 s[0:1], 0.15915494309189532 ; encoding: [0xf8,0x01,0x80,0xbe] +// NOSICI: :[[@LINE-2]]:23: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-2]]:23: error: invalid operand for instruction -// SICI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xff,0x02,0x00,0x36,0x83,0xf9,0x22,0x3e] -// GFX89: v_and_b32_e32 v0, 0.15915494, v1 ; encoding: [0xf8,0x02,0x00,0x26] v_and_b32_e32 v0, 0.159154943091895317852646485335, v1 +// SICI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xff,0x02,0x00,0x36,0x83,0xf9,0x22,0x3e] +// GFX89: v_and_b32_e32 v0, 0.15915494, v1 ; encoding: [0xf8,0x02,0x00,0x26] +// GFX12XX: v_and_b32_e32 v0, 0.15915494, v1 ; encoding: [0xf8,0x02,0x00,0x36] +// GFX11: v_and_b32_e32 v0, 0.15915494, v1 ; encoding: [0xf8,0x02,0x00,0x36] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: literal operands are not supported -// GFX89: v_and_b32_e64 v0, 0.15915494, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf8,0x02,0x02,0x00] v_and_b32_e64 v0, 0.159154943091895317852646485335, v1 +// GFX89: v_and_b32_e64 v0, 0.15915494, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf8,0x02,0x02,0x00] +// GFX12XX: v_and_b32_e64 v0, 0.15915494, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf8,0x02,0x02,0x00] +// NOSICI: :[[@LINE-3]]:19: error: literal operands are not supported +// GFX11: v_and_b32_e64 v0, 0.15915494, v1 ; encoding: [0x00,0x00,0x1b,0xd5,0xf8,0x02,0x02,0x00] +// NOSICIVI: :[[@LINE-2]]:19: error: literal operands are not supported -// SICI: v_fract_f64_e32 v[0:1], 0x3fc45f30 ; encoding: [0xff,0x7c,0x00,0x7e,0x30,0x5f,0xc4,0x3f] -// GFX89: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e] v_fract_f64 v[0:1], 0.159154943091895317852646485335 +// SICI: v_fract_f64_e32 v[0:1], 0x3fc45f30 ; encoding: [0xff,0x7c,0x00,0x7e,0x30,0x5f,0xc4,0x3f] +// GFX89: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e] +// GFX12XX: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x7c,0x00,0x7e] +// NOSICI: :[[@LINE-4]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero +// GFX11: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x7c,0x00,0x7e] +// NOSICIVI: :[[@LINE-3]]:1: warning: Can't encode literal as exact 64-bit floating-point operand. Low 32-bits will be set to zero -// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] -// GFX89: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e] v_trunc_f32 v0, 0.159154943091895317852646485335 +// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX89: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e] +// GFX12XX: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x42,0x00,0x7e] +// GFX11: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x42,0x00,0x7e] + +v_trunc_f32 v0, lit(0.159154943091895317852646485335) +// SICI: v_trunc_f32_e32 v0, lit(0x3e22f983) ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX89: v_trunc_f32_e32 v0, lit(0x3e22f983) ; encoding: [0xff,0x38,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX12XX: v_trunc_f32_e32 v0, lit(0x3e22f983) ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] +// GFX11: v_trunc_f32_e32 v0, lit(0x3e22f983) ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e] //---------------------------------------------------------------------------// // integer literal truncation checks //---------------------------------------------------------------------------// -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s0, 0x101ffffffff +// NOGCN: :[[@LINE-1]]:15: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s0, 0x1000000001 +// NOGCN: :[[@LINE-1]]:15: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s0, 0x1000000fff +// NOGCN: :[[@LINE-1]]:15: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32 v0, 0x1fffffffff0 +// NOGCN: :[[@LINE-1]]:17: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32 v0, 0x100000001 +// NOGCN: :[[@LINE-1]]:17: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f32 v0, 0x1fffffff000 +// NOGCN: :[[@LINE-1]]:17: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64 s[0:1], 0x101ffffffff +// NOSICI: :[[@LINE-1]]:19: error: invalid operand for instruction +// NOGFX89: :[[@LINE-2]]:19: error: invalid operand for instruction +// GFX1250: s_mov_b64 s[0:1], 0x101ffffffff ; encoding: [0xfe,0x01,0x80,0xbe,0xff,0xff,0xff,0xff,0x01,0x01,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:19: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:19: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:19: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64 s[0:1], 0x1000000001 +// NOSICI: :[[@LINE-1]]:19: error: invalid operand for instruction +// NOGFX89: :[[@LINE-2]]:19: error: invalid operand for instruction +// GFX1250: s_mov_b64 s[0:1], 0x1000000001 ; encoding: [0xfe,0x01,0x80,0xbe,0x01,0x00,0x00,0x00,0x10,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:19: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:19: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:19: error: invalid operand for instruction -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b64 s[0:1], 0x1000000fff +// NOSICI: :[[@LINE-1]]:19: error: invalid operand for instruction +// NOGFX89: :[[@LINE-2]]:19: error: invalid operand for instruction +// GFX1250: s_mov_b64 s[0:1], 0x1000000fff ; encoding: [0xfe,0x01,0x80,0xbe,0xff,0x0f,0x00,0x00,0x10,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-4]]:19: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:19: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:19: error: invalid operand for instruction -// NOGFX89: :[[@LINE+3]]:{{[0-9]+}}: error: invalid operand for instruction -// NOSI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOCIVI: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f64 v[0:1], 0x1fffffffff0 +// NOGFX89: :[[@LINE-1]]:21: error: invalid operand for instruction +// GFX1250: v_trunc_f64_e32 v[0:1], 0x1fffffffff0 ; encoding: [0xfe,0x2e,0x00,0x7e,0xf0,0xff,0xff,0xff,0xff,0x01,0x00,0x00] +// NOSI: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOCI: :[[@LINE-4]]:21: error: invalid operand for instruction +// NOGFX11: :[[@LINE-5]]:21: error: invalid operand for instruction +// NOGFX12: :[[@LINE-6]]:21: error: invalid operand for instruction +// NOCIVI: :[[@LINE-4]]:21: error: invalid operand for instruction -// NOGFX89: :[[@LINE+3]]:{{[0-9]+}}: error: invalid operand for instruction -// NOSI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOCIVI: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f64 v[0:1], 0x100000001 +// NOGFX89: :[[@LINE-1]]:21: error: invalid operand for instruction +// GFX1250: v_trunc_f64_e32 v[0:1], 0x100000001 ; encoding: [0xfe,0x2e,0x00,0x7e,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00] +// NOSI: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOCI: :[[@LINE-4]]:21: error: invalid operand for instruction +// NOGFX11: :[[@LINE-5]]:21: error: invalid operand for instruction +// NOGFX12: :[[@LINE-6]]:21: error: invalid operand for instruction +// NOCIVI: :[[@LINE-4]]:21: error: invalid operand for instruction -// NOGFX89: :[[@LINE+3]]:{{[0-9]+}}: error: invalid operand for instruction -// NOSI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOCIVI: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_trunc_f64 v[0:1], 0x1fffffff000 +// NOGFX89: :[[@LINE-1]]:21: error: invalid operand for instruction +// GFX1250: v_trunc_f64_e32 v[0:1], 0x1fffffff000 ; encoding: [0xfe,0x2e,0x00,0x7e,0x00,0xf0,0xff,0xff,0xff,0x01,0x00,0x00] +// NOSI: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOCI: :[[@LINE-4]]:21: error: invalid operand for instruction +// NOGFX11: :[[@LINE-5]]:21: error: invalid operand for instruction +// NOGFX12: :[[@LINE-6]]:21: error: invalid operand for instruction +// NOCIVI: :[[@LINE-4]]:21: error: invalid operand for instruction //---------------------------------------------------------------------------// // named inline values: scc, vccz, execz //---------------------------------------------------------------------------// +buffer_atomic_add v0, off, s[0:3], scc offset:4095 // SICI: buffer_atomic_add v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x00,0x00,0xfd] // GFX89: buffer_atomic_add v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xfd] -buffer_atomic_add v0, off, s[0:3], scc offset:4095 +// GFX12XX: buffer_atomic_add_u32 v0, off, s[0:3], src_scc offset:4095 ; encoding: [0x7d,0x40,0x0d,0xc4,0x00,0x00,0x80,0x00,0x00,0xff,0x0f,0x00] +// GFX11: buffer_atomic_add_u32 v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x00,0x00,0xfd] -// SICI: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81] -// GFX89: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81] s_add_i32 s0, vccz, s0 +// SICI: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81] +// GFX89: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81] +// NOGFX11: :[[@LINE-3]]:15: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:15: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:15: error: src_vccz register not available on this GPU -// SICI: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81] -// GFX89: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81] s_add_i32 s0, execz, s0 +// SICI: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81] +// GFX89: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81] +// NOGFX11: :[[@LINE-3]]:15: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:15: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:15: error: src_execz register not available on this GPU -// SICI: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81] -// GFX89: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81] s_add_i32 s0, scc, s0 +// SICI: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81] +// GFX89: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81] +// GFX12XX: s_add_co_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81] +// GFX11: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81] -// SICI: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x87] -// GFX89: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_vccz +// SICI: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x87] +// GFX89: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x86] +// NOGFX11: :[[@LINE-3]]:27: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:27: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:27: error: src_vccz register not available on this GPU -// SICI: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x87] -// GFX89: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_execz +// SICI: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x87] +// GFX89: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x86] +// NOGFX11: :[[@LINE-3]]:27: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:27: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:27: error: src_execz register not available on this GPU -// SICI: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x87] -// GFX89: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_scc +// SICI: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x87] +// GFX89: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x86] +// GFX12XX: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x8b] +// GFX11: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x8b] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// GFX89: v_add_u16_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x4c] v_add_u16 v0, vccz, v0 +// GFX89: v_add_u16_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x4c] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-2]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX9: v_add_u16_sdwa v0, src_scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xfd,0x06,0x86,0x06] v_add_u16_sdwa v0, scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u16_sdwa v0, src_scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xfd,0x06,0x86,0x06] +// NOVI: :[[@LINE-3]]:20: error: invalid operand for instruction +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX9: v_add_u16_sdwa v0, v0, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfa,0x01,0x4c,0x00,0x06,0x06,0x86] v_add_u16_sdwa v0, v0, scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u16_sdwa v0, v0, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfa,0x01,0x4c,0x00,0x06,0x06,0x86] +// NOVI: :[[@LINE-3]]:24: error: invalid operand for instruction +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_add_u32_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x68] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_add_u32 v0, execz, v0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u32_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x68] +// NOVI: :[[@LINE-3]]:1: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-4]]:15: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-5]]:15: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-6]]:15: error: src_execz register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_add_u32_e64 v0, src_scc, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xfd,0x00,0x02,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_add_u32_e64 v0, scc, v0 +// GFX12XX: v_add_nc_u32_e64 v0, src_scc, v0 ; encoding: [0x00,0x00,0x25,0xd5,0xfd,0x00,0x02,0x00] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u32_e64 v0, src_scc, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xfd,0x00,0x02,0x00] +// GFX11: v_add_nc_u32_e64 v0, src_scc, v0 ; encoding: [0x00,0x00,0x25,0xd5,0xfd,0x00,0x02,0x00] +// NOVI: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// SICI: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0x44,0x7d] -// GFX89: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0xc4,0x7d] v_cmp_eq_i64 vcc, scc, v[0:1] +// SICI: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0x44,0x7d] +// GFX89: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0xc4,0x7d] +// NOGFX11: :[[@LINE-3]]:1: error: operands are not valid for this GPU or mode +// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// GFX89: v_max_f16_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x5a] v_max_f16 v0, execz, v0 +// GFX89: v_max_f16_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x5a] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-3]]:15: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:15: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:15: error: src_execz register not available on this GPU +// NOSICIVI: :[[@LINE-2]]:1: error: instruction not supported on this GPU -// SICI: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x20] -// GFX89: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x16] v_max_f32 v0, vccz, v0 +// SICI: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x20] +// GFX89: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x16] +// NOGFX11: :[[@LINE-3]]:15: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:15: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:15: error: src_vccz register not available on this GPU -// SICI: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0xce,0xd2,0xfd,0x00,0x02,0x00] -// GFX89: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xfd,0x00,0x02,0x00] v_max_f64 v[0:1], scc, v[0:1] +// SICI: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0xce,0xd2,0xfd,0x00,0x02,0x00] +// GFX89: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xfd,0x00,0x02,0x00] +// GFX12XX: v_max_num_f64_e32 v[0:1], src_scc, v[0:1] ; encoding: [0xfd,0x00,0x00,0x1c] +// GFX11: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0x2a,0xd7,0xfd,0x00,0x02,0x00] -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// GFX9: v_pk_add_f16 v0, src_execz, v0 ; encoding: [0x00,0x40,0x8f,0xd3,0xfc,0x00,0x02,0x18] v_pk_add_f16 v0, execz, v0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_pk_add_f16 v0, src_execz, v0 ; encoding: [0x00,0x40,0x8f,0xd3,0xfc,0x00,0x02,0x18] +// NOVI: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-4]]:18: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-5]]:18: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-6]]:18: error: src_execz register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// GFX89: v_ceil_f16_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x85,0xd1,0xfb,0x00,0x00,0x20] v_ceil_f16 v0, neg(vccz) +// GFX89: v_ceil_f16_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x85,0xd1,0xfb,0x00,0x00,0x20] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-3]]:20: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:20: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:20: error: src_vccz register not available on this GPU +// NOSICIVI: :[[@LINE-2]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// GFX89: v_ceil_f16_e64 v0, |src_scc| ; encoding: [0x00,0x01,0x85,0xd1,0xfd,0x00,0x00,0x00] v_ceil_f16 v0, abs(scc) +// GFX89: v_ceil_f16_e64 v0, |src_scc| ; encoding: [0x00,0x01,0x85,0xd1,0xfd,0x00,0x00,0x00] +// GFX12XX: v_ceil_f16_e64 v0, |src_scc| ; encoding: [0x00,0x01,0xdc,0xd5,0xfd,0x00,0x00,0x00] +// NOSICI: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// GFX11: v_ceil_f16_e64 v0, |src_scc| ; encoding: [0x00,0x01,0xdc,0xd5,0xfd,0x00,0x00,0x00] +// NOSICIVI: :[[@LINE-2]]:1: error: instruction not supported on this GPU -// NOSI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// CI: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x30,0xd3,0xfc,0x00,0x00,0x00] -// GFX89: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x58,0xd1,0xfc,0x00,0x00,0x00] v_ceil_f64 v[5:6], |execz| +// GFX89: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x58,0xd1,0xfc,0x00,0x00,0x00] +// CI: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x30,0xd3,0xfc,0x00,0x00,0x00] +// NOSI: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX11: :[[@LINE-4]]:21: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-5]]:21: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-6]]:21: error: src_execz register not available on this GPU -// NOSI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// CI: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x30,0xd3,0x6a,0x00,0x00,0x20] -// GFX89: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x20] v_ceil_f64 v[5:6], -vcc +// GFX89: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x20] +// CI: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x30,0xd3,0x6a,0x00,0x00,0x20] +// GFX11: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x20] +// GFX12: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x20] +// NOSI: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:12: error: invalid operand for instruction -// SICI: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x44,0xd3,0xfb,0x00,0x00,0x20] -// GFX89: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x20] v_ceil_f32 v0, -vccz +// SICI: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x44,0xd3,0xfb,0x00,0x00,0x20] +// GFX89: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x20] +// NOGFX11: :[[@LINE-3]]:17: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:17: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:17: error: src_vccz register not available on this GPU -// SICI: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x44,0xd3,0xfc,0x00,0x00,0x00] -// GFX89: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x5d,0xd1,0xfc,0x00,0x00,0x00] v_ceil_f32 v0, |execz| +// SICI: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x44,0xd3,0xfc,0x00,0x00,0x00] +// GFX89: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x5d,0xd1,0xfc,0x00,0x00,0x00] +// NOGFX11: :[[@LINE-3]]:17: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:17: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:17: error: src_execz register not available on this GPU -// NOSICI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX9: v_ceil_f16_sdwa v5, |src_vccz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfb,0x16,0xa6,0x00] v_ceil_f16_sdwa v5, |vccz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_ceil_f16_sdwa v5, |src_vccz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfb,0x16,0xa6,0x00] +// NOVI: :[[@LINE-3]]:22: error: invalid operand for instruction +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction -// GFX9: v_ceil_f16_sdwa v5, -src_scc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfd,0x16,0x96,0x00] v_ceil_f16_sdwa v5, -scc dst_sel:DWORD dst_unused:UNUSED_PRESERVE +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_ceil_f16_sdwa v5, -src_scc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfd,0x16,0x96,0x00] +// NOVI: :[[@LINE-3]]:22: error: invalid operand for instruction +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_ceil_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfb,0x16,0x86,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_ceil_f32_sdwa v5, vccz dst_sel:DWORD src0_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported +// GFX9: v_ceil_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfb,0x16,0x86,0x00] +// NOVI: :[[@LINE-3]]:21: error: invalid operand for instruction +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported -// GFX9: v_ceil_f32_sdwa v5, |src_execz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfc,0x16,0xa6,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction v_ceil_f32_sdwa v5, |execz| dst_sel:DWORD src0_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported +// GFX9: v_ceil_f32_sdwa v5, |src_execz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfc,0x16,0xa6,0x00] +// NOVI: :[[@LINE-3]]:22: error: invalid operand for instruction +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported //---------------------------------------------------------------------------// // named inline values: shared_base, shared_limit, private_base, etc //---------------------------------------------------------------------------// -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xeb] buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095 +// NOSICI: :[[@LINE-1]]:36: error: src_shared_base register not available on this GPU +// GFX9: buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xeb] +// GFX11: buffer_atomic_add_u32 v0, off, s[0:3], src_shared_base offset:4095 ; encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x00,0x00,0xeb] +// NOVI: :[[@LINE-4]]:36: error: src_shared_base register not available on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-6]]:1: error: operands are not valid for this GPU or mode +// NOSICIVI: :[[@LINE-1]]:36: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81] s_add_i32 s0, src_shared_base, s0 +// GFX12XX: s_add_co_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81] +// NOSICI: :[[@LINE-2]]:15: error: src_shared_base register not available on this GPU +// GFX9: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81] +// GFX11: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81] +// NOVI: :[[@LINE-5]]:15: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:15: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_limit register not available on this GPU -// GFX9: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81] s_add_i32 s0, src_shared_limit, s0 +// GFX12XX: s_add_co_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81] +// NOSICI: :[[@LINE-2]]:15: error: src_shared_limit register not available on this GPU +// GFX9: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81] +// GFX11: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81] +// NOVI: :[[@LINE-5]]:15: error: src_shared_limit register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:15: error: src_shared_limit register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_base register not available on this GPU -// GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81] s_add_i32 s0, src_private_base, s0 +// GFX12XX: s_add_co_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81] +// NOSICI: :[[@LINE-2]]:15: error: src_private_base register not available on this GPU +// GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81] +// GFX11: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81] +// NOVI: :[[@LINE-5]]:15: error: src_private_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:15: error: src_private_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU -// GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81] s_add_i32 s0, src_private_limit, s0 +// GFX12XX: s_add_co_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81] +// NOSICI: :[[@LINE-2]]:15: error: src_private_limit register not available on this GPU +// GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81] +// GFX11: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81] +// NOVI: :[[@LINE-5]]:15: error: src_private_limit register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:15: error: src_private_limit register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU -// GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81] s_add_i32 s0, src_pops_exiting_wave_id, s0 +// NOSICI: :[[@LINE-1]]:15: error: src_pops_exiting_wave_id register not available on this GPU +// GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81] +// NOVI: :[[@LINE-3]]:15: error: src_pops_exiting_wave_id register not available on this GPU +// NOGFX11: :[[@LINE-4]]:15: error: src_pops_exiting_wave_id register not available on this GPU +// NOGFX12: :[[@LINE-5]]:15: error: src_pops_exiting_wave_id register not available on this GPU +// NOGFX1250: :[[@LINE-6]]:15: error: src_pops_exiting_wave_id register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:15: error: src_pops_exiting_wave_id register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_base ; encoding: [0x00,0xeb,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_shared_base +// GFX12XX: s_and_b64 s[0:1], s[0:1], src_shared_base ; encoding: [0x00,0xeb,0x80,0x8b] +// NOSICI: :[[@LINE-2]]:27: error: src_shared_base register not available on this GPU +// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_base ; encoding: [0x00,0xeb,0x80,0x86] +// GFX11: s_and_b64 s[0:1], s[0:1], src_shared_base ; encoding: [0x00,0xeb,0x80,0x8b] +// NOVI: :[[@LINE-5]]:27: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_limit register not available on this GPU -// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_limit ; encoding: [0x00,0xec,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_shared_limit +// GFX12XX: s_and_b64 s[0:1], s[0:1], src_shared_limit ; encoding: [0x00,0xec,0x80,0x8b] +// NOSICI: :[[@LINE-2]]:27: error: src_shared_limit register not available on this GPU +// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_limit ; encoding: [0x00,0xec,0x80,0x86] +// GFX11: s_and_b64 s[0:1], s[0:1], src_shared_limit ; encoding: [0x00,0xec,0x80,0x8b] +// NOVI: :[[@LINE-5]]:27: error: src_shared_limit register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: src_shared_limit register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_base register not available on this GPU -// GFX9: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_private_base +// GFX12XX: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x8b] +// NOSICI: :[[@LINE-2]]:27: error: src_private_base register not available on this GPU +// GFX9: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x86] +// GFX11: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x8b] +// NOVI: :[[@LINE-5]]:27: error: src_private_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: src_private_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU -// GFX9: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_private_limit +// GFX12XX: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x8b] +// NOSICI: :[[@LINE-2]]:27: error: src_private_limit register not available on this GPU +// GFX9: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x86] +// GFX11: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x8b] +// NOVI: :[[@LINE-5]]:27: error: src_private_limit register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: src_private_limit register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU -// GFX9: s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id ; encoding: [0x00,0xef,0x80,0x86] s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id +// NOSICI: :[[@LINE-1]]:27: error: src_pops_exiting_wave_id register not available on this GPU +// GFX9: s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id ; encoding: [0x00,0xef,0x80,0x86] +// NOVI: :[[@LINE-3]]:27: error: src_pops_exiting_wave_id register not available on this GPU +// NOGFX11: :[[@LINE-4]]:27: error: src_pops_exiting_wave_id register not available on this GPU +// NOGFX12: :[[@LINE-5]]:27: error: src_pops_exiting_wave_id register not available on this GPU +// NOGFX1250: :[[@LINE-6]]:27: error: src_pops_exiting_wave_id register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: src_pops_exiting_wave_id register not available on this GPU -// GFX9: v_add_u16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x4c] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_add_u16 v0, src_shared_base, v0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x4c] +// NOVI: :[[@LINE-3]]:15: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_add_u16_sdwa v0, src_shared_base, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xeb,0x06,0x86,0x06] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_add_u16_sdwa v0, src_shared_base, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u16_sdwa v0, src_shared_base, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xeb,0x06,0x86,0x06] +// NOVI: :[[@LINE-3]]:20: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_add_u16_sdwa v0, v0, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xd6,0x01,0x4c,0x00,0x06,0x06,0x86] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_add_u16_sdwa v0, v0, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u16_sdwa v0, v0, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xd6,0x01,0x4c,0x00,0x06,0x06,0x86] +// NOVI: :[[@LINE-3]]:24: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_add_u32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x68] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_add_u32 v0, src_shared_base, v0 +// GFX12XX: v_add_nc_u32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x4a] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x68] +// GFX11: v_add_nc_u32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x4a] +// NOVI: :[[@LINE-5]]:15: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_add_u32_e64 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xeb,0x00,0x02,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_add_u32_e64 v0, src_shared_base, v0 +// GFX12XX: v_add_nc_u32_e64 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x25,0xd5,0xeb,0x00,0x02,0x00] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_add_u32_e64 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xeb,0x00,0x02,0x00] +// GFX11: v_add_nc_u32_e64 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x25,0xd5,0xeb,0x00,0x02,0x00] +// NOVI: :[[@LINE-5]]:19: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: v_cmp_eq_i64_e32 vcc, src_shared_base, v[0:1] ; encoding: [0xeb,0x00,0xc4,0x7d] v_cmp_eq_i64 vcc, src_shared_base, v[0:1] +// NOSICI: :[[@LINE-1]]:19: error: src_shared_base register not available on this GPU +// GFX9: v_cmp_eq_i64_e32 vcc, src_shared_base, v[0:1] ; encoding: [0xeb,0x00,0xc4,0x7d] +// NOVI: :[[@LINE-3]]:19: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode +// NOGFX1250: :[[@LINE-6]]:1: error: operands are not valid for this GPU or mode +// NOSICIVI: :[[@LINE-1]]:19: error: src_shared_base register not available on this GPU -// GFX9: v_max_f16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x5a] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_max_f16 v0, src_shared_base, v0 +// GFX12XX: v_max_num_f16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x62] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_max_f16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x5a] +// GFX11: v_max_f16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x72] +// NOVI: :[[@LINE-5]]:15: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: v_max_f32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x16] v_max_f32 v0, src_shared_base, v0 +// GFX12XX: v_max_num_f32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x2c] +// NOSICI: :[[@LINE-2]]:15: error: src_shared_base register not available on this GPU +// GFX9: v_max_f32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x16] +// GFX11: v_max_f32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x20] +// NOVI: :[[@LINE-5]]:15: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:15: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: v_max_f64 v[0:1], src_shared_base, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xeb,0x00,0x02,0x00] v_max_f64 v[0:1], src_shared_base, v[0:1] +// GFX12XX: v_max_num_f64_e32 v[0:1], src_shared_base, v[0:1] ; encoding: [0xeb,0x00,0x00,0x1c] +// NOSICI: :[[@LINE-2]]:19: error: src_shared_base register not available on this GPU +// GFX9: v_max_f64 v[0:1], src_shared_base, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xeb,0x00,0x02,0x00] +// GFX11: v_max_f64 v[0:1], src_shared_base, v[0:1] ; encoding: [0x00,0x00,0x2a,0xd7,0xeb,0x00,0x02,0x00] +// NOVI: :[[@LINE-5]]:19: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:19: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// GFX9: v_pk_add_f16 v0, src_shared_base, v0 ; encoding: [0x00,0x40,0x8f,0xd3,0xeb,0x00,0x02,0x18] v_pk_add_f16 v0, src_shared_base, v0 +// GFX12XX: v_pk_add_f16 v0, src_shared_base, v0 ; encoding: [0x00,0x40,0x0f,0xcc,0xeb,0x00,0x02,0x18] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_pk_add_f16 v0, src_shared_base, v0 ; encoding: [0x00,0x40,0x8f,0xd3,0xeb,0x00,0x02,0x18] +// GFX11: v_pk_add_f16 v0, src_shared_base, v0 ; encoding: [0x00,0x40,0x0f,0xcc,0xeb,0x00,0x02,0x18] +// NOVI: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_ceil_f16_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0x85,0xd1,0xeb,0x00,0x00,0x20] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f16 v0, neg(src_shared_base) +// GFX12XX: v_ceil_f16_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0xdc,0xd5,0xeb,0x00,0x00,0x20] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_ceil_f16_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0x85,0xd1,0xeb,0x00,0x00,0x20] +// GFX11: v_ceil_f16_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0xdc,0xd5,0xeb,0x00,0x00,0x20] +// NOVI: :[[@LINE-5]]:20: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_ceil_f16_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0x85,0xd1,0xeb,0x00,0x00,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f16 v0, abs(src_shared_base) +// GFX12XX: v_ceil_f16_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0xdc,0xd5,0xeb,0x00,0x00,0x00] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX9: v_ceil_f16_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0x85,0xd1,0xeb,0x00,0x00,0x00] +// GFX11: v_ceil_f16_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0xdc,0xd5,0xeb,0x00,0x00,0x00] +// NOVI: :[[@LINE-5]]:20: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_ceil_f64_e64 v[5:6], |src_shared_base| ; encoding: [0x05,0x01,0x58,0xd1,0xeb,0x00,0x00,0x00] -// NOSI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOCIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f64 v[5:6], |src_shared_base| +// GFX9: v_ceil_f64_e64 v[5:6], |src_shared_base| ; encoding: [0x05,0x01,0x58,0xd1,0xeb,0x00,0x00,0x00] +// GFX11: v_ceil_f64_e64 v[5:6], |src_shared_base| ; encoding: [0x05,0x01,0x98,0xd5,0xeb,0x00,0x00,0x00] +// GFX12: v_ceil_f64_e64 v[5:6], |src_shared_base| ; encoding: [0x05,0x01,0x98,0xd5,0xeb,0x00,0x00,0x00] +// NOSI: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOCI: :[[@LINE-5]]:21: error: src_shared_base register not available on this GPU +// NOVI: :[[@LINE-6]]:21: error: src_shared_base register not available on this GPU +// NOGFX1250: :[[@LINE-7]]:12: error: invalid operand for instruction +// NOCIVI: :[[@LINE-5]]:21: error: src_shared_base register not available on this GPU -// GFX9: v_ceil_f64_e64 v[5:6], -src_shared_base ; encoding: [0x05,0x00,0x58,0xd1,0xeb,0x00,0x00,0x20] -// NOSI: :[[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOCIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f64 v[5:6], -src_shared_base +// GFX9: v_ceil_f64_e64 v[5:6], -src_shared_base ; encoding: [0x05,0x00,0x58,0xd1,0xeb,0x00,0x00,0x20] +// GFX11: v_ceil_f64_e64 v[5:6], -src_shared_base ; encoding: [0x05,0x00,0x98,0xd5,0xeb,0x00,0x00,0x20] +// GFX12: v_ceil_f64_e64 v[5:6], -src_shared_base ; encoding: [0x05,0x00,0x98,0xd5,0xeb,0x00,0x00,0x20] +// NOSI: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOCI: :[[@LINE-5]]:21: error: src_shared_base register not available on this GPU +// NOVI: :[[@LINE-6]]:21: error: src_shared_base register not available on this GPU +// NOGFX1250: :[[@LINE-7]]:12: error: invalid operand for instruction +// NOCIVI: :[[@LINE-5]]:21: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: v_ceil_f32_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0x5d,0xd1,0xeb,0x00,0x00,0x20] v_ceil_f32 v0, -src_shared_base +// GFX12XX: v_ceil_f32_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0xa2,0xd5,0xeb,0x00,0x00,0x20] +// NOSICI: :[[@LINE-2]]:17: error: src_shared_base register not available on this GPU +// GFX9: v_ceil_f32_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0x5d,0xd1,0xeb,0x00,0x00,0x20] +// GFX11: v_ceil_f32_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0xa2,0xd5,0xeb,0x00,0x00,0x20] +// NOVI: :[[@LINE-5]]:17: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:17: error: src_shared_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// GFX9: v_ceil_f32_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0x5d,0xd1,0xeb,0x00,0x00,0x00] v_ceil_f32 v0, |src_shared_base| +// GFX12XX: v_ceil_f32_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0xa2,0xd5,0xeb,0x00,0x00,0x00] +// NOSICI: :[[@LINE-2]]:17: error: src_shared_base register not available on this GPU +// GFX9: v_ceil_f32_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0x5d,0xd1,0xeb,0x00,0x00,0x00] +// GFX11: v_ceil_f32_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0xa2,0xd5,0xeb,0x00,0x00,0x00] +// NOVI: :[[@LINE-5]]:17: error: src_shared_base register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:17: error: src_shared_base register not available on this GPU -// GFX9: v_ceil_f16_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xeb,0x16,0xa6,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f16_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_ceil_f16_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xeb,0x16,0xa6,0x00] +// NOVI: :[[@LINE-3]]:22: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_ceil_f16_sdwa v5, -src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xeb,0x16,0x96,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f16_sdwa v5, -src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// GFX9: v_ceil_f16_sdwa v5, -src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xeb,0x16,0x96,0x00] +// NOVI: :[[@LINE-3]]:22: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// GFX9: v_ceil_f32_sdwa v5, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0x86,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f32_sdwa v5, src_shared_base dst_sel:DWORD src0_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported +// GFX9: v_ceil_f32_sdwa v5, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0x86,0x00] +// NOVI: :[[@LINE-3]]:21: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported -// GFX9: v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0xa6,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD src0_sel:DWORD +// NOSICI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported +// GFX9: v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0xa6,0x00] +// NOVI: :[[@LINE-3]]:22: error: src_shared_base register not available on this GPU +// NOGFX11: :[[@LINE-4]]:1: error: sdwa variant of this instruction is not supported +// NOGFX12: :[[@LINE-5]]:1: error: sdwa variant of this instruction is not supported +// NOGFX1250: :[[@LINE-6]]:1: error: sdwa variant of this instruction is not supported +// NOSICIVI: :[[@LINE-1]]:1: error: sdwa variant of this instruction is not supported //---------------------------------------------------------------------------// // named inline values compete with other scalars for constant bus access //---------------------------------------------------------------------------// -// NOGFX9: :[[@LINE+3]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_private_base register not available on this GPU v_add_u32 v0, private_base, s0 +// GFX12XX: v_add_nc_u32_e64 v0, src_private_base, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xed,0x00,0x00,0x00] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_add_nc_u32_e64 v0, src_private_base, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xed,0x00,0x00,0x00] +// NOVI: :[[@LINE-4]]:15: error: src_private_base register not available on this GPU +// NOGFX9: :[[@LINE-5]]:29: error: invalid operand (violates constant bus restrictions) +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOGFX9: :[[@LINE+3]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_add_u32 v0, scc, s0 +// GFX12XX: v_add_nc_u32_e64 v0, src_scc, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xfd,0x00,0x00,0x00] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_add_nc_u32_e64 v0, src_scc, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xfd,0x00,0x00,0x00] +// NOVI: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode +// NOGFX9: :[[@LINE-5]]:20: error: invalid operand (violates constant bus restrictions) +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU // v_div_fmas implicitly reads VCC -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_div_fmas_f32 v0, shared_base, v0, v1 +// GFX12XX: v_div_fmas_f32 v0, src_shared_base, v0, v1 ; encoding: [0x00,0x00,0x37,0xd6,0xeb,0x00,0x06,0x04] +// NOSICI: :[[@LINE-2]]:20: error: src_shared_base register not available on this GPU +// GFX11: v_div_fmas_f32 v0, src_shared_base, v0, v1 ; encoding: [0x00,0x00,0x37,0xd6,0xeb,0x00,0x06,0x04] +// NOVI: :[[@LINE-4]]:20: error: src_shared_base register not available on this GPU +// NOGFX9: :[[@LINE-5]]:20: error: invalid operand (violates constant bus restrictions) +// NOSICIVI: :[[@LINE-1]]:20: error: src_shared_base register not available on this GPU // v_div_fmas implicitly reads VCC -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_limit register not available on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_div_fmas_f32 v0, v0, shared_limit, v1 +// GFX12XX: v_div_fmas_f32 v0, v0, src_shared_limit, v1 ; encoding: [0x00,0x00,0x37,0xd6,0x00,0xd9,0x05,0x04] +// NOSICI: :[[@LINE-2]]:24: error: src_shared_limit register not available on this GPU +// GFX11: v_div_fmas_f32 v0, v0, src_shared_limit, v1 ; encoding: [0x00,0x00,0x37,0xd6,0x00,0xd9,0x05,0x04] +// NOVI: :[[@LINE-4]]:24: error: src_shared_limit register not available on this GPU +// NOGFX9: :[[@LINE-5]]:24: error: invalid operand (violates constant bus restrictions) +// NOSICIVI: :[[@LINE-1]]:24: error: src_shared_limit register not available on this GPU // v_div_fmas implicitly reads VCC -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_div_fmas_f32 v0, v0, v1, private_limit +// GFX12XX: v_div_fmas_f32 v0, v0, v1, src_private_limit ; encoding: [0x00,0x00,0x37,0xd6,0x00,0x03,0xba,0x03] +// NOSICI: :[[@LINE-2]]:28: error: src_private_limit register not available on this GPU +// GFX11: v_div_fmas_f32 v0, v0, v1, src_private_limit ; encoding: [0x00,0x00,0x37,0xd6,0x00,0x03,0xba,0x03] +// NOVI: :[[@LINE-4]]:28: error: src_private_limit register not available on this GPU +// NOGFX9: :[[@LINE-5]]:28: error: invalid operand (violates constant bus restrictions) +// NOSICIVI: :[[@LINE-1]]:28: error: src_private_limit register not available on this GPU // v_div_fmas implicitly reads VCC -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_div_fmas_f32 v0, execz, v0, v1 +// NOSICI: :[[@LINE-1]]:20: error: invalid operand (violates constant bus restrictions) +// NOGFX89: :[[@LINE-2]]:20: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-3]]:20: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:20: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:20: error: src_execz register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:20: error: invalid operand (violates constant bus restrictions) // v_div_fmas implicitly reads VCC -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_div_fmas_f32 v0, v0, scc, v1 +// GFX12XX: v_div_fmas_f32 v0, v0, src_scc, v1 ; encoding: [0x00,0x00,0x37,0xd6,0x00,0xfb,0x05,0x04] +// NOSICI: :[[@LINE-2]]:24: error: invalid operand (violates constant bus restrictions) +// NOGFX89: :[[@LINE-3]]:24: error: invalid operand (violates constant bus restrictions) +// GFX11: v_div_fmas_f32 v0, v0, src_scc, v1 ; encoding: [0x00,0x00,0x37,0xd6,0x00,0xfb,0x05,0x04] +// NOSICIVI: :[[@LINE-1]]:24: error: invalid operand (violates constant bus restrictions) // v_div_fmas implicitly reads VCC -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_div_fmas_f32 v0, v0, v1, vccz +// NOSICI: :[[@LINE-1]]:28: error: invalid operand (violates constant bus restrictions) +// NOGFX89: :[[@LINE-2]]:28: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-3]]:28: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:28: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:28: error: src_vccz register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:28: error: invalid operand (violates constant bus restrictions) // v_addc_co_u32 implicitly reads VCC (VOP2) -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_addc_co_u32 v0, vcc, shared_base, v0, vcc +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOVI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX9: :[[@LINE-3]]:24: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_madak_f32 v0, shared_base, v0, 0x11213141 +// NOSICI: :[[@LINE-1]]:17: error: src_shared_base register not available on this GPU +// NOVI: :[[@LINE-2]]:17: error: src_shared_base register not available on this GPU +// NOGFX9: :[[@LINE-3]]:17: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-6]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:17: error: src_shared_base register not available on this GPU -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_madak_f32 v0, scc, v0, 0x11213141 +// NOSICI: :[[@LINE-1]]:17: error: invalid operand (violates constant bus restrictions) +// NOGFX89: :[[@LINE-2]]:17: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:17: error: invalid operand (violates constant bus restrictions) -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madak_f32 v0, 0xff32ff, v0, 0x11213141 +// NOSICI: :[[@LINE-1]]:31: error: only one unique literal operand is allowed +// NOGFX89: :[[@LINE-2]]:31: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:31: error: only one unique literal operand is allowed -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madak_f32 v0, 0xff32ff, v0, 1 +// NOSICI: :[[@LINE-1]]:31: error: only one unique literal operand is allowed +// NOGFX89: :[[@LINE-2]]:31: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:31: error: only one unique literal operand is allowed -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madmk_f32 v0, 0xff32ff, 0x11213141, v0 +// NOSICI: :[[@LINE-1]]:27: error: only one unique literal operand is allowed +// NOGFX89: :[[@LINE-2]]:27: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: only one unique literal operand is allowed -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madmk_f32 v0, 0xff32ff, -1, v0 +// NOSICI: :[[@LINE-1]]:27: error: only one unique literal operand is allowed +// NOGFX89: :[[@LINE-2]]:27: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:27: error: only one unique literal operand is allowed -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madak_f16 v0, 0xff32, v0, 0x1122 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:29: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madak_f16 v0, 0xff32, v0, 0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:29: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madmk_f16 v0, 0xff32, 0x1122, v0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:25: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: only one unique literal operand is allowed v_madmk_f16 v0, 0xff32, 1, v0 +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOGFX89: :[[@LINE-2]]:25: error: only one unique literal operand is allowed +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_base register not available on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_cmp_eq_f32 s[0:1], private_base, private_limit +// NOSICI: :[[@LINE-1]]:22: error: src_private_base register not available on this GPU +// NOVI: :[[@LINE-2]]:22: error: src_private_base register not available on this GPU +// NOGFX9: :[[@LINE-3]]:36: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-4]]:14: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:14: error: invalid operand for instruction +// NOGFX1250: :[[@LINE-6]]:14: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:22: error: src_private_base register not available on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_base register not available on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_cmp_eq_f32 s[0:1], private_base, s0 +// NOSICI: :[[@LINE-1]]:22: error: src_private_base register not available on this GPU +// NOVI: :[[@LINE-2]]:22: error: src_private_base register not available on this GPU +// NOGFX9: :[[@LINE-3]]:36: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-4]]:14: error: invalid operand for instruction +// NOGFX12: :[[@LINE-5]]:14: error: invalid operand for instruction +// NOGFX1250: :[[@LINE-6]]:14: error: invalid operand for instruction +// NOSICIVI: :[[@LINE-1]]:22: error: src_private_base register not available on this GPU -// NOGCN: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_cmp_eq_f32 s[0:1], execz, s0 +// NOSICI: :[[@LINE-1]]:29: error: invalid operand (violates constant bus restrictions) +// NOGFX89: :[[@LINE-2]]:29: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-3]]:22: error: src_execz register not available on this GPU +// NOGFX12: :[[@LINE-4]]:22: error: src_execz register not available on this GPU +// NOGFX1250: :[[@LINE-5]]:22: error: src_execz register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:29: error: invalid operand (violates constant bus restrictions) -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_pk_add_f16 v255, private_base, private_limit +// GFX12XX: v_pk_add_f16 v255, src_private_base, src_private_limit ; encoding: [0xff,0x40,0x0f,0xcc,0xed,0xdc,0x01,0x18] +// NOSICI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// GFX11: v_pk_add_f16 v255, src_private_base, src_private_limit ; encoding: [0xff,0x40,0x0f,0xcc,0xed,0xdc,0x01,0x18] +// NOVI: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX9: :[[@LINE-5]]:34: error: invalid operand (violates constant bus restrictions) +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU -// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU -// NOGFX9: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions) v_pk_add_f16 v255, vccz, execz +// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU +// NOVI: :[[@LINE-2]]:1: error: instruction not supported on this GPU +// NOGFX9: :[[@LINE-3]]:26: error: invalid operand (violates constant bus restrictions) +// NOGFX11: :[[@LINE-4]]:20: error: src_vccz register not available on this GPU +// NOGFX12: :[[@LINE-5]]:20: error: src_vccz register not available on this GPU +// NOGFX1250: :[[@LINE-6]]:20: error: src_vccz register not available on this GPU +// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU //---------------------------------------------------------------------------// -// check dummy lit() syntax for sp3 compatibility. +// check lit() syntax. //---------------------------------------------------------------------------// -// SICI: v_sqrt_f32_e32 v2, 0x7b ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] -// GFX89: v_sqrt_f32_e32 v2, 0x7b ; encoding: [0xff,0x4e,0x04,0x7e,0x7b,0x00,0x00,0x00] v_sqrt_f32 v2, lit(123) +// SICI: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX89: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x4e,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX12XX: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX11: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] -// SICI: v_sqrt_f32_e32 v2, 0x7b ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] -// GFX89: v_sqrt_f32_e32 v2, 0x7b ; encoding: [0xff,0x4e,0x04,0x7e,0x7b,0x00,0x00,0x00] v_sqrt_f32 v2, abs(lit(123)) +// SICI: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX89: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x4e,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX12XX: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX11: v_sqrt_f32_e32 v2, lit(0x7b) ; encoding: [0xff,0x66,0x04,0x7e,0x7b,0x00,0x00,0x00] -// SICI: v_sqrt_f32_e32 v2, 0x42f60000 ; encoding: [0xff,0x66,0x04,0x7e,0x00,0x00,0xf6,0x42 -// GFX89: v_sqrt_f32_e32 v2, 0x42f60000 ; encoding: [0xff,0x4e,0x04,0x7e,0x00,0x00,0xf6,0x42] v_sqrt_f32 v2, lit(123.0) +// SICI: v_sqrt_f32_e32 v2, lit(0x42f60000) ; encoding: [0xff,0x66,0x04,0x7e,0x00,0x00,0xf6,0x42] +// GFX89: v_sqrt_f32_e32 v2, lit(0x42f60000) ; encoding: [0xff,0x4e,0x04,0x7e,0x00,0x00,0xf6,0x42] +// GFX12XX: v_sqrt_f32_e32 v2, lit(0x42f60000) ; encoding: [0xff,0x66,0x04,0x7e,0x00,0x00,0xf6,0x42] +// GFX11: v_sqrt_f32_e32 v2, lit(0x42f60000) ; encoding: [0xff,0x66,0x04,0x7e,0x00,0x00,0xf6,0x42] -// SICI: v_sqrt_f64_e32 v[2:3], 0x405ec000 ; encoding: [0xff,0x68,0x04,0x7e,0x00,0xc0,0x5e,0x40] -// GFX89: v_sqrt_f64_e32 v[2:3], 0x405ec000 ; encoding: [0xff,0x50,0x04,0x7e,0x00,0xc0,0x5e,0x40] v_sqrt_f64 v[2:3], lit(123.0) +// SICI: v_sqrt_f64_e32 v[2:3], lit(0x405ec000) ; encoding: [0xff,0x68,0x04,0x7e,0x00,0xc0,0x5e,0x40] +// GFX89: v_sqrt_f64_e32 v[2:3], lit(0x405ec000) ; encoding: [0xff,0x50,0x04,0x7e,0x00,0xc0,0x5e,0x40] +// GFX11: v_sqrt_f64_e32 v[2:3], lit(0x405ec000) ; encoding: [0xff,0x68,0x04,0x7e,0x00,0xc0,0x5e,0x40] +// GFX12: v_sqrt_f64_e32 v[2:3], lit(0x405ec000) ; encoding: [0xff,0x68,0x04,0x7e,0x00,0xc0,0x5e,0x40] +// GFX1250: v_sqrt_f64_e32 v[2:3], lit(0x405ec000) ; encoding: [0xfe,0x68,0x04,0x7e,0x00,0xc0,0x5e,0x40,0x00,0x00,0x00,0x00] -// SICI: v_sqrt_f64_e32 v[2:3], 0x7b ; encoding: [0xff,0x68,0x04,0x7e,0x7b,0x00,0x00,0x00] -// GFX89: v_sqrt_f64_e32 v[2:3], 0x7b ; encoding: [0xff,0x50,0x04,0x7e,0x7b,0x00,0x00,0x00] v_sqrt_f64 v[2:3], lit(123) +// SICI: v_sqrt_f64_e32 v[2:3], lit(0x7b) ; encoding: [0xff,0x68,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX89: v_sqrt_f64_e32 v[2:3], lit(0x7b) ; encoding: [0xff,0x50,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX11: v_sqrt_f64_e32 v[2:3], lit(0x7b) ; encoding: [0xff,0x68,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX12: v_sqrt_f64_e32 v[2:3], lit(0x7b) ; encoding: [0xff,0x68,0x04,0x7e,0x7b,0x00,0x00,0x00] +// GFX1250: v_sqrt_f64_e32 v[2:3], lit(0x7b) ; encoding: [0xfe,0x68,0x04,0x7e,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00] -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: expected left paren after lit -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: expected left paren after lit v_sqrt_f32 v2, lit 123.0 +// NOGCN: :[[@LINE-1]]:20: error: expected left paren after lit -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: expected closing parentheses -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: expected closing parentheses v_sqrt_f32 v2, lit(123.0 +// NOGCN: :[[@LINE-1]]:25: error: expected closing parentheses -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: expected immediate with lit modifier -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: expected immediate with lit modifier v_sqrt_f32 v2, lit(v1) +// NOGCN: :[[@LINE-1]]:20: error: expected immediate with lit modifier // Make sure lit() is accepted on operands without modifiers. -// SICI: v_madak_f32 v4, 0x7e8, v8, 0x7e8 ; encoding: [0xff,0x10,0x08,0x42,0xe8,0x07,0x00,0x00] -// GFX89: v_madak_f32 v4, 0x7e8, v8, 0x7e8 ; encoding: [0xff,0x10,0x08,0x30,0xe8,0x07,0x00,0x00] v_madak_f32 v4, lit(0x7e8), v8, lit(0x7e8) +// SICI: v_madak_f32 v4, lit(0x7e8), v8, lit(0x7e8) ; encoding: [0xff,0x10,0x08,0x42,0xe8,0x07,0x00,0x00] +// GFX89: v_madak_f32 v4, lit(0x7e8), v8, lit(0x7e8) ; encoding: [0xff,0x10,0x08,0x30,0xe8,0x07,0x00,0x00] +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU -// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. -// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand. v_madak_f32 v4, lit(lit(0x7e8)), v8, lit(0x7e8) +// NOSICI: :[[@LINE-1]]:24: error: not a valid operand. +// NOGFX89: :[[@LINE-2]]:24: error: not a valid operand. +// NOGFX11: :[[@LINE-3]]:1: error: instruction not supported on this GPU +// NOGFX12: :[[@LINE-4]]:1: error: instruction not supported on this GPU +// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU +// NOSICIVI: :[[@LINE-1]]:24: error: not a valid operand. diff --git a/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s b/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s index c935c37..dbaddc1 100644 --- a/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s +++ b/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s @@ -1,103 +1,103 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=GFX90A --implicit-check-not=error: %s v_add_f64 v[1:2], v[1:2], v[1:2] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx2 v[1:2], v[0:1], off -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx3 v[1:3], v[0:1], off -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx4 v[1:4], v[0:1], off -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx2 a[1:2], v[0:1], off -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx3 a[1:3], v[0:1], off -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction global_load_dwordx4 a[1:4], v[0:1], off -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_load v[1:2], v2, s[0:7] dmask:0x3 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_load v[1:3], v2, s[0:7] dmask:0x7 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_load v[1:4], v2, s[0:7] dmask:0xf unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[1:2], v2, s[0:7] dmask:0x3 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[1:3], v2, s[0:7] dmask:0x7 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_load a[1:4], v2, s[0:7] dmask:0xf unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_store v[193:194], v[238:241], s[28:35] dmask:0x3 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_store v[193:195], v[238:241], s[28:35] dmask:0x7 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_store v[193:196], v[238:241], s[28:35] dmask:0xf unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[193:194], v[238:241], s[28:35] dmask:0x3 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[193:195], v[238:241], s[28:35] dmask:0x7 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_store a[193:196], v[238:241], s[28:35] dmask:0xf unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_swap v4, v[193:196], s[28:35] dmask:0x1 unorm glc // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode image_atomic_swap v[5:6], v1, s[8:15] dmask:0x3 unorm -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap v[5:6], v[192:195], s[28:35] dmask:0x3 unorm glc -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap v[4:5], v[193:196], s[28:35] dmask:0x3 unorm glc // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode image_atomic_cmpswap v[5:8], v[192:195], s[28:35] dmask:0xf unorm glc -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap v[4:7], v[193:196], s[28:35] dmask:0xf unorm glc // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode image_atomic_cmpswap a[5:6], v[192:195], s[28:35] dmask:0x3 unorm glc -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[4:5], v[193:196], s[28:35] dmask:0x3 unorm glc // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode image_atomic_cmpswap a[5:8], v[192:195], s[28:35] dmask:0xf unorm glc -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction image_atomic_cmpswap a[4:7], v[193:196], s[28:35] dmask:0xf unorm glc // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_mfma_f32_32x32x8f16 a[0:15], a[1:2], v[0:1], a[0:15] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction v_mfma_i32_4x4x4i8 a[1:4], a0, v1, 2 -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned +// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction v_mfma_f32_16x16x1f32 a[0:15], a0, v1, a[17:32] // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned diff --git a/llvm/test/MC/AMDGPU/vop3-literal.s b/llvm/test/MC/AMDGPU/vop3-literal.s index 56e71b9..dd6be544 100644 --- a/llvm/test/MC/AMDGPU/vop3-literal.s +++ b/llvm/test/MC/AMDGPU/vop3-literal.s @@ -3,6 +3,7 @@ // RUN: not llvm-mc -triple=amdgcn %s -show-encoding -mcpu=gfx900 | FileCheck %s -check-prefix=GFX9 // RUN: not llvm-mc -triple=amdgcn %s -show-encoding -mcpu=gfx1010 -mattr=+wavefrontsize64 | FileCheck %s -check-prefix=GFX10 // RUN: not llvm-mc -triple=amdgcn %s -show-encoding -mcpu=gfx1250 -mattr=+wavefrontsize64 | FileCheck %s -check-prefix=GFX1250 +// RUN: not llvm-mc -triple=amdgcn %s -show-encoding -mcpu=gfx1250 -mattr=+wavefrontsize64 | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+wavefrontsize64 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250 %s // RUN: not llvm-mc -triple=amdgcn %s -filetype=null -no-warn 2>&1 -mcpu=gfx900 | FileCheck %s -implicit-check-not=error: -check-prefix=GFX9-ERR // RUN: not llvm-mc -triple=amdgcn %s -filetype=null -no-warn 2>&1 -mcpu=gfx1010 -mattr=+wavefrontsize64 | FileCheck %s -implicit-check-not=error: -check-prefix=GFX10-ERR @@ -185,7 +186,7 @@ v_add_f16_e64 v0, 0xfe0b, neg(0xfe0b) v_add_f64 v[0:1], 1.23456, v[0:1] // GFX10: v_add_f64 v[0:1], 0x3ff3c0c1, v[0:1] ; encoding: [0x00,0x00,0x64,0xd5,0xff,0x00,0x02,0x00,0xc1,0xc0,0xf3,0x3f] -// GFX1250: v_add_f64_e32 v[0:1], lit64(0x3ff3c0c1fc8f3238), v[0:1] ; encoding: [0xfe,0x00,0x00,0x04,0x38,0x32,0x8f,0xfc,0xc1,0xc0,0xf3,0x3f] +// GFX1250: v_add_f64_e32 v[0:1], 0x3ff3c0c1fc8f3238, v[0:1] ; encoding: [0xfe,0x00,0x00,0x04,0x38,0x32,0x8f,0xfc,0xc1,0xc0,0xf3,0x3f] // GFX9-ERR: :[[@LINE-3]]:19: error: literal operands are not supported v_add_f64 v[0:1], v[0:1], -abs(1.23456) diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt index 7064479..d44400e 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt @@ -2,55 +2,55 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1250 %s 0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_mov_b64 s[2:3], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_mov_b64 s[2:3], 0x10abcdef12345678 ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_add_nc_u64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_and_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), lit64(0x10abcdef12345678) ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678 ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_ashr_i64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_ashr_i64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80 -# GFX1250: s_bfe_i64 s[2:3], lit64(0x80abcdef12345678), 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80] +# GFX1250: s_bfe_i64 s[2:3], 0x80abcdef12345678, 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80] 0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_bfe_u64 s[2:3], lit64(0x10abcdef12345678), 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_bfe_u64 s[2:3], 0x10abcdef12345678, 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_cselect_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_lshl_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_lshl_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_lshr_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_lshr_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_mul_u64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_nand_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_nor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_or_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_xnor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: s_xor_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt index 227e1c4..34a4646 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt @@ -2,7 +2,7 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1250 %s 0xfe,0x4b,0x80,0xbe,0xd0,0xbc,0x8a,0x67,0x45,0x23,0x01,0x00 -# GFX1250: s_add_pc_i64 lit64(0x12345678abcd0) ; encoding: [0xfe,0x4b,0x80,0xbe,0xd0,0xbc,0x8a,0x67,0x45,0x23,0x01,0x00] +# GFX1250: s_add_pc_i64 0x12345678abcd0 ; encoding: [0xfe,0x4b,0x80,0xbe,0xd0,0xbc,0x8a,0x67,0x45,0x23,0x01,0x00] 0xff,0x4b,0x80,0xbe,0x64,0x00,0x00,0x00 # GFX1250: s_add_pc_i64 0x64 ; encoding: [0xff,0x4b,0x80,0xbe,0x64,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt index 1571fb9..cce6a74 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt @@ -2,211 +2,211 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1250 %s 0xfe,0xfc,0xfd,0x05,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_add_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x05,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_add_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x05,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x30,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x30,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_ceil_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x30,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfe,0xff,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_class_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v255 ; encoding: [0xfe,0xfe,0xff,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_class_f64_e32 vcc_lo, 0x10abcdef12345678, v255 ; encoding: [0xfe,0xfe,0xff,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x45,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_eq_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_eq_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x4d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_ge_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_ge_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x49,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_gt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_gt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_gt_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_gt_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_gt_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_gt_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x47,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_le_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_le_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_le_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_le_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_le_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_le_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x4b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_lg_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_lg_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x43,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_lt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_lt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_lt_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_lt_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_lt_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_lt_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xab,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_ne_i64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_ne_i64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xbb,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_ne_u64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_ne_u64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x5b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_neq_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_neq_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x53,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_nge_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_nge_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x57,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_ngt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_ngt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x59,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_nle_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_nle_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x55,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_nlg_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_nlg_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x5d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_nlt_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_nlt_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x4f,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_o_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_o_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x51,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmp_u_f64_e32 vcc_lo, lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmp_u_f64_e32 vcc_lo, 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfe,0xff,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_class_f64_e32 lit64(0x10abcdef12345678), v255 ; encoding: [0xfe,0xfe,0xff,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_class_f64_e32 0x10abcdef12345678, v255 ; encoding: [0xfe,0xfe,0xff,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x45,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_eq_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_eq_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x45,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_eq_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_eq_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_eq_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_eq_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb5,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x4d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_ge_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_ge_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xad,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_ge_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xad,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_ge_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xad,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xbd,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_ge_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xbd,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_ge_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xbd,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x49,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_gt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_gt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x49,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_gt_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_gt_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_gt_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_gt_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb9,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x47,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_le_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_le_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x47,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_le_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_le_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_le_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_le_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb7,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x4b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_lg_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_lg_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x43,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_lt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_lt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x43,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xa3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_lt_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_lt_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xa3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xb3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_lt_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_lt_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xb3,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xab,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_ne_i64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_ne_i64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xab,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xbb,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_ne_u64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_ne_u64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xbb,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x5b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_neq_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_neq_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5b,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x53,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_nge_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_nge_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x53,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x57,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_ngt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_ngt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x57,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x59,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_nle_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_nle_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x59,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x55,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_nlg_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_nlg_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x55,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x5d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_nlt_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_nlt_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x5d,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x4f,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_o_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_o_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x4f,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0x51,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cmpx_u_f64_e32 lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cmpx_u_f64_e32 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0x51,0x7d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x1e,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cvt_f32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x1e,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cvt_f32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x1e,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x06,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cvt_i32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x06,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cvt_i32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x06,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x2a,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_cvt_u32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x2a,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_cvt_u32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x2a,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x34,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_floor_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x34,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_floor_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x34,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x7c,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_fract_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x7c,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_fract_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x7c,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x78,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_frexp_exp_i32_f64_e32 v255, lit64(0x10abcdef12345678) ; encoding: [0xfe,0x78,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_frexp_exp_i32_f64_e32 v255, 0x10abcdef12345678 ; encoding: [0xfe,0x78,0xfe,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x7a,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_frexp_mant_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x7a,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_frexp_mant_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x7a,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xfd,0x1d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_max_num_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_max_num_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xfd,0x1b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_min_num_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_min_num_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x1b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0xfc,0xfd,0x0d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_mul_f64_e32 v[254:255], lit64(0x10abcdef12345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x0d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_mul_f64_e32 v[254:255], 0x10abcdef12345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x0d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x5e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_rcp_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x5e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_rcp_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x5e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x32,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_rndne_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x32,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_rndne_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x32,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x62,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_rsq_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x62,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_rsq_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x62,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x68,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_sqrt_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x68,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_sqrt_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x68,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x2e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10 -# GFX1250: v_trunc_f64_e32 v[254:255], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x2e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] +# GFX1250: v_trunc_f64_e32 v[254:255], 0x10abcdef12345678 ; encoding: [0xfe,0x2e,0xfc,0x7f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10] 0xfe,0x30,0xfc,0x7f,0x33,0x33,0x33,0x33,0x33,0x23,0x63,0x40 -# GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x4063233333333333) ; encoding: [0xfe,0x30,0xfc,0x7f,0x33,0x33,0x33,0x33,0x33,0x23,0x63,0x40] +# GFX1250: v_ceil_f64_e32 v[254:255], 0x4063233333333333 ; encoding: [0xfe,0x30,0xfc,0x7f,0x33,0x33,0x33,0x33,0x33,0x23,0x63,0x40] 0xfe,0x30,0xfc,0x7f,0x5b,0xc0,0x74,0x89,0x36,0x69,0x89,0x44 -# GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x448969368974c05b) ; encoding: [0xfe,0x30,0xfc,0x7f,0x5b,0xc0,0x74,0x89,0x36,0x69,0x89,0x44] +# GFX1250: v_ceil_f64_e32 v[254:255], 0x448969368974c05b ; encoding: [0xfe,0x30,0xfc,0x7f,0x5b,0xc0,0x74,0x89,0x36,0x69,0x89,0x44] 0xff,0x30,0xfc,0x7f,0x00,0x20,0x63,0x40 # GFX1250: v_ceil_f64_e32 v[254:255], 0x40632000 ; encoding: [0xff,0x30,0xfc,0x7f,0x00,0x20,0x63,0x40] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt index 94edf22..acf7ded 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt @@ -3,7 +3,7 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s 0xff,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf -# GFX1250: v_mov_b64_e32 v[254:255], lit64(0xaf123456) ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: v_mov_b64_e32 v[254:255], 0xaf123456 ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x3a,0x08,0x7e # GFX1250: v_mov_b64_e32 v[4:5], -1 ; encoding: [0xc1,0x3a,0x08,0x7e] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt index fb3f1b2..b117d7b0 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt @@ -25,7 +25,7 @@ 0xe9,0x3e,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_tanh_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x3e,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_tanh_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -41,7 +41,7 @@ 0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_tanh_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0x96,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX1250: v_prng_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x96,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -66,7 +66,7 @@ 0xe9,0xf2,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_rcp_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf2,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xf4,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_sqrt_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xf4,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -82,7 +82,7 @@ 0xe9,0xf4,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_sqrt_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf4,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xf6,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_rsq_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xf6,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -98,7 +98,7 @@ 0xe9,0xf6,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_rsq_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf6,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xf8,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_log_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xf8,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -114,7 +114,7 @@ 0xe9,0xf8,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_log_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf8,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xfa,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_exp_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfa,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -130,7 +130,7 @@ 0xe9,0xfa,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_exp_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfa,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xfc,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_sin_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfc,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -146,7 +146,7 @@ 0xe9,0xfc,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_sin_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfc,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xfe,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_cos_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -162,7 +162,7 @@ 0xe9,0xfe,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX1250-REAL16: v_cos_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xe9,0xe4,0xfe,0x7e,0x7f,0x00,0x00,0x00 # GFX1250-REAL16: v_cvt_f32_bf16_dpp v127, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xe4,0xfe,0x7e,0x7f,0x00,0x00,0x00] @@ -186,7 +186,7 @@ 0xe9,0xf0,0x02,0x7f,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_cvt_f16_bf8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xf0,0x02,0x7f,0x02,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188] ; encoding: [0x02,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05] 0xea,0xf0,0x02,0x7e,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_cvt_f16_bf8_dpp v1.l, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xf0,0x02,0x7e,0x02,0x77,0x39,0x05] @@ -202,7 +202,7 @@ 0xe9,0xee,0x02,0x7f,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_cvt_f16_fp8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xee,0x02,0x7f,0x02,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188] ; encoding: [0x02,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05] 0xea,0xec,0x02,0x7e,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_cvt_pk_f16_bf8_dpp v1, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xec,0x02,0x7e,0x02,0x77,0x39,0x05] @@ -230,7 +230,7 @@ 0xe9,0xe6,0x02,0x7f,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_sat_pk4_i4_i8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe6,0x02,0x7f,0x02,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188] ; encoding: [0x02,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05] 0xe9,0xe8,0x02,0x7e,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_sat_pk4_u4_u8_dpp v1.l, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe8,0x02,0x7e,0x02,0x77,0x39,0x05] @@ -242,4 +242,4 @@ 0xe9,0xe8,0x02,0x7f,0x02,0x77,0x39,0x05 # GFX1250-REAL16: v_sat_pk4_u4_u8_dpp v1.h, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xe8,0x02,0x7f,0x02,0x77,0x39,0x05] -# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188] ; encoding: [0x02,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[2:3], v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt index 130941c..58ac4e9 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt @@ -146,7 +146,7 @@ # GFX1250: v_add_nc_u64_e32 v[4:5], 0x3f717273, v[4:5] ; encoding: [0xff,0x08,0x08,0x50,0x73,0x72,0x71,0x3f] 0xff,0x08,0x08,0x50,0x56,0x34,0x12,0xaf -# GFX1250: v_add_nc_u64_e32 v[4:5], lit64(0xaf123456), v[4:5] ; encoding: [0xfe,0x08,0x08,0x50,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: v_add_nc_u64_e32 v[4:5], 0xaf123456, v[4:5] ; encoding: [0xfe,0x08,0x08,0x50,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x7e,0x08,0x08,0x50 # GFX1250: v_add_nc_u64_e32 v[4:5], exec, v[4:5] ; encoding: [0x7e,0x08,0x08,0x50] @@ -233,7 +233,7 @@ # GFX1250: v_sub_nc_u64_e32 v[4:5], 0x3f717273, v[4:5] ; encoding: [0xff,0x08,0x08,0x52,0x73,0x72,0x71,0x3f] 0xff,0x08,0x08,0x52,0x56,0x34,0x12,0xaf -# GFX1250: v_sub_nc_u64_e32 v[4:5], lit64(0xaf123456), v[4:5] ; encoding: [0xfe,0x08,0x08,0x52,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: v_sub_nc_u64_e32 v[4:5], 0xaf123456, v[4:5] ; encoding: [0xfe,0x08,0x08,0x52,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x7e,0x08,0x08,0x52 # GFX1250: v_sub_nc_u64_e32 v[4:5], exec, v[4:5] ; encoding: [0x7e,0x08,0x08,0x52] @@ -320,7 +320,7 @@ # GFX1250: v_mul_u64_e32 v[4:5], 0x3f717273, v[4:5] ; encoding: [0xff,0x08,0x08,0x54,0x73,0x72,0x71,0x3f] 0xff,0x08,0x08,0x54,0x56,0x34,0x12,0xaf -# GFX1250: v_mul_u64_e32 v[4:5], lit64(0xaf123456), v[4:5] ; encoding: [0xfe,0x08,0x08,0x54,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: v_mul_u64_e32 v[4:5], 0xaf123456, v[4:5] ; encoding: [0xfe,0x08,0x08,0x54,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x7e,0x08,0x08,0x54 # GFX1250: v_mul_u64_e32 v[4:5], exec, v[4:5] ; encoding: [0x7e,0x08,0x08,0x54] @@ -377,13 +377,13 @@ # GFX1250: v_fmaak_f64 v[254:255], 0x405ec000, v[2:3], 0x405ec000 ; encoding: [0xfe,0x04,0xfc,0x49,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] 0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40 -# GFX1250: v_fmaak_f64 v[254:255], lit64(0x405ec00012345678), v[254:255], lit64(0x405ec00012345678) ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +# GFX1250: v_fmaak_f64 v[254:255], 0x405ec00012345678, v[254:255], 0x405ec00012345678 ; encoding: [0xfe,0xfc,0xfd,0x49,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] 0xfe,0x0c,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40 -# GFX1250: v_fmaak_f64 v[4:5], lit64(0x405ec66666666666), v[6:7], lit64(0x405ec66666666666) ; encoding: [0xfe,0x0c,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +# GFX1250: v_fmaak_f64 v[4:5], 0x405ec66666666666, v[6:7], 0x405ec66666666666 ; encoding: [0xfe,0x0c,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] 0xfe,0x10,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40 -# GFX1250: v_fmaak_f64 v[4:5], lit64(0x405ec66666666666), v[8:9], lit64(0x405ec66666666666) ; encoding: [0xfe,0x10,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +# GFX1250: v_fmaak_f64 v[4:5], 0x405ec66666666666, v[8:9], 0x405ec66666666666 ; encoding: [0xfe,0x10,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] 0xf2,0x10,0x08,0x48,0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x3f # GFX1250: v_fmaak_f64 v[4:5], 1.0, v[8:9], 0x3ff00000 ; encoding: [0xf2,0x10,0x08,0x48,0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x3f] @@ -395,7 +395,7 @@ # GFX1250: v_fmaak_f64 v[4:5], lit64(0x7e8), v[8:9], lit64(0x7e8) ; encoding: [0xfe,0x10,0x08,0x48,0xe8,0x07,0x00,0x00,0x00,0x00,0x00,0x00] 0x02,0x05,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40 -# GFX1250: v_fmaak_f64 v[4:5], v[2:3], v[2:3], lit64(0x405ec66666666666) ; encoding: [0x02,0x05,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +# GFX1250: v_fmaak_f64 v[4:5], v[2:3], v[2:3], 0x405ec66666666666 ; encoding: [0x02,0x05,0x08,0x48,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] 0xc1,0x10,0x0c,0x48,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40 # GFX1250: v_fmaak_f64 v[6:7], -1, v[8:9], 0x405ec000 ; encoding: [0xc1,0x10,0x0c,0x48,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] @@ -410,7 +410,7 @@ # GFX1250: v_fmaak_f64 v[6:7], null, v[8:9], 0x405ec000 ; encoding: [0x7c,0x10,0x0c,0x48,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] 0x02,0x10,0x0c,0x48,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40 -# GFX1250: v_fmaak_f64 v[6:7], s[2:3], v[8:9], lit64(0x405ec00012345678) ; encoding: [0x02,0x10,0x0c,0x48,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +# GFX1250: v_fmaak_f64 v[6:7], s[2:3], v[8:9], 0x405ec00012345678 ; encoding: [0x02,0x10,0x0c,0x48,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] 0xfd,0x10,0x0c,0x48,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40 # GFX1250: v_fmaak_f64 v[6:7], src_scc, v[8:9], 0x405ec000 ; encoding: [0xfd,0x10,0x0c,0x48,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] @@ -431,13 +431,13 @@ # GFX1250: v_fmamk_f64 v[254:255], 0x405ec000, 0x405ec000, v[2:3] ; encoding: [0xfe,0x04,0xfc,0x47,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] 0xfe,0xfc,0xfd,0x47,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40 -# GFX1250: v_fmamk_f64 v[254:255], lit64(0x405ec00012345678), lit64(0x405ec00012345678), v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x47,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +# GFX1250: v_fmamk_f64 v[254:255], 0x405ec00012345678, 0x405ec00012345678, v[254:255] ; encoding: [0xfe,0xfc,0xfd,0x47,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] 0xfe,0x0c,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40 -# GFX1250: v_fmamk_f64 v[4:5], lit64(0x405ec66666666666), lit64(0x405ec66666666666), v[6:7] ; encoding: [0xfe,0x0c,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +# GFX1250: v_fmamk_f64 v[4:5], 0x405ec66666666666, 0x405ec66666666666, v[6:7] ; encoding: [0xfe,0x0c,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] 0xfe,0x10,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40 -# GFX1250: v_fmamk_f64 v[4:5], lit64(0x405ec66666666666), lit64(0x405ec66666666666), v[8:9] ; encoding: [0xfe,0x10,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +# GFX1250: v_fmamk_f64 v[4:5], 0x405ec66666666666, 0x405ec66666666666, v[8:9] ; encoding: [0xfe,0x10,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] 0xf2,0x0c,0x08,0x46,0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x3f # GFX1250: v_fmamk_f64 v[4:5], 1.0, 0x3ff00000, v[6:7] ; encoding: [0xf2,0x0c,0x08,0x46,0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x3f] @@ -449,7 +449,7 @@ # GFX1250: v_fmamk_f64 v[4:5], lit64(0x7e8), lit64(0x7e8), v[8:9] ; encoding: [0xfe,0x10,0x08,0x46,0xe8,0x07,0x00,0x00,0x00,0x00,0x00,0x00] 0x02,0x0d,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40 -# GFX1250: v_fmamk_f64 v[4:5], v[2:3], lit64(0x405ec66666666666), v[6:7] ; encoding: [0x02,0x0d,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] +# GFX1250: v_fmamk_f64 v[4:5], v[2:3], 0x405ec66666666666, v[6:7] ; encoding: [0x02,0x0d,0x08,0x46,0x66,0x66,0x66,0x66,0x66,0xc6,0x5e,0x40] 0xc1,0x04,0x0c,0x46,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40 # GFX1250: v_fmamk_f64 v[6:7], -1, 0x405ec000, v[2:3] ; encoding: [0xc1,0x04,0x0c,0x46,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] @@ -464,7 +464,7 @@ # GFX1250: v_fmamk_f64 v[6:7], null, 0x405ec000, v[2:3] ; encoding: [0x7c,0x04,0x0c,0x46,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] 0x02,0x04,0x0c,0x46,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40 -# GFX1250: v_fmamk_f64 v[6:7], s[2:3], lit64(0x405ec00012345678), v[2:3] ; encoding: [0x02,0x04,0x0c,0x46,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] +# GFX1250: v_fmamk_f64 v[6:7], s[2:3], 0x405ec00012345678, v[2:3] ; encoding: [0x02,0x04,0x0c,0x46,0x78,0x56,0x34,0x12,0x00,0xc0,0x5e,0x40] 0xfd,0x04,0x0c,0x46,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40 # GFX1250: v_fmamk_f64 v[6:7], src_scc, 0x405ec000, v[2:3] ; encoding: [0xfd,0x04,0x0c,0x46,0x00,0x00,0x00,0x00,0x00,0xc0,0x5e,0x40] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt index c88fbc2..06ef877 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt @@ -868,7 +868,7 @@ 0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_and_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_not0_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x2d,0x80,0xbe # GFX12: s_and_not0_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x2d,0x80,0xbe] @@ -959,7 +959,7 @@ 0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_and_not0_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_not0_wrexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_not0_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x35,0x80,0xbe # GFX12: s_and_not0_wrexec_b64 s[0:1], -1 ; encoding: [0xc1,0x35,0x80,0xbe] @@ -1050,7 +1050,7 @@ 0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_and_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_not1_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x31,0x80,0xbe # GFX12: s_and_not1_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x31,0x80,0xbe] @@ -1141,7 +1141,7 @@ 0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_and_not1_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_not1_wrexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_not1_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x37,0x80,0xbe # GFX12: s_and_not1_wrexec_b64 s[0:1], -1 ; encoding: [0xc1,0x37,0x80,0xbe] @@ -1232,7 +1232,7 @@ 0xff,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_and_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x21,0x80,0xbe # GFX12: s_and_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x21,0x80,0xbe] @@ -1341,7 +1341,7 @@ 0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_bcnt0_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_bcnt0_i32_b64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_bcnt0_i32_b64 s0, 0xaf123456 ; encoding: [0xfe,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x17,0x80,0xbe # GFX12: s_bcnt0_i32_b64 s0, -1 ; encoding: [0xc1,0x17,0x80,0xbe] @@ -1453,7 +1453,7 @@ 0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_bcnt1_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_bcnt1_i32_b64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_bcnt1_i32_b64 s0, 0xaf123456 ; encoding: [0xfe,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x19,0x80,0xbe # GFX12: s_bcnt1_i32_b64 s0, -1 ; encoding: [0xc1,0x19,0x80,0xbe] @@ -1832,7 +1832,7 @@ 0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_brev_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_brev_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_brev_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x05,0x80,0xbe # GFX12: s_brev_b64 s[0:1], -1 ; encoding: [0xc1,0x05,0x80,0xbe] @@ -1887,7 +1887,7 @@ 0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_cls_i32_i64 s0, 0xaf123456 ; encoding: [0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_cls_i32_i64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_cls_i32_i64 s0, 0xaf123456 ; encoding: [0xfe,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x0d,0x80,0xbe # GFX12: s_cls_i32_i64 s0, -1 ; encoding: [0xc1,0x0d,0x80,0xbe] @@ -2053,7 +2053,7 @@ 0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_clz_i32_u64 s0, 0xaf123456 ; encoding: [0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_clz_i32_u64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_clz_i32_u64 s0, 0xaf123456 ; encoding: [0xfe,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x0b,0x80,0xbe # GFX12: s_clz_i32_u64 s0, -1 ; encoding: [0xc1,0x0b,0x80,0xbe] @@ -2159,7 +2159,7 @@ 0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_cmov_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_cmov_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_cmov_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x03,0x80,0xbe # GFX12: s_cmov_b64 s[0:1], -1 ; encoding: [0xc1,0x03,0x80,0xbe] @@ -2268,7 +2268,7 @@ 0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_ctz_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_ctz_i32_b64 s0, lit64(0xaf123456) ; encoding: [0xfe,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_ctz_i32_b64 s0, 0xaf123456 ; encoding: [0xfe,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x09,0x80,0xbe # GFX12: s_ctz_i32_b64 s0, -1 ; encoding: [0xc1,0x09,0x80,0xbe] @@ -2396,7 +2396,7 @@ 0xff,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_mov_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_mov_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_mov_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x01,0x80,0xbe # GFX12: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x01,0x80,0xbe] @@ -2493,7 +2493,7 @@ 0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_movreld_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_movreld_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_movreld_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x43,0x80,0xbe # GFX12: s_movreld_b64 s[0:1], -1 ; encoding: [0xc1,0x43,0x80,0xbe] @@ -2662,7 +2662,7 @@ 0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_nand_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_nand_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_nand_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x27,0x80,0xbe # GFX12: s_nand_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x27,0x80,0xbe] @@ -2753,7 +2753,7 @@ 0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_nor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_nor_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_nor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x29,0x80,0xbe # GFX12: s_nor_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x29,0x80,0xbe] @@ -2856,7 +2856,7 @@ 0xff,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_not_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_not_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_not_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x1f,0x80,0xbe # GFX12: s_not_b64 s[0:1], -1 ; encoding: [0xc1,0x1f,0x80,0xbe] @@ -2947,7 +2947,7 @@ 0xff,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_or_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_not0_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x2f,0x80,0xbe # GFX12: s_or_not0_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x2f,0x80,0xbe] @@ -3038,7 +3038,7 @@ 0xff,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_or_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_not1_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x33,0x80,0xbe # GFX12: s_or_not1_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x33,0x80,0xbe] @@ -3129,7 +3129,7 @@ 0xff,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_or_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x23,0x80,0xbe # GFX12: s_or_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x23,0x80,0xbe] @@ -3232,7 +3232,7 @@ 0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_quadmask_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_quadmask_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_quadmask_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x1b,0x80,0xbe # GFX12: s_quadmask_b64 s[0:1], -1 ; encoding: [0xc1,0x1b,0x80,0xbe] @@ -3549,7 +3549,7 @@ 0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_wqm_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_wqm_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_wqm_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x1d,0x80,0xbe # GFX12: s_wqm_b64 s[0:1], -1 ; encoding: [0xc1,0x1d,0x80,0xbe] @@ -3640,7 +3640,7 @@ 0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_xnor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_xnor_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_xnor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x2b,0x80,0xbe # GFX12: s_xnor_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x2b,0x80,0xbe] @@ -3731,7 +3731,7 @@ 0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf # GFX1200: s_xor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf] -# GFX1250: s_xor_saveexec_b64 s[0:1], lit64(0xaf123456) ; encoding: [0xfe,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_xor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xfe,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x25,0x80,0xbe # GFX12: s_xor_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x25,0x80,0xbe] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt index d889931..47b7408 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt @@ -56,7 +56,7 @@ 0xff,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf # GFX1200: s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf] -# GFX1250: s_add_nc_u64 s[0:1], lit64(0xaf123456), s[2:3] ; encoding: [0xfe,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xfe,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0x7e,0x80,0xa9 # GFX12: s_add_nc_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0xa9] @@ -81,7 +81,7 @@ 0x02,0xff,0x80,0xa9,0x56,0x34,0x12,0xaf # GFX1200: s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0xa9,0x56,0x34,0x12,0xaf] -# GFX1250: s_add_nc_u64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0xa9,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0x04,0x00,0xaa # GFX12: s_sub_nc_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x00,0xaa] @@ -136,7 +136,7 @@ 0xff,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf # GFX1200: s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf] -# GFX1250: s_sub_nc_u64 s[0:1], lit64(0xaf123456), s[2:3] ; encoding: [0xfe,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xfe,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0x7e,0x00,0xaa # GFX12: s_sub_nc_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x00,0xaa] @@ -161,7 +161,7 @@ 0x02,0xff,0x00,0xaa,0x56,0x34,0x12,0xaf # GFX1200: s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x00,0xaa,0x56,0x34,0x12,0xaf] -# GFX1250: s_sub_nc_u64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x00,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0x04,0x80,0xaa # GFX12: s_mul_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0xaa] @@ -216,7 +216,7 @@ 0xff,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf # GFX1200: s_mul_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf] -# GFX1250: s_mul_u64 s[0:1], lit64(0xaf123456), s[2:3] ; encoding: [0xfe,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_mul_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xfe,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0x7e,0x80,0xaa # GFX12: s_mul_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0xaa] @@ -241,7 +241,7 @@ 0x02,0xff,0x80,0xaa,0x56,0x34,0x12,0xaf # GFX1200: s_mul_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0xaa,0x56,0x34,0x12,0xaf] -# GFX1250: s_mul_u64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_mul_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0xaa,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x01,0x02,0x05,0xa0 # GFX12: s_add_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa0] @@ -1697,7 +1697,7 @@ 0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf # GFX1200: s_and_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x8b # GFX12: s_and_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8b] @@ -1725,7 +1725,7 @@ 0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf # GFX1200: s_and_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8b,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x8b # GFX12: s_and_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8b] @@ -1882,7 +1882,7 @@ 0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf # GFX1200: s_and_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_not1_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x91 # GFX12: s_and_not1_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x91] @@ -1910,7 +1910,7 @@ 0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf # GFX1200: s_and_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf] -# GFX1250: s_and_not1_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_and_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x91,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x91 # GFX12: s_and_not1_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x91] @@ -2067,7 +2067,7 @@ 0xff,0x04,0x80,0x86,0x56,0x34,0x12,0xaf # GFX1200: s_ashr_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x86,0x56,0x34,0x12,0xaf] -# GFX1250: s_ashr_i64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x86,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_ashr_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x86,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x86 # GFX12: s_ashr_i64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x86] @@ -2251,7 +2251,7 @@ 0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf # GFX1200: s_bfe_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf] -# GFX1250: s_bfe_i64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_bfe_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x94 # GFX12: s_bfe_i64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x94] @@ -2435,7 +2435,7 @@ 0xff,0x04,0x00,0x94,0x56,0x34,0x12,0xaf # GFX1200: s_bfe_u64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x00,0x94,0x56,0x34,0x12,0xaf] -# GFX1250: s_bfe_u64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x00,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_bfe_u64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x00,0x94,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x00,0x94 # GFX12: s_bfe_u64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x00,0x94] @@ -2820,7 +2820,7 @@ 0xff,0x04,0x80,0x98,0x56,0x34,0x12,0xaf # GFX1200: s_cselect_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x98,0x56,0x34,0x12,0xaf] -# GFX1250: s_cselect_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_cselect_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x98 # GFX12: s_cselect_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x98] @@ -2848,7 +2848,7 @@ 0x02,0xff,0x80,0x98,0x56,0x34,0x12,0xaf # GFX1200: s_cselect_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x98,0x56,0x34,0x12,0xaf] -# GFX1250: s_cselect_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_cselect_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x98,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x98 # GFX12: s_cselect_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x98] @@ -3425,7 +3425,7 @@ 0xff,0x04,0x80,0x84,0x56,0x34,0x12,0xaf # GFX1200: s_lshl_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x84,0x56,0x34,0x12,0xaf] -# GFX1250: s_lshl_b64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x84,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_lshl_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x84,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x84 # GFX12: s_lshl_b64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x84] @@ -3609,7 +3609,7 @@ 0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf # GFX1200: s_lshr_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf] -# GFX1250: s_lshr_b64 s[0:1], lit64(0xaf123456), s4 ; encoding: [0xfe,0x04,0x80,0x85,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_lshr_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xfe,0x04,0x80,0x85,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x85 # GFX12: s_lshr_b64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x85] @@ -4528,7 +4528,7 @@ 0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf # GFX1200: s_nand_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf] -# GFX1250: s_nand_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_nand_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x8e # GFX12: s_nand_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8e] @@ -4556,7 +4556,7 @@ 0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf # GFX1200: s_nand_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf] -# GFX1250: s_nand_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_nand_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8e,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x8e # GFX12: s_nand_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8e] @@ -4713,7 +4713,7 @@ 0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf # GFX1200: s_nor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf] -# GFX1250: s_nor_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_nor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x8f # GFX12: s_nor_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8f] @@ -4741,7 +4741,7 @@ 0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf # GFX1200: s_nor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf] -# GFX1250: s_nor_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_nor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x8f # GFX12: s_nor_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8f] @@ -4898,7 +4898,7 @@ 0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf # GFX1200: s_or_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x8c # GFX12: s_or_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8c] @@ -4926,7 +4926,7 @@ 0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf # GFX1200: s_or_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8c,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x8c # GFX12: s_or_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8c] @@ -5083,7 +5083,7 @@ 0xff,0x04,0x80,0x92,0x56,0x34,0x12,0xaf # GFX1200: s_or_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x92,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_not1_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x92 # GFX12: s_or_not1_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x92] @@ -5111,7 +5111,7 @@ 0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf # GFX1200: s_or_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf] -# GFX1250: s_or_not1_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_or_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x92,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x92 # GFX12: s_or_not1_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x92] @@ -5898,7 +5898,7 @@ 0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf # GFX1200: s_xnor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf] -# GFX1250: s_xnor_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_xnor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x90 # GFX12: s_xnor_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x90] @@ -5926,7 +5926,7 @@ 0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf # GFX1200: s_xnor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf] -# GFX1250: s_xnor_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_xnor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x90,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x90 # GFX12: s_xnor_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x90] @@ -6083,7 +6083,7 @@ 0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf # GFX1200: s_xor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf] -# GFX1250: s_xor_b64 s[0:1], lit64(0xaf123456), s[4:5] ; encoding: [0xfe,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_xor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xfe,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0xc1,0x04,0x80,0x8d # GFX12: s_xor_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8d] @@ -6111,7 +6111,7 @@ 0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf # GFX1200: s_xor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf] -# GFX1250: s_xor_b64 s[0:1], s[2:3], lit64(0xaf123456) ; encoding: [0x02,0xfe,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_xor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xfe,0x80,0x8d,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x02,0xc1,0x80,0x8d # GFX12: s_xor_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8d] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt index a8da16f..9355582 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt @@ -1492,7 +1492,7 @@ 0x00,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf # GFX1200: s_cmp_eq_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf] -# GFX1250: s_cmp_eq_u64 s[0:1], lit64(0xaf123456) ; encoding: [0x00,0xfe,0x10,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_cmp_eq_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xfe,0x10,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x00,0xc1,0x10,0xbf # GFX12: s_cmp_eq_u64 s[0:1], -1 ; encoding: [0x00,0xc1,0x10,0xbf] @@ -2015,7 +2015,7 @@ 0x00,0xff,0x11,0xbf,0x56,0x34,0x12,0xaf # GFX1200: s_cmp_lg_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x11,0xbf,0x56,0x34,0x12,0xaf] -# GFX1250: s_cmp_lg_u64 s[0:1], lit64(0xaf123456) ; encoding: [0x00,0xfe,0x11,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] +# GFX1250: s_cmp_lg_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xfe,0x11,0xbf,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00] 0x00,0xc1,0x11,0xbf # GFX12: s_cmp_lg_u64 s[0:1], -1 ; encoding: [0x00,0xc1,0x11,0xbf] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt index 7a7be57..d6a176e 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt @@ -1,10 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-REAL16 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX1200-FAKE16 %s # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-REAL16 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX1200-FAKE16 %s # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-REAL16 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX1250-FAKE16 %s 0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05 # GFX12: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05] @@ -22,7 +22,8 @@ 0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_ceil_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_ceil_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -55,7 +56,8 @@ 0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cos_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cos_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -94,7 +96,8 @@ 0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_f16_f32_dpp v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[1:2], v[187:188] ; encoding: [0x01,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[1:2], v[187:188] ; encoding: [0x01,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[1:2]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x01,0x77,0x39,0x05] 0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_f16_f32_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -109,7 +112,8 @@ 0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_f16_i16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_f16_i16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -124,7 +128,8 @@ 0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_f16_u16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_f16_u16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -197,7 +202,8 @@ 0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -240,7 +246,8 @@ 0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_norm_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_norm_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -255,7 +262,8 @@ 0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_norm_u16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_norm_u16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -276,7 +284,8 @@ 0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_cvt_u16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_cvt_u16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -313,7 +322,8 @@ 0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_exp_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_exp_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -334,7 +344,8 @@ 0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_floor_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_floor_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -355,7 +366,8 @@ 0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_fract_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_fract_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -376,7 +388,8 @@ 0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_frexp_exp_i16_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_frexp_exp_i16_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -397,7 +410,8 @@ 0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -418,7 +432,8 @@ 0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_log_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_log_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -469,7 +484,8 @@ 0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_not_b16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_not_b16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -491,7 +507,8 @@ 0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_rcp_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_rcp_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -518,7 +535,8 @@ 0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_rndne_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_rndne_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -539,7 +557,8 @@ 0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_rsq_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_rsq_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -560,7 +579,8 @@ 0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05 # GFX12-REAL16: v_sat_pk_u8_i16_dpp v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0x0a,0x7f,0x01,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[1:2], v[187:188] ; encoding: [0x01,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[1:2], v[187:188] ; encoding: [0x01,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[1:2]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x01,0x77,0x39,0x05] 0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_sat_pk_u8_i16_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -575,7 +595,8 @@ 0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_sin_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_sin_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -596,7 +617,8 @@ 0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_sqrt_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_sqrt_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7f,0xff,0x00,0x00,0x00] @@ -617,7 +639,8 @@ 0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05 # GFX12-REAL16: v_trunc_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05] -# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1200-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05] +# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130]/*Invalid register, operand has 'VS_64_Align2' register class*/, v[187:188]/*Invalid register, operand has 'VReg_64_Align2' register class*/ ; encoding: [0x81,0x77,0x39,0x05] 0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00 # GFX12-REAL16: v_trunc_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index b8cd6de..111616d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -420,8 +420,8 @@ .attribute arch, "rv32ia_zacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0" -.attribute arch, "rv32izalasr0p1" -# CHECK: attribute 5, "rv32i2p1_zalasr0p1" +.attribute arch, "rv32izalasr0p9" +# CHECK: attribute 5, "rv32i2p1_zalasr0p9" .attribute arch, "rv32i_xcvalu" # CHECK: attribute 5, "rv32i2p1_xcvalu1p0" diff --git a/llvm/test/Other/new-pm-print-pipeline.ll b/llvm/test/Other/new-pm-print-pipeline.ll index 6fa57f1..3536932 100644 --- a/llvm/test/Other/new-pm-print-pipeline.ll +++ b/llvm/test/Other/new-pm-print-pipeline.ll @@ -50,7 +50,7 @@ ; CHECK-17: function(print<stack-lifetime><may>,print<stack-lifetime><must>) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='function(simplifycfg<bonus-inst-threshold=5;forward-switch-cond;switch-to-lookup;keep-loops;hoist-common-insts;hoist-loads-stores-with-cond-faulting;sink-common-insts;speculate-blocks;simplify-cond-branch;speculate-unpredictables>,simplifycfg<bonus-inst-threshold=7;no-forward-switch-cond;no-switch-to-lookup;no-keep-loops;no-hoist-common-insts;no-hoist-loads-stores-with-cond-faulting;no-sink-common-insts;no-speculate-blocks;no-simplify-cond-branch;no-speculate-unpredictables>)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-18 -; CHECK-18: function(simplifycfg<bonus-inst-threshold=5;forward-switch-cond;no-switch-range-to-icmp;switch-to-lookup;keep-loops;hoist-common-insts;hoist-loads-stores-with-cond-faulting;sink-common-insts;speculate-blocks;simplify-cond-branch;speculate-unpredictables>,simplifycfg<bonus-inst-threshold=7;no-forward-switch-cond;no-switch-range-to-icmp;no-switch-to-lookup;no-keep-loops;no-hoist-common-insts;no-hoist-loads-stores-with-cond-faulting;no-sink-common-insts;no-speculate-blocks;no-simplify-cond-branch;no-speculate-unpredictables>) +; CHECK-18: function(simplifycfg<bonus-inst-threshold=5;forward-switch-cond;no-switch-range-to-icmp;no-switch-to-arithmetic;switch-to-lookup;keep-loops;hoist-common-insts;hoist-loads-stores-with-cond-faulting;sink-common-insts;speculate-blocks;simplify-cond-branch;speculate-unpredictables>,simplifycfg<bonus-inst-threshold=7;no-forward-switch-cond;no-switch-range-to-icmp;no-switch-to-arithmetic;no-switch-to-lookup;no-keep-loops;no-hoist-common-insts;no-hoist-loads-stores-with-cond-faulting;no-sink-common-insts;no-speculate-blocks;no-simplify-cond-branch;no-speculate-unpredictables>) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='function(loop-vectorize<no-interleave-forced-only;no-vectorize-forced-only>,loop-vectorize<interleave-forced-only;vectorize-forced-only>)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-19 ; CHECK-19: function(loop-vectorize<no-interleave-forced-only;no-vectorize-forced-only;>,loop-vectorize<interleave-forced-only;vectorize-forced-only;>) diff --git a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll index 3a306a4..ccef61d 100644 --- a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll +++ b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll @@ -12,7 +12,7 @@ target triple = "sparcv9-unknown-unknown" define i8 @test_cmpxchg_i8(ptr %arg, i8 %old, i8 %new) { ; CHECK-LABEL: @test_cmpxchg_i8( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -45,7 +45,7 @@ define i8 @test_cmpxchg_i8(ptr %arg, i8 %old, i8 %new) { ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } poison, i8 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i8, i1 } [[TMP17]], i1 [[TMP14]], 1 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: [[RET:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i8 [[RET]] ; @@ -58,7 +58,7 @@ entry: define i16 @test_cmpxchg_i16(ptr %arg, i16 %old, i16 %new) { ; CHECK-LABEL: @test_cmpxchg_i16( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -91,7 +91,7 @@ define i16 @test_cmpxchg_i16(ptr %arg, i16 %old, i16 %new) { ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i16, i1 } [[TMP17]], i1 [[TMP14]], 1 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: [[RET:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i16 [[RET]] ; @@ -104,7 +104,7 @@ entry: define i16 @test_add_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_add_i16( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -130,7 +130,7 @@ define i16 @test_add_i16(ptr %arg, i16 %val) { ; CHECK: atomicrmw.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: @@ -141,7 +141,7 @@ entry: define i16 @test_xor_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_xor_i16( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -164,7 +164,7 @@ define i16 @test_xor_i16(ptr %arg, i16 %val) { ; CHECK: atomicrmw.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: @@ -175,7 +175,7 @@ entry: define i16 @test_or_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_or_i16( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -198,7 +198,7 @@ define i16 @test_or_i16(ptr %arg, i16 %val) { ; CHECK: atomicrmw.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: @@ -209,7 +209,7 @@ entry: define i16 @test_and_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_and_i16( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -233,7 +233,7 @@ define i16 @test_and_i16(ptr %arg, i16 %val) { ; CHECK: atomicrmw.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: @@ -244,7 +244,7 @@ entry: define i16 @test_min_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_min_i16( ; CHECK-NEXT: entry: -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 @@ -272,7 +272,7 @@ define i16 @test_min_i16(ptr %arg, i16 %val) { ; CHECK: atomicrmw.end: ; CHECK-NEXT: [[SHIFTED2:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i16 -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: ret i16 [[EXTRACTED3]] ; entry: @@ -282,7 +282,7 @@ entry: define half @test_atomicrmw_fadd_f16(ptr %ptr, half %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f16( -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence release ; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 @@ -312,7 +312,7 @@ define half @test_atomicrmw_fadd_f16(ptr %ptr, half %value) { ; CHECK-NEXT: [[SHIFTED2:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i16 ; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED3]] to half -; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: fence acquire ; CHECK-NEXT: ret half [[TMP8]] ; %res = atomicrmw fadd ptr %ptr, half %value seq_cst diff --git a/llvm/test/Transforms/GVN/ptrtoaddr.ll b/llvm/test/Transforms/GVN/ptrtoaddr.ll new file mode 100644 index 0000000..6d02bc6 --- /dev/null +++ b/llvm/test/Transforms/GVN/ptrtoaddr.ll @@ -0,0 +1,30 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=gvn < %s | FileCheck %s + +define i64 @ptrtoaddr_same(ptr %p) { +; CHECK-LABEL: define i64 @ptrtoaddr_same( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[J:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: ret i64 0 +; + %i = ptrtoaddr ptr %p to i64 + %j = ptrtoaddr ptr %p to i64 + %sub = sub i64 %i, %j + ret i64 %sub +} + +; Note that unlike for ptrtoint, it's not possible for ptrtoaddr to differ +; in result type for the same input. +define i64 @ptrtoaddr_different(ptr %p, ptr %p2) { +; CHECK-LABEL: define i64 @ptrtoaddr_different( +; CHECK-SAME: ptr [[P:%.*]], ptr [[P2:%.*]]) { +; CHECK-NEXT: [[I:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[J:%.*]] = ptrtoaddr ptr [[P2]] to i64 +; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[I]], [[J]] +; CHECK-NEXT: ret i64 [[SUB]] +; + %i = ptrtoaddr ptr %p to i64 + %j = ptrtoaddr ptr %p2 to i64 + %sub = sub i64 %i, %j + ret i64 %sub +} diff --git a/llvm/test/Transforms/InstCombine/fold-selective-shift.ll b/llvm/test/Transforms/InstCombine/fold-selective-shift.ll new file mode 100644 index 0000000..2b22965 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/fold-selective-shift.ll @@ -0,0 +1,323 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -passes=instcombine %s -S | FileCheck %s + +declare void @clobber.i32(i32) + +define i16 @selective_shift_16(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]] +; CHECK-NEXT: ret i16 [[SEL_V]] +; + %upper.zext = zext i16 %upper to i32 + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + %pack = or disjoint i32 %upper.shl, %lower.zext + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +define i16 @selective_shift_16.commute(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.commute( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]] +; CHECK-NEXT: ret i16 [[SEL_V]] +; + %upper.zext = zext i16 %upper to i32 + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + %pack = or disjoint i32 %lower.zext, %upper.shl + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +define i16 @selective_shift_16.range(i32 %mask, i32 %upper, i32 range(i32 0, 65536) %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.range( +; CHECK-SAME: i32 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 range(i32 0, 65536) [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.shl = shl nuw i32 %upper, 16 + %pack = or disjoint i32 %upper.shl, %lower + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +define i16 @selective_shift_16.range.commute(i32 %mask, i32 %upper, i32 range(i32 0, 65536) %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.range.commute( +; CHECK-SAME: i32 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 range(i32 0, 65536) [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.shl = shl nuw i32 %upper, 16 + %pack = or disjoint i32 %lower, %upper.shl + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +define i32 @selective_shift_16.masked(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i32 @selective_shift_16.masked( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]] +; CHECK-NEXT: [[SEL:%.*]] = zext i16 [[SEL_V]] to i32 +; CHECK-NEXT: ret i32 [[SEL]] +; + %upper.zext = zext i16 %upper to i32 + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + %pack = or disjoint i32 %lower.zext, %upper.shl + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %sel.masked = and i32 %sel, 65535 + ret i32 %sel.masked +} + +define i32 @selective_shift_16.masked.commute(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i32 @selective_shift_16.masked.commute( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]] +; CHECK-NEXT: [[SEL:%.*]] = zext i16 [[SEL_V]] to i32 +; CHECK-NEXT: ret i32 [[SEL]] +; + %upper.zext = zext i16 %upper to i32 + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + %pack = or disjoint i32 %upper.shl, %lower.zext + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %sel.masked = and i32 %sel, 65535 + ret i32 %sel.masked +} + +define <2 x i16> @selective_shift.v16(<2 x i32> %mask, <2 x i16> %upper, <2 x i16> %lower) { +; CHECK-LABEL: define <2 x i16> @selective_shift.v16( +; CHECK-SAME: <2 x i32> [[MASK:%.*]], <2 x i16> [[UPPER:%.*]], <2 x i16> [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and <2 x i32> [[MASK]], splat (i32 16) +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq <2 x i32> [[MASK_BIT]], zeroinitializer +; CHECK-NEXT: [[SEL_V:%.*]] = select <2 x i1> [[MASK_BIT_Z]], <2 x i16> [[LOWER]], <2 x i16> [[UPPER]] +; CHECK-NEXT: ret <2 x i16> [[SEL_V]] +; + %upper.zext = zext <2 x i16> %upper to <2 x i32> + %upper.shl = shl nuw <2 x i32> %upper.zext, splat(i32 16) + %lower.zext = zext <2 x i16> %lower to <2 x i32> + %pack = or disjoint <2 x i32> %upper.shl, %lower.zext + %mask.bit = and <2 x i32> %mask, splat(i32 16) + %sel = lshr <2 x i32> %pack, %mask.bit + %trunc = trunc <2 x i32> %sel to <2 x i16> + ret <2 x i16> %trunc +} + +define i16 @selective_shift_16.wide(i64 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.wide( +; CHECK-SAME: i64 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i64 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i64 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]] +; CHECK-NEXT: ret i16 [[SEL_V]] +; + %upper.zext = zext i16 %upper to i64 + %upper.shl = shl nuw i64 %upper.zext, 16 + %lower.zext = zext i16 %lower to i64 + %pack = or disjoint i64 %upper.shl, %lower.zext + %mask.bit = and i64 %mask, 16 + %sel = lshr i64 %pack, %mask.bit + %trunc = trunc i64 %sel to i16 + ret i16 %trunc +} + +; narrow zext type blocks fold +define i16 @selective_shift_16.narrow(i24 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.narrow( +; CHECK-SAME: i24 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i24 +; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl i24 [[UPPER_ZEXT]], 16 +; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i24 +; CHECK-NEXT: [[PACK:%.*]] = or disjoint i24 [[UPPER_SHL]], [[LOWER_ZEXT]] +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i24 [[MASK]], 16 +; CHECK-NEXT: [[SEL:%.*]] = lshr i24 [[PACK]], [[MASK_BIT]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i24 [[SEL]] to i16 +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.zext = zext i16 %upper to i24 + %upper.shl = shl i24 %upper.zext, 16 + %lower.zext = zext i16 %lower to i24 + %pack = or disjoint i24 %upper.shl, %lower.zext + %mask.bit = and i24 %mask, 16 + %sel = lshr i24 %pack, %mask.bit + %trunc = trunc i24 %sel to i16 + ret i16 %trunc +} + +; %lower's upper bits block fold +define i16 @selective_shift_16_norange(i32 %mask, i32 %upper, i32 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16_norange( +; CHECK-SAME: i32 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 [[LOWER:%.*]]) { +; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i32 [[UPPER]], 16 +; CHECK-NEXT: [[PACK:%.*]] = or i32 [[UPPER_SHL]], [[LOWER]] +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[SEL:%.*]] = lshr i32 [[PACK]], [[MASK_BIT]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.shl = shl nuw i32 %upper, 16 + %pack = or i32 %upper.shl, %lower + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +define i16 @selective_shift_16.mu.0(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.mu.0( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i32 +; CHECK-NEXT: call void @clobber.i32(i32 [[UPPER_ZEXT]]) +; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i32 +; CHECK-NEXT: call void @clobber.i32(i32 [[LOWER_ZEXT]]) +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0 +; CHECK-NEXT: [[TRUNC:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]] +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.zext = zext i16 %upper to i32 + call void @clobber.i32(i32 %upper.zext) + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + call void @clobber.i32(i32 %lower.zext) + %pack = or disjoint i32 %upper.shl, %lower.zext + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +; multi-use of %pack blocks fold +define i16 @selective_shift_16.mu.1(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.mu.1( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i32 +; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i32 [[UPPER_ZEXT]], 16 +; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i32 +; CHECK-NEXT: [[PACK:%.*]] = or disjoint i32 [[UPPER_SHL]], [[LOWER_ZEXT]] +; CHECK-NEXT: call void @clobber.i32(i32 [[PACK]]) +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[SEL:%.*]] = lshr i32 [[PACK]], [[MASK_BIT]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.zext = zext i16 %upper to i32 + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + %pack = or disjoint i32 %upper.shl, %lower.zext + call void @clobber.i32(i32 %pack) + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +; non-truncated use of %sel blocks fold +define i16 @selective_shift_16.mu.2(i32 %mask, i16 %upper, i16 %lower) { +; CHECK-LABEL: define i16 @selective_shift_16.mu.2( +; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) { +; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i32 +; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i32 [[UPPER_ZEXT]], 16 +; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i32 +; CHECK-NEXT: [[PACK:%.*]] = or disjoint i32 [[UPPER_SHL]], [[LOWER_ZEXT]] +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16 +; CHECK-NEXT: [[SEL:%.*]] = lshr i32 [[PACK]], [[MASK_BIT]] +; CHECK-NEXT: call void @clobber.i32(i32 [[SEL]]) +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: ret i16 [[TRUNC]] +; + %upper.zext = zext i16 %upper to i32 + %upper.shl = shl nuw i32 %upper.zext, 16 + %lower.zext = zext i16 %lower to i32 + %pack = or disjoint i32 %upper.shl, %lower.zext + %mask.bit = and i32 %mask, 16 + %sel = lshr i32 %pack, %mask.bit + call void @clobber.i32(i32 %sel) + %trunc = trunc i32 %sel to i16 + ret i16 %trunc +} + +; bitwidth must be a power of 2 to fold +define i24 @selective_shift_24(i48 %mask, i24 %upper, i24 %lower) { +; CHECK-LABEL: define i24 @selective_shift_24( +; CHECK-SAME: i48 [[MASK:%.*]], i24 [[UPPER:%.*]], i24 [[LOWER:%.*]]) { +; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i24 [[UPPER]] to i48 +; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i48 [[UPPER_ZEXT]], 24 +; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i24 [[LOWER]] to i48 +; CHECK-NEXT: [[PACK:%.*]] = or disjoint i48 [[UPPER_SHL]], [[LOWER_ZEXT]] +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i48 [[MASK]], 24 +; CHECK-NEXT: [[SEL:%.*]] = lshr i48 [[PACK]], [[MASK_BIT]] +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i48 [[SEL]] to i24 +; CHECK-NEXT: ret i24 [[TRUNC]] +; + %upper.zext = zext i24 %upper to i48 + %upper.shl = shl nuw i48 %upper.zext, 24 + %lower.zext = zext i24 %lower to i48 + %pack = or disjoint i48 %upper.shl, %lower.zext + %mask.bit = and i48 %mask, 24 + %sel = lshr i48 %pack, %mask.bit + %trunc = trunc i48 %sel to i24 + ret i24 %trunc +} + +define i32 @selective_shift_32(i64 %mask, i32 %upper, i32 %lower) { +; CHECK-LABEL: define i32 @selective_shift_32( +; CHECK-SAME: i64 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i64 [[MASK]], 32 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i64 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]] +; CHECK-NEXT: ret i32 [[SEL_V]] +; + %upper.zext = zext i32 %upper to i64 + %upper.shl = shl nuw i64 %upper.zext, 32 + %lower.zext = zext i32 %lower to i64 + %pack = or disjoint i64 %upper.shl, %lower.zext + %mask.bit = and i64 %mask, 32 + %sel = lshr i64 %pack, %mask.bit + %trunc = trunc i64 %sel to i32 + ret i32 %trunc +} + +define i32 @selective_shift_32.commute(i64 %mask, i32 %upper, i32 %lower) { +; CHECK-LABEL: define i32 @selective_shift_32.commute( +; CHECK-SAME: i64 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 [[LOWER:%.*]]) { +; CHECK-NEXT: [[MASK_BIT:%.*]] = and i64 [[MASK]], 32 +; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i64 [[MASK_BIT]], 0 +; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]] +; CHECK-NEXT: ret i32 [[SEL_V]] +; + %upper.zext = zext i32 %upper to i64 + %upper.shl = shl nuw i64 %upper.zext, 32 + %lower.zext = zext i32 %lower to i64 + %pack = or disjoint i64 %lower.zext, %upper.shl + %mask.bit = and i64 %mask, 32 + %sel = lshr i64 %pack, %mask.bit + %trunc = trunc i64 %sel to i32 + ret i32 %trunc +} diff --git a/llvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll b/llvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll deleted file mode 100644 index 72bc543..0000000 --- a/llvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll +++ /dev/null @@ -1,164 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S < %s -passes='loop(loop-rotate)' -loop-rotate-multi=true | FileCheck %s - -; Test loop rotation with multiple exits, some of them - deoptimizing. -; We should end up with a latch which exit is non-deoptimizing, so we should rotate -; more than once. - -declare i32 @llvm.experimental.deoptimize.i32(...) - -define i32 @test_cond_with_one_deopt_exit(ptr nonnull %a, i64 %x) { -; Rotation done twice. -; Latch should be at the 2nd condition (for.cond2), exiting to %return. -; -; CHECK-LABEL: @test_cond_with_one_deopt_exit( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[VAL_A_IDX3:%.*]] = load i32, ptr %a, align 4 -; CHECK-NEXT: [[ZERO_CHECK4:%.*]] = icmp eq i32 [[VAL_A_IDX3]], 0 -; CHECK-NEXT: br i1 [[ZERO_CHECK4]], label %deopt.exit, label %for.cond2.lr.ph -; CHECK: for.cond2.lr.ph: -; CHECK-NEXT: [[FOR_CHECK8:%.*]] = icmp ult i64 0, %x -; CHECK-NEXT: br i1 [[FOR_CHECK8]], label %for.body.lr.ph, label %return -; CHECK: for.body.lr.ph: -; CHECK-NEXT: br label %for.body -; CHECK: for.cond2: -; CHECK: [[FOR_CHECK:%.*]] = icmp ult i64 {{%.*}}, %x -; CHECK-NEXT: br i1 [[FOR_CHECK]], label %for.body, label %for.cond2.return_crit_edge -; CHECK: for.body: -; CHECK: br label %for.tail -; CHECK: for.tail: -; CHECK: [[VAL_A_IDX:%.*]] = load i32, ptr -; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[VAL_A_IDX]], 0 -; CHECK-NEXT: br i1 [[ZERO_CHECK]], label %for.cond1.deopt.exit_crit_edge, label %for.cond2 -; CHECK: for.cond2.return_crit_edge: -; CHECK-NEXT: {{%.*}} = phi i32 -; CHECK-NEXT: br label %return -; CHECK: return: -; CHECK-NEXT: [[SUM_LCSSA2:%.*]] = phi i32 -; CHECK-NEXT: ret i32 [[SUM_LCSSA2]] -; CHECK: for.cond1.deopt.exit_crit_edge: -; CHECK-NEXT: {{%.*}} = phi i32 -; CHECK-NEXT: br label %deopt.exit -; CHECK: deopt.exit: -; CHECK: [[DEOPT_VAL:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 {{%.*}}) ] -; CHECK-NEXT: ret i32 [[DEOPT_VAL]] -; -entry: - br label %for.cond1 - -for.cond1: - %idx = phi i64 [ 0, %entry ], [ %idx.next, %for.tail ] - %sum = phi i32 [ 0, %entry ], [ %sum.next, %for.tail ] - %a.idx = getelementptr inbounds i32, ptr %a, i64 %idx - %val.a.idx = load i32, ptr %a.idx, align 4 - %zero.check = icmp eq i32 %val.a.idx, 0 - br i1 %zero.check, label %deopt.exit, label %for.cond2 - -for.cond2: - %for.check = icmp ult i64 %idx, %x - br i1 %for.check, label %for.body, label %return - -for.body: - br label %for.tail - -for.tail: - %sum.next = add i32 %sum, %val.a.idx - %idx.next = add nuw nsw i64 %idx, 1 - br label %for.cond1 - -return: - ret i32 %sum - -deopt.exit: - %deopt.val = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 %val.a.idx) ] - ret i32 %deopt.val -} - -define i32 @test_cond_with_two_deopt_exits(ptr nonnull %a, i64 %x) { -; Rotation done three times. -; Latch should be at the 3rd condition (for.cond3), exiting to %return. -; -; CHECK-LABEL: @test_cond_with_two_deopt_exits( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[A_IDX_DEREF4:%.*]] = load ptr, ptr %a -; CHECK-NEXT: [[NULL_CHECK5:%.*]] = icmp eq ptr [[A_IDX_DEREF4]], null -; CHECK-NEXT: br i1 [[NULL_CHECK5]], label %deopt.exit1, label %for.cond2.lr.ph -; CHECK: for.cond2.lr.ph: -; CHECK-NEXT: [[VAL_A_IDX9:%.*]] = load i32, ptr [[A_IDX_DEREF4]], align 4 -; CHECK-NEXT: [[ZERO_CHECK10:%.*]] = icmp eq i32 [[VAL_A_IDX9]], 0 -; CHECK-NEXT: br i1 [[ZERO_CHECK10]], label %deopt.exit2, label %for.cond3.lr.ph -; CHECK: for.cond3.lr.ph: -; CHECK-NEXT: [[FOR_CHECK14:%.*]] = icmp ult i64 0, %x -; CHECK-NEXT: br i1 [[FOR_CHECK14]], label %for.body.lr.ph, label %return -; CHECK: for.body.lr.ph: -; CHECK-NEXT: br label %for.body -; CHECK: for.cond2: -; CHECK: [[VAL_A_IDX:%.*]] = load i32, ptr -; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[VAL_A_IDX]], 0 -; CHECK-NEXT: br i1 [[ZERO_CHECK]], label %for.cond2.deopt.exit2_crit_edge, label %for.cond3 -; CHECK: for.cond3: -; CHECK: [[FOR_CHECK:%.*]] = icmp ult i64 {{%.*}}, %x -; CHECK-NEXT: br i1 [[FOR_CHECK]], label %for.body, label %for.cond3.return_crit_edge -; CHECK: for.body: -; CHECK: br label %for.tail -; CHECK: for.tail: -; CHECK: [[IDX_NEXT:%.*]] = add nuw nsw i64 {{%.*}}, 1 -; CHECK: [[NULL_CHECK:%.*]] = icmp eq ptr {{%.*}}, null -; CHECK-NEXT: br i1 [[NULL_CHECK]], label %for.cond1.deopt.exit1_crit_edge, label %for.cond2 -; CHECK: for.cond3.return_crit_edge: -; CHECK-NEXT: [[SPLIT18:%.*]] = phi i32 -; CHECK-NEXT: br label %return -; CHECK: return: -; CHECK-NEXT: [[SUM_LCSSA2:%.*]] = phi i32 -; CHECK-NEXT: ret i32 [[SUM_LCSSA2]] -; CHECK: for.cond1.deopt.exit1_crit_edge: -; CHECK-NEXT: br label %deopt.exit1 -; CHECK: deopt.exit1: -; CHECK-NEXT: [[DEOPT_VAL1:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 0) ] -; CHECK-NEXT: ret i32 [[DEOPT_VAL1]] -; CHECK: for.cond2.deopt.exit2_crit_edge: -; CHECK-NEXT: [[SPLIT:%.*]] = phi i32 -; CHECK-NEXT: br label %deopt.exit2 -; CHECK: deopt.exit2: -; CHECK-NEXT: [[VAL_A_IDX_LCSSA:%.*]] = phi i32 -; CHECK-NEXT: [[DEOPT_VAL2:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 [[VAL_A_IDX_LCSSA]]) ] -; CHECK-NEXT: ret i32 [[DEOPT_VAL2]] -; -entry: - br label %for.cond1 - -for.cond1: - %idx = phi i64 [ 0, %entry ], [ %idx.next, %for.tail ] - %sum = phi i32 [ 0, %entry ], [ %sum.next, %for.tail ] - %a.idx = getelementptr inbounds ptr, ptr %a, i64 %idx - %a.idx.deref = load ptr, ptr %a.idx - %null.check = icmp eq ptr %a.idx.deref, null - br i1 %null.check, label %deopt.exit1, label %for.cond2 - -for.cond2: - %val.a.idx = load i32, ptr %a.idx.deref, align 4 - %zero.check = icmp eq i32 %val.a.idx, 0 - br i1 %zero.check, label %deopt.exit2, label %for.cond3 - -for.cond3: - %for.check = icmp ult i64 %idx, %x - br i1 %for.check, label %for.body, label %return - -for.body: - br label %for.tail - -for.tail: - %sum.next = add i32 %sum, %val.a.idx - %idx.next = add nuw nsw i64 %idx, 1 - br label %for.cond1 - -return: - ret i32 %sum - -deopt.exit1: - %deopt.val1 = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 0) ] - ret i32 %deopt.val1 -deopt.exit2: - %deopt.val2 = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 %val.a.idx) ] - ret i32 %deopt.val2 -} diff --git a/llvm/test/Transforms/LoopRotate/multiple-exits.ll b/llvm/test/Transforms/LoopRotate/multiple-exits.ll deleted file mode 100644 index 748700c..0000000 --- a/llvm/test/Transforms/LoopRotate/multiple-exits.ll +++ /dev/null @@ -1,236 +0,0 @@ -; RUN: opt -S -passes=loop-rotate < %s -verify-loop-info -verify-dom-info -verify-memoryssa | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -target triple = "x86_64-apple-macosx10.8.0" - -; PR7447 -define i32 @test1(ptr nocapture %a) nounwind readonly { -entry: - br label %for.cond - -for.cond: ; preds = %for.cond1, %entry - %sum.0 = phi i32 [ 0, %entry ], [ %sum.1, %for.cond1 ] - %i.0 = phi i1 [ true, %entry ], [ false, %for.cond1 ] - br i1 %i.0, label %for.cond1, label %return - -for.cond1: ; preds = %for.cond, %land.rhs - %sum.1 = phi i32 [ %add, %land.rhs ], [ %sum.0, %for.cond ] - %i.1 = phi i32 [ %inc, %land.rhs ], [ 0, %for.cond ] - %cmp2 = icmp ult i32 %i.1, 100 - br i1 %cmp2, label %land.rhs, label %for.cond - -land.rhs: ; preds = %for.cond1 - %conv = zext i32 %i.1 to i64 - %arrayidx = getelementptr inbounds [100 x i32], ptr %a, i64 0, i64 %conv - %0 = load i32, ptr %arrayidx, align 4 - %add = add i32 %0, %sum.1 - %cmp4 = icmp ugt i32 %add, 1000 - %inc = add i32 %i.1, 1 - br i1 %cmp4, label %return, label %for.cond1 - -return: ; preds = %for.cond, %land.rhs - %retval.0 = phi i32 [ 1000, %land.rhs ], [ %sum.0, %for.cond ] - ret i32 %retval.0 - -; CHECK-LABEL: @test1( -; CHECK: for.cond1.preheader: -; CHECK: %sum.04 = phi i32 [ 0, %entry ], [ %sum.1.lcssa, %for.cond.loopexit ] -; CHECK: br label %for.cond1 - -; CHECK: for.cond1: -; CHECK: %sum.1 = phi i32 [ %add, %land.rhs ], [ %sum.04, %for.cond1.preheader ] -; CHECK: %i.1 = phi i32 [ %inc, %land.rhs ], [ 0, %for.cond1.preheader ] -; CHECK: %cmp2 = icmp ult i32 %i.1, 100 -; CHECK: br i1 %cmp2, label %land.rhs, label %for.cond.loopexit -} - -define void @test2(i32 %x) nounwind { -entry: - br label %for.cond - -for.cond: ; preds = %if.end, %entry - %i.0 = phi i32 [ 0, %entry ], [ %inc, %if.end ] - %cmp = icmp eq i32 %i.0, %x - br i1 %cmp, label %return.loopexit, label %for.body - -for.body: ; preds = %for.cond - %call = tail call i32 @foo(i32 %i.0) nounwind - %tobool = icmp eq i32 %call, 0 - br i1 %tobool, label %if.end, label %a - -if.end: ; preds = %for.body - %call1 = tail call i32 @foo(i32 42) nounwind - %inc = add i32 %i.0, 1 - br label %for.cond - -a: ; preds = %for.body - %call2 = tail call i32 @bar(i32 1) nounwind - br label %return - -return.loopexit: ; preds = %for.cond - br label %return - -return: ; preds = %return.loopexit, %a - ret void - -; CHECK-LABEL: @test2( -; CHECK: if.end: -; CHECK: %inc = add i32 %i.02, 1 -; CHECK: %cmp = icmp eq i32 %inc, %x -; CHECK: br i1 %cmp, label %for.cond.return.loopexit_crit_edge, label %for.body -} - -declare i32 @foo(i32) - -declare i32 @bar(i32) - -@_ZTIi = external constant ptr - -; Verify dominators. -define void @test3(i32 %x) personality ptr @__gxx_personality_v0 { -entry: - %cmp2 = icmp eq i32 0, %x - br i1 %cmp2, label %try.cont.loopexit, label %for.body.lr.ph - -for.body.lr.ph: ; preds = %entry - br label %for.body - -for.body: ; preds = %for.body.lr.ph, %for.inc - %i.03 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ] - invoke void @_Z3fooi(i32 %i.03) - to label %for.inc unwind label %lpad - -for.inc: ; preds = %for.body - %inc = add i32 %i.03, 1 - %cmp = icmp eq i32 %inc, %x - br i1 %cmp, label %for.cond.try.cont.loopexit_crit_edge, label %for.body - -lpad: ; preds = %for.body - %0 = landingpad { ptr, i32 } - catch ptr @_ZTIi - %1 = extractvalue { ptr, i32 } %0, 0 - %2 = extractvalue { ptr, i32 } %0, 1 - %3 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIi) nounwind - %matches = icmp eq i32 %2, %3 - br i1 %matches, label %catch, label %eh.resume - -catch: ; preds = %lpad - %4 = tail call ptr @__cxa_begin_catch(ptr %1) nounwind - br i1 true, label %invoke.cont2.loopexit, label %for.body.i.lr.ph - -for.body.i.lr.ph: ; preds = %catch - br label %for.body.i - -for.body.i: ; preds = %for.body.i.lr.ph, %for.inc.i - %i.0.i1 = phi i32 [ 0, %for.body.i.lr.ph ], [ %inc.i, %for.inc.i ] - invoke void @_Z3fooi(i32 %i.0.i1) - to label %for.inc.i unwind label %lpad.i - -for.inc.i: ; preds = %for.body.i - %inc.i = add i32 %i.0.i1, 1 - %cmp.i = icmp eq i32 %inc.i, 0 - br i1 %cmp.i, label %for.cond.i.invoke.cont2.loopexit_crit_edge, label %for.body.i - -lpad.i: ; preds = %for.body.i - %5 = landingpad { ptr, i32 } - catch ptr @_ZTIi - %6 = extractvalue { ptr, i32 } %5, 0 - %7 = extractvalue { ptr, i32 } %5, 1 - %matches.i = icmp eq i32 %7, %3 - br i1 %matches.i, label %catch.i, label %lpad1.body - -catch.i: ; preds = %lpad.i - %8 = tail call ptr @__cxa_begin_catch(ptr %6) nounwind - invoke void @test3(i32 0) - to label %invoke.cont2.i unwind label %lpad1.i - -invoke.cont2.i: ; preds = %catch.i - tail call void @__cxa_end_catch() nounwind - br label %invoke.cont2 - -lpad1.i: ; preds = %catch.i - %9 = landingpad { ptr, i32 } - cleanup - %10 = extractvalue { ptr, i32 } %9, 0 - %11 = extractvalue { ptr, i32 } %9, 1 - tail call void @__cxa_end_catch() nounwind - br label %lpad1.body - -for.cond.i.invoke.cont2.loopexit_crit_edge: ; preds = %for.inc.i - br label %invoke.cont2.loopexit - -invoke.cont2.loopexit: ; preds = %for.cond.i.invoke.cont2.loopexit_crit_edge, %catch - br label %invoke.cont2 - -invoke.cont2: ; preds = %invoke.cont2.loopexit, %invoke.cont2.i - tail call void @__cxa_end_catch() nounwind - br label %try.cont - -for.cond.try.cont.loopexit_crit_edge: ; preds = %for.inc - br label %try.cont.loopexit - -try.cont.loopexit: ; preds = %for.cond.try.cont.loopexit_crit_edge, %entry - br label %try.cont - -try.cont: ; preds = %try.cont.loopexit, %invoke.cont2 - ret void - -lpad1.body: ; preds = %lpad1.i, %lpad.i - %exn.slot.0.i = phi ptr [ %10, %lpad1.i ], [ %6, %lpad.i ] - %ehselector.slot.0.i = phi i32 [ %11, %lpad1.i ], [ %7, %lpad.i ] - tail call void @__cxa_end_catch() nounwind - br label %eh.resume - -eh.resume: ; preds = %lpad1.body, %lpad - %exn.slot.0 = phi ptr [ %exn.slot.0.i, %lpad1.body ], [ %1, %lpad ] - %ehselector.slot.0 = phi i32 [ %ehselector.slot.0.i, %lpad1.body ], [ %2, %lpad ] - %lpad.val = insertvalue { ptr, i32 } undef, ptr %exn.slot.0, 0 - %lpad.val5 = insertvalue { ptr, i32 } %lpad.val, i32 %ehselector.slot.0, 1 - resume { ptr, i32 } %lpad.val5 -} - -declare void @_Z3fooi(i32) - -declare i32 @__gxx_personality_v0(...) - -declare i32 @llvm.eh.typeid.for(ptr) nounwind readnone - -declare ptr @__cxa_begin_catch(ptr) - -declare void @__cxa_end_catch() - -define void @test4(i1 %arg) nounwind uwtable { -entry: - br label %"7" - -"3": ; preds = %"7" - br i1 %arg, label %"31", label %"4" - -"4": ; preds = %"3" - %. = select i1 undef, float 0x3F50624DE0000000, float undef - %0 = add i32 %1, 1 - br label %"7" - -"7": ; preds = %"4", %entry - %1 = phi i32 [ %0, %"4" ], [ 0, %entry ] - %2 = icmp slt i32 %1, 100 - br i1 %2, label %"3", label %"8" - -"8": ; preds = %"7" - br i1 %arg, label %"9", label %"31" - -"9": ; preds = %"8" - br label %"33" - -"27": ; preds = %"31" - unreachable - -"31": ; preds = %"8", %"3" - br i1 %arg, label %"27", label %"32" - -"32": ; preds = %"31" - br label %"33" - -"33": ; preds = %"32", %"9" - ret void -} diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll b/llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll index 649e34e..7548bf6 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll @@ -45,9 +45,6 @@ define void @fixed_wide_active_lane_mask(ptr noalias %dst, ptr noalias readonly ; CHECK-UF4-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 8) ; CHECK-UF4-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 4) ; CHECK-UF4-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 0) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY1:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 4, i64 [[N]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY2:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 8, i64 [[N]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY3:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 12, i64 [[N]]) ; CHECK-UF4-NEXT: br label [[VECTOR_BODY1:%.*]] ; CHECK-UF4: vector.body: ; CHECK-UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY1]] ] @@ -67,17 +64,11 @@ define void @fixed_wide_active_lane_mask(ptr noalias %dst, ptr noalias readonly ; CHECK-UF4-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[BROADCAST_SPLAT]], ptr [[TMP18]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK5]]) ; CHECK-UF4-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[BROADCAST_SPLAT]], ptr [[TMP19]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK6]]) ; CHECK-UF4-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 -; CHECK-UF4-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 4 -; CHECK-UF4-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 8 -; CHECK-UF4-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 12 ; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 [[INDEX]], i64 [[TMP6]]) ; CHECK-UF4-NEXT: [[TMP12]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 12) ; CHECK-UF4-NEXT: [[TMP11]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 8) ; CHECK-UF4-NEXT: [[TMP10]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 4) ; CHECK-UF4-NEXT: [[TMP9]] = call <4 x i1> @llvm.vector.extract.v4i1.v16i1(<16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT7:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[TMP13]], i64 [[TMP6]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT8:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[TMP14]], i64 [[TMP6]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT9:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[TMP15]], i64 [[TMP6]]) ; CHECK-UF4-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP9]], i32 0 ; CHECK-UF4-NEXT: [[TMP20:%.*]] = xor i1 [[TMP21]], true ; CHECK-UF4-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY1]], !llvm.loop [[LOOP0:![0-9]+]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll index 5ee4e9e..75acbea9 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll @@ -46,23 +46,11 @@ define void @scalable_wide_active_lane_mask(ptr noalias %dst, ptr readonly %src, ; CHECK-UF4-NEXT: [[TMP7:%.*]] = sub i64 [[N]], [[TMP3]] ; CHECK-UF4-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[N]], [[TMP3]] ; CHECK-UF4-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP7]], i64 0 -; CHECK-UF4-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 4 -; CHECK-UF4-NEXT: [[INDEX_PART_NEXT:%.*]] = add i64 0, [[TMP11]] -; CHECK-UF4-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP13:%.*]] = shl nuw i64 [[TMP12]], 5 -; CHECK-UF4-NEXT: [[INDEX_PART_NEXT1:%.*]] = add i64 0, [[TMP13]] -; CHECK-UF4-NEXT: [[TMP14:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP15:%.*]] = mul nuw i64 [[TMP14]], 48 -; CHECK-UF4-NEXT: [[INDEX_PART_NEXT2:%.*]] = add i64 0, [[TMP15]] ; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 64 x i1> @llvm.get.active.lane.mask.nxv64i1.i64(i64 0, i64 [[N]]) ; CHECK-UF4-NEXT: [[TMP19:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 48) ; CHECK-UF4-NEXT: [[TMP18:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 32) ; CHECK-UF4-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 16) ; CHECK-UF4-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 0) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY3:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX_PART_NEXT]], i64 [[N]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY4:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX_PART_NEXT1]], i64 [[N]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY5:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX_PART_NEXT2]], i64 [[N]]) ; CHECK-UF4-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-UF4: vector.body: ; CHECK-UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -103,23 +91,11 @@ define void @scalable_wide_active_lane_mask(ptr noalias %dst, ptr readonly %src, ; CHECK-UF4-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> [[TMP27]], ptr [[TMP42]], i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK7]]) ; CHECK-UF4-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> [[TMP28]], ptr [[TMP45]], i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK8]]) ; CHECK-UF4-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP62]] -; CHECK-UF4-NEXT: [[TMP46:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP47:%.*]] = shl nuw i64 [[TMP46]], 4 -; CHECK-UF4-NEXT: [[TMP48:%.*]] = add i64 [[INDEX]], [[TMP47]] -; CHECK-UF4-NEXT: [[TMP49:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP50:%.*]] = shl nuw i64 [[TMP49]], 5 -; CHECK-UF4-NEXT: [[TMP51:%.*]] = add i64 [[INDEX]], [[TMP50]] -; CHECK-UF4-NEXT: [[TMP52:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP53:%.*]] = mul nuw i64 [[TMP52]], 48 -; CHECK-UF4-NEXT: [[TMP54:%.*]] = add i64 [[INDEX]], [[TMP53]] ; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT:%.*]] = call <vscale x 64 x i1> @llvm.get.active.lane.mask.nxv64i1.i64(i64 [[INDEX]], i64 [[TMP9]]) ; CHECK-UF4-NEXT: [[TMP58]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 48) ; CHECK-UF4-NEXT: [[TMP57]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 32) ; CHECK-UF4-NEXT: [[TMP56]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 16) ; CHECK-UF4-NEXT: [[TMP55]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT12:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP48]], i64 [[TMP9]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT13:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP51]], i64 [[TMP9]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT14:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[TMP54]], i64 [[TMP9]]) ; CHECK-UF4-NEXT: [[TMP59:%.*]] = extractelement <vscale x 16 x i1> [[TMP55]], i32 0 ; CHECK-UF4-NEXT: [[TMP60:%.*]] = xor i1 [[TMP59]], true ; CHECK-UF4-NEXT: br i1 [[TMP60]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] @@ -191,23 +167,11 @@ define void @scalable_wide_active_lane_mask_double(ptr noalias %dst, ptr readonl ; CHECK-UF4-NEXT: [[TMP31:%.*]] = sub i64 [[N]], [[TMP26]] ; CHECK-UF4-NEXT: [[TMP56:%.*]] = icmp ugt i64 [[N]], [[TMP26]] ; CHECK-UF4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = select i1 [[TMP56]], i64 [[TMP31]], i64 0 -; CHECK-UF4-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 1 -; CHECK-UF4-NEXT: [[INDEX_PART_NEXT:%.*]] = add i64 0, [[TMP6]] -; CHECK-UF4-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP7]], 2 -; CHECK-UF4-NEXT: [[INDEX_PART_NEXT1:%.*]] = add i64 0, [[TMP8]] -; CHECK-UF4-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 6 -; CHECK-UF4-NEXT: [[INDEX_PART_NEXT2:%.*]] = add i64 0, [[TMP10]] ; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 [[N]]) ; CHECK-UF4-NEXT: [[TMP14:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 6) ; CHECK-UF4-NEXT: [[TMP13:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 4) ; CHECK-UF4-NEXT: [[TMP12:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 2) ; CHECK-UF4-NEXT: [[TMP11:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 0) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY3:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_PART_NEXT]], i64 [[N]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY4:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_PART_NEXT1]], i64 [[N]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_ENTRY5:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_PART_NEXT2]], i64 [[N]]) ; CHECK-UF4-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-UF4: vector.body: ; CHECK-UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -248,23 +212,11 @@ define void @scalable_wide_active_lane_mask_double(ptr noalias %dst, ptr readonl ; CHECK-UF4-NEXT: call void @llvm.masked.store.nxv2f64.p0(<vscale x 2 x double> [[TMP18]], ptr [[TMP37]], i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK7]]) ; CHECK-UF4-NEXT: call void @llvm.masked.store.nxv2f64.p0(<vscale x 2 x double> [[TMP19]], ptr [[TMP40]], i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK8]]) ; CHECK-UF4-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP3]] -; CHECK-UF4-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP42:%.*]] = shl nuw i64 [[TMP41]], 1 -; CHECK-UF4-NEXT: [[TMP43:%.*]] = add i64 [[INDEX]], [[TMP42]] -; CHECK-UF4-NEXT: [[TMP44:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP45:%.*]] = shl nuw i64 [[TMP44]], 2 -; CHECK-UF4-NEXT: [[TMP46:%.*]] = add i64 [[INDEX]], [[TMP45]] -; CHECK-UF4-NEXT: [[TMP47:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-UF4-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 6 -; CHECK-UF4-NEXT: [[TMP49:%.*]] = add i64 [[INDEX]], [[TMP48]] ; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 [[INDEX]], i64 [[WIDE_TRIP_COUNT]]) ; CHECK-UF4-NEXT: [[TMP53]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 6) ; CHECK-UF4-NEXT: [[TMP52]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 4) ; CHECK-UF4-NEXT: [[TMP51]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 2) ; CHECK-UF4-NEXT: [[TMP50]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT12:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[TMP43]], i64 [[WIDE_TRIP_COUNT]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT13:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[TMP46]], i64 [[WIDE_TRIP_COUNT]]) -; CHECK-UF4-NEXT: [[ACTIVE_LANE_MASK_NEXT14:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[TMP49]], i64 [[WIDE_TRIP_COUNT]]) ; CHECK-UF4-NEXT: [[TMP54:%.*]] = extractelement <vscale x 2 x i1> [[TMP50]], i32 0 ; CHECK-UF4-NEXT: [[TMP55:%.*]] = xor i1 [[TMP54]], true ; CHECK-UF4-NEXT: br i1 [[TMP55]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] diff --git a/llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll new file mode 100644 index 0000000..b020e59 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll @@ -0,0 +1,73 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 +; RUN: opt -p loop-vectorize -force-vector-width=4 -enable-epilogue-vectorization -epilogue-vectorization-force-VF=4 -S %s | FileCheck %s + +@end = external global [128 x i8] + +; Test case for https://github.com/llvm/llvm-project/issues/162128. +define void @test_epilogue_step_scev_expansion(ptr %dst) { +; CHECK-LABEL: define void @test_epilogue_step_scev_expansion( +; CHECK-SAME: ptr [[DST:%.*]]) { +; CHECK-NEXT: [[ITER_CHECK:.*]]: +; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] +; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: +; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_MOD_VF]] +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] +; CHECK-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP0]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] +; CHECK: [[VEC_EPILOG_ITER_CHECK]]: +; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_VEC]] +; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 4 +; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] +; CHECK: [[VEC_EPILOG_PH]]: +; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; CHECK-NEXT: [[N_MOD_VF1:%.*]] = urem i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), 4 +; CHECK-NEXT: [[N_VEC2:%.*]] = sub i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_MOD_VF1]] +; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] +; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX3:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT4:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX3]] +; CHECK-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP2]], align 1 +; CHECK-NEXT: [[INDEX_NEXT4]] = add nuw i64 [[INDEX3]], 4 +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT4]], [[N_VEC2]] +; CHECK-NEXT: br i1 [[TMP3]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N5:%.*]] = icmp eq i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_VEC2]] +; CHECK-NEXT: br i1 [[CMP_N5]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] +; CHECK: [[VEC_EPILOG_SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC2]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; CHECK-NEXT: store i8 0, ptr [[GEP_DST]], align 1 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], sub (i64 0, i64 ptrtoint (ptr getelementptr inbounds nuw (i8, ptr @end, i64 1) to i64)) +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.dst = getelementptr i8, ptr %dst, i64 %iv + store i8 0, ptr %gep.dst, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, sub (i64 0, i64 ptrtoint (ptr getelementptr inbounds nuw (i8, ptr @end, i64 1) to i64)) + br i1 %ec, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/Transforms/LoopVectorize/scalable-predication.ll b/llvm/test/Transforms/LoopVectorize/scalable-predication.ll index af57967..b63ab8f 100644 --- a/llvm/test/Transforms/LoopVectorize/scalable-predication.ll +++ b/llvm/test/Transforms/LoopVectorize/scalable-predication.ll @@ -22,7 +22,6 @@ define void @foo(i32 %val, ptr dereferenceable(1024) %ptr) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX1]], i64 256) ; CHECK-NEXT: [[INDEX_NEXT2]] = add i64 [[INDEX1]], [[TMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT2]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] diff --git a/llvm/test/Transforms/NewGVN/ptrtoaddr.ll b/llvm/test/Transforms/NewGVN/ptrtoaddr.ll new file mode 100644 index 0000000..e51b42a --- /dev/null +++ b/llvm/test/Transforms/NewGVN/ptrtoaddr.ll @@ -0,0 +1,29 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=newgvn < %s | FileCheck %s + +define i64 @ptrtoaddr_same(ptr %p) { +; CHECK-LABEL: define i64 @ptrtoaddr_same( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: ret i64 0 +; + %i = ptrtoaddr ptr %p to i64 + %j = ptrtoaddr ptr %p to i64 + %sub = sub i64 %i, %j + ret i64 %sub +} + +; Note that unlike for ptrtoint, it's not possible for ptrtoaddr to differ +; in result type for the same input. +define i64 @ptrtoaddr_different(ptr %p, ptr %p2) { +; CHECK-LABEL: define i64 @ptrtoaddr_different( +; CHECK-SAME: ptr [[P:%.*]], ptr [[P2:%.*]]) { +; CHECK-NEXT: [[I:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[J:%.*]] = ptrtoaddr ptr [[P2]] to i64 +; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[I]], [[J]] +; CHECK-NEXT: ret i64 [[SUB]] +; + %i = ptrtoaddr ptr %p to i64 + %j = ptrtoaddr ptr %p2 to i64 + %sub = sub i64 %i, %j + ret i64 %sub +} diff --git a/llvm/test/Transforms/PhaseOrdering/switch-to-arithmetic-inlining.ll b/llvm/test/Transforms/PhaseOrdering/switch-to-arithmetic-inlining.ll new file mode 100644 index 0000000..7c9888f --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/switch-to-arithmetic-inlining.ll @@ -0,0 +1,448 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -O3 < %s | FileCheck %s + +target datalayout = "n64:32:16:8" + +define i8 @test(i8 %x) { +; CHECK-LABEL: define range(i8 0, 53) i8 @test( +; CHECK-SAME: i8 [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[START:.*:]] +; CHECK-NEXT: [[X_:%.*]] = tail call i8 @llvm.umin.i8(i8 [[X]], i8 52) +; CHECK-NEXT: ret i8 [[X_]] +; +start: + %_0 = alloca [1 x i8], align 1 + %0 = icmp eq i8 %x, 0 + br i1 %0, label %bb1, label %bb2 + +bb1: ; preds = %start + store i8 0, ptr %_0, align 1 + br label %bb105 + +bb2: ; preds = %start + %1 = icmp eq i8 %x, 1 + br i1 %1, label %bb3, label %bb4 + +bb105: ; preds = %bb104, %bb103, %bb101, %bb99, %bb97, %bb95, %bb93, %bb91, %bb89, %bb87, %bb85, %bb83, %bb81, %bb79, %bb77, %bb75, %bb73, %bb71, %bb69, %bb67, %bb65, %bb63, %bb61, %bb59, %bb57, %bb55, %bb53, %bb51, %bb49, %bb47, %bb45, %bb43, %bb41, %bb39, %bb37, %bb35, %bb33, %bb31, %bb29, %bb27, %bb25, %bb23, %bb21, %bb19, %bb17, %bb15, %bb13, %bb11, %bb9, %bb7, %bb5, %bb3, %bb1 + %2 = load i8, ptr %_0, align 1 + ret i8 %2 + +bb3: ; preds = %bb2 + store i8 1, ptr %_0, align 1 + br label %bb105 + +bb4: ; preds = %bb2 + %3 = icmp eq i8 %x, 2 + br i1 %3, label %bb5, label %bb6 + +bb5: ; preds = %bb4 + store i8 2, ptr %_0, align 1 + br label %bb105 + +bb6: ; preds = %bb4 + %4 = icmp eq i8 %x, 3 + br i1 %4, label %bb7, label %bb8 + +bb7: ; preds = %bb6 + store i8 3, ptr %_0, align 1 + br label %bb105 + +bb8: ; preds = %bb6 + %5 = icmp eq i8 %x, 4 + br i1 %5, label %bb9, label %bb10 + +bb9: ; preds = %bb8 + store i8 4, ptr %_0, align 1 + br label %bb105 + +bb10: ; preds = %bb8 + %6 = icmp eq i8 %x, 5 + br i1 %6, label %bb11, label %bb12 + +bb11: ; preds = %bb10 + store i8 5, ptr %_0, align 1 + br label %bb105 + +bb12: ; preds = %bb10 + %7 = icmp eq i8 %x, 6 + br i1 %7, label %bb13, label %bb14 + +bb13: ; preds = %bb12 + store i8 6, ptr %_0, align 1 + br label %bb105 + +bb14: ; preds = %bb12 + %8 = icmp eq i8 %x, 7 + br i1 %8, label %bb15, label %bb16 + +bb15: ; preds = %bb14 + store i8 7, ptr %_0, align 1 + br label %bb105 + +bb16: ; preds = %bb14 + %9 = icmp eq i8 %x, 8 + br i1 %9, label %bb17, label %bb18 + +bb17: ; preds = %bb16 + store i8 8, ptr %_0, align 1 + br label %bb105 + +bb18: ; preds = %bb16 + %10 = icmp eq i8 %x, 9 + br i1 %10, label %bb19, label %bb20 + +bb19: ; preds = %bb18 + store i8 9, ptr %_0, align 1 + br label %bb105 + +bb20: ; preds = %bb18 + %11 = icmp eq i8 %x, 10 + br i1 %11, label %bb21, label %bb22 + +bb21: ; preds = %bb20 + store i8 10, ptr %_0, align 1 + br label %bb105 + +bb22: ; preds = %bb20 + %12 = icmp eq i8 %x, 11 + br i1 %12, label %bb23, label %bb24 + +bb23: ; preds = %bb22 + store i8 11, ptr %_0, align 1 + br label %bb105 + +bb24: ; preds = %bb22 + %13 = icmp eq i8 %x, 12 + br i1 %13, label %bb25, label %bb26 + +bb25: ; preds = %bb24 + store i8 12, ptr %_0, align 1 + br label %bb105 + +bb26: ; preds = %bb24 + %14 = icmp eq i8 %x, 13 + br i1 %14, label %bb27, label %bb28 + +bb27: ; preds = %bb26 + store i8 13, ptr %_0, align 1 + br label %bb105 + +bb28: ; preds = %bb26 + %15 = icmp eq i8 %x, 14 + br i1 %15, label %bb29, label %bb30 + +bb29: ; preds = %bb28 + store i8 14, ptr %_0, align 1 + br label %bb105 + +bb30: ; preds = %bb28 + %16 = icmp eq i8 %x, 15 + br i1 %16, label %bb31, label %bb32 + +bb31: ; preds = %bb30 + store i8 15, ptr %_0, align 1 + br label %bb105 + +bb32: ; preds = %bb30 + %17 = icmp eq i8 %x, 16 + br i1 %17, label %bb33, label %bb34 + +bb33: ; preds = %bb32 + store i8 16, ptr %_0, align 1 + br label %bb105 + +bb34: ; preds = %bb32 + %18 = icmp eq i8 %x, 17 + br i1 %18, label %bb35, label %bb36 + +bb35: ; preds = %bb34 + store i8 17, ptr %_0, align 1 + br label %bb105 + +bb36: ; preds = %bb34 + %19 = icmp eq i8 %x, 18 + br i1 %19, label %bb37, label %bb38 + +bb37: ; preds = %bb36 + store i8 18, ptr %_0, align 1 + br label %bb105 + +bb38: ; preds = %bb36 + %20 = icmp eq i8 %x, 19 + br i1 %20, label %bb39, label %bb40 + +bb39: ; preds = %bb38 + store i8 19, ptr %_0, align 1 + br label %bb105 + +bb40: ; preds = %bb38 + %21 = icmp eq i8 %x, 20 + br i1 %21, label %bb41, label %bb42 + +bb41: ; preds = %bb40 + store i8 20, ptr %_0, align 1 + br label %bb105 + +bb42: ; preds = %bb40 + %22 = icmp eq i8 %x, 21 + br i1 %22, label %bb43, label %bb44 + +bb43: ; preds = %bb42 + store i8 21, ptr %_0, align 1 + br label %bb105 + +bb44: ; preds = %bb42 + %23 = icmp eq i8 %x, 22 + br i1 %23, label %bb45, label %bb46 + +bb45: ; preds = %bb44 + store i8 22, ptr %_0, align 1 + br label %bb105 + +bb46: ; preds = %bb44 + %24 = icmp eq i8 %x, 23 + br i1 %24, label %bb47, label %bb48 + +bb47: ; preds = %bb46 + store i8 23, ptr %_0, align 1 + br label %bb105 + +bb48: ; preds = %bb46 + %25 = icmp eq i8 %x, 24 + br i1 %25, label %bb49, label %bb50 + +bb49: ; preds = %bb48 + store i8 24, ptr %_0, align 1 + br label %bb105 + +bb50: ; preds = %bb48 + %26 = icmp eq i8 %x, 25 + br i1 %26, label %bb51, label %bb52 + +bb51: ; preds = %bb50 + store i8 25, ptr %_0, align 1 + br label %bb105 + +bb52: ; preds = %bb50 + %27 = icmp eq i8 %x, 26 + br i1 %27, label %bb53, label %bb54 + +bb53: ; preds = %bb52 + store i8 26, ptr %_0, align 1 + br label %bb105 + +bb54: ; preds = %bb52 + %28 = icmp eq i8 %x, 27 + br i1 %28, label %bb55, label %bb56 + +bb55: ; preds = %bb54 + store i8 27, ptr %_0, align 1 + br label %bb105 + +bb56: ; preds = %bb54 + %29 = icmp eq i8 %x, 28 + br i1 %29, label %bb57, label %bb58 + +bb57: ; preds = %bb56 + store i8 28, ptr %_0, align 1 + br label %bb105 + +bb58: ; preds = %bb56 + %30 = icmp eq i8 %x, 29 + br i1 %30, label %bb59, label %bb60 + +bb59: ; preds = %bb58 + store i8 29, ptr %_0, align 1 + br label %bb105 + +bb60: ; preds = %bb58 + %31 = icmp eq i8 %x, 30 + br i1 %31, label %bb61, label %bb62 + +bb61: ; preds = %bb60 + store i8 30, ptr %_0, align 1 + br label %bb105 + +bb62: ; preds = %bb60 + %32 = icmp eq i8 %x, 31 + br i1 %32, label %bb63, label %bb64 + +bb63: ; preds = %bb62 + store i8 31, ptr %_0, align 1 + br label %bb105 + +bb64: ; preds = %bb62 + %33 = icmp eq i8 %x, 32 + br i1 %33, label %bb65, label %bb66 + +bb65: ; preds = %bb64 + store i8 32, ptr %_0, align 1 + br label %bb105 + +bb66: ; preds = %bb64 + %34 = icmp eq i8 %x, 33 + br i1 %34, label %bb67, label %bb68 + +bb67: ; preds = %bb66 + store i8 33, ptr %_0, align 1 + br label %bb105 + +bb68: ; preds = %bb66 + %35 = icmp eq i8 %x, 34 + br i1 %35, label %bb69, label %bb70 + +bb69: ; preds = %bb68 + store i8 34, ptr %_0, align 1 + br label %bb105 + +bb70: ; preds = %bb68 + %36 = icmp eq i8 %x, 35 + br i1 %36, label %bb71, label %bb72 + +bb71: ; preds = %bb70 + store i8 35, ptr %_0, align 1 + br label %bb105 + +bb72: ; preds = %bb70 + %37 = icmp eq i8 %x, 36 + br i1 %37, label %bb73, label %bb74 + +bb73: ; preds = %bb72 + store i8 36, ptr %_0, align 1 + br label %bb105 + +bb74: ; preds = %bb72 + %38 = icmp eq i8 %x, 37 + br i1 %38, label %bb75, label %bb76 + +bb75: ; preds = %bb74 + store i8 37, ptr %_0, align 1 + br label %bb105 + +bb76: ; preds = %bb74 + %39 = icmp eq i8 %x, 38 + br i1 %39, label %bb77, label %bb78 + +bb77: ; preds = %bb76 + store i8 38, ptr %_0, align 1 + br label %bb105 + +bb78: ; preds = %bb76 + %40 = icmp eq i8 %x, 39 + br i1 %40, label %bb79, label %bb80 + +bb79: ; preds = %bb78 + store i8 39, ptr %_0, align 1 + br label %bb105 + +bb80: ; preds = %bb78 + %41 = icmp eq i8 %x, 40 + br i1 %41, label %bb81, label %bb82 + +bb81: ; preds = %bb80 + store i8 40, ptr %_0, align 1 + br label %bb105 + +bb82: ; preds = %bb80 + %42 = icmp eq i8 %x, 41 + br i1 %42, label %bb83, label %bb84 + +bb83: ; preds = %bb82 + store i8 41, ptr %_0, align 1 + br label %bb105 + +bb84: ; preds = %bb82 + %43 = icmp eq i8 %x, 42 + br i1 %43, label %bb85, label %bb86 + +bb85: ; preds = %bb84 + store i8 42, ptr %_0, align 1 + br label %bb105 + +bb86: ; preds = %bb84 + %44 = icmp eq i8 %x, 43 + br i1 %44, label %bb87, label %bb88 + +bb87: ; preds = %bb86 + store i8 43, ptr %_0, align 1 + br label %bb105 + +bb88: ; preds = %bb86 + %45 = icmp eq i8 %x, 44 + br i1 %45, label %bb89, label %bb90 + +bb89: ; preds = %bb88 + store i8 44, ptr %_0, align 1 + br label %bb105 + +bb90: ; preds = %bb88 + %46 = icmp eq i8 %x, 45 + br i1 %46, label %bb91, label %bb92 + +bb91: ; preds = %bb90 + store i8 45, ptr %_0, align 1 + br label %bb105 + +bb92: ; preds = %bb90 + %47 = icmp eq i8 %x, 46 + br i1 %47, label %bb93, label %bb94 + +bb93: ; preds = %bb92 + store i8 46, ptr %_0, align 1 + br label %bb105 + +bb94: ; preds = %bb92 + %48 = icmp eq i8 %x, 47 + br i1 %48, label %bb95, label %bb96 + +bb95: ; preds = %bb94 + store i8 47, ptr %_0, align 1 + br label %bb105 + +bb96: ; preds = %bb94 + %49 = icmp eq i8 %x, 48 + br i1 %49, label %bb97, label %bb98 + +bb97: ; preds = %bb96 + store i8 48, ptr %_0, align 1 + br label %bb105 + +bb98: ; preds = %bb96 + %50 = icmp eq i8 %x, 49 + br i1 %50, label %bb99, label %bb100 + +bb99: ; preds = %bb98 + store i8 49, ptr %_0, align 1 + br label %bb105 + +bb100: ; preds = %bb98 + %51 = icmp eq i8 %x, 50 + br i1 %51, label %bb101, label %bb102 + +bb101: ; preds = %bb100 + store i8 50, ptr %_0, align 1 + br label %bb105 + +bb102: ; preds = %bb100 + %52 = icmp eq i8 %x, 51 + br i1 %52, label %bb103, label %bb104 + +bb103: ; preds = %bb102 + store i8 51, ptr %_0, align 1 + br label %bb105 + +bb104: ; preds = %bb102 + store i8 52, ptr %_0, align 1 + br label %bb105 +} + +; Make sure the call is inlined. +define i8 @test2(i8 %x) { +; CHECK-LABEL: define range(i8 0, 53) i8 @test2( +; CHECK-SAME: i8 [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { +; CHECK-NEXT: [[CALL:%.*]] = tail call range(i8 0, 53) i8 @llvm.umin.i8(i8 [[X]], i8 52) +; CHECK-NEXT: ret i8 [[CALL]] +; + %call = call i8 @test(i8 %x) + ret i8 %call +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll b/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll index cf62fd5..a8880274 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll @@ -4,21 +4,14 @@ define void @test_add_sdiv(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) { ; CHECK-LABEL: @test_add_sdiv( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[GEP2_2:%.*]] = getelementptr i32, ptr [[ARR2:%.*]], i32 2 -; CHECK-NEXT: [[GEP2_3:%.*]] = getelementptr i32, ptr [[ARR2]], i32 3 -; CHECK-NEXT: [[V2:%.*]] = load i32, ptr [[GEP2_2]], align 4 -; CHECK-NEXT: [[V3:%.*]] = load i32, ptr [[GEP2_3]], align 4 -; CHECK-NEXT: [[Y2:%.*]] = add nsw i32 [[A2:%.*]], 42 -; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[ARR2]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2 +; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i32> [[TMP5]], <i32 1, i32 1, i32 42, i32 1> ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3 ; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]] -; CHECK-NEXT: [[RES2:%.*]] = sdiv i32 [[V2]], [[Y2]] -; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i32 2 -; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[V3]], i32 3 -; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> -; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> +; CHECK-NEXT: [[TMP8:%.*]] = sdiv <4 x i32> [[TMP0]], [[TMP6]] ; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP8]], [[TMP4]] ; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[ARR3:%.*]], align 4 ; CHECK-NEXT: ret void @@ -58,21 +51,14 @@ entry: define void @test_add_udiv(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) { ; CHECK-LABEL: @test_add_udiv( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[GEP1_2:%.*]] = getelementptr i32, ptr [[ARR1:%.*]], i32 2 -; CHECK-NEXT: [[GEP1_3:%.*]] = getelementptr i32, ptr [[ARR1]], i32 3 -; CHECK-NEXT: [[V2:%.*]] = load i32, ptr [[GEP1_2]], align 4 -; CHECK-NEXT: [[V3:%.*]] = load i32, ptr [[GEP1_3]], align 4 -; CHECK-NEXT: [[Y2:%.*]] = add nsw i32 [[A2:%.*]], 42 -; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[ARR1]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2 +; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i32> [[TMP5]], <i32 1, i32 1, i32 42, i32 1> ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3 ; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]] -; CHECK-NEXT: [[RES2:%.*]] = udiv i32 [[V2]], [[Y2]] -; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i32 2 -; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[V3]], i32 3 -; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> -; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> +; CHECK-NEXT: [[TMP8:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP6]] ; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP8]], [[TMP4]] ; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[ARR2:%.*]], align 4 ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll b/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll index c9063d3..25267dc 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -passes='simplifycfg' < %s | FileCheck %s --check-prefix=OPTNOLUT +; RUN: opt -S -passes='simplifycfg<switch-to-arithmetic>' < %s | FileCheck %s --check-prefix=OPTNOLUT ; RUN: %if amdgpu-registered-target %{ opt -mtriple=amdgcn--amdpal -S -passes='simplifycfg<switch-to-lookup>' < %s | FileCheck %s --check-prefix=TTINOLUT %} ; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -7,23 +7,11 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" define i32 @linear_transform_with_default(i32 %x) { ; OPTNOLUT-LABEL: define i32 @linear_transform_with_default( ; OPTNOLUT-SAME: i32 [[X:%.*]]) { -; OPTNOLUT-NEXT: [[ENTRY:.*]]: -; OPTNOLUT-NEXT: switch i32 [[X]], label %[[END:.*]] [ -; OPTNOLUT-NEXT: i32 0, label %[[CASE0:.*]] -; OPTNOLUT-NEXT: i32 1, label %[[CASE1:.*]] -; OPTNOLUT-NEXT: i32 2, label %[[CASE2:.*]] -; OPTNOLUT-NEXT: i32 3, label %[[CASE3:.*]] -; OPTNOLUT-NEXT: ] -; OPTNOLUT: [[CASE0]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[CASE1]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[CASE2]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[CASE3]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[END]]: -; OPTNOLUT-NEXT: [[IDX:%.*]] = phi i32 [ 1, %[[CASE0]] ], [ 4, %[[CASE1]] ], [ 7, %[[CASE2]] ], [ 10, %[[CASE3]] ], [ 13, %[[ENTRY]] ] +; OPTNOLUT-NEXT: [[ENTRY:.*:]] +; OPTNOLUT-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 4 +; OPTNOLUT-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul nsw i32 [[X]], 3 +; OPTNOLUT-NEXT: [[SWITCH_OFFSET:%.*]] = add nsw i32 [[SWITCH_IDX_MULT]], 1 +; OPTNOLUT-NEXT: [[IDX:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 13 ; OPTNOLUT-NEXT: ret i32 [[IDX]] ; ; TTINOLUT-LABEL: define i32 @linear_transform_with_default( @@ -138,26 +126,8 @@ end: define i32 @linear_transform_no_default(i32 %x) { ; OPTNOLUT-LABEL: define i32 @linear_transform_no_default( ; OPTNOLUT-SAME: i32 [[X:%.*]]) { -; OPTNOLUT-NEXT: [[ENTRY:.*]]: -; OPTNOLUT-NEXT: switch i32 [[X]], label %[[DEFAULT:.*]] [ -; OPTNOLUT-NEXT: i32 0, label %[[END:.*]] -; OPTNOLUT-NEXT: i32 1, label %[[CASE1:.*]] -; OPTNOLUT-NEXT: i32 2, label %[[CASE2:.*]] -; OPTNOLUT-NEXT: i32 3, label %[[CASE3:.*]] -; OPTNOLUT-NEXT: i32 4, label %[[CASE4:.*]] -; OPTNOLUT-NEXT: ] -; OPTNOLUT: [[CASE1]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[CASE2]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[CASE3]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[CASE4]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[DEFAULT]]: -; OPTNOLUT-NEXT: unreachable -; OPTNOLUT: [[END]]: -; OPTNOLUT-NEXT: [[SWITCH_IDX_MULT:%.*]] = phi i32 [ 3, %[[CASE1]] ], [ 6, %[[CASE2]] ], [ 9, %[[CASE3]] ], [ 12, %[[CASE4]] ], [ 0, %[[ENTRY]] ] +; OPTNOLUT-NEXT: [[ENTRY:.*:]] +; OPTNOLUT-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul nsw i32 [[X]], 3 ; OPTNOLUT-NEXT: ret i32 [[SWITCH_IDX_MULT]] ; ; TTINOLUT-LABEL: define i32 @linear_transform_no_default( @@ -350,18 +320,9 @@ end: define i32 @single_value_withdefault(i32 %x) { ; OPTNOLUT-LABEL: define i32 @single_value_withdefault( ; OPTNOLUT-SAME: i32 [[X:%.*]]) { -; OPTNOLUT-NEXT: [[ENTRY:.*]]: -; OPTNOLUT-NEXT: switch i32 [[X]], label %[[DEFAULT:.*]] [ -; OPTNOLUT-NEXT: i32 0, label %[[END:.*]] -; OPTNOLUT-NEXT: i32 1, label %[[END]] -; OPTNOLUT-NEXT: i32 2, label %[[END]] -; OPTNOLUT-NEXT: i32 3, label %[[END]] -; OPTNOLUT-NEXT: i32 4, label %[[END]] -; OPTNOLUT-NEXT: ] -; OPTNOLUT: [[DEFAULT]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[END]]: -; OPTNOLUT-NEXT: [[DOT:%.*]] = phi i32 [ 3, %[[DEFAULT]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ] +; OPTNOLUT-NEXT: [[ENTRY:.*:]] +; OPTNOLUT-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 5 +; OPTNOLUT-NEXT: [[DOT:%.*]] = select i1 [[TMP0]], i32 2, i32 3 ; OPTNOLUT-NEXT: ret i32 [[DOT]] ; ; TTINOLUT-LABEL: define i32 @single_value_withdefault( @@ -401,18 +362,9 @@ end: define i32 @single_value_no_jump_tables(i32 %x) "no-jump-tables"="true" { ; OPTNOLUT-LABEL: define i32 @single_value_no_jump_tables( ; OPTNOLUT-SAME: i32 [[X:%.*]]) #[[ATTR0:[0-9]+]] { -; OPTNOLUT-NEXT: [[ENTRY:.*]]: -; OPTNOLUT-NEXT: switch i32 [[X]], label %[[DEFAULT:.*]] [ -; OPTNOLUT-NEXT: i32 0, label %[[END:.*]] -; OPTNOLUT-NEXT: i32 1, label %[[END]] -; OPTNOLUT-NEXT: i32 2, label %[[END]] -; OPTNOLUT-NEXT: i32 3, label %[[END]] -; OPTNOLUT-NEXT: i32 4, label %[[END]] -; OPTNOLUT-NEXT: ] -; OPTNOLUT: [[DEFAULT]]: -; OPTNOLUT-NEXT: br label %[[END]] -; OPTNOLUT: [[END]]: -; OPTNOLUT-NEXT: [[IDX:%.*]] = phi i32 [ 3, %[[DEFAULT]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ], [ 2, %[[ENTRY]] ] +; OPTNOLUT-NEXT: [[ENTRY:.*:]] +; OPTNOLUT-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 5 +; OPTNOLUT-NEXT: [[IDX:%.*]] = select i1 [[TMP0]], i32 2, i32 3 ; OPTNOLUT-NEXT: ret i32 [[IDX]] ; ; TTINOLUT-LABEL: define i32 @single_value_no_jump_tables( @@ -449,6 +401,60 @@ end: ret i32 %idx } +define i1 @single_value_with_mask(i32 %x) { +; OPTNOLUT-LABEL: define i1 @single_value_with_mask( +; OPTNOLUT-SAME: i32 [[X:%.*]]) { +; OPTNOLUT-NEXT: [[ENTRY:.*]]: +; OPTNOLUT-NEXT: switch i32 [[X]], label %[[DEFAULT:.*]] [ +; OPTNOLUT-NEXT: i32 18, label %[[END:.*]] +; OPTNOLUT-NEXT: i32 21, label %[[END]] +; OPTNOLUT-NEXT: i32 48, label %[[END]] +; OPTNOLUT-NEXT: i32 16, label %[[END]] +; OPTNOLUT-NEXT: ] +; OPTNOLUT: [[DEFAULT]]: +; OPTNOLUT-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 80 +; OPTNOLUT-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i1 false, i1 true +; OPTNOLUT-NEXT: br label %[[END]] +; OPTNOLUT: [[END]]: +; OPTNOLUT-NEXT: [[RES:%.*]] = phi i1 [ false, %[[ENTRY]] ], [ false, %[[ENTRY]] ], [ false, %[[ENTRY]] ], [ false, %[[ENTRY]] ], [ [[SEL]], %[[DEFAULT]] ] +; OPTNOLUT-NEXT: ret i1 [[RES]] +; +; TTINOLUT-LABEL: define i1 @single_value_with_mask( +; TTINOLUT-SAME: i32 [[X:%.*]]) { +; TTINOLUT-NEXT: [[ENTRY:.*]]: +; TTINOLUT-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[X]], 16 +; TTINOLUT-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 33 +; TTINOLUT-NEXT: [[SWITCH_MASKINDEX:%.*]] = zext i32 [[SWITCH_TABLEIDX]] to i64 +; TTINOLUT-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i64 4294967333, [[SWITCH_MASKINDEX]] +; TTINOLUT-NEXT: [[SWITCH_LOBIT:%.*]] = trunc i64 [[SWITCH_SHIFTED]] to i1 +; TTINOLUT-NEXT: [[OR_COND:%.*]] = select i1 [[TMP0]], i1 [[SWITCH_LOBIT]], i1 false +; TTINOLUT-NEXT: br i1 [[OR_COND]], label %[[END:.*]], label %[[DEFAULT:.*]] +; TTINOLUT: [[DEFAULT]]: +; TTINOLUT-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 80 +; TTINOLUT-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i1 false, i1 true +; TTINOLUT-NEXT: br label %[[END]] +; TTINOLUT: [[END]]: +; TTINOLUT-NEXT: [[RES:%.*]] = phi i1 [ [[SEL]], %[[DEFAULT]] ], [ false, %[[ENTRY]] ] +; TTINOLUT-NEXT: ret i1 [[RES]] +; +entry: + switch i32 %x, label %default [ + i32 18, label %end + i32 21, label %end + i32 48, label %end + i32 16, label %end + ] + +default: + %cmp = icmp eq i32 %x, 80 + %sel = select i1 %cmp, i1 false, i1 true + br label %end + +end: + %res = phi i1 [ false, %entry ], [ false, %entry ], [ false, %entry ], [ false, %entry ], [ %sel, %default ] + ret i1 %res +} + define i32 @lookup_table(i32 %x) { ; OPTNOLUT-LABEL: define i32 @lookup_table( ; OPTNOLUT-SAME: i32 [[X:%.*]]) { diff --git a/llvm/test/tools/llvm-ar/extract.test b/llvm/test/tools/llvm-ar/extract.test index bf46cc0..f8be7fd 100644 --- a/llvm/test/tools/llvm-ar/extract.test +++ b/llvm/test/tools/llvm-ar/extract.test @@ -1,5 +1,4 @@ ## Test extract operation. -# XFAIL: target={{.*}}-darwin{{.*}} # RUN: rm -rf %t && mkdir -p %t/extracted/ @@ -9,7 +8,7 @@ # RUN: echo filea > %t/a.txt # RUN: echo fileb > %t/b.txt -# RUN: llvm-ar rc %t/archive.a %t/a.txt %t/b.txt +# RUN: llvm-ar rc --format=gnu %t/archive.a %t/a.txt %t/b.txt ## Single member: # RUN: cd %t/extracted && llvm-ar xv %t/archive.a a.txt | FileCheck %s --check-prefix=A diff --git a/llvm/test/tools/llvm-ar/print.test b/llvm/test/tools/llvm-ar/print.test index 997c05f..c104fb4 100644 --- a/llvm/test/tools/llvm-ar/print.test +++ b/llvm/test/tools/llvm-ar/print.test @@ -1,12 +1,11 @@ ## Test Print output -# XFAIL: target={{.*}}-darwin{{.*}} # RUN: rm -rf %t && mkdir -p %t # RUN: echo file1 > %t/1.txt # RUN: echo file2 > %t/2.txt # RUN: echo file3 > %t/3.txt -# RUN: llvm-ar -rc %t/archive.a %t/1.txt %t/2.txt %t/3.txt +# RUN: llvm-ar -rc --format=gnu %t/archive.a %t/1.txt %t/2.txt %t/3.txt ## Print empty archive: # RUN: llvm-ar --format=gnu cr %t/empty.a diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s index bdc02d4..a540d7d 100644 --- a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s +++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s @@ -4,7 +4,7 @@ AMOAND_D: --- AMOAND_D-NEXT: mode: latency AMOAND_D-NEXT: key: AMOAND_D-NEXT: instructions: -AMOAND_D-NEXT: - 'AMOAND_D [[RE01:X[0-9]+]] X10 [[RE01:X[0-9]+]]' +AMOAND_D-NEXT: - 'AMOAND_D [[RE01:X[0-9]+]] [[RE01:X[0-9]+]] X10' AMOAND_D-NEXT: config: '' AMOAND_D-NEXT: register_initial_values: AMOAND_D-NEXT: - '[[RE01:X[0-9]+]]=0x0' @@ -16,7 +16,7 @@ AMOADD_W: --- AMOADD_W-NEXT: mode: latency AMOADD_W-NEXT: key: AMOADD_W-NEXT: instructions: -AMOADD_W-NEXT: - 'AMOADD_W [[RE02:X[0-9]+]] X10 [[RE02:X[0-9]+]]' +AMOADD_W-NEXT: - 'AMOADD_W [[RE02:X[0-9]+]] [[RE02:X[0-9]+]] X10' AMOADD_W-NEXT: config: '' AMOADD_W-NEXT: register_initial_values: AMOADD_W-NEXT: - '[[RE02:X[0-9]+]]=0x0' @@ -28,7 +28,7 @@ AMOMAXU_D: --- AMOMAXU_D-NEXT: mode: latency AMOMAXU_D-NEXT: key: AMOMAXU_D-NEXT: instructions: -AMOMAXU_D-NEXT: - 'AMOMAXU_D [[RE03:X[0-9]+]] X10 [[RE03:X[0-9]+]]' +AMOMAXU_D-NEXT: - 'AMOMAXU_D [[RE03:X[0-9]+]] [[RE03:X[0-9]+]] X10' AMOMAXU_D-NEXT: config: '' AMOMAXU_D-NEXT: register_initial_values: AMOMAXU_D-NEXT: - '[[RE03:X[0-9]+]]=0x0' @@ -40,7 +40,7 @@ AMOMIN_W: --- AMOMIN_W-NEXT: mode: latency AMOMIN_W-NEXT: key: AMOMIN_W-NEXT: instructions: -AMOMIN_W-NEXT: - 'AMOMIN_W [[RE04:X[0-9]+]] X10 [[RE04:X[0-9]+]]' +AMOMIN_W-NEXT: - 'AMOMIN_W [[RE04:X[0-9]+]] [[RE04:X[0-9]+]] X10' AMOMIN_W-NEXT: config: '' AMOMIN_W-NEXT: register_initial_values: AMOMIN_W-NEXT: - '[[RE04:X[0-9]+]]=0x0' @@ -52,7 +52,7 @@ AMOXOR_D: --- AMOXOR_D-NEXT: mode: latency AMOXOR_D-NEXT: key: AMOXOR_D-NEXT: instructions: -AMOXOR_D-NEXT: - 'AMOXOR_D [[RE05:X[0-9]+]] X10 [[RE05:X[0-9]+]]' +AMOXOR_D-NEXT: - 'AMOXOR_D [[RE05:X[0-9]+]] [[RE05:X[0-9]+]] X10' AMOXOR_D-NEXT: config: '' AMOXOR_D-NEXT: register_initial_values: AMOXOR_D-NEXT: - '[[RE05:X[0-9]+]]=0x0' diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s new file mode 100644 index 0000000..b20206f --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s @@ -0,0 +1,4848 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -instruction-tables=full -iterations=1 < %s | FileCheck %s + +# The legal (SEW, LMUL) pairs for FP on sifive-x390 are: +# (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8) +# (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8) +# (e64, m1) (e64, m2) (e64, m4) (e64, m8) +# Widening instructions do not have e64 + +# Vector Single-Width FP +vsetvli zero, zero, e16, mf4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, mf2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m1, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 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v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, mf2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m1, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 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v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m8, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m1, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m8, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +# Vector Widening FP +# no e64 +vsetvli zero, zero, e16, mf4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, mf2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m1, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e16, m8, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, mf2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m1, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 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v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m8, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1 +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1 +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1 +# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1 +# CHECK-NEXT: [5] - VLEN512SiFive7VA:1 +# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1 +# CHECK-NEXT: [7] - VLEN512SiFive7VL:1 +# CHECK-NEXT: [8] - VLEN512SiFive7VS:1 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle]) +# CHECK-NEXT: [9]: LLVM Opcode Name + +# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA +# CHECK-NEXT: [3] - VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7VA +# CHECK-NEXT: [5] - VLEN512SiFive7VCQ +# CHECK-NEXT: [6] - VLEN512SiFive7VL +# CHECK-NEXT: [7] - VLEN512SiFive7VS + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: - - 32.00 - 32088.00 1558.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s index 8838c86..ecd96a3 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s @@ -126,19 +126,19 @@ amomaxu.d.aqrl s5, s4, (s3) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W lr.w t0, (t1) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ lr.w.aq t1, (t2) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_RL lr.w.rl t2, (t3) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ_RL lr.w.aqrl t3, (t4) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQRL lr.w.aqrl t3, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W sc.w t6, t5, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ sc.w.aq t5, t4, (t3) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_RL sc.w.rl t4, t3, (t2) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ_RL sc.w.aqrl t3, t2, (t1) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQRL sc.w.aqrl t3, t2, (t1) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D lr.d t0, (t1) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ lr.d.aq t1, (t2) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_RL lr.d.rl t2, (t3) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ_RL lr.d.aqrl t3, (t4) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQRL lr.d.aqrl t3, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D sc.d t6, t5, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ sc.d.aq t5, t4, (t3) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_RL sc.d.rl t4, t3, (t2) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ_RL sc.d.aqrl t3, t2, (t1) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQRL sc.d.aqrl t3, t2, (t1) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W amoswap.w a4, ra, (s0) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W amoadd.w a1, a2, (a3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W amoxor.w a2, a3, (a4) @@ -166,15 +166,15 @@ amomaxu.d.aqrl s5, s4, (s3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_RL amomax.w.rl s7, s6, (s5) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_RL amominu.w.rl s6, s5, (s4) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQ_RL amoswap.w.aqrl a4, ra, (s0) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQ_RL amoadd.w.aqrl a1, a2, (a3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQ_RL amoxor.w.aqrl a2, a3, (a4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQ_RL amoand.w.aqrl a3, a4, (a5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQ_RL amoor.w.aqrl a4, a5, (a6) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQ_RL amomin.w.aqrl a5, a6, (a7) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQ_RL amomax.w.aqrl s7, s6, (s5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQ_RL amominu.w.aqrl s6, s5, (s4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQ_RL amomaxu.w.aqrl s5, s4, (s3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQRL amoswap.w.aqrl a4, ra, (s0) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQRL amoadd.w.aqrl a1, a2, (a3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQRL amoxor.w.aqrl a2, a3, (a4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQRL amoand.w.aqrl a3, a4, (a5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQRL amoor.w.aqrl a4, a5, (a6) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQRL amomin.w.aqrl a5, a6, (a7) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQRL amomax.w.aqrl s7, s6, (s5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQRL amominu.w.aqrl s6, s5, (s4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQRL amomaxu.w.aqrl s5, s4, (s3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D amoswap.d a4, ra, (s0) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D amoadd.d a1, a2, (a3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D amoxor.d a2, a3, (a4) @@ -202,15 +202,15 @@ amomaxu.d.aqrl s5, s4, (s3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_RL amomax.d.rl s7, s6, (s5) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_RL amominu.d.rl s6, s5, (s4) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQ_RL amoswap.d.aqrl a4, ra, (s0) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQ_RL amoadd.d.aqrl a1, a2, (a3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQ_RL amoxor.d.aqrl a2, a3, (a4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQ_RL amoand.d.aqrl a3, a4, (a5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQ_RL amoor.d.aqrl a4, a5, (a6) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQ_RL amomin.d.aqrl a5, a6, (a7) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQ_RL amomax.d.aqrl s7, s6, (s5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQ_RL amominu.d.aqrl s6, s5, (s4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQ_RL amomaxu.d.aqrl s5, s4, (s3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQRL amoswap.d.aqrl a4, ra, (s0) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQRL amoadd.d.aqrl a1, a2, (a3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQRL amoxor.d.aqrl a2, a3, (a4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQRL amoand.d.aqrl a3, a4, (a5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQRL amoor.d.aqrl a4, a5, (a6) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQRL amomin.d.aqrl a5, a6, (a7) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQRL amomax.d.aqrl s7, s6, (s5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQRL amominu.d.aqrl s6, s5, (s4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQRL amomaxu.d.aqrl s5, s4, (s3) # CHECK: Resources: # CHECK-NEXT: [0] - SMX60_FP |