diff options
Diffstat (limited to 'llvm/test/tools')
15 files changed, 6481 insertions, 6223 deletions
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll new file mode 100644 index 0000000..2926371 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s --check-prefix=ASM +; RUN: llc -mtriple=x86_64 -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=MIR + +define i64 @test1(i64 %i) nounwind readnone { + %loc = alloca i64 + %j = load i64, ptr %loc + %r = add i64 %i, %j + ret i64 %r +} + +define i64 @test2(i32 %i) nounwind readnone { + %loc = alloca i32 + %j = load i32, ptr %loc + %r = add i32 %i, %j + %ext = zext i32 %r to i64 + ret i64 %ext +} diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected new file mode 100644 index 0000000..88cb03e --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected @@ -0,0 +1,45 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s --check-prefix=ASM +; RUN: llc -mtriple=x86_64 -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=MIR + +define i64 @test1(i64 %i) nounwind readnone { +; ASM-LABEL: test1: +; ASM: # %bb.0: +; ASM-NEXT: movq %rdi, %rax +; ASM-NEXT: addq -{{[0-9]+}}(%rsp), %rax +; ASM-NEXT: retq +; MIR-LABEL: name: test1 +; MIR: bb.0 (%ir-block.0): +; MIR-NEXT: liveins: $rdi +; MIR-NEXT: {{ $}} +; MIR-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi +; MIR-NEXT: [[ADD64rm:%[0-9]+]]:gr64 = ADD64rm [[COPY]], %stack.0.loc, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (dereferenceable load (s64) from %ir.loc) +; MIR-NEXT: $rax = COPY [[ADD64rm]] +; MIR-NEXT: RET 0, $rax + %loc = alloca i64 + %j = load i64, ptr %loc + %r = add i64 %i, %j + ret i64 %r +} + +define i64 @test2(i32 %i) nounwind readnone { +; ASM-LABEL: test2: +; ASM: # %bb.0: +; ASM-NEXT: movl %edi, %eax +; ASM-NEXT: addl -{{[0-9]+}}(%rsp), %eax +; ASM-NEXT: retq +; MIR-LABEL: name: test2 +; MIR: bb.0 (%ir-block.0): +; MIR-NEXT: liveins: $edi +; MIR-NEXT: {{ $}} +; MIR-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi +; MIR-NEXT: [[ADD32rm:%[0-9]+]]:gr32 = ADD32rm [[COPY]], %stack.0.loc, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (dereferenceable load (s32) from %ir.loc) +; MIR-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[ADD32rm]], %subreg.sub_32bit +; MIR-NEXT: $rax = COPY [[SUBREG_TO_REG]] +; MIR-NEXT: RET 0, $rax + %loc = alloca i32 + %j = load i32, ptr %loc + %r = add i32 %i, %j + %ext = zext i32 %r to i64 + ret i64 %ext +} diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_same_prefix.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_same_prefix.ll new file mode 100644 index 0000000..7167bcf --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_same_prefix.ll @@ -0,0 +1,13 @@ +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=x86_64 -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=CHECK + +define i32 @add(i32 %a, i32 %b) { + %sum = add i32 %a, %b + ret i32 %sum +} + +define i32 @sub(i32 %a, i32 %b) { + %diff = sub i32 %a, %b + ret i32 %diff +} + diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_same_prefix.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_same_prefix.ll.expected new file mode 100644 index 0000000..1ba920d --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_same_prefix.ll.expected @@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=x86_64 -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=CHECK + +define i32 @add(i32 %a, i32 %b) { + %sum = add i32 %a, %b + ret i32 %sum +} + +define i32 @sub(i32 %a, i32 %b) { + %diff = sub i32 %a, %b + ret i32 %diff +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-asm-mir-mixed.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-asm-mir-mixed.test new file mode 100644 index 0000000..6fc57b5 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-asm-mir-mixed.test @@ -0,0 +1,9 @@ +# REQUIRES: x86-registered-target +## Test checking that update_llc_test_checks.py can generate both ASM and MIR checks in the same file + +# RUN: cp -f %S/Inputs/x86_asm_mir_mixed.ll %t.ll && %update_llc_test_checks %t.ll +# RUN: diff -u %S/Inputs/x86_asm_mir_mixed.ll.expected %t.ll + +## Verify that running the script again on an already updated file doesn't add duplicate checks +# RUN: %update_llc_test_checks %t.ll +# RUN: diff -u %S/Inputs/x86_asm_mir_mixed.ll.expected %t.ll diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-asm-mir-same-prefix.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-asm-mir-same-prefix.test new file mode 100644 index 0000000..0f8aaa54 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-asm-mir-same-prefix.test @@ -0,0 +1,8 @@ +# REQUIRES: x86-registered-target +## Test that using the same prefix for both ASM and MIR outputs generates a warning +## and doesn't produce any checks. + +# RUN: cp -f %S/Inputs/x86_asm_mir_same_prefix.ll %t.ll && %update_llc_test_checks %t.ll 2>&1 | FileCheck %s --check-prefix=WARNING +# RUN: diff -u %S/Inputs/x86_asm_mir_same_prefix.ll.expected %t.ll + +# WARNING: WARNING: The following prefixes are used for both ASM and MIR output, which will cause FileCheck failures: CHECK diff --git a/llvm/test/tools/dxil-dis/llvm_assume.ll b/llvm/test/tools/dxil-dis/llvm_assume.ll deleted file mode 100644 index f5be66c..0000000 --- a/llvm/test/tools/dxil-dis/llvm_assume.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc --filetype=obj %s -o - | dxil-dis -o - | FileCheck %s - -target triple = "dxil-pc-shadermodel6.7-library" - -define void @test_llvm_assume(i1 %0) { -; CHECK-LABEL: test_llvm_assume -; CHECK-NEXT: tail call void @llvm.assume(i1 %0) -tail call void @llvm.assume(i1 %0) -ret void -} - diff --git a/llvm/test/tools/llc/new-pm/start-stop.ll b/llvm/test/tools/llc/new-pm/start-stop.ll index e4c4549..0e68cdb 100644 --- a/llvm/test/tools/llc/new-pm/start-stop.ll +++ b/llvm/test/tools/llc/new-pm/start-stop.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -filetype=null %s | FileCheck --match-full-lines %s --check-prefix=NULL ; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -o /dev/null %s | FileCheck --match-full-lines %s --check-prefix=OBJ -; NULL: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify) -; OBJ: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify),PrintMIRPreparePass,function(machine-function(print),free-machine-function) +; NULL: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,require<runtime-libcall-info>,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify) +; OBJ: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,require<runtime-libcall-info>,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify),PrintMIRPreparePass,function(machine-function(print),free-machine-function) diff --git a/llvm/test/tools/llvm-dwarfdump/X86/filter-child-tag.yaml b/llvm/test/tools/llvm-dwarfdump/X86/filter-child-tag.yaml new file mode 100644 index 0000000..2a8c37d --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/X86/filter-child-tag.yaml @@ -0,0 +1,136 @@ +## Tests the --filter-child-tag (-t) option. + +# RUN: yaml2obj %s -o %t.o + +# RUN: llvm-dwarfdump %t.o --filter-child-tag=DW_TAG_structure_type | FileCheck %s --check-prefix=ONLY_STRUCT + +# ONLY_STRUCT: DW_TAG_compile_unit +# ONLY_STRUCT-NOT: DW_TAG_namespace +# ONLY_STRUCT-NOT: DW_TAG_structure_type + +# RUN: llvm-dwarfdump %t.o -t DW_TAG_structure_type -t DW_TAG_namespace | \ +# RUN: FileCheck %s --check-prefix=STRUCT_AND_NS --implicit-check-not=DW_TAG_subprogram --implicit-check-not=DW_TAG_member + +# STRUCT_AND_NS: DW_TAG_compile_unit +# STRUCT_AND_NS: DW_TAG_namespace +# STRUCT_AND_NS: DW_TAG_structure_type +# STRUCT_AND_NS: DW_TAG_structure_type + +# RUN: llvm-dwarfdump %t.o -c --name=Foo -t DW_TAG_member | \ +# RUN: FileCheck %s --check-prefix=FOO_MEM --implicit-check-not=DW_TAG_compile_unit --implicit-check-not=DW_TAG_subprogram --implicit-check-not=DW_TAG_namespace + +# FOO_MEM: DW_TAG_structure_type +# FOO_MEM: DW_TAG_member +# FOO_MEM: DW_TAG_member +# FOO_MEM: DW_TAG_member +# FOO_MEM-NOT: DW_TAG_structure_type +# FOO_MEM-NOT: DW_TAG_member + +# RUN: llvm-dwarfdump %t.o -c --name=Foo -t not_a_tag -t DW_TAG_member | \ +# RUN: FileCheck %s --check-prefix=SINGLE_INVALID_TAG --implicit-check-not=DW_TAG_compile_unit --implicit-check-not=DW_TAG_subprogram --implicit-check-not=DW_TAG_namespace + +# SINGLE_INVALID_TAG: DW_TAG_structure_type +# SINGLE_INVALID_TAG: DW_TAG_member +# SINGLE_INVALID_TAG: DW_TAG_member +# SINGLE_INVALID_TAG: DW_TAG_member +# SINGLE_INVALID_TAG-NOT: DW_TAG_structure_type +# SINGLE_INVALID_TAG-NOT: DW_TAG_member + +# RUN: llvm-dwarfdump %t.o -c --name=Foo -t not_a_tag | \ +# RUN: FileCheck %s --check-prefix=ONLY_INVALID_TAGS --implicit-check-not=DW_TAG_compile_unit --implicit-check-not=DW_TAG_subprogram --implicit-check-not=DW_TAG_namespace --implicit-check-not=DW_TAG_member + +# ONLY_INVALID_TAGS: DW_TAG_structure_type +# ONLY_INVALID_TAGS-NOT: DW_TAG_structure_type + +# RUN: llvm-dwarfdump %t.o -c -p --name=Foo -t DW_TAG_member | \ +# RUN: FileCheck %s --check-prefix=FOO_MEM_WITH_PARENT --implicit-check-not=DW_TAG_subprogram + +# FOO_MEM_WITH_PARENT: DW_TAG_compile_unit +# FOO_MEM_WITH_PARENT: DW_TAG_namespace +# FOO_MEM_WITH_PARENT: DW_TAG_structure_type +# FOO_MEM_WITH_PARENT: DW_TAG_member +# FOO_MEM_WITH_PARENT: DW_TAG_member +# FOO_MEM_WITH_PARENT: DW_TAG_member +# FOO_MEM_WITH_PARENT-NOT: DW_TAG_structure_type +# FOO_MEM_WITH_PARENT-NOT: DW_TAG_member + +## Not specifying --show-children ignores the --filter-child-tag option. +# RUN: llvm-dwarfdump %t.o --name=Foo -t DW_TAG_member 2>&1 | FileCheck %s --check-prefix=NO_SHOW_CHILDREN + +# NO_SHOW_CHILDREN: DW_TAG_structure_type + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +DWARF: + debug_abbrev: + - Table: + - Tag: DW_TAG_compile_unit + Children: DW_CHILDREN_yes + Attributes: + - Attribute: DW_AT_producer + Form: DW_FORM_string + - Tag: DW_TAG_namespace + Children: DW_CHILDREN_yes + Attributes: + - Attribute: DW_AT_name + Form: DW_FORM_string + - Tag: DW_TAG_structure_type + Children: DW_CHILDREN_yes + Attributes: + - Attribute: DW_AT_name + Form: DW_FORM_string + - Tag: DW_TAG_member + Children: DW_CHILDREN_no + Attributes: + - Attribute: DW_AT_name + Form: DW_FORM_string + - Tag: DW_TAG_subprogram + Children: DW_CHILDREN_no + Attributes: + - Attribute: DW_AT_name + Form: DW_FORM_string + debug_info: + - Version: 5 + UnitType: DW_UT_compile + Entries: + - AbbrCode: 1 + Values: + - CStr: handwritten + - AbbrCode: 2 + Values: + - CStr: ns + - AbbrCode: 3 + Values: + - CStr: Foo + - AbbrCode: 4 + Values: + - CStr: mem1 + - AbbrCode: 4 + Values: + - CStr: mem2 + - AbbrCode: 4 + Values: + - CStr: mem3 + - AbbrCode: 3 + Values: + - CStr: NestedInFoo + - AbbrCode: 4 + Values: + - CStr: NestedMem1 + - AbbrCode: 4 + Values: + - CStr: NestedMem2 + - AbbrCode: 5 + Values: + - CStr: NestedFunc + - AbbrCode: 0x0 + - AbbrCode: 5 + Values: + - CStr: FooFunc + - AbbrCode: 0x0 + - AbbrCode: 0x0 + - AbbrCode: 0x0 diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt index 141a56a..ec061ff 100644 --- a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt +++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt @@ -1,33 +1,33 @@ MAX_RELATION=4 -187 7051 1 -187 6948 2 -187 187 0 -187 7051 1 +187 7052 1 187 6949 2 +187 187 0 +187 7052 1 +187 6950 2 187 10 0 -10 7051 1 -10 7051 2 -10 7051 3 -10 6941 4 +10 7052 1 +10 7052 2 +10 7052 3 +10 6942 4 10 187 0 -187 6932 1 -187 7051 2 -187 1543 0 -1543 6862 1 -1543 6932 2 -187 7051 1 -187 6948 2 -187 187 0 -187 7051 1 +187 6933 1 +187 7052 2 +187 1544 0 +1544 6863 1 +1544 6933 2 +187 7052 1 187 6949 2 +187 187 0 +187 7052 1 +187 6950 2 187 601 0 -601 7051 1 -601 7051 2 -601 7051 3 -601 6941 4 +601 7052 1 +601 7052 2 +601 7052 3 +601 6942 4 601 187 0 -187 6932 1 -187 7051 2 -187 1543 0 -1543 6862 1 -1543 6932 2 +187 6933 1 +187 7052 2 +187 1544 0 +1544 6863 1 +1544 6933 2 diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt index dbbbbc7..1b90a8a 100644 --- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt +++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt @@ -1,4 +1,4 @@ -7151 +7152 AAA 0 AAD 1 AADD 2 @@ -1532,5621 +1532,5622 @@ RDSSPQ 1529 RDTSC 1530 RDTSCP 1531 REG_SEQUENCE 1532 -REPNE_PREFIX 1533 -REP_MOVSB 1534 -REP_MOVSD 1535 -REP_MOVSQ 1536 -REP_MOVSW 1537 -REP_PREFIX 1538 -REP_STOSB 1539 -REP_STOSD 1540 -REP_STOSQ 1541 -REP_STOSW 1542 -RET 1543 -RETI 1544 -REX 1545 -RMPADJUST 1546 -RMPQUERY 1547 -RMPUPDATE 1548 -ROL 1549 -ROR 1550 -RORX 1551 -ROUNDPDmi 1552 -ROUNDPDri 1553 -ROUNDPSmi 1554 -ROUNDPSri 1555 -ROUNDSDmi 1556 -ROUNDSDmi_Int 1557 -ROUNDSDri 1558 -ROUNDSDri_Int 1559 -ROUNDSSmi 1560 -ROUNDSSmi_Int 1561 -ROUNDSSri 1562 -ROUNDSSri_Int 1563 -RSM 1564 -RSQRTPSm 1565 -RSQRTPSr 1566 -RSQRTSSm 1567 -RSQRTSSm_Int 1568 -RSQRTSSr 1569 -RSQRTSSr_Int 1570 -RSTORSSP 1571 -SAHF 1572 -SALC 1573 -SAR 1574 -SARX 1575 -SAVEPREVSSP 1576 -SBB 1577 -SCASB 1578 -SCASL 1579 -SCASQ 1580 -SCASW 1581 -SEAMCALL 1582 -SEAMOPS 1583 -SEAMRET 1584 -SEG_ALLOCA 1585 -SEH_BeginEpilogue 1586 -SEH_EndEpilogue 1587 -SEH_EndPrologue 1588 -SEH_PushFrame 1589 -SEH_PushReg 1590 -SEH_SaveReg 1591 -SEH_SaveXMM 1592 -SEH_SetFrame 1593 -SEH_StackAlign 1594 -SEH_StackAlloc 1595 -SEH_UnwindV 1596 -SEH_UnwindVersion 1597 -SENDUIPI 1598 -SERIALIZE 1599 -SETB_C 1600 -SETCCm 1601 -SETCCm_EVEX 1602 -SETCCr 1603 -SETCCr_EVEX 1604 -SETSSBSY 1605 -SETZUCCm 1606 -SETZUCCr 1607 -SFENCE 1608 -SGDT 1609 -SHA 1610 -SHL 1611 -SHLD 1612 -SHLDROT 1613 -SHLX 1614 -SHR 1615 -SHRD 1616 -SHRDROT 1617 -SHRX 1618 -SHUFPDrmi 1619 -SHUFPDrri 1620 -SHUFPSrmi 1621 -SHUFPSrri 1622 -SIDT 1623 -SKINIT 1624 -SLDT 1625 -SLWPCB 1626 -SMSW 1627 -SQRTPDm 1628 -SQRTPDr 1629 -SQRTPSm 1630 -SQRTPSr 1631 -SQRTSDm 1632 -SQRTSDm_Int 1633 -SQRTSDr 1634 -SQRTSDr_Int 1635 -SQRTSSm 1636 -SQRTSSm_Int 1637 -SQRTSSr 1638 -SQRTSSr_Int 1639 -SQRT_F 1640 -SQRT_Fp 1641 -SS_PREFIX 1642 -STAC 1643 -STACKALLOC_W_PROBING 1644 -STACKMAP 1645 -STATEPOINT 1646 -STC 1647 -STD 1648 -STGI 1649 -STI 1650 -STMXCSR 1651 -STOSB 1652 -STOSL 1653 -STOSQ 1654 -STOSW 1655 -STR 1656 -STRm 1657 -STTILECFG 1658 -STTILECFG_EVEX 1659 -STUI 1660 -ST_F 1661 -ST_FP 1662 -ST_FPrr 1663 -ST_Fp 1664 -ST_FpP 1665 -ST_Frr 1666 -SUB 1667 -SUBPDrm 1668 -SUBPDrr 1669 -SUBPSrm 1670 -SUBPSrr 1671 -SUBREG_TO_REG 1672 -SUBR_F 1673 -SUBR_FI 1674 -SUBR_FPrST 1675 -SUBR_FST 1676 -SUBR_Fp 1677 -SUBR_FpI 1678 -SUBR_FrST 1679 -SUBSDrm 1680 -SUBSDrm_Int 1681 -SUBSDrr 1682 -SUBSDrr_Int 1683 -SUBSSrm 1684 -SUBSSrm_Int 1685 -SUBSSrr 1686 -SUBSSrr_Int 1687 -SUB_F 1688 -SUB_FI 1689 -SUB_FPrST 1690 -SUB_FST 1691 -SUB_Fp 1692 -SUB_FpI 1693 -SUB_FrST 1694 -SWAPGS 1695 -SYSCALL 1696 -SYSENTER 1697 -SYSEXIT 1698 -SYSRET 1699 -T 1700 -TAILJMPd 1701 -TAILJMPd_CC 1702 -TAILJMPm 1703 -TAILJMPr 1704 -TCMMIMFP 1705 -TCMMRLFP 1706 -TCRETURN_HIPE 1707 -TCRETURN_WIN 1708 -TCRETURN_WINmi 1709 -TCRETURNdi 1710 -TCRETURNdicc 1711 -TCRETURNmi 1712 -TCRETURNri 1713 -TCVTROWD 1714 -TCVTROWPS 1715 -TDCALL 1716 -TDPBF 1717 -TDPBHF 1718 -TDPBSSD 1719 -TDPBSUD 1720 -TDPBUSD 1721 -TDPBUUD 1722 -TDPFP 1723 -TDPHBF 1724 -TDPHF 1725 -TEST 1726 -TESTUI 1727 -TILELOADD 1728 -TILELOADDRS 1729 -TILELOADDRST 1730 -TILELOADDRS_EVEX 1731 -TILELOADDT 1732 -TILELOADD_EVEX 1733 -TILEMOVROWrre 1734 -TILEMOVROWrri 1735 -TILERELEASE 1736 -TILESTORED 1737 -TILESTORED_EVEX 1738 -TILEZERO 1739 -TLBSYNC 1740 -TLSCall 1741 -TLS_addr 1742 -TLS_addrX 1743 -TLS_base_addr 1744 -TLS_base_addrX 1745 -TLS_desc 1746 -TMMULTF 1747 -TPAUSE 1748 -TRAP 1749 -TST_F 1750 -TST_Fp 1751 -TZCNT 1752 -TZMSK 1753 -UBSAN_UD 1754 -UCOMISDrm 1755 -UCOMISDrm_Int 1756 -UCOMISDrr 1757 -UCOMISDrr_Int 1758 -UCOMISSrm 1759 -UCOMISSrm_Int 1760 -UCOMISSrr 1761 -UCOMISSrr_Int 1762 -UCOM_FIPr 1763 -UCOM_FIr 1764 -UCOM_FPPr 1765 -UCOM_FPr 1766 -UCOM_FpIr 1767 -UCOM_Fpr 1768 -UCOM_Fr 1769 -UD 1770 -UIRET 1771 -UMONITOR 1772 -UMWAIT 1773 -UNPCKHPDrm 1774 -UNPCKHPDrr 1775 -UNPCKHPSrm 1776 -UNPCKHPSrr 1777 -UNPCKLPDrm 1778 -UNPCKLPDrr 1779 -UNPCKLPSrm 1780 -UNPCKLPSrr 1781 -URDMSRri 1782 -URDMSRri_EVEX 1783 -URDMSRrr 1784 -URDMSRrr_EVEX 1785 -UWRMSRir 1786 -UWRMSRir_EVEX 1787 -UWRMSRrr 1788 -UWRMSRrr_EVEX 1789 -V 1790 -VAARG 1791 -VAARG_X 1792 -VADDBF 1793 -VADDPDYrm 1794 -VADDPDYrr 1795 -VADDPDZ 1796 -VADDPDZrm 1797 -VADDPDZrmb 1798 -VADDPDZrmbk 1799 -VADDPDZrmbkz 1800 -VADDPDZrmk 1801 -VADDPDZrmkz 1802 -VADDPDZrr 1803 -VADDPDZrrb 1804 -VADDPDZrrbk 1805 -VADDPDZrrbkz 1806 -VADDPDZrrk 1807 -VADDPDZrrkz 1808 -VADDPDrm 1809 -VADDPDrr 1810 -VADDPHZ 1811 -VADDPHZrm 1812 -VADDPHZrmb 1813 -VADDPHZrmbk 1814 -VADDPHZrmbkz 1815 -VADDPHZrmk 1816 -VADDPHZrmkz 1817 -VADDPHZrr 1818 -VADDPHZrrb 1819 -VADDPHZrrbk 1820 -VADDPHZrrbkz 1821 -VADDPHZrrk 1822 -VADDPHZrrkz 1823 -VADDPSYrm 1824 -VADDPSYrr 1825 -VADDPSZ 1826 -VADDPSZrm 1827 -VADDPSZrmb 1828 -VADDPSZrmbk 1829 -VADDPSZrmbkz 1830 -VADDPSZrmk 1831 -VADDPSZrmkz 1832 -VADDPSZrr 1833 -VADDPSZrrb 1834 -VADDPSZrrbk 1835 -VADDPSZrrbkz 1836 -VADDPSZrrk 1837 -VADDPSZrrkz 1838 -VADDPSrm 1839 -VADDPSrr 1840 -VADDSDZrm 1841 -VADDSDZrm_Int 1842 -VADDSDZrmk_Int 1843 -VADDSDZrmkz_Int 1844 -VADDSDZrr 1845 -VADDSDZrr_Int 1846 -VADDSDZrrb_Int 1847 -VADDSDZrrbk_Int 1848 -VADDSDZrrbkz_Int 1849 -VADDSDZrrk_Int 1850 -VADDSDZrrkz_Int 1851 -VADDSDrm 1852 -VADDSDrm_Int 1853 -VADDSDrr 1854 -VADDSDrr_Int 1855 -VADDSHZrm 1856 -VADDSHZrm_Int 1857 -VADDSHZrmk_Int 1858 -VADDSHZrmkz_Int 1859 -VADDSHZrr 1860 -VADDSHZrr_Int 1861 -VADDSHZrrb_Int 1862 -VADDSHZrrbk_Int 1863 -VADDSHZrrbkz_Int 1864 -VADDSHZrrk_Int 1865 -VADDSHZrrkz_Int 1866 -VADDSSZrm 1867 -VADDSSZrm_Int 1868 -VADDSSZrmk_Int 1869 -VADDSSZrmkz_Int 1870 -VADDSSZrr 1871 -VADDSSZrr_Int 1872 -VADDSSZrrb_Int 1873 -VADDSSZrrbk_Int 1874 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6667 -VSUBSSZrrkz_Int 6668 -VSUBSSrm 6669 -VSUBSSrm_Int 6670 -VSUBSSrr 6671 -VSUBSSrr_Int 6672 -VTESTPDYrm 6673 -VTESTPDYrr 6674 -VTESTPDrm 6675 -VTESTPDrr 6676 -VTESTPSYrm 6677 -VTESTPSYrr 6678 -VTESTPSrm 6679 -VTESTPSrr 6680 -VUCOMISDZrm 6681 -VUCOMISDZrm_Int 6682 -VUCOMISDZrr 6683 -VUCOMISDZrr_Int 6684 -VUCOMISDZrrb 6685 -VUCOMISDrm 6686 -VUCOMISDrm_Int 6687 -VUCOMISDrr 6688 -VUCOMISDrr_Int 6689 -VUCOMISHZrm 6690 -VUCOMISHZrm_Int 6691 -VUCOMISHZrr 6692 -VUCOMISHZrr_Int 6693 -VUCOMISHZrrb 6694 -VUCOMISSZrm 6695 -VUCOMISSZrm_Int 6696 -VUCOMISSZrr 6697 -VUCOMISSZrr_Int 6698 -VUCOMISSZrrb 6699 -VUCOMISSrm 6700 -VUCOMISSrm_Int 6701 -VUCOMISSrr 6702 -VUCOMISSrr_Int 6703 -VUCOMXSDZrm 6704 -VUCOMXSDZrm_Int 6705 -VUCOMXSDZrr 6706 -VUCOMXSDZrr_Int 6707 -VUCOMXSDZrrb_Int 6708 -VUCOMXSHZrm 6709 -VUCOMXSHZrm_Int 6710 -VUCOMXSHZrr 6711 -VUCOMXSHZrr_Int 6712 -VUCOMXSHZrrb_Int 6713 -VUCOMXSSZrm 6714 -VUCOMXSSZrm_Int 6715 -VUCOMXSSZrr 6716 -VUCOMXSSZrr_Int 6717 -VUCOMXSSZrrb_Int 6718 -VUNPCKHPDYrm 6719 -VUNPCKHPDYrr 6720 -VUNPCKHPDZ 6721 -VUNPCKHPDZrm 6722 -VUNPCKHPDZrmb 6723 -VUNPCKHPDZrmbk 6724 -VUNPCKHPDZrmbkz 6725 -VUNPCKHPDZrmk 6726 -VUNPCKHPDZrmkz 6727 -VUNPCKHPDZrr 6728 -VUNPCKHPDZrrk 6729 -VUNPCKHPDZrrkz 6730 -VUNPCKHPDrm 6731 -VUNPCKHPDrr 6732 -VUNPCKHPSYrm 6733 -VUNPCKHPSYrr 6734 -VUNPCKHPSZ 6735 -VUNPCKHPSZrm 6736 -VUNPCKHPSZrmb 6737 -VUNPCKHPSZrmbk 6738 -VUNPCKHPSZrmbkz 6739 -VUNPCKHPSZrmk 6740 -VUNPCKHPSZrmkz 6741 -VUNPCKHPSZrr 6742 -VUNPCKHPSZrrk 6743 -VUNPCKHPSZrrkz 6744 -VUNPCKHPSrm 6745 -VUNPCKHPSrr 6746 -VUNPCKLPDYrm 6747 -VUNPCKLPDYrr 6748 -VUNPCKLPDZ 6749 -VUNPCKLPDZrm 6750 -VUNPCKLPDZrmb 6751 -VUNPCKLPDZrmbk 6752 -VUNPCKLPDZrmbkz 6753 -VUNPCKLPDZrmk 6754 -VUNPCKLPDZrmkz 6755 -VUNPCKLPDZrr 6756 -VUNPCKLPDZrrk 6757 -VUNPCKLPDZrrkz 6758 -VUNPCKLPDrm 6759 -VUNPCKLPDrr 6760 -VUNPCKLPSYrm 6761 -VUNPCKLPSYrr 6762 -VUNPCKLPSZ 6763 -VUNPCKLPSZrm 6764 -VUNPCKLPSZrmb 6765 -VUNPCKLPSZrmbk 6766 -VUNPCKLPSZrmbkz 6767 -VUNPCKLPSZrmk 6768 -VUNPCKLPSZrmkz 6769 -VUNPCKLPSZrr 6770 -VUNPCKLPSZrrk 6771 -VUNPCKLPSZrrkz 6772 -VUNPCKLPSrm 6773 -VUNPCKLPSrr 6774 -VXORPDYrm 6775 -VXORPDYrr 6776 -VXORPDZ 6777 -VXORPDZrm 6778 -VXORPDZrmb 6779 -VXORPDZrmbk 6780 -VXORPDZrmbkz 6781 -VXORPDZrmk 6782 -VXORPDZrmkz 6783 -VXORPDZrr 6784 -VXORPDZrrk 6785 -VXORPDZrrkz 6786 -VXORPDrm 6787 -VXORPDrr 6788 -VXORPSYrm 6789 -VXORPSYrr 6790 -VXORPSZ 6791 -VXORPSZrm 6792 -VXORPSZrmb 6793 -VXORPSZrmbk 6794 -VXORPSZrmbkz 6795 -VXORPSZrmk 6796 -VXORPSZrmkz 6797 -VXORPSZrr 6798 -VXORPSZrrk 6799 -VXORPSZrrkz 6800 -VXORPSrm 6801 -VXORPSrr 6802 -VZEROALL 6803 -VZEROUPPER 6804 -V_SET 6805 -V_SETALLONES 6806 -WAIT 6807 -WBINVD 6808 -WBNOINVD 6809 -WRFLAGS 6810 -WRFSBASE 6811 -WRGSBASE 6812 -WRMSR 6813 -WRMSRLIST 6814 -WRMSRNS 6815 -WRMSRNSir 6816 -WRMSRNSir_EVEX 6817 -WRPKRUr 6818 -WRSSD 6819 -WRSSD_EVEX 6820 -WRSSQ 6821 -WRSSQ_EVEX 6822 -WRUSSD 6823 -WRUSSD_EVEX 6824 -WRUSSQ 6825 -WRUSSQ_EVEX 6826 -XABORT 6827 -XABORT_DEF 6828 -XACQUIRE_PREFIX 6829 -XADD 6830 -XAM_F 6831 -XAM_Fp 6832 -XBEGIN 6833 -XCHG 6834 -XCH_F 6835 -XCRYPTCBC 6836 -XCRYPTCFB 6837 -XCRYPTCTR 6838 -XCRYPTECB 6839 -XCRYPTOFB 6840 -XEND 6841 -XGETBV 6842 -XLAT 6843 -XOR 6844 -XORPDrm 6845 -XORPDrr 6846 -XORPSrm 6847 -XORPSrr 6848 -XRELEASE_PREFIX 6849 -XRESLDTRK 6850 -XRSTOR 6851 -XRSTORS 6852 -XSAVE 6853 -XSAVEC 6854 -XSAVEOPT 6855 -XSAVES 6856 -XSETBV 6857 -XSHA 6858 -XSTORE 6859 -XSUSLDTRK 6860 -XTEST 6861 -Immediate 6862 -CImmediate 6863 -FPImmediate 6864 -MBB 6865 -FrameIndex 6866 -ConstantPoolIndex 6867 -TargetIndex 6868 -JumpTableIndex 6869 -ExternalSymbol 6870 -GlobalAddress 6871 -BlockAddress 6872 -RegisterMask 6873 -RegisterLiveOut 6874 -Metadata 6875 -MCSymbol 6876 -CFIIndex 6877 -IntrinsicID 6878 -Predicate 6879 -ShuffleMask 6880 -PhyReg_GR8 6881 -PhyReg_GRH8 6882 -PhyReg_GR8_NOREX2 6883 -PhyReg_GR8_NOREX 6884 -PhyReg_GR8_ABCD_H 6885 -PhyReg_GR8_ABCD_L 6886 -PhyReg_GRH16 6887 -PhyReg_GR16 6888 -PhyReg_GR16_NOREX2 6889 -PhyReg_GR16_NOREX 6890 -PhyReg_VK1 6891 -PhyReg_VK16 6892 -PhyReg_VK2 6893 -PhyReg_VK4 6894 -PhyReg_VK8 6895 -PhyReg_VK16WM 6896 -PhyReg_VK1WM 6897 -PhyReg_VK2WM 6898 -PhyReg_VK4WM 6899 -PhyReg_VK8WM 6900 -PhyReg_SEGMENT_REG 6901 -PhyReg_GR16_ABCD 6902 -PhyReg_FPCCR 6903 -PhyReg_FR16X 6904 -PhyReg_FR16 6905 -PhyReg_VK16PAIR 6906 -PhyReg_VK1PAIR 6907 -PhyReg_VK2PAIR 6908 -PhyReg_VK4PAIR 6909 -PhyReg_VK8PAIR 6910 -PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6911 -PhyReg_LOW32_ADDR_ACCESS_RBP 6912 -PhyReg_LOW32_ADDR_ACCESS 6913 -PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6914 -PhyReg_FR32X 6915 -PhyReg_GR32 6916 -PhyReg_GR32_NOSP 6917 -PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6918 -PhyReg_DEBUG_REG 6919 -PhyReg_FR32 6920 -PhyReg_GR32_NOREX2 6921 -PhyReg_GR32_NOREX2_NOSP 6922 -PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6923 -PhyReg_GR32_NOREX 6924 -PhyReg_VK32 6925 -PhyReg_GR32_NOREX_NOSP 6926 -PhyReg_RFP32 6927 -PhyReg_VK32WM 6928 -PhyReg_GR32_ABCD 6929 -PhyReg_GR32_TC 6930 -PhyReg_GR32_ABCD_and_GR32_TC 6931 -PhyReg_GR32_AD 6932 -PhyReg_GR32_ArgRef 6933 -PhyReg_GR32_BPSP 6934 -PhyReg_GR32_BSI 6935 -PhyReg_GR32_CB 6936 -PhyReg_GR32_DC 6937 -PhyReg_GR32_DIBP 6938 -PhyReg_GR32_SIDI 6939 -PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6940 -PhyReg_CCR 6941 -PhyReg_DFCCR 6942 -PhyReg_GR32_ABCD_and_GR32_BSI 6943 -PhyReg_GR32_AD_and_GR32_ArgRef 6944 -PhyReg_GR32_ArgRef_and_GR32_CB 6945 -PhyReg_GR32_BPSP_and_GR32_DIBP 6946 -PhyReg_GR32_BPSP_and_GR32_TC 6947 -PhyReg_GR32_BSI_and_GR32_SIDI 6948 -PhyReg_GR32_DIBP_and_GR32_SIDI 6949 -PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6950 -PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6951 -PhyReg_RFP64 6952 -PhyReg_GR64 6953 -PhyReg_FR64X 6954 -PhyReg_GR64_with_sub_8bit 6955 -PhyReg_GR64_NOSP 6956 -PhyReg_GR64_NOREX2 6957 -PhyReg_CONTROL_REG 6958 -PhyReg_FR64 6959 -PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6960 -PhyReg_GR64_NOREX2_NOSP 6961 -PhyReg_GR64PLTSafe 6962 -PhyReg_GR64_TC 6963 -PhyReg_GR64_NOREX 6964 -PhyReg_GR64_TCW64 6965 -PhyReg_GR64_TC_with_sub_8bit 6966 -PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6967 -PhyReg_GR64_TCW64_with_sub_8bit 6968 -PhyReg_GR64_TC_and_GR64_TCW64 6969 -PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6970 -PhyReg_VK64 6971 -PhyReg_VR64 6972 -PhyReg_GR64PLTSafe_and_GR64_TC 6973 -PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6974 -PhyReg_GR64_NOREX_NOSP 6975 -PhyReg_GR64_NOREX_and_GR64_TC 6976 -PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6977 -PhyReg_VK64WM 6978 -PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6979 -PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6980 -PhyReg_GR64PLTSafe_and_GR64_TCW64 6981 -PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6982 -PhyReg_GR64_NOREX_and_GR64_TCW64 6983 -PhyReg_GR64_ABCD 6984 -PhyReg_GR64_with_sub_32bit_in_GR32_TC 6985 -PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6986 -PhyReg_GR64_AD 6987 -PhyReg_GR64_ArgRef 6988 -PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6989 -PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6990 -PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6991 -PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6992 -PhyReg_GR64_with_sub_32bit_in_GR32_CB 6993 -PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6994 -PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6995 -PhyReg_GR64_A 6996 -PhyReg_GR64_ArgRef_and_GR64_TC 6997 -PhyReg_GR64_and_LOW32_ADDR_ACCESS 6998 -PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 6999 -PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7000 -PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7001 -PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7002 -PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7003 -PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7004 -PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7005 -PhyReg_RST 7006 -PhyReg_RFP80 7007 -PhyReg_RFP80_7 7008 -PhyReg_VR128X 7009 -PhyReg_VR128 7010 -PhyReg_VR256X 7011 -PhyReg_VR256 7012 -PhyReg_VR512 7013 -PhyReg_VR512_0_15 7014 -PhyReg_TILE 7015 -VirtReg_GR8 7016 -VirtReg_GRH8 7017 -VirtReg_GR8_NOREX2 7018 -VirtReg_GR8_NOREX 7019 -VirtReg_GR8_ABCD_H 7020 -VirtReg_GR8_ABCD_L 7021 -VirtReg_GRH16 7022 -VirtReg_GR16 7023 -VirtReg_GR16_NOREX2 7024 -VirtReg_GR16_NOREX 7025 -VirtReg_VK1 7026 -VirtReg_VK16 7027 -VirtReg_VK2 7028 -VirtReg_VK4 7029 -VirtReg_VK8 7030 -VirtReg_VK16WM 7031 -VirtReg_VK1WM 7032 -VirtReg_VK2WM 7033 -VirtReg_VK4WM 7034 -VirtReg_VK8WM 7035 -VirtReg_SEGMENT_REG 7036 -VirtReg_GR16_ABCD 7037 -VirtReg_FPCCR 7038 -VirtReg_FR16X 7039 -VirtReg_FR16 7040 -VirtReg_VK16PAIR 7041 -VirtReg_VK1PAIR 7042 -VirtReg_VK2PAIR 7043 -VirtReg_VK4PAIR 7044 -VirtReg_VK8PAIR 7045 -VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7046 -VirtReg_LOW32_ADDR_ACCESS_RBP 7047 -VirtReg_LOW32_ADDR_ACCESS 7048 -VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7049 -VirtReg_FR32X 7050 -VirtReg_GR32 7051 -VirtReg_GR32_NOSP 7052 -VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7053 -VirtReg_DEBUG_REG 7054 -VirtReg_FR32 7055 -VirtReg_GR32_NOREX2 7056 -VirtReg_GR32_NOREX2_NOSP 7057 -VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7058 -VirtReg_GR32_NOREX 7059 -VirtReg_VK32 7060 -VirtReg_GR32_NOREX_NOSP 7061 -VirtReg_RFP32 7062 -VirtReg_VK32WM 7063 -VirtReg_GR32_ABCD 7064 -VirtReg_GR32_TC 7065 -VirtReg_GR32_ABCD_and_GR32_TC 7066 -VirtReg_GR32_AD 7067 -VirtReg_GR32_ArgRef 7068 -VirtReg_GR32_BPSP 7069 -VirtReg_GR32_BSI 7070 -VirtReg_GR32_CB 7071 -VirtReg_GR32_DC 7072 -VirtReg_GR32_DIBP 7073 -VirtReg_GR32_SIDI 7074 -VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7075 -VirtReg_CCR 7076 -VirtReg_DFCCR 7077 -VirtReg_GR32_ABCD_and_GR32_BSI 7078 -VirtReg_GR32_AD_and_GR32_ArgRef 7079 -VirtReg_GR32_ArgRef_and_GR32_CB 7080 -VirtReg_GR32_BPSP_and_GR32_DIBP 7081 -VirtReg_GR32_BPSP_and_GR32_TC 7082 -VirtReg_GR32_BSI_and_GR32_SIDI 7083 -VirtReg_GR32_DIBP_and_GR32_SIDI 7084 -VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7085 -VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7086 -VirtReg_RFP64 7087 -VirtReg_GR64 7088 -VirtReg_FR64X 7089 -VirtReg_GR64_with_sub_8bit 7090 -VirtReg_GR64_NOSP 7091 -VirtReg_GR64_NOREX2 7092 -VirtReg_CONTROL_REG 7093 -VirtReg_FR64 7094 -VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7095 -VirtReg_GR64_NOREX2_NOSP 7096 -VirtReg_GR64PLTSafe 7097 -VirtReg_GR64_TC 7098 -VirtReg_GR64_NOREX 7099 -VirtReg_GR64_TCW64 7100 -VirtReg_GR64_TC_with_sub_8bit 7101 -VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7102 -VirtReg_GR64_TCW64_with_sub_8bit 7103 -VirtReg_GR64_TC_and_GR64_TCW64 7104 -VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7105 -VirtReg_VK64 7106 -VirtReg_VR64 7107 -VirtReg_GR64PLTSafe_and_GR64_TC 7108 -VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7109 -VirtReg_GR64_NOREX_NOSP 7110 -VirtReg_GR64_NOREX_and_GR64_TC 7111 -VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7112 -VirtReg_VK64WM 7113 -VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7114 -VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7115 -VirtReg_GR64PLTSafe_and_GR64_TCW64 7116 -VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7117 -VirtReg_GR64_NOREX_and_GR64_TCW64 7118 -VirtReg_GR64_ABCD 7119 -VirtReg_GR64_with_sub_32bit_in_GR32_TC 7120 -VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7121 -VirtReg_GR64_AD 7122 -VirtReg_GR64_ArgRef 7123 -VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7124 -VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7125 -VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7126 -VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7127 -VirtReg_GR64_with_sub_32bit_in_GR32_CB 7128 -VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7129 -VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7130 -VirtReg_GR64_A 7131 -VirtReg_GR64_ArgRef_and_GR64_TC 7132 -VirtReg_GR64_and_LOW32_ADDR_ACCESS 7133 -VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7134 -VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7135 -VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7136 -VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7137 -VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7138 -VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7139 -VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7140 -VirtReg_RST 7141 -VirtReg_RFP80 7142 -VirtReg_RFP80_7 7143 -VirtReg_VR128X 7144 -VirtReg_VR128 7145 -VirtReg_VR256X 7146 -VirtReg_VR256 7147 -VirtReg_VR512 7148 -VirtReg_VR512_0_15 7149 -VirtReg_TILE 7150 +RELOC_NONE 1533 +REPNE_PREFIX 1534 +REP_MOVSB 1535 +REP_MOVSD 1536 +REP_MOVSQ 1537 +REP_MOVSW 1538 +REP_PREFIX 1539 +REP_STOSB 1540 +REP_STOSD 1541 +REP_STOSQ 1542 +REP_STOSW 1543 +RET 1544 +RETI 1545 +REX 1546 +RMPADJUST 1547 +RMPQUERY 1548 +RMPUPDATE 1549 +ROL 1550 +ROR 1551 +RORX 1552 +ROUNDPDmi 1553 +ROUNDPDri 1554 +ROUNDPSmi 1555 +ROUNDPSri 1556 +ROUNDSDmi 1557 +ROUNDSDmi_Int 1558 +ROUNDSDri 1559 +ROUNDSDri_Int 1560 +ROUNDSSmi 1561 +ROUNDSSmi_Int 1562 +ROUNDSSri 1563 +ROUNDSSri_Int 1564 +RSM 1565 +RSQRTPSm 1566 +RSQRTPSr 1567 +RSQRTSSm 1568 +RSQRTSSm_Int 1569 +RSQRTSSr 1570 +RSQRTSSr_Int 1571 +RSTORSSP 1572 +SAHF 1573 +SALC 1574 +SAR 1575 +SARX 1576 +SAVEPREVSSP 1577 +SBB 1578 +SCASB 1579 +SCASL 1580 +SCASQ 1581 +SCASW 1582 +SEAMCALL 1583 +SEAMOPS 1584 +SEAMRET 1585 +SEG_ALLOCA 1586 +SEH_BeginEpilogue 1587 +SEH_EndEpilogue 1588 +SEH_EndPrologue 1589 +SEH_PushFrame 1590 +SEH_PushReg 1591 +SEH_SaveReg 1592 +SEH_SaveXMM 1593 +SEH_SetFrame 1594 +SEH_StackAlign 1595 +SEH_StackAlloc 1596 +SEH_UnwindV 1597 +SEH_UnwindVersion 1598 +SENDUIPI 1599 +SERIALIZE 1600 +SETB_C 1601 +SETCCm 1602 +SETCCm_EVEX 1603 +SETCCr 1604 +SETCCr_EVEX 1605 +SETSSBSY 1606 +SETZUCCm 1607 +SETZUCCr 1608 +SFENCE 1609 +SGDT 1610 +SHA 1611 +SHL 1612 +SHLD 1613 +SHLDROT 1614 +SHLX 1615 +SHR 1616 +SHRD 1617 +SHRDROT 1618 +SHRX 1619 +SHUFPDrmi 1620 +SHUFPDrri 1621 +SHUFPSrmi 1622 +SHUFPSrri 1623 +SIDT 1624 +SKINIT 1625 +SLDT 1626 +SLWPCB 1627 +SMSW 1628 +SQRTPDm 1629 +SQRTPDr 1630 +SQRTPSm 1631 +SQRTPSr 1632 +SQRTSDm 1633 +SQRTSDm_Int 1634 +SQRTSDr 1635 +SQRTSDr_Int 1636 +SQRTSSm 1637 +SQRTSSm_Int 1638 +SQRTSSr 1639 +SQRTSSr_Int 1640 +SQRT_F 1641 +SQRT_Fp 1642 +SS_PREFIX 1643 +STAC 1644 +STACKALLOC_W_PROBING 1645 +STACKMAP 1646 +STATEPOINT 1647 +STC 1648 +STD 1649 +STGI 1650 +STI 1651 +STMXCSR 1652 +STOSB 1653 +STOSL 1654 +STOSQ 1655 +STOSW 1656 +STR 1657 +STRm 1658 +STTILECFG 1659 +STTILECFG_EVEX 1660 +STUI 1661 +ST_F 1662 +ST_FP 1663 +ST_FPrr 1664 +ST_Fp 1665 +ST_FpP 1666 +ST_Frr 1667 +SUB 1668 +SUBPDrm 1669 +SUBPDrr 1670 +SUBPSrm 1671 +SUBPSrr 1672 +SUBREG_TO_REG 1673 +SUBR_F 1674 +SUBR_FI 1675 +SUBR_FPrST 1676 +SUBR_FST 1677 +SUBR_Fp 1678 +SUBR_FpI 1679 +SUBR_FrST 1680 +SUBSDrm 1681 +SUBSDrm_Int 1682 +SUBSDrr 1683 +SUBSDrr_Int 1684 +SUBSSrm 1685 +SUBSSrm_Int 1686 +SUBSSrr 1687 +SUBSSrr_Int 1688 +SUB_F 1689 +SUB_FI 1690 +SUB_FPrST 1691 +SUB_FST 1692 +SUB_Fp 1693 +SUB_FpI 1694 +SUB_FrST 1695 +SWAPGS 1696 +SYSCALL 1697 +SYSENTER 1698 +SYSEXIT 1699 +SYSRET 1700 +T 1701 +TAILJMPd 1702 +TAILJMPd_CC 1703 +TAILJMPm 1704 +TAILJMPr 1705 +TCMMIMFP 1706 +TCMMRLFP 1707 +TCRETURN_HIPE 1708 +TCRETURN_WIN 1709 +TCRETURN_WINmi 1710 +TCRETURNdi 1711 +TCRETURNdicc 1712 +TCRETURNmi 1713 +TCRETURNri 1714 +TCVTROWD 1715 +TCVTROWPS 1716 +TDCALL 1717 +TDPBF 1718 +TDPBHF 1719 +TDPBSSD 1720 +TDPBSUD 1721 +TDPBUSD 1722 +TDPBUUD 1723 +TDPFP 1724 +TDPHBF 1725 +TDPHF 1726 +TEST 1727 +TESTUI 1728 +TILELOADD 1729 +TILELOADDRS 1730 +TILELOADDRST 1731 +TILELOADDRS_EVEX 1732 +TILELOADDT 1733 +TILELOADD_EVEX 1734 +TILEMOVROWrre 1735 +TILEMOVROWrri 1736 +TILERELEASE 1737 +TILESTORED 1738 +TILESTORED_EVEX 1739 +TILEZERO 1740 +TLBSYNC 1741 +TLSCall 1742 +TLS_addr 1743 +TLS_addrX 1744 +TLS_base_addr 1745 +TLS_base_addrX 1746 +TLS_desc 1747 +TMMULTF 1748 +TPAUSE 1749 +TRAP 1750 +TST_F 1751 +TST_Fp 1752 +TZCNT 1753 +TZMSK 1754 +UBSAN_UD 1755 +UCOMISDrm 1756 +UCOMISDrm_Int 1757 +UCOMISDrr 1758 +UCOMISDrr_Int 1759 +UCOMISSrm 1760 +UCOMISSrm_Int 1761 +UCOMISSrr 1762 +UCOMISSrr_Int 1763 +UCOM_FIPr 1764 +UCOM_FIr 1765 +UCOM_FPPr 1766 +UCOM_FPr 1767 +UCOM_FpIr 1768 +UCOM_Fpr 1769 +UCOM_Fr 1770 +UD 1771 +UIRET 1772 +UMONITOR 1773 +UMWAIT 1774 +UNPCKHPDrm 1775 +UNPCKHPDrr 1776 +UNPCKHPSrm 1777 +UNPCKHPSrr 1778 +UNPCKLPDrm 1779 +UNPCKLPDrr 1780 +UNPCKLPSrm 1781 +UNPCKLPSrr 1782 +URDMSRri 1783 +URDMSRri_EVEX 1784 +URDMSRrr 1785 +URDMSRrr_EVEX 1786 +UWRMSRir 1787 +UWRMSRir_EVEX 1788 +UWRMSRrr 1789 +UWRMSRrr_EVEX 1790 +V 1791 +VAARG 1792 +VAARG_X 1793 +VADDBF 1794 +VADDPDYrm 1795 +VADDPDYrr 1796 +VADDPDZ 1797 +VADDPDZrm 1798 +VADDPDZrmb 1799 +VADDPDZrmbk 1800 +VADDPDZrmbkz 1801 +VADDPDZrmk 1802 +VADDPDZrmkz 1803 +VADDPDZrr 1804 +VADDPDZrrb 1805 +VADDPDZrrbk 1806 +VADDPDZrrbkz 1807 +VADDPDZrrk 1808 +VADDPDZrrkz 1809 +VADDPDrm 1810 +VADDPDrr 1811 +VADDPHZ 1812 +VADDPHZrm 1813 +VADDPHZrmb 1814 +VADDPHZrmbk 1815 +VADDPHZrmbkz 1816 +VADDPHZrmk 1817 +VADDPHZrmkz 1818 +VADDPHZrr 1819 +VADDPHZrrb 1820 +VADDPHZrrbk 1821 +VADDPHZrrbkz 1822 +VADDPHZrrk 1823 +VADDPHZrrkz 1824 +VADDPSYrm 1825 +VADDPSYrr 1826 +VADDPSZ 1827 +VADDPSZrm 1828 +VADDPSZrmb 1829 +VADDPSZrmbk 1830 +VADDPSZrmbkz 1831 +VADDPSZrmk 1832 +VADDPSZrmkz 1833 +VADDPSZrr 1834 +VADDPSZrrb 1835 +VADDPSZrrbk 1836 +VADDPSZrrbkz 1837 +VADDPSZrrk 1838 +VADDPSZrrkz 1839 +VADDPSrm 1840 +VADDPSrr 1841 +VADDSDZrm 1842 +VADDSDZrm_Int 1843 +VADDSDZrmk_Int 1844 +VADDSDZrmkz_Int 1845 +VADDSDZrr 1846 +VADDSDZrr_Int 1847 +VADDSDZrrb_Int 1848 +VADDSDZrrbk_Int 1849 +VADDSDZrrbkz_Int 1850 +VADDSDZrrk_Int 1851 +VADDSDZrrkz_Int 1852 +VADDSDrm 1853 +VADDSDrm_Int 1854 +VADDSDrr 1855 +VADDSDrr_Int 1856 +VADDSHZrm 1857 +VADDSHZrm_Int 1858 +VADDSHZrmk_Int 1859 +VADDSHZrmkz_Int 1860 +VADDSHZrr 1861 +VADDSHZrr_Int 1862 +VADDSHZrrb_Int 1863 +VADDSHZrrbk_Int 1864 +VADDSHZrrbkz_Int 1865 +VADDSHZrrk_Int 1866 +VADDSHZrrkz_Int 1867 +VADDSSZrm 1868 +VADDSSZrm_Int 1869 +VADDSSZrmk_Int 1870 +VADDSSZrmkz_Int 1871 +VADDSSZrr 1872 +VADDSSZrr_Int 1873 +VADDSSZrrb_Int 1874 +VADDSSZrrbk_Int 1875 +VADDSSZrrbkz_Int 1876 +VADDSSZrrk_Int 1877 +VADDSSZrrkz_Int 1878 +VADDSSrm 1879 +VADDSSrm_Int 1880 +VADDSSrr 1881 +VADDSSrr_Int 1882 +VADDSUBPDYrm 1883 +VADDSUBPDYrr 1884 +VADDSUBPDrm 1885 +VADDSUBPDrr 1886 +VADDSUBPSYrm 1887 +VADDSUBPSYrr 1888 +VADDSUBPSrm 1889 +VADDSUBPSrr 1890 +VAESDECLASTYrm 1891 +VAESDECLASTYrr 1892 +VAESDECLASTZ 1893 +VAESDECLASTZrm 1894 +VAESDECLASTZrr 1895 +VAESDECLASTrm 1896 +VAESDECLASTrr 1897 +VAESDECYrm 1898 +VAESDECYrr 1899 +VAESDECZ 1900 +VAESDECZrm 1901 +VAESDECZrr 1902 +VAESDECrm 1903 +VAESDECrr 1904 +VAESENCLASTYrm 1905 +VAESENCLASTYrr 1906 +VAESENCLASTZ 1907 +VAESENCLASTZrm 1908 +VAESENCLASTZrr 1909 +VAESENCLASTrm 1910 +VAESENCLASTrr 1911 +VAESENCYrm 1912 +VAESENCYrr 1913 +VAESENCZ 1914 +VAESENCZrm 1915 +VAESENCZrr 1916 +VAESENCrm 1917 +VAESENCrr 1918 +VAESIMCrm 1919 +VAESIMCrr 1920 +VAESKEYGENASSISTrmi 1921 +VAESKEYGENASSISTrri 1922 +VALIGNDZ 1923 +VALIGNDZrmbi 1924 +VALIGNDZrmbik 1925 +VALIGNDZrmbikz 1926 +VALIGNDZrmi 1927 +VALIGNDZrmik 1928 +VALIGNDZrmikz 1929 +VALIGNDZrri 1930 +VALIGNDZrrik 1931 +VALIGNDZrrikz 1932 +VALIGNQZ 1933 +VALIGNQZrmbi 1934 +VALIGNQZrmbik 1935 +VALIGNQZrmbikz 1936 +VALIGNQZrmi 1937 +VALIGNQZrmik 1938 +VALIGNQZrmikz 1939 +VALIGNQZrri 1940 +VALIGNQZrrik 1941 +VALIGNQZrrikz 1942 +VANDNPDYrm 1943 +VANDNPDYrr 1944 +VANDNPDZ 1945 +VANDNPDZrm 1946 +VANDNPDZrmb 1947 +VANDNPDZrmbk 1948 +VANDNPDZrmbkz 1949 +VANDNPDZrmk 1950 +VANDNPDZrmkz 1951 +VANDNPDZrr 1952 +VANDNPDZrrk 1953 +VANDNPDZrrkz 1954 +VANDNPDrm 1955 +VANDNPDrr 1956 +VANDNPSYrm 1957 +VANDNPSYrr 1958 +VANDNPSZ 1959 +VANDNPSZrm 1960 +VANDNPSZrmb 1961 +VANDNPSZrmbk 1962 +VANDNPSZrmbkz 1963 +VANDNPSZrmk 1964 +VANDNPSZrmkz 1965 +VANDNPSZrr 1966 +VANDNPSZrrk 1967 +VANDNPSZrrkz 1968 +VANDNPSrm 1969 +VANDNPSrr 1970 +VANDPDYrm 1971 +VANDPDYrr 1972 +VANDPDZ 1973 +VANDPDZrm 1974 +VANDPDZrmb 1975 +VANDPDZrmbk 1976 +VANDPDZrmbkz 1977 +VANDPDZrmk 1978 +VANDPDZrmkz 1979 +VANDPDZrr 1980 +VANDPDZrrk 1981 +VANDPDZrrkz 1982 +VANDPDrm 1983 +VANDPDrr 1984 +VANDPSYrm 1985 +VANDPSYrr 1986 +VANDPSZ 1987 +VANDPSZrm 1988 +VANDPSZrmb 1989 +VANDPSZrmbk 1990 +VANDPSZrmbkz 1991 +VANDPSZrmk 1992 +VANDPSZrmkz 1993 +VANDPSZrr 1994 +VANDPSZrrk 1995 +VANDPSZrrkz 1996 +VANDPSrm 1997 +VANDPSrr 1998 +VASTART_SAVE_XMM_REGS 1999 +VBCSTNEBF 2000 +VBCSTNESH 2001 +VBLENDMPDZ 2002 +VBLENDMPDZrm 2003 +VBLENDMPDZrmb 2004 +VBLENDMPDZrmbk 2005 +VBLENDMPDZrmbkz 2006 +VBLENDMPDZrmk 2007 +VBLENDMPDZrmkz 2008 +VBLENDMPDZrr 2009 +VBLENDMPDZrrk 2010 +VBLENDMPDZrrkz 2011 +VBLENDMPSZ 2012 +VBLENDMPSZrm 2013 +VBLENDMPSZrmb 2014 +VBLENDMPSZrmbk 2015 +VBLENDMPSZrmbkz 2016 +VBLENDMPSZrmk 2017 +VBLENDMPSZrmkz 2018 +VBLENDMPSZrr 2019 +VBLENDMPSZrrk 2020 +VBLENDMPSZrrkz 2021 +VBLENDPDYrmi 2022 +VBLENDPDYrri 2023 +VBLENDPDrmi 2024 +VBLENDPDrri 2025 +VBLENDPSYrmi 2026 +VBLENDPSYrri 2027 +VBLENDPSrmi 2028 +VBLENDPSrri 2029 +VBLENDVPDYrmr 2030 +VBLENDVPDYrrr 2031 +VBLENDVPDrmr 2032 +VBLENDVPDrrr 2033 +VBLENDVPSYrmr 2034 +VBLENDVPSYrrr 2035 +VBLENDVPSrmr 2036 +VBLENDVPSrrr 2037 +VBROADCASTF 2038 +VBROADCASTI 2039 +VBROADCASTSDYrm 2040 +VBROADCASTSDYrr 2041 +VBROADCASTSDZ 2042 +VBROADCASTSDZrm 2043 +VBROADCASTSDZrmk 2044 +VBROADCASTSDZrmkz 2045 +VBROADCASTSDZrr 2046 +VBROADCASTSDZrrk 2047 +VBROADCASTSDZrrkz 2048 +VBROADCASTSSYrm 2049 +VBROADCASTSSYrr 2050 +VBROADCASTSSZ 2051 +VBROADCASTSSZrm 2052 +VBROADCASTSSZrmk 2053 +VBROADCASTSSZrmkz 2054 +VBROADCASTSSZrr 2055 +VBROADCASTSSZrrk 2056 +VBROADCASTSSZrrkz 2057 +VBROADCASTSSrm 2058 +VBROADCASTSSrr 2059 +VCMPBF 2060 +VCMPPDYrmi 2061 +VCMPPDYrri 2062 +VCMPPDZ 2063 +VCMPPDZrmbi 2064 +VCMPPDZrmbik 2065 +VCMPPDZrmi 2066 +VCMPPDZrmik 2067 +VCMPPDZrri 2068 +VCMPPDZrrib 2069 +VCMPPDZrribk 2070 +VCMPPDZrrik 2071 +VCMPPDrmi 2072 +VCMPPDrri 2073 +VCMPPHZ 2074 +VCMPPHZrmbi 2075 +VCMPPHZrmbik 2076 +VCMPPHZrmi 2077 +VCMPPHZrmik 2078 +VCMPPHZrri 2079 +VCMPPHZrrib 2080 +VCMPPHZrribk 2081 +VCMPPHZrrik 2082 +VCMPPSYrmi 2083 +VCMPPSYrri 2084 +VCMPPSZ 2085 +VCMPPSZrmbi 2086 +VCMPPSZrmbik 2087 +VCMPPSZrmi 2088 +VCMPPSZrmik 2089 +VCMPPSZrri 2090 +VCMPPSZrrib 2091 +VCMPPSZrribk 2092 +VCMPPSZrrik 2093 +VCMPPSrmi 2094 +VCMPPSrri 2095 +VCMPSDZrmi 2096 +VCMPSDZrmi_Int 2097 +VCMPSDZrmik_Int 2098 +VCMPSDZrri 2099 +VCMPSDZrri_Int 2100 +VCMPSDZrrib_Int 2101 +VCMPSDZrribk_Int 2102 +VCMPSDZrrik_Int 2103 +VCMPSDrmi 2104 +VCMPSDrmi_Int 2105 +VCMPSDrri 2106 +VCMPSDrri_Int 2107 +VCMPSHZrmi 2108 +VCMPSHZrmi_Int 2109 +VCMPSHZrmik_Int 2110 +VCMPSHZrri 2111 +VCMPSHZrri_Int 2112 +VCMPSHZrrib_Int 2113 +VCMPSHZrribk_Int 2114 +VCMPSHZrrik_Int 2115 +VCMPSSZrmi 2116 +VCMPSSZrmi_Int 2117 +VCMPSSZrmik_Int 2118 +VCMPSSZrri 2119 +VCMPSSZrri_Int 2120 +VCMPSSZrrib_Int 2121 +VCMPSSZrribk_Int 2122 +VCMPSSZrrik_Int 2123 +VCMPSSrmi 2124 +VCMPSSrmi_Int 2125 +VCMPSSrri 2126 +VCMPSSrri_Int 2127 +VCOMISBF 2128 +VCOMISDZrm 2129 +VCOMISDZrm_Int 2130 +VCOMISDZrr 2131 +VCOMISDZrr_Int 2132 +VCOMISDZrrb 2133 +VCOMISDrm 2134 +VCOMISDrm_Int 2135 +VCOMISDrr 2136 +VCOMISDrr_Int 2137 +VCOMISHZrm 2138 +VCOMISHZrm_Int 2139 +VCOMISHZrr 2140 +VCOMISHZrr_Int 2141 +VCOMISHZrrb 2142 +VCOMISSZrm 2143 +VCOMISSZrm_Int 2144 +VCOMISSZrr 2145 +VCOMISSZrr_Int 2146 +VCOMISSZrrb 2147 +VCOMISSrm 2148 +VCOMISSrm_Int 2149 +VCOMISSrr 2150 +VCOMISSrr_Int 2151 +VCOMPRESSPDZ 2152 +VCOMPRESSPDZmr 2153 +VCOMPRESSPDZmrk 2154 +VCOMPRESSPDZrr 2155 +VCOMPRESSPDZrrk 2156 +VCOMPRESSPDZrrkz 2157 +VCOMPRESSPSZ 2158 +VCOMPRESSPSZmr 2159 +VCOMPRESSPSZmrk 2160 +VCOMPRESSPSZrr 2161 +VCOMPRESSPSZrrk 2162 +VCOMPRESSPSZrrkz 2163 +VCOMXSDZrm_Int 2164 +VCOMXSDZrr_Int 2165 +VCOMXSDZrrb_Int 2166 +VCOMXSHZrm_Int 2167 +VCOMXSHZrr_Int 2168 +VCOMXSHZrrb_Int 2169 +VCOMXSSZrm_Int 2170 +VCOMXSSZrr_Int 2171 +VCOMXSSZrrb_Int 2172 +VCVT 2173 +VCVTBF 2174 +VCVTBIASPH 2175 +VCVTDQ 2176 +VCVTHF 2177 +VCVTNE 2178 +VCVTNEEBF 2179 +VCVTNEEPH 2180 +VCVTNEOBF 2181 +VCVTNEOPH 2182 +VCVTNEPS 2183 +VCVTPD 2184 +VCVTPH 2185 +VCVTPS 2186 +VCVTQQ 2187 +VCVTSD 2188 +VCVTSH 2189 +VCVTSI 2190 +VCVTSS 2191 +VCVTTBF 2192 +VCVTTPD 2193 +VCVTTPH 2194 +VCVTTPS 2195 +VCVTTSD 2196 +VCVTTSH 2197 +VCVTTSS 2198 +VCVTUDQ 2199 +VCVTUQQ 2200 +VCVTUSI 2201 +VCVTUW 2202 +VCVTW 2203 +VDBPSADBWZ 2204 +VDBPSADBWZrmi 2205 +VDBPSADBWZrmik 2206 +VDBPSADBWZrmikz 2207 +VDBPSADBWZrri 2208 +VDBPSADBWZrrik 2209 +VDBPSADBWZrrikz 2210 +VDIVBF 2211 +VDIVPDYrm 2212 +VDIVPDYrr 2213 +VDIVPDZ 2214 +VDIVPDZrm 2215 +VDIVPDZrmb 2216 +VDIVPDZrmbk 2217 +VDIVPDZrmbkz 2218 +VDIVPDZrmk 2219 +VDIVPDZrmkz 2220 +VDIVPDZrr 2221 +VDIVPDZrrb 2222 +VDIVPDZrrbk 2223 +VDIVPDZrrbkz 2224 +VDIVPDZrrk 2225 +VDIVPDZrrkz 2226 +VDIVPDrm 2227 +VDIVPDrr 2228 +VDIVPHZ 2229 +VDIVPHZrm 2230 +VDIVPHZrmb 2231 +VDIVPHZrmbk 2232 +VDIVPHZrmbkz 2233 +VDIVPHZrmk 2234 +VDIVPHZrmkz 2235 +VDIVPHZrr 2236 +VDIVPHZrrb 2237 +VDIVPHZrrbk 2238 +VDIVPHZrrbkz 2239 +VDIVPHZrrk 2240 +VDIVPHZrrkz 2241 +VDIVPSYrm 2242 +VDIVPSYrr 2243 +VDIVPSZ 2244 +VDIVPSZrm 2245 +VDIVPSZrmb 2246 +VDIVPSZrmbk 2247 +VDIVPSZrmbkz 2248 +VDIVPSZrmk 2249 +VDIVPSZrmkz 2250 +VDIVPSZrr 2251 +VDIVPSZrrb 2252 +VDIVPSZrrbk 2253 +VDIVPSZrrbkz 2254 +VDIVPSZrrk 2255 +VDIVPSZrrkz 2256 +VDIVPSrm 2257 +VDIVPSrr 2258 +VDIVSDZrm 2259 +VDIVSDZrm_Int 2260 +VDIVSDZrmk_Int 2261 +VDIVSDZrmkz_Int 2262 +VDIVSDZrr 2263 +VDIVSDZrr_Int 2264 +VDIVSDZrrb_Int 2265 +VDIVSDZrrbk_Int 2266 +VDIVSDZrrbkz_Int 2267 +VDIVSDZrrk_Int 2268 +VDIVSDZrrkz_Int 2269 +VDIVSDrm 2270 +VDIVSDrm_Int 2271 +VDIVSDrr 2272 +VDIVSDrr_Int 2273 +VDIVSHZrm 2274 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+VEXPANDPSZrm 2330 +VEXPANDPSZrmk 2331 +VEXPANDPSZrmkz 2332 +VEXPANDPSZrr 2333 +VEXPANDPSZrrk 2334 +VEXPANDPSZrrkz 2335 +VEXTRACTF 2336 +VEXTRACTI 2337 +VEXTRACTPSZmri 2338 +VEXTRACTPSZrri 2339 +VEXTRACTPSmri 2340 +VEXTRACTPSrri 2341 +VFCMADDCPHZ 2342 +VFCMADDCPHZm 2343 +VFCMADDCPHZmb 2344 +VFCMADDCPHZmbk 2345 +VFCMADDCPHZmbkz 2346 +VFCMADDCPHZmk 2347 +VFCMADDCPHZmkz 2348 +VFCMADDCPHZr 2349 +VFCMADDCPHZrb 2350 +VFCMADDCPHZrbk 2351 +VFCMADDCPHZrbkz 2352 +VFCMADDCPHZrk 2353 +VFCMADDCPHZrkz 2354 +VFCMADDCSHZm 2355 +VFCMADDCSHZmk 2356 +VFCMADDCSHZmkz 2357 +VFCMADDCSHZr 2358 +VFCMADDCSHZrb 2359 +VFCMADDCSHZrbk 2360 +VFCMADDCSHZrbkz 2361 +VFCMADDCSHZrk 2362 +VFCMADDCSHZrkz 2363 +VFCMULCPHZ 2364 +VFCMULCPHZrm 2365 +VFCMULCPHZrmb 2366 +VFCMULCPHZrmbk 2367 +VFCMULCPHZrmbkz 2368 +VFCMULCPHZrmk 2369 +VFCMULCPHZrmkz 2370 +VFCMULCPHZrr 2371 +VFCMULCPHZrrb 2372 +VFCMULCPHZrrbk 2373 +VFCMULCPHZrrbkz 2374 +VFCMULCPHZrrk 2375 +VFCMULCPHZrrkz 2376 +VFCMULCSHZrm 2377 +VFCMULCSHZrmk 2378 +VFCMULCSHZrmkz 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6631 +VSUBPSrr 6632 +VSUBSDZrm 6633 +VSUBSDZrm_Int 6634 +VSUBSDZrmk_Int 6635 +VSUBSDZrmkz_Int 6636 +VSUBSDZrr 6637 +VSUBSDZrr_Int 6638 +VSUBSDZrrb_Int 6639 +VSUBSDZrrbk_Int 6640 +VSUBSDZrrbkz_Int 6641 +VSUBSDZrrk_Int 6642 +VSUBSDZrrkz_Int 6643 +VSUBSDrm 6644 +VSUBSDrm_Int 6645 +VSUBSDrr 6646 +VSUBSDrr_Int 6647 +VSUBSHZrm 6648 +VSUBSHZrm_Int 6649 +VSUBSHZrmk_Int 6650 +VSUBSHZrmkz_Int 6651 +VSUBSHZrr 6652 +VSUBSHZrr_Int 6653 +VSUBSHZrrb_Int 6654 +VSUBSHZrrbk_Int 6655 +VSUBSHZrrbkz_Int 6656 +VSUBSHZrrk_Int 6657 +VSUBSHZrrkz_Int 6658 +VSUBSSZrm 6659 +VSUBSSZrm_Int 6660 +VSUBSSZrmk_Int 6661 +VSUBSSZrmkz_Int 6662 +VSUBSSZrr 6663 +VSUBSSZrr_Int 6664 +VSUBSSZrrb_Int 6665 +VSUBSSZrrbk_Int 6666 +VSUBSSZrrbkz_Int 6667 +VSUBSSZrrk_Int 6668 +VSUBSSZrrkz_Int 6669 +VSUBSSrm 6670 +VSUBSSrm_Int 6671 +VSUBSSrr 6672 +VSUBSSrr_Int 6673 +VTESTPDYrm 6674 +VTESTPDYrr 6675 +VTESTPDrm 6676 +VTESTPDrr 6677 +VTESTPSYrm 6678 +VTESTPSYrr 6679 +VTESTPSrm 6680 +VTESTPSrr 6681 +VUCOMISDZrm 6682 +VUCOMISDZrm_Int 6683 +VUCOMISDZrr 6684 +VUCOMISDZrr_Int 6685 +VUCOMISDZrrb 6686 +VUCOMISDrm 6687 +VUCOMISDrm_Int 6688 +VUCOMISDrr 6689 +VUCOMISDrr_Int 6690 +VUCOMISHZrm 6691 +VUCOMISHZrm_Int 6692 +VUCOMISHZrr 6693 +VUCOMISHZrr_Int 6694 +VUCOMISHZrrb 6695 +VUCOMISSZrm 6696 +VUCOMISSZrm_Int 6697 +VUCOMISSZrr 6698 +VUCOMISSZrr_Int 6699 +VUCOMISSZrrb 6700 +VUCOMISSrm 6701 +VUCOMISSrm_Int 6702 +VUCOMISSrr 6703 +VUCOMISSrr_Int 6704 +VUCOMXSDZrm 6705 +VUCOMXSDZrm_Int 6706 +VUCOMXSDZrr 6707 +VUCOMXSDZrr_Int 6708 +VUCOMXSDZrrb_Int 6709 +VUCOMXSHZrm 6710 +VUCOMXSHZrm_Int 6711 +VUCOMXSHZrr 6712 +VUCOMXSHZrr_Int 6713 +VUCOMXSHZrrb_Int 6714 +VUCOMXSSZrm 6715 +VUCOMXSSZrm_Int 6716 +VUCOMXSSZrr 6717 +VUCOMXSSZrr_Int 6718 +VUCOMXSSZrrb_Int 6719 +VUNPCKHPDYrm 6720 +VUNPCKHPDYrr 6721 +VUNPCKHPDZ 6722 +VUNPCKHPDZrm 6723 +VUNPCKHPDZrmb 6724 +VUNPCKHPDZrmbk 6725 +VUNPCKHPDZrmbkz 6726 +VUNPCKHPDZrmk 6727 +VUNPCKHPDZrmkz 6728 +VUNPCKHPDZrr 6729 +VUNPCKHPDZrrk 6730 +VUNPCKHPDZrrkz 6731 +VUNPCKHPDrm 6732 +VUNPCKHPDrr 6733 +VUNPCKHPSYrm 6734 +VUNPCKHPSYrr 6735 +VUNPCKHPSZ 6736 +VUNPCKHPSZrm 6737 +VUNPCKHPSZrmb 6738 +VUNPCKHPSZrmbk 6739 +VUNPCKHPSZrmbkz 6740 +VUNPCKHPSZrmk 6741 +VUNPCKHPSZrmkz 6742 +VUNPCKHPSZrr 6743 +VUNPCKHPSZrrk 6744 +VUNPCKHPSZrrkz 6745 +VUNPCKHPSrm 6746 +VUNPCKHPSrr 6747 +VUNPCKLPDYrm 6748 +VUNPCKLPDYrr 6749 +VUNPCKLPDZ 6750 +VUNPCKLPDZrm 6751 +VUNPCKLPDZrmb 6752 +VUNPCKLPDZrmbk 6753 +VUNPCKLPDZrmbkz 6754 +VUNPCKLPDZrmk 6755 +VUNPCKLPDZrmkz 6756 +VUNPCKLPDZrr 6757 +VUNPCKLPDZrrk 6758 +VUNPCKLPDZrrkz 6759 +VUNPCKLPDrm 6760 +VUNPCKLPDrr 6761 +VUNPCKLPSYrm 6762 +VUNPCKLPSYrr 6763 +VUNPCKLPSZ 6764 +VUNPCKLPSZrm 6765 +VUNPCKLPSZrmb 6766 +VUNPCKLPSZrmbk 6767 +VUNPCKLPSZrmbkz 6768 +VUNPCKLPSZrmk 6769 +VUNPCKLPSZrmkz 6770 +VUNPCKLPSZrr 6771 +VUNPCKLPSZrrk 6772 +VUNPCKLPSZrrkz 6773 +VUNPCKLPSrm 6774 +VUNPCKLPSrr 6775 +VXORPDYrm 6776 +VXORPDYrr 6777 +VXORPDZ 6778 +VXORPDZrm 6779 +VXORPDZrmb 6780 +VXORPDZrmbk 6781 +VXORPDZrmbkz 6782 +VXORPDZrmk 6783 +VXORPDZrmkz 6784 +VXORPDZrr 6785 +VXORPDZrrk 6786 +VXORPDZrrkz 6787 +VXORPDrm 6788 +VXORPDrr 6789 +VXORPSYrm 6790 +VXORPSYrr 6791 +VXORPSZ 6792 +VXORPSZrm 6793 +VXORPSZrmb 6794 +VXORPSZrmbk 6795 +VXORPSZrmbkz 6796 +VXORPSZrmk 6797 +VXORPSZrmkz 6798 +VXORPSZrr 6799 +VXORPSZrrk 6800 +VXORPSZrrkz 6801 +VXORPSrm 6802 +VXORPSrr 6803 +VZEROALL 6804 +VZEROUPPER 6805 +V_SET 6806 +V_SETALLONES 6807 +WAIT 6808 +WBINVD 6809 +WBNOINVD 6810 +WRFLAGS 6811 +WRFSBASE 6812 +WRGSBASE 6813 +WRMSR 6814 +WRMSRLIST 6815 +WRMSRNS 6816 +WRMSRNSir 6817 +WRMSRNSir_EVEX 6818 +WRPKRUr 6819 +WRSSD 6820 +WRSSD_EVEX 6821 +WRSSQ 6822 +WRSSQ_EVEX 6823 +WRUSSD 6824 +WRUSSD_EVEX 6825 +WRUSSQ 6826 +WRUSSQ_EVEX 6827 +XABORT 6828 +XABORT_DEF 6829 +XACQUIRE_PREFIX 6830 +XADD 6831 +XAM_F 6832 +XAM_Fp 6833 +XBEGIN 6834 +XCHG 6835 +XCH_F 6836 +XCRYPTCBC 6837 +XCRYPTCFB 6838 +XCRYPTCTR 6839 +XCRYPTECB 6840 +XCRYPTOFB 6841 +XEND 6842 +XGETBV 6843 +XLAT 6844 +XOR 6845 +XORPDrm 6846 +XORPDrr 6847 +XORPSrm 6848 +XORPSrr 6849 +XRELEASE_PREFIX 6850 +XRESLDTRK 6851 +XRSTOR 6852 +XRSTORS 6853 +XSAVE 6854 +XSAVEC 6855 +XSAVEOPT 6856 +XSAVES 6857 +XSETBV 6858 +XSHA 6859 +XSTORE 6860 +XSUSLDTRK 6861 +XTEST 6862 +Immediate 6863 +CImmediate 6864 +FPImmediate 6865 +MBB 6866 +FrameIndex 6867 +ConstantPoolIndex 6868 +TargetIndex 6869 +JumpTableIndex 6870 +ExternalSymbol 6871 +GlobalAddress 6872 +BlockAddress 6873 +RegisterMask 6874 +RegisterLiveOut 6875 +Metadata 6876 +MCSymbol 6877 +CFIIndex 6878 +IntrinsicID 6879 +Predicate 6880 +ShuffleMask 6881 +PhyReg_GR8 6882 +PhyReg_GRH8 6883 +PhyReg_GR8_NOREX2 6884 +PhyReg_GR8_NOREX 6885 +PhyReg_GR8_ABCD_H 6886 +PhyReg_GR8_ABCD_L 6887 +PhyReg_GRH16 6888 +PhyReg_GR16 6889 +PhyReg_GR16_NOREX2 6890 +PhyReg_GR16_NOREX 6891 +PhyReg_VK1 6892 +PhyReg_VK16 6893 +PhyReg_VK2 6894 +PhyReg_VK4 6895 +PhyReg_VK8 6896 +PhyReg_VK16WM 6897 +PhyReg_VK1WM 6898 +PhyReg_VK2WM 6899 +PhyReg_VK4WM 6900 +PhyReg_VK8WM 6901 +PhyReg_SEGMENT_REG 6902 +PhyReg_GR16_ABCD 6903 +PhyReg_FPCCR 6904 +PhyReg_FR16X 6905 +PhyReg_FR16 6906 +PhyReg_VK16PAIR 6907 +PhyReg_VK1PAIR 6908 +PhyReg_VK2PAIR 6909 +PhyReg_VK4PAIR 6910 +PhyReg_VK8PAIR 6911 +PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6912 +PhyReg_LOW32_ADDR_ACCESS_RBP 6913 +PhyReg_LOW32_ADDR_ACCESS 6914 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6915 +PhyReg_FR32X 6916 +PhyReg_GR32 6917 +PhyReg_GR32_NOSP 6918 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6919 +PhyReg_DEBUG_REG 6920 +PhyReg_FR32 6921 +PhyReg_GR32_NOREX2 6922 +PhyReg_GR32_NOREX2_NOSP 6923 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6924 +PhyReg_GR32_NOREX 6925 +PhyReg_VK32 6926 +PhyReg_GR32_NOREX_NOSP 6927 +PhyReg_RFP32 6928 +PhyReg_VK32WM 6929 +PhyReg_GR32_ABCD 6930 +PhyReg_GR32_TC 6931 +PhyReg_GR32_ABCD_and_GR32_TC 6932 +PhyReg_GR32_AD 6933 +PhyReg_GR32_ArgRef 6934 +PhyReg_GR32_BPSP 6935 +PhyReg_GR32_BSI 6936 +PhyReg_GR32_CB 6937 +PhyReg_GR32_DC 6938 +PhyReg_GR32_DIBP 6939 +PhyReg_GR32_SIDI 6940 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6941 +PhyReg_CCR 6942 +PhyReg_DFCCR 6943 +PhyReg_GR32_ABCD_and_GR32_BSI 6944 +PhyReg_GR32_AD_and_GR32_ArgRef 6945 +PhyReg_GR32_ArgRef_and_GR32_CB 6946 +PhyReg_GR32_BPSP_and_GR32_DIBP 6947 +PhyReg_GR32_BPSP_and_GR32_TC 6948 +PhyReg_GR32_BSI_and_GR32_SIDI 6949 +PhyReg_GR32_DIBP_and_GR32_SIDI 6950 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6951 +PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6952 +PhyReg_RFP64 6953 +PhyReg_GR64 6954 +PhyReg_FR64X 6955 +PhyReg_GR64_with_sub_8bit 6956 +PhyReg_GR64_NOSP 6957 +PhyReg_GR64_NOREX2 6958 +PhyReg_CONTROL_REG 6959 +PhyReg_FR64 6960 +PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6961 +PhyReg_GR64_NOREX2_NOSP 6962 +PhyReg_GR64PLTSafe 6963 +PhyReg_GR64_TC 6964 +PhyReg_GR64_NOREX 6965 +PhyReg_GR64_TCW64 6966 +PhyReg_GR64_TC_with_sub_8bit 6967 +PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6968 +PhyReg_GR64_TCW64_with_sub_8bit 6969 +PhyReg_GR64_TC_and_GR64_TCW64 6970 +PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6971 +PhyReg_VK64 6972 +PhyReg_VR64 6973 +PhyReg_GR64PLTSafe_and_GR64_TC 6974 +PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6975 +PhyReg_GR64_NOREX_NOSP 6976 +PhyReg_GR64_NOREX_and_GR64_TC 6977 +PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6978 +PhyReg_VK64WM 6979 +PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6980 +PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6981 +PhyReg_GR64PLTSafe_and_GR64_TCW64 6982 +PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6983 +PhyReg_GR64_NOREX_and_GR64_TCW64 6984 +PhyReg_GR64_ABCD 6985 +PhyReg_GR64_with_sub_32bit_in_GR32_TC 6986 +PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6987 +PhyReg_GR64_AD 6988 +PhyReg_GR64_ArgRef 6989 +PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6990 +PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6991 +PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6992 +PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6993 +PhyReg_GR64_with_sub_32bit_in_GR32_CB 6994 +PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6995 +PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6996 +PhyReg_GR64_A 6997 +PhyReg_GR64_ArgRef_and_GR64_TC 6998 +PhyReg_GR64_and_LOW32_ADDR_ACCESS 6999 +PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7000 +PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7001 +PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7002 +PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7003 +PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7004 +PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7005 +PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7006 +PhyReg_RST 7007 +PhyReg_RFP80 7008 +PhyReg_RFP80_7 7009 +PhyReg_VR128X 7010 +PhyReg_VR128 7011 +PhyReg_VR256X 7012 +PhyReg_VR256 7013 +PhyReg_VR512 7014 +PhyReg_VR512_0_15 7015 +PhyReg_TILE 7016 +VirtReg_GR8 7017 +VirtReg_GRH8 7018 +VirtReg_GR8_NOREX2 7019 +VirtReg_GR8_NOREX 7020 +VirtReg_GR8_ABCD_H 7021 +VirtReg_GR8_ABCD_L 7022 +VirtReg_GRH16 7023 +VirtReg_GR16 7024 +VirtReg_GR16_NOREX2 7025 +VirtReg_GR16_NOREX 7026 +VirtReg_VK1 7027 +VirtReg_VK16 7028 +VirtReg_VK2 7029 +VirtReg_VK4 7030 +VirtReg_VK8 7031 +VirtReg_VK16WM 7032 +VirtReg_VK1WM 7033 +VirtReg_VK2WM 7034 +VirtReg_VK4WM 7035 +VirtReg_VK8WM 7036 +VirtReg_SEGMENT_REG 7037 +VirtReg_GR16_ABCD 7038 +VirtReg_FPCCR 7039 +VirtReg_FR16X 7040 +VirtReg_FR16 7041 +VirtReg_VK16PAIR 7042 +VirtReg_VK1PAIR 7043 +VirtReg_VK2PAIR 7044 +VirtReg_VK4PAIR 7045 +VirtReg_VK8PAIR 7046 +VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7047 +VirtReg_LOW32_ADDR_ACCESS_RBP 7048 +VirtReg_LOW32_ADDR_ACCESS 7049 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7050 +VirtReg_FR32X 7051 +VirtReg_GR32 7052 +VirtReg_GR32_NOSP 7053 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7054 +VirtReg_DEBUG_REG 7055 +VirtReg_FR32 7056 +VirtReg_GR32_NOREX2 7057 +VirtReg_GR32_NOREX2_NOSP 7058 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7059 +VirtReg_GR32_NOREX 7060 +VirtReg_VK32 7061 +VirtReg_GR32_NOREX_NOSP 7062 +VirtReg_RFP32 7063 +VirtReg_VK32WM 7064 +VirtReg_GR32_ABCD 7065 +VirtReg_GR32_TC 7066 +VirtReg_GR32_ABCD_and_GR32_TC 7067 +VirtReg_GR32_AD 7068 +VirtReg_GR32_ArgRef 7069 +VirtReg_GR32_BPSP 7070 +VirtReg_GR32_BSI 7071 +VirtReg_GR32_CB 7072 +VirtReg_GR32_DC 7073 +VirtReg_GR32_DIBP 7074 +VirtReg_GR32_SIDI 7075 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7076 +VirtReg_CCR 7077 +VirtReg_DFCCR 7078 +VirtReg_GR32_ABCD_and_GR32_BSI 7079 +VirtReg_GR32_AD_and_GR32_ArgRef 7080 +VirtReg_GR32_ArgRef_and_GR32_CB 7081 +VirtReg_GR32_BPSP_and_GR32_DIBP 7082 +VirtReg_GR32_BPSP_and_GR32_TC 7083 +VirtReg_GR32_BSI_and_GR32_SIDI 7084 +VirtReg_GR32_DIBP_and_GR32_SIDI 7085 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7086 +VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7087 +VirtReg_RFP64 7088 +VirtReg_GR64 7089 +VirtReg_FR64X 7090 +VirtReg_GR64_with_sub_8bit 7091 +VirtReg_GR64_NOSP 7092 +VirtReg_GR64_NOREX2 7093 +VirtReg_CONTROL_REG 7094 +VirtReg_FR64 7095 +VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7096 +VirtReg_GR64_NOREX2_NOSP 7097 +VirtReg_GR64PLTSafe 7098 +VirtReg_GR64_TC 7099 +VirtReg_GR64_NOREX 7100 +VirtReg_GR64_TCW64 7101 +VirtReg_GR64_TC_with_sub_8bit 7102 +VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7103 +VirtReg_GR64_TCW64_with_sub_8bit 7104 +VirtReg_GR64_TC_and_GR64_TCW64 7105 +VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7106 +VirtReg_VK64 7107 +VirtReg_VR64 7108 +VirtReg_GR64PLTSafe_and_GR64_TC 7109 +VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7110 +VirtReg_GR64_NOREX_NOSP 7111 +VirtReg_GR64_NOREX_and_GR64_TC 7112 +VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7113 +VirtReg_VK64WM 7114 +VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7115 +VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7116 +VirtReg_GR64PLTSafe_and_GR64_TCW64 7117 +VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7118 +VirtReg_GR64_NOREX_and_GR64_TCW64 7119 +VirtReg_GR64_ABCD 7120 +VirtReg_GR64_with_sub_32bit_in_GR32_TC 7121 +VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7122 +VirtReg_GR64_AD 7123 +VirtReg_GR64_ArgRef 7124 +VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7125 +VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7126 +VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7127 +VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7128 +VirtReg_GR64_with_sub_32bit_in_GR32_CB 7129 +VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7130 +VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7131 +VirtReg_GR64_A 7132 +VirtReg_GR64_ArgRef_and_GR64_TC 7133 +VirtReg_GR64_and_LOW32_ADDR_ACCESS 7134 +VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7135 +VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7136 +VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7137 +VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7138 +VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7139 +VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7140 +VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7141 +VirtReg_RST 7142 +VirtReg_RFP80 7143 +VirtReg_RFP80_7 7144 +VirtReg_VR128X 7145 +VirtReg_VR128 7146 +VirtReg_VR256X 7147 +VirtReg_VR256 7148 +VirtReg_VR512 7149 +VirtReg_VR512_0_15 7150 +VirtReg_TILE 7151 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s index 3d7a67d..621cad6 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s @@ -630,593 +630,593 @@ vfwredusum.vs v8, v8, v8 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUMU_VS vwredsumu.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24 +# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUM_VS vwredsum.vs v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMAX_VS vfredmax.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMAX_VS vfredmax.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDMIN_VS vfredmin.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMIN_VS vfredmin.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 24 20.00 24 SMX60_VFP[20] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 48 24.00 48 SMX60_VFP[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 96 48.00 96 SMX60_VFP[48] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 192 96.00 192 SMX60_VFP[96] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 384 384.00 384 SMX60_VFP[384] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 24 12.00 24 SMX60_VFP[12] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 48 24.00 48 SMX60_VFP[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 96 48.00 96 SMX60_VFP[48] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 192 192.00 192 SMX60_VFP[192] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 12 6.00 12 SMX60_VFP[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 24 12.00 24 SMX60_VFP[12] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 48 24.00 48 SMX60_VFP[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDOSUM_VS vfredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 96 96.00 96 SMX60_VFP[96] VFREDOSUM_VS vfredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFREDUSUM_VS vfredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDUSUM_VS vfredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 32 27.00 32 SMX60_VFP[27] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 256 128.00 256 SMX60_VFP[128] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 512 512.00 512 SMX60_VFP[512] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 32 16.00 32 SMX60_VFP[16] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: 1 256 256.00 256 SMX60_VFP[256] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 32 27.00 32 SMX60_VFP[27] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 256 128.00 256 SMX60_VFP[128] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 512 512.00 512 SMX60_VFP[512] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 32 16.00 32 SMX60_VFP[16] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 SMX60_VFP VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: 1 256 256.00 256 SMX60_VFP[256] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8 # CHECK: Resources: # CHECK-NEXT: [0] - SMX60_FP @@ -1230,595 +1230,595 @@ vfwredusum.vs v8, v8, v8 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] -# CHECK-NEXT: - 294.00 - - - 82.00 212.00 - +# CHECK-NEXT: - 294.00 - - - 4271.00 2028.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions: # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8 +# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 4.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 10.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 35.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 4.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 10.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 35.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 4.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 10.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 35.00 - vwredsumu.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 4.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 10.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 35.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 4.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 10.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 35.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 4.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 10.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24 +# CHECK-NEXT: - - - - - - 35.00 - vwredsum.vs v8, v16, v24 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmax.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredmax.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredmin.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredmin.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 24.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 48.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 96.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 384.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 12.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 24.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 48.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 192.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 6.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 12.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 24.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 96.00 - - vfredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 14.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 20.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 57.00 - - vfredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 27.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 11.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 32.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 64.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 128.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 512.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 11.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 16.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 32.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 64.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredosum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 256.00 - - vfwredosum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 27.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 11.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 32.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 64.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 128.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 512.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 11.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 16.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 32.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 64.00 - - vfwredusum.vs v8, v8, v8 # CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - 1.00 - - vfwredusum.vs v8, v8, v8 +# CHECK-NEXT: - - - - - 256.00 - - vfwredusum.vs v8, v8, v8 diff --git a/llvm/test/tools/llvm-profdata/profile-version.test b/llvm/test/tools/llvm-profdata/profile-version.test index cb68a64..e811699 100644 --- a/llvm/test/tools/llvm-profdata/profile-version.test +++ b/llvm/test/tools/llvm-profdata/profile-version.test @@ -2,7 +2,7 @@ Test the profile version. RUN: llvm-profdata merge -o %t.profdata %p/Inputs/basic.proftext RUN: llvm-profdata show --profile-version %t.profdata | FileCheck %s -CHECK: Profile version: 12 +CHECK: Profile version: 13 RUN: llvm-profdata merge -o %t.prev.profdata %p/Inputs/basic.proftext --write-prev-version RUN: llvm-profdata show --profile-version %t.prev.profdata | FileCheck %s --check-prefix=PREV diff --git a/llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsics.ll b/llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsics.ll index a6ace22..b800f9a 100644 --- a/llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsics.ll +++ b/llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsics.ll @@ -26,7 +26,7 @@ define i32 @t(i32 %a) { ; CHECK-ALL: declare i32 @llvm.uadd.sat.i32(i32, i32) #0 declare i32 @llvm.uadd.sat.i32(i32, i32) #0 -; CHECK-ALL: attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +; CHECK-ALL: attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } ; CHECK-INTERESTINGNESS: attributes #1 = { ; CHECK-INTERESTINGNESS-SAME: "arg4" diff --git a/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml b/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml index 51a5a63..ff2c9ae 100644 --- a/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml +++ b/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml @@ -34,7 +34,7 @@ # # CHECK: << Total TLI yes SDK no: 18 # CHECK: >> Total TLI no SDK yes: 0 -# CHECK: == Total TLI yes SDK yes: 271 +# CHECK: == Total TLI yes SDK yes: 277 # # WRONG_DETAIL: << TLI yes SDK no : '_ZdaPv' aka operator delete[](void*) # WRONG_DETAIL: >> TLI no SDK yes: '_ZdaPvj' aka operator delete[](void*, unsigned int) @@ -48,14 +48,14 @@ # WRONG_DETAIL: << TLI yes SDK no : 'fminimum_numl' # WRONG_SUMMARY: << Total TLI yes SDK no: 19{{$}} # WRONG_SUMMARY: >> Total TLI no SDK yes: 1{{$}} -# WRONG_SUMMARY: == Total TLI yes SDK yes: 270 +# WRONG_SUMMARY: == Total TLI yes SDK yes: 276 # ## The -COUNT suffix doesn't care if there are too many matches, so check ## the exact count first; the two directives should add up to that. ## Yes, this means additions to TLI will fail this test, but the argument ## to -COUNT can't be an expression. -# AVAIL: TLI knows 524 symbols, 289 available -# AVAIL-COUNT-289: {{^}} available +# AVAIL: TLI knows 530 symbols, 295 available +# AVAIL-COUNT-295: {{^}} available # AVAIL-NOT: {{^}} available # UNAVAIL-COUNT-235: not available # UNAVAIL-NOT: not available @@ -778,6 +778,30 @@ DynamicSymbols: Type: STT_FUNC Section: .text Binding: STB_GLOBAL + - Name: nextafter + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL + - Name: nextafterf + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL + - Name: nextafterl + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL + - Name: nexttoward + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL + - Name: nexttowardf + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL + - Name: nexttowardl + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL - Name: perror Type: STT_FUNC Section: .text |