aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir4
-rw-r--r--llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir4
-rw-r--r--llvm/test/CodeGen/X86/fcmove.ll15
-rw-r--r--llvm/test/CodeGen/X86/isel-select-fcmov.ll175
-rw-r--r--llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll46
5 files changed, 225 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
index 470a30fd..bd4e9a4 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
@@ -37,9 +37,9 @@ body: |
; X86-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; X86-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[CTLZ]], [[C1]]
; X86-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)
+ ; X86-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)
; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CTLZ_ZERO_UNDEF]](s64)
- ; X86-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT1]](s32), [[UV2]], [[UV4]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT1]](s32), [[UV3]], [[UV5]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
@@ -111,9 +111,9 @@ body: |
; X86-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; X86-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[CTLZ]], [[C1]]
; X86-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)
+ ; X86-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)
; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CTLZ_ZERO_UNDEF]](s64)
- ; X86-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT]](s32), [[UV2]], [[UV4]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT]](s32), [[UV3]], [[UV5]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir
index a7cbb35..6ab424e 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir
@@ -33,9 +33,9 @@ body: |
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF2:%[0-9]+]]:_(s1) = IMPLICIT_DEF
+ ; X86-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
- ; X86-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT]](s32), [[UV]], [[UV2]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ZEXT]](s32), [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
@@ -115,9 +115,9 @@ body: |
; X64: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; X64-NEXT: [[DEF2:%[0-9]+]]:_(s1) = IMPLICIT_DEF
+ ; X64-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF1]](s8)
; X64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF]](s8)
- ; X64-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
; X64-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ZEXT]](s32), [[ANYEXT]], [[ANYEXT1]]
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16)
; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
diff --git a/llvm/test/CodeGen/X86/fcmove.ll b/llvm/test/CodeGen/X86/fcmove.ll
deleted file mode 100644
index 6bb0148..0000000
--- a/llvm/test/CodeGen/X86/fcmove.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
-
-target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-unknown"
-
-; Test that we can generate an fcmove, and also that it passes verification.
-
-; CHECK-LABEL: cmove_f
-; CHECK: fcmove %st({{[0-7]}}), %st
-define x86_fp80 @cmove_f(x86_fp80 %a, x86_fp80 %b, i32 %c) {
- %test = icmp eq i32 %c, 0
- %add = fadd x86_fp80 %a, %b
- %ret = select i1 %test, x86_fp80 %add, x86_fp80 %b
- ret x86_fp80 %ret
-}
diff --git a/llvm/test/CodeGen/X86/isel-select-fcmov.ll b/llvm/test/CodeGen/X86/isel-select-fcmov.ll
new file mode 100644
index 0000000..cb441b8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/isel-select-fcmov.ll
@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=i686-linux-gnu -mattr=+cmov -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=i686-linux-gnu -mattr=+cmov -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=X86-GISEL
+; RUN: llc < %s -mtriple=i686-linux-gnu -mattr=+cmov -fast-isel=0 -global-isel=0 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=X64-GISEL
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -fast-isel=0 -global-isel=0 | FileCheck %s --check-prefix=X64
+
+; Test that we can generate an fcmove, and also that it passes verification.
+
+define x86_fp80 @cmove_cmp(x86_fp80 %a, x86_fp80 %b, i32 %c) {
+; X86-LABEL: cmove_cmp:
+; X86: # %bb.0:
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT: fadd %st(1), %st
+; X86-NEXT: fxch %st(1)
+; X86-NEXT: fcmove %st(1), %st
+; X86-NEXT: fstp %st(1)
+; X86-NEXT: retl
+;
+; X86-GISEL-LABEL: cmove_cmp:
+; X86-GISEL: # %bb.0:
+; X86-GISEL-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: xorl %eax, %eax
+; X86-GISEL-NEXT: cmpl $0, {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: sete %al
+; X86-GISEL-NEXT: fadd %st, %st(1)
+; X86-GISEL-NEXT: andl $1, %eax
+; X86-GISEL-NEXT: testl %eax, %eax
+; X86-GISEL-NEXT: fxch %st(1)
+; X86-GISEL-NEXT: fcmove %st(1), %st
+; X86-GISEL-NEXT: fstp %st(1)
+; X86-GISEL-NEXT: retl
+;
+; X64-LABEL: cmove_cmp:
+; X64: # %bb.0:
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: testl %edi, %edi
+; X64-NEXT: fadd %st(1), %st
+; X64-NEXT: fxch %st(1)
+; X64-NEXT: fcmove %st(1), %st
+; X64-NEXT: fstp %st(1)
+; X64-NEXT: retq
+;
+; X64-GISEL-LABEL: cmove_cmp:
+; X64-GISEL: # %bb.0:
+; X64-GISEL-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-GISEL-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-GISEL-NEXT: xorl %eax, %eax
+; X64-GISEL-NEXT: cmpl $0, %edi
+; X64-GISEL-NEXT: sete %al
+; X64-GISEL-NEXT: fadd %st, %st(1)
+; X64-GISEL-NEXT: andl $1, %eax
+; X64-GISEL-NEXT: testl %eax, %eax
+; X64-GISEL-NEXT: fxch %st(1)
+; X64-GISEL-NEXT: fcmove %st(1), %st
+; X64-GISEL-NEXT: fstp %st(1)
+; X64-GISEL-NEXT: retq
+ %test = icmp eq i32 %c, 0
+ %add = fadd x86_fp80 %a, %b
+ %ret = select i1 %test, x86_fp80 %add, x86_fp80 %b
+ ret x86_fp80 %ret
+}
+
+define x86_fp80 @cmove_arg(x86_fp80 %a, x86_fp80 %b, i1 %test) {
+; X86-LABEL: cmove_arg:
+; X86: # %bb.0:
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fadd %st(1), %st
+; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
+; X86-NEXT: fxch %st(1)
+; X86-NEXT: fcmovne %st(1), %st
+; X86-NEXT: fstp %st(1)
+; X86-NEXT: retl
+;
+; X86-GISEL-LABEL: cmove_arg:
+; X86-GISEL: # %bb.0:
+; X86-GISEL-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: fadd %st, %st(1)
+; X86-GISEL-NEXT: movl $1, %eax
+; X86-GISEL-NEXT: andl {{[0-9]+}}(%esp), %eax
+; X86-GISEL-NEXT: testl %eax, %eax
+; X86-GISEL-NEXT: fxch %st(1)
+; X86-GISEL-NEXT: fcmove %st(1), %st
+; X86-GISEL-NEXT: fstp %st(1)
+; X86-GISEL-NEXT: retl
+;
+; X64-LABEL: cmove_arg:
+; X64: # %bb.0:
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: fadd %st(1), %st
+; X64-NEXT: testb $1, %dil
+; X64-NEXT: fxch %st(1)
+; X64-NEXT: fcmovne %st(1), %st
+; X64-NEXT: fstp %st(1)
+; X64-NEXT: retq
+;
+; X64-GISEL-LABEL: cmove_arg:
+; X64-GISEL: # %bb.0:
+; X64-GISEL-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-GISEL-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-GISEL-NEXT: fadd %st, %st(1)
+; X64-GISEL-NEXT: andl $1, %edi
+; X64-GISEL-NEXT: testl %edi, %edi
+; X64-GISEL-NEXT: fxch %st(1)
+; X64-GISEL-NEXT: fcmove %st(1), %st
+; X64-GISEL-NEXT: fstp %st(1)
+; X64-GISEL-NEXT: retq
+ %add = fadd x86_fp80 %a, %b
+ %ret = select i1 %test, x86_fp80 %add, x86_fp80 %b
+ ret x86_fp80 %ret
+}
+
+define x86_fp80 @cmove_load(x86_fp80 %a, x86_fp80 %b, ptr %p) {
+; X86-LABEL: cmove_load:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fadd %st(1), %st
+; X86-NEXT: cmpb $0, (%eax)
+; X86-NEXT: fxch %st(1)
+; X86-NEXT: fcmovne %st(1), %st
+; X86-NEXT: fstp %st(1)
+; X86-NEXT: retl
+;
+; X86-GISEL-LABEL: cmove_load:
+; X86-GISEL: # %bb.0:
+; X86-GISEL-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-GISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-GISEL-NEXT: fadd %st, %st(1)
+; X86-GISEL-NEXT: movzbl (%eax), %eax
+; X86-GISEL-NEXT: andl $1, %eax
+; X86-GISEL-NEXT: testl %eax, %eax
+; X86-GISEL-NEXT: fxch %st(1)
+; X86-GISEL-NEXT: fcmove %st(1), %st
+; X86-GISEL-NEXT: fstp %st(1)
+; X86-GISEL-NEXT: retl
+;
+; X64-LABEL: cmove_load:
+; X64: # %bb.0:
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: fadd %st(1), %st
+; X64-NEXT: cmpb $0, (%rdi)
+; X64-NEXT: fxch %st(1)
+; X64-NEXT: fcmovne %st(1), %st
+; X64-NEXT: fstp %st(1)
+; X64-NEXT: retq
+;
+; X64-GISEL-LABEL: cmove_load:
+; X64-GISEL: # %bb.0:
+; X64-GISEL-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-GISEL-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-GISEL-NEXT: fadd %st, %st(1)
+; X64-GISEL-NEXT: movzbl (%rdi), %eax
+; X64-GISEL-NEXT: andl $1, %eax
+; X64-GISEL-NEXT: testl %eax, %eax
+; X64-GISEL-NEXT: fxch %st(1)
+; X64-GISEL-NEXT: fcmove %st(1), %st
+; X64-GISEL-NEXT: fstp %st(1)
+; X64-GISEL-NEXT: retq
+ %test = load i1, ptr %p
+ %add = fadd x86_fp80 %a, %b
+ %ret = select i1 %test, x86_fp80 %add, x86_fp80 %b
+ ret x86_fp80 %ret
+}
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
index 3279a50..7a08f3e 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
@@ -624,6 +624,52 @@ define void @PR48908(<4 x double> %v0, <4 x double> %v1, <4 x double> %v2, ptr n
ret void
}
+define i32 @PR164107(<16 x i1> %0) {
+; AVX1-LABEL: PR164107:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0
+; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
+; AVX1-NEXT: vpmovsxwq %xmm0, %xmm0
+; AVX1-NEXT: vmovd %xmm0, %eax
+; AVX1-NEXT: ret{{[l|q]}}
+;
+; AVX2-LABEL: PR164107:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
+; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0
+; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0
+; AVX2-NEXT: vpmovsxwq %xmm0, %ymm0
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vmovd %xmm0, %eax
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: ret{{[l|q]}}
+;
+; AVX512-LABEL: PR164107:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
+; AVX512-NEXT: vpslld $31, %zmm0, %zmm0
+; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vpternlogq {{.*#+}} zmm0 {%k1} {z} = -1
+; AVX512-NEXT: vpbroadcastq %xmm0, %zmm0
+; AVX512-NEXT: vptestmq %zmm0, %zmm0, %k1
+; AVX512-NEXT: vpternlogq {{.*#+}} zmm0 {%k1} {z} = -1
+; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm0
+; AVX512-NEXT: vpbroadcastw %xmm0, %xmm0
+; AVX512-NEXT: vpmovsxwq %xmm0, %zmm0
+; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm0
+; AVX512-NEXT: vmovd %xmm0, %eax
+; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: ret{{[l|q]}}
+ %cmp = shufflevector <16 x i1> %0, <16 x i1> zeroinitializer, <16 x i32> zeroinitializer
+ %sext = sext <16 x i1> %cmp to <16 x i64>
+ %bc.1 = bitcast <16 x i64> %sext to <64 x i16>
+ %vecinit15.i = shufflevector <64 x i16> %bc.1, <64 x i16> zeroinitializer, <16 x i32> <i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56>
+ %conv16.i = sext <16 x i16> %vecinit15.i to <16 x i64>
+ %bc.2 = bitcast <16 x i64> %conv16.i to <32 x i32>
+ %conv22.i = extractelement <32 x i32> %bc.2, i64 4
+ ret i32 %conv22.i
+}
+
define <4 x i64> @concat_self_v4i64(<2 x i64> %x) {
; AVX1-LABEL: concat_self_v4i64:
; AVX1: # %bb.0: