diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll (renamed from llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll) | 374 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/mad_int24.ll | 313 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/mad_uint24.ll | 1492 | ||||
| -rw-r--r-- | llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags_V1.ll | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/DirectX/ContainerData/RootSignature-StaticSamplers-Invalid-Flag_V1.ll | 19 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll | 36 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll | 48 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/saturating-truncation.ll | 87 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll | 11 |
9 files changed, 2177 insertions, 221 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll index 2ad6e68..f730199 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll @@ -70,7 +70,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_def() { define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: [[DEF:%.*]] = call i64 asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -118,7 +118,7 @@ define amdgpu_kernel void @kernel_uses_asm_physreg() { define amdgpu_kernel void @kernel_uses_asm_physreg_tuple() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_tuple( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR2]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -154,7 +154,7 @@ define void @func_uses_asm_physreg_agpr() { define void @func_uses_asm_physreg_agpr_tuple() { ; CHECK-LABEL: define void @func_uses_asm_physreg_agpr_tuple( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR2]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -168,7 +168,7 @@ declare void @unknown() define amdgpu_kernel void @kernel_calls_extern() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR3:[0-9]+]] { ; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -180,8 +180,8 @@ define amdgpu_kernel void @kernel_calls_extern() { define amdgpu_kernel void @kernel_calls_extern_marked_callsite() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern_marked_callsite( -; CHECK-SAME: ) #[[ATTR1]] { -; CHECK-NEXT: call void @unknown() #[[ATTR10:[0-9]+]] +; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-NEXT: call void @unknown() #[[ATTR29:[0-9]+]] ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; @@ -192,7 +192,7 @@ define amdgpu_kernel void @kernel_calls_extern_marked_callsite() { define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect( -; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR1]] { +; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: call void [[INDIRECT]]() ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -204,8 +204,8 @@ define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) { define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(ptr %indirect) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect_marked_callsite( -; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR10]] +; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR29]] ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; @@ -316,7 +316,7 @@ define amdgpu_kernel void @kernel_calls_workitem_id_x(ptr addrspace(1) %out) { define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) { ; CHECK-LABEL: define amdgpu_kernel void @indirect_calls_none_agpr( -; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR1]] { +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty ; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] @@ -342,7 +342,7 @@ define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) { define amdgpu_kernel void @kernel_uses_asm_virtreg_def_struct_0() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_struct_0( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR2]] { ; CHECK-NEXT: [[DEF:%.*]] = call { i32, i32 } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -354,7 +354,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_def_struct_0() { define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_1() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_1( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR5:[0-9]+]] { ; CHECK-NEXT: [[DEF:%.*]] = call { i32, <2 x i32> } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -378,7 +378,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_use_struct_2() { define amdgpu_kernel void @kernel_uses_asm_virtreg_ptr_ty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_ptr_ty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR2]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -390,7 +390,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_ptr_ty() { define amdgpu_kernel void @kernel_uses_asm_virtreg_def_ptr_ty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_ptr_ty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR2]] { ; CHECK-NEXT: [[DEF:%.*]] = call ptr asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -402,7 +402,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_def_ptr_ty() { define amdgpu_kernel void @kernel_uses_asm_virtreg_def_vector_ptr_ty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_vector_ptr_ty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR5]] { ; CHECK-NEXT: [[DEF:%.*]] = call <2 x ptr> asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -414,7 +414,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_def_vector_ptr_ty() { define amdgpu_kernel void @kernel_uses_asm_physreg_def_struct_0() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_def_struct_0( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR6:[0-9]+]] { ; CHECK-NEXT: [[DEF:%.*]] = call { i32, i32 } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -426,7 +426,7 @@ define amdgpu_kernel void @kernel_uses_asm_physreg_def_struct_0() { define amdgpu_kernel void @kernel_uses_asm_clobber() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR7:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -438,7 +438,7 @@ define amdgpu_kernel void @kernel_uses_asm_clobber() { define amdgpu_kernel void @kernel_uses_asm_clobber_tuple() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber_tuple( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR8:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -450,7 +450,7 @@ define amdgpu_kernel void @kernel_uses_asm_clobber_tuple() { define amdgpu_kernel void @kernel_uses_asm_clobber_oob() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber_oob( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR9:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -462,7 +462,7 @@ define amdgpu_kernel void @kernel_uses_asm_clobber_oob() { define amdgpu_kernel void @kernel_uses_asm_clobber_max() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_clobber_max( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR9]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -474,7 +474,7 @@ define amdgpu_kernel void @kernel_uses_asm_clobber_max() { define amdgpu_kernel void @kernel_uses_asm_physreg_oob() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_oob( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR9]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -486,7 +486,7 @@ define amdgpu_kernel void @kernel_uses_asm_physreg_oob() { define amdgpu_kernel void @kernel_uses_asm_virtreg_def_max_ty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def_max_ty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR10:[0-9]+]] { ; CHECK-NEXT: [[DEF:%.*]] = call <32 x i32> asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -498,7 +498,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_def_max_ty() { define amdgpu_kernel void @kernel_uses_asm_virtreg_use_max_ty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_max_ty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR10]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -510,7 +510,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_use_max_ty() { define amdgpu_kernel void @kernel_uses_asm_virtreg_use_def_max_ty() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_use_def_max_ty( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR10]] { ; CHECK-NEXT: [[DEF:%.*]] = call <32 x i32> asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -522,7 +522,7 @@ define amdgpu_kernel void @kernel_uses_asm_virtreg_use_def_max_ty() { define amdgpu_kernel void @vreg_use_exceeds_register_file() { ; CHECK-LABEL: define amdgpu_kernel void @vreg_use_exceeds_register_file( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR9]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -534,7 +534,7 @@ define amdgpu_kernel void @vreg_use_exceeds_register_file() { define amdgpu_kernel void @vreg_def_exceeds_register_file() { ; CHECK-LABEL: define amdgpu_kernel void @vreg_def_exceeds_register_file( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR9]] { ; CHECK-NEXT: [[DEF:%.*]] = call <257 x i32> asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -546,7 +546,7 @@ define amdgpu_kernel void @vreg_def_exceeds_register_file() { define amdgpu_kernel void @multiple() { ; CHECK-LABEL: define amdgpu_kernel void @multiple( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR10]] { ; CHECK-NEXT: [[DEF:%.*]] = call { <16 x i32>, <8 x i32>, <8 x i32> } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -558,7 +558,7 @@ define amdgpu_kernel void @multiple() { define amdgpu_kernel void @earlyclobber_0() { ; CHECK-LABEL: define amdgpu_kernel void @earlyclobber_0( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR11:[0-9]+]] { ; CHECK-NEXT: [[DEF:%.*]] = call <8 x i32> asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -570,7 +570,7 @@ define amdgpu_kernel void @earlyclobber_0() { define amdgpu_kernel void @earlyclobber_1() { ; CHECK-LABEL: define amdgpu_kernel void @earlyclobber_1( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR12:[0-9]+]] { ; CHECK-NEXT: [[DEF:%.*]] = call { <8 x i32>, <16 x i32> } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -582,7 +582,7 @@ define amdgpu_kernel void @earlyclobber_1() { define amdgpu_kernel void @physreg_a32__vreg_a256__vreg_a512() { ; CHECK-LABEL: define amdgpu_kernel void @physreg_a32__vreg_a256__vreg_a512( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR13:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -594,7 +594,7 @@ define amdgpu_kernel void @physreg_a32__vreg_a256__vreg_a512() { define amdgpu_kernel void @physreg_def_a32__def_vreg_a256__def_vreg_a512() { ; CHECK-LABEL: define amdgpu_kernel void @physreg_def_a32__def_vreg_a256__def_vreg_a512( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR13]] { ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, <8 x i32>, <16 x i32> } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -606,7 +606,7 @@ define amdgpu_kernel void @physreg_def_a32__def_vreg_a256__def_vreg_a512() { define amdgpu_kernel void @physreg_def_a32___def_vreg_a512_use_vreg_a256() { ; CHECK-LABEL: define amdgpu_kernel void @physreg_def_a32___def_vreg_a512_use_vreg_a256( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR14:[0-9]+]] { ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, <16 x i32> } asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -618,7 +618,7 @@ define amdgpu_kernel void @physreg_def_a32___def_vreg_a512_use_vreg_a256() { define amdgpu_kernel void @mixed_physreg_vreg_tuples_0() { ; CHECK-LABEL: define amdgpu_kernel void @mixed_physreg_vreg_tuples_0( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR11]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -630,7 +630,7 @@ define amdgpu_kernel void @mixed_physreg_vreg_tuples_0() { define amdgpu_kernel void @mixed_physreg_vreg_tuples_1() { ; CHECK-LABEL: define amdgpu_kernel void @mixed_physreg_vreg_tuples_1( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR15:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -642,7 +642,7 @@ define amdgpu_kernel void @mixed_physreg_vreg_tuples_1() { define amdgpu_kernel void @physreg_raises_limit() { ; CHECK-LABEL: define amdgpu_kernel void @physreg_raises_limit( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR16:[0-9]+]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -652,10 +652,9 @@ define amdgpu_kernel void @physreg_raises_limit() { ret void } -; FIXME: This should require 9. We cannot allocate an a128 at a0. define amdgpu_kernel void @physreg_tuple_alignment_raises_limit() { ; CHECK-LABEL: define amdgpu_kernel void @physreg_tuple_alignment_raises_limit( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR11]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -667,7 +666,7 @@ define amdgpu_kernel void @physreg_tuple_alignment_raises_limit() { define amdgpu_kernel void @align3_virtreg() { ; CHECK-LABEL: define amdgpu_kernel void @align3_virtreg( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR6]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -679,7 +678,7 @@ define amdgpu_kernel void @align3_virtreg() { define amdgpu_kernel void @align3_align4_virtreg() { ; CHECK-LABEL: define amdgpu_kernel void @align3_align4_virtreg( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR15]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -691,7 +690,7 @@ define amdgpu_kernel void @align3_align4_virtreg() { define amdgpu_kernel void @align2_align4_virtreg() { ; CHECK-LABEL: define amdgpu_kernel void @align2_align4_virtreg( -; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-SAME: ) #[[ATTR15]] { ; CHECK-NEXT: call void asm sideeffect " ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void @@ -703,7 +702,7 @@ define amdgpu_kernel void @align2_align4_virtreg() { define amdgpu_kernel void @kernel_uses_write_register_a55() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_a55( -; CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +; CHECK-SAME: ) #[[ATTR17:[0-9]+]] { ; CHECK-NEXT: call void @llvm.write_register.i32(metadata [[META0:![0-9]+]], i32 0) ; CHECK-NEXT: ret void ; @@ -713,71 +712,313 @@ define amdgpu_kernel void @kernel_uses_write_register_a55() { define amdgpu_kernel void @kernel_uses_write_register_v55() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_v55( -; CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: call void @llvm.write_register.i32(metadata [[META1:![0-9]+]], i32 0) +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @llvm.write_register.i64(metadata !1, i32 0) + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_write_register_a55_57() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_a55_57( -; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-SAME: ) #[[ATTR18:[0-9]+]] { ; CHECK-NEXT: call void @llvm.write_register.i96(metadata [[META2:![0-9]+]], i96 0) +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @llvm.write_register.i64(metadata !2, i96 0) + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_read_register_a55(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_read_register_a55( -; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR19:[0-9]+]] { ; CHECK-NEXT: [[REG:%.*]] = call i32 @llvm.read_register.i32(metadata [[META0]]) ; CHECK-NEXT: store i32 [[REG]], ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %reg = call i32 @llvm.read_register.i64(metadata !0) store i32 %reg, ptr addrspace(1) %ptr + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_read_volatile_register_a55(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_read_volatile_register_a55( -; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR19]] { ; CHECK-NEXT: [[REG:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META0]]) ; CHECK-NEXT: store i32 [[REG]], ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %reg = call i32 @llvm.read_volatile_register.i64(metadata !0) store i32 %reg, ptr addrspace(1) %ptr + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_read_register_a56_59(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_read_register_a56_59( -; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR3]] { +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR20:[0-9]+]] { ; CHECK-NEXT: [[REG:%.*]] = call i128 @llvm.read_register.i128(metadata [[META3:![0-9]+]]) ; CHECK-NEXT: store i128 [[REG]], ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; %reg = call i128 @llvm.read_register.i64(metadata !3) store i128 %reg, ptr addrspace(1) %ptr + call void @use_most() ret void } define amdgpu_kernel void @kernel_uses_write_register_out_of_bounds_a256() { ; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_write_register_out_of_bounds_a256( -; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-SAME: ) #[[ATTR9]] { ; CHECK-NEXT: call void @llvm.write_register.i32(metadata [[META4:![0-9]+]], i32 0) +; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; call void @llvm.write_register.i64(metadata !4, i32 0) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_multiple_uses() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_multiple_uses( +; CHECK-SAME: ) #[[ATTR5]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(i64 poison) + call void asm sideeffect "; use $0", "a"(i32 poison) + call void asm sideeffect "; use $0", "a"(i128 poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_multiple_defs() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_multiple_defs( +; CHECK-SAME: ) #[[ATTR5]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i64 asm sideeffect " +; CHECK-NEXT: [[TMP2:%.*]] = call i32 asm sideeffect " +; CHECK-NEXT: [[TMP3:%.*]] = call i128 asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call i64 asm sideeffect "; def $0", "=a"() + call i32 asm sideeffect "; def $0", "=a"() + call i128 asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_multiple_use_defs() { +; CHECK-LABEL: define amdgpu_kernel void @kernel_multiple_use_defs( +; CHECK-SAME: ) #[[ATTR5]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: [[TMP1:%.*]] = call i128 asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(i32 poison) + call i128 asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define void @callgraph_b() { +; CHECK-LABEL: define void @callgraph_b( +; CHECK-SAME: ) #[[ATTR15]] { +; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call <4 x i32> asm sideeffect "; def $0", "=a"() + call void asm sideeffect "; use $0", "a"(<8 x i32> poison) + call void @use_most() + ret void +} + +define void @callgraph_c() { +; CHECK-LABEL: define void @callgraph_c( +; CHECK-SAME: ) #[[ATTR2]] { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call i32 asm sideeffect "; def $0", "=a"() + call void asm sideeffect "; use $0", "a"(<2 x i32> poison) + call void @use_most() + ret void +} + +define void @callgraph_a(i1 %cond) { +; CHECK-LABEL: define void @callgraph_a( +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR15]] { +; CHECK-NEXT: br i1 [[COND]], label [[A:%.*]], label [[B:%.*]] +; CHECK: a: +; CHECK-NEXT: call void @callgraph_b() +; CHECK-NEXT: ret void +; CHECK: b: +; CHECK-NEXT: call void @callgraph_c() +; CHECK-NEXT: ret void +; + br i1 %cond, label %a, label %b + +a: + call void @callgraph_b() + ret void + +b: + call void @callgraph_c() + ret void +} + + +define void @kernel_max_callgraph(i1 %cond) { +; CHECK-LABEL: define void @kernel_max_callgraph( +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR15]] { +; CHECK-NEXT: call void @callgraph_a(i1 [[COND]]) +; CHECK-NEXT: ret void +; + call void @callgraph_a(i1 %cond) + ret void +} + +define amdgpu_kernel void @kernel_uses_all_virtregs() #1 { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_all_virtregs( +; CHECK-SAME: ) #[[ATTR21:[0-9]+]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a,a,a,a,a,a,a,a"(<32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison) + call void @use_most() + ret void +} + +define amdgpu_kernel void @kernel_uses_all_virtregs_plus_1() #1 { +; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_all_virtregs_plus_1( +; CHECK-SAME: ) #[[ATTR21]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a,a,a,a,a,a,a,a,a"(<32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, <32 x i32> poison, i32 poison) + call void @use_most() + ret void +} + +define void @recursive() { +; CHECK-LABEL: define void @recursive( +; CHECK-SAME: ) #[[ATTR22:[0-9]+]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: call void @recursive() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(<7 x i32> poison) + call void @use_most() + call void @recursive() + ret void +} + +define void @indirect_0() { +; CHECK-LABEL: define void @indirect_0( +; CHECK-SAME: ) #[[ATTR22]] { +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void asm sideeffect "; use $0", "a"(<7 x i32> poison) + call void @use_most() + ret void +} + +define void @indirect_1() { +; CHECK-LABEL: define void @indirect_1( +; CHECK-SAME: ) #[[ATTR23:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i32> asm sideeffect " +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call <3 x i32> asm sideeffect "; def $0", "=a"() + call void @use_most() + ret void +} + +define amdgpu_kernel void @knowable_indirect_call(i1 %cond) { +; CHECK-LABEL: define amdgpu_kernel void @knowable_indirect_call( +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR22]] { +; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @indirect_0, ptr @indirect_1 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @indirect_1 +; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] +; CHECK: 2: +; CHECK-NEXT: call void @indirect_1() +; CHECK-NEXT: br label [[TMP6:%.*]] +; CHECK: 3: +; CHECK-NEXT: br i1 true, label [[TMP4:%.*]], label [[TMP5:%.*]] +; CHECK: 4: +; CHECK-NEXT: call void @indirect_0() +; CHECK-NEXT: br label [[TMP6]] +; CHECK: 5: +; CHECK-NEXT: unreachable +; CHECK: 6: +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + %fptr = select i1 %cond, ptr @indirect_0, ptr @indirect_1 + call void %fptr() + call void @use_most() + ret void +} + +define amdgpu_kernel void @calls_poison(i1 %cond) { +; CHECK-LABEL: define amdgpu_kernel void @calls_poison( +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: call void poison() +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void poison() + call void @use_most() + ret void +} + +define amdgpu_kernel void @calls_null(i1 %cond) { +; CHECK-LABEL: define amdgpu_kernel void @calls_null( +; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: call void null() +; CHECK-NEXT: call void @use_most() +; CHECK-NEXT: ret void +; + call void null() + call void @use_most() + ret void +} + +define amdgpu_kernel void @indirect_unknown(ptr %fptr) { +; CHECK-LABEL: define amdgpu_kernel void @indirect_unknown( +; CHECK-SAME: ptr [[FPTR:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: call void [[FPTR]]() +; CHECK-NEXT: ret void +; + call void %fptr() ret void } attributes #0 = { "amdgpu-agpr-alloc"="0" } +attributes #1 = { "amdgpu-waves-per-eu"="1,1" } !0 = !{!"a55"} !1 = !{!"v55"} @@ -787,16 +1028,35 @@ attributes #0 = { "amdgpu-agpr-alloc"="0" } ;. ; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR2:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(read) "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR8:[0-9]+]] = { nounwind "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR9:[0-9]+]] = { nocallback nounwind "target-cpu"="gfx90a" } -; CHECK: attributes #[[ATTR10]] = { "amdgpu-agpr-alloc"="0" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="1" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="2" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR3]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="4" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="6" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR7]] = { "amdgpu-agpr-alloc"="5" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR8]] = { "amdgpu-agpr-alloc"="14" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR9]] = { "amdgpu-agpr-alloc"="256" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR10]] = { "amdgpu-agpr-alloc"="32" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR11]] = { "amdgpu-agpr-alloc"="9" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR12]] = { "amdgpu-agpr-alloc"="64" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR13]] = { "amdgpu-agpr-alloc"="49" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR14]] = { "amdgpu-agpr-alloc"="33" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR15]] = { "amdgpu-agpr-alloc"="8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR16]] = { "amdgpu-agpr-alloc"="13" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR17]] = { "amdgpu-agpr-alloc"="56" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR18]] = { "amdgpu-agpr-alloc"="58" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR19]] = { "amdgpu-agpr-alloc"="56" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR20]] = { "amdgpu-agpr-alloc"="60" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR21]] = { "amdgpu-agpr-alloc"="256" "amdgpu-waves-per-eu"="1,1" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR22]] = { "amdgpu-agpr-alloc"="7" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR23]] = { "amdgpu-agpr-alloc"="3" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR24:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR25:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR26:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(read) "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR27:[0-9]+]] = { nounwind "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR28:[0-9]+]] = { nocallback nounwind "target-cpu"="gfx90a" } +; CHECK: attributes #[[ATTR29]] = { "amdgpu-agpr-alloc"="0" } ;. ; CHECK: [[META0]] = !{!"a55"} ; CHECK: [[META1]] = !{!"v55"} diff --git a/llvm/test/CodeGen/AMDGPU/mad_int24.ll b/llvm/test/CodeGen/AMDGPU/mad_int24.ll index 93fda94..dd88310 100644 --- a/llvm/test/CodeGen/AMDGPU/mad_int24.ll +++ b/llvm/test/CodeGen/AMDGPU/mad_int24.ll @@ -1,17 +1,79 @@ -; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefix=GCN --check-prefix=FUNC -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefix=GCN --check-prefix=FUNC -; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=amdgcn| FileCheck %s --check-prefixes=GCN +; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=VI +; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG,R600,RW +; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=EG,R600,CM -; FUNC-LABEL: {{^}}i32_mad24: ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. -; EG: MULLO_INT -; CM: MULLO_INT -; GCN: s_bfe_i32 -; GCN: s_bfe_i32 -; GCN: s_mul_i32 -; GCN: s_add_i32 define amdgpu_kernel void @i32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) { +; GCN-LABEL: i32_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000 +; GCN-NEXT: s_bfe_i32 s1, s1, 0x180000 +; GCN-NEXT: s_mul_i32 s0, s0, s1 +; GCN-NEXT: s_add_i32 s0, s0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: i32_mad24: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_bfe_i32 s0, s0, 0x180000 +; VI-NEXT: s_bfe_i32 s1, s1, 0x180000 +; VI-NEXT: s_mul_i32 s0, s0, s1 +; VI-NEXT: s_add_i32 s0, s0, s2 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; VI-NEXT: s_endpgm +; +; RW-LABEL: i32_mad24: +; RW: ; %bb.0: ; %entry +; RW-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] +; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; RW-NEXT: CF_END +; RW-NEXT: PAD +; RW-NEXT: ALU clause starting at 4: +; RW-NEXT: LSHL T0.W, KC0[2].Z, literal.x, +; RW-NEXT: LSHL * T1.W, KC0[2].W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR T1.W, PS, literal.x, +; RW-NEXT: ASHR * T0.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PS, PV.W, +; RW-NEXT: ADD_INT T0.X, PS, KC0[3].X, +; RW-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: i32_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHL T0.Z, KC0[2].Z, literal.x, +; CM-NEXT: LSHL * T0.W, KC0[2].W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR T1.Z, PV.W, literal.x, +; CM-NEXT: ASHR * T0.W, PV.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z, +; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) entry: %0 = shl i32 %a, 8 %a_24 = ashr i32 %0, 8 @@ -23,13 +85,25 @@ entry: ret void } -; GCN-LABEL: {{^}}mad24_known_bits_destroyed: -; GCN: s_waitcnt -; GCN-NEXT: v_mad_i32_i24 -; GCN-NEXT: v_mul_i32_i24 -; GCN-NEXT: s_setpc_b64 define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { - +; GCN-LABEL: mad24_known_bits_destroyed: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mad24_known_bits_destroyed: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: mad24_known_bits_destroyed: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD %shl.0 = shl i32 %a, 8 %sra.0 = ashr i32 %shl.0, 8 %shl.1 = shl i32 %b, 8 @@ -48,12 +122,25 @@ define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { ret i32 %mul1 } -; GCN-LABEL: {{^}}mad24_intrin_known_bits_destroyed: -; GCN: s_waitcnt -; GCN-NEXT: v_mad_i32_i24 -; GCN-NEXT: v_mul_i32_i24 -; GCN-NEXT: s_setpc_b64 define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { +; GCN-LABEL: mad24_intrin_known_bits_destroyed: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mad24_intrin_known_bits_destroyed: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2 +; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: mad24_intrin_known_bits_destroyed: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD %shl.0 = shl i32 %a, 8 %sra.0 = ashr i32 %shl.0, 8 %shl.1 = shl i32 %b, 8 @@ -73,17 +160,177 @@ define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) { } ; Make sure no unnecessary BFEs are emitted in the loop. -; GCN-LABEL: {{^}}mad24_destroyed_knownbits_2: -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe -; GCN: v_mad_i32_i24 -; GCN-NOT: v_bfe define void @mad24_destroyed_knownbits_2(i32 %arg, i32 %arg1, i32 %arg2, ptr addrspace(1) %arg3) { +; GCN-LABEL: mad24_destroyed_knownbits_2: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, 1 +; GCN-NEXT: s_mov_b64 s[4:5], 0 +; GCN-NEXT: .LBB3_1: ; %bb6 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v5 +; GCN-NEXT: v_add_i32_e32 v1, vcc, -1, v1 +; GCN-NEXT: v_mad_i32_i24 v5, v0, v5, v0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GCN-NEXT: v_mad_i32_i24 v0, v5, v0, v5 +; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v0 +; GCN-NEXT: v_mov_b32_e32 v5, v2 +; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GCN-NEXT: s_cbranch_execnz .LBB3_1 +; GCN-NEXT: ; %bb.2: ; %bb5 +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: mad24_destroyed_knownbits_2: +; VI: ; %bb.0: ; %bb +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 1 +; VI-NEXT: s_mov_b64 s[4:5], 0 +; VI-NEXT: .LBB3_1: ; %bb6 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v5 +; VI-NEXT: v_mad_i32_i24 v5, v0, v5, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v1 +; VI-NEXT: v_mad_i32_i24 v0, v5, v0, v5 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v0 +; VI-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; VI-NEXT: v_mov_b32_e32 v5, v2 +; VI-NEXT: s_andn2_b64 exec, exec, s[4:5] +; VI-NEXT: s_cbranch_execnz .LBB3_1 +; VI-NEXT: ; %bb.2: ; %bb5 +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[3:4], v0 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; RW-LABEL: mad24_destroyed_knownbits_2: +; RW: ; %bb.0: ; %bb +; RW-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; RW-NEXT: LOOP_START_DX10 @7 +; RW-NEXT: ALU_PUSH_BEFORE 30, @16, KC0[], KC1[] +; RW-NEXT: JUMP @6 POP:1 +; RW-NEXT: LOOP_BREAK @6 +; RW-NEXT: POP @6 POP:1 +; RW-NEXT: END_LOOP @2 +; RW-NEXT: ALU 1, @47, KC0[], KC1[] +; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; RW-NEXT: CF_END +; RW-NEXT: ALU clause starting at 10: +; RW-NEXT: MOV T0.X, KC0[2].Y, +; RW-NEXT: MOV T0.Y, KC0[2].Z, +; RW-NEXT: MOV * T0.Z, KC0[2].W, +; RW-NEXT: MOV T0.W, KC0[3].X, +; RW-NEXT: MOV * T1.W, literal.x, +; RW-NEXT: 1(1.401298e-45), 0(0.000000e+00) +; RW-NEXT: ALU clause starting at 16: +; RW-NEXT: LSHL T2.W, T1.W, literal.x, +; RW-NEXT: LSHL * T3.W, T0.X, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR T3.W, PS, literal.x, +; RW-NEXT: ASHR * T2.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PV.W, PS, +; RW-NEXT: ADD_INT * T1.W, PS, T1.W, +; RW-NEXT: LSHL * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W, +; RW-NEXT: ADD_INT * T1.W, PS, T1.W, +; RW-NEXT: LSHL * T2.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR * T2.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: MULLO_INT * T0.X, PV.W, T3.W, +; RW-NEXT: ADD_INT * T1.W, PS, T1.W, +; RW-NEXT: LSHL * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ASHR * T3.W, PV.W, literal.x, +; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; RW-NEXT: ADD_INT T0.Y, T0.Y, literal.x, +; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W, +; RW-NEXT: -1(nan), 0(0.000000e+00) +; RW-NEXT: ADD_INT T0.X, PS, T1.W, +; RW-NEXT: SETE_INT T2.W, PV.Y, 0.0, +; RW-NEXT: MOV * T1.W, T0.Z, +; RW-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; RW-NEXT: ALU clause starting at 47: +; RW-NEXT: LSHR * T1.X, T0.W, literal.x, +; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: mad24_destroyed_knownbits_2: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @7 +; CM-NEXT: ALU_PUSH_BEFORE 41, @16, KC0[], KC1[] +; CM-NEXT: JUMP @6 POP:1 +; CM-NEXT: LOOP_BREAK @6 +; CM-NEXT: POP @6 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: ALU 1, @58, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T1.X, KC0[2].Y, +; CM-NEXT: MOV T0.X, KC0[2].Z, +; CM-NEXT: MOV T0.Y, KC0[2].W, +; CM-NEXT: MOV T0.Z, KC0[3].X, +; CM-NEXT: MOV * T0.W, literal.x, +; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: LSHL T1.Z, T0.W, literal.x, +; CM-NEXT: LSHL * T1.W, T1.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR T2.Z, PV.W, literal.x, +; CM-NEXT: ASHR * T1.W, PV.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T1.X, T2.Z, T1.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.Z, T1.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.Z, T1.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.Z, T1.W, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W, +; CM-NEXT: LSHL * T2.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR * T2.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W, +; CM-NEXT: LSHL * T1.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ASHR * T1.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T1.X, T1.W, T2.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T1.W, T2.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T1.W, T2.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T1.W, T2.W, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W, +; CM-NEXT: LSHL * T2.W, PV.W, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: ADD_INT T0.X, T0.X, literal.x, +; CM-NEXT: ASHR * T2.W, PV.W, literal.y, +; CM-NEXT: -1(nan), 8(1.121039e-44) +; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W, +; CM-NEXT: ADD_INT T1.X, PV.X, T0.W, +; CM-NEXT: SETE_INT T1.Z, T0.X, 0.0, +; CM-NEXT: MOV * T0.W, T0.Y, +; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.Z, 0.0, +; CM-NEXT: ALU clause starting at 58: +; CM-NEXT: LSHR * T0.X, T0.Z, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) bb: br label %bb6 @@ -119,3 +366,5 @@ bb6: ; preds = %bb6, %bb } declare i32 @llvm.amdgcn.mul.i24(i32, i32) +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; R600: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/mad_uint24.ll b/llvm/test/CodeGen/AMDGPU/mad_uint24.ll index a6d458e..46b8df4 100644 --- a/llvm/test/CodeGen/AMDGPU/mad_uint24.ll +++ b/llvm/test/CodeGen/AMDGPU/mad_uint24.ll @@ -1,19 +1,75 @@ -; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2 -; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG +; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=CM +; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefixes=GCN +; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX8,SI +; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX8,VI declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone -; FUNC-LABEL: {{^}}u32_mad24: -; EG: MULLO_INT -; SI: s_mul_i32 -; SI: s_add_i32 -; VI: s_mul_{{[iu]}}32 -; VI: s_add_{{[iu]}}32 - define amdgpu_kernel void @u32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) { +; EG-LABEL: u32_mad24: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x, +; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.X, PS, PV.W, +; EG-NEXT: ADD_INT T0.X, PS, KC0[3].X, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: u32_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: AND_INT T0.Z, KC0[2].W, literal.x, +; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z, +; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: u32_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s0, s0, 0xffffff +; GCN-NEXT: s_and_b32 s1, s1, 0xffffff +; GCN-NEXT: s_mul_i32 s0, s0, s1 +; GCN-NEXT: s_add_i32 s0, s0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: u32_mad24: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s0, s0, 0xffffff +; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff +; GFX8-NEXT: s_mul_i32 s0, s0, s1 +; GFX8-NEXT: s_add_i32 s0, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm entry: %0 = shl i32 %a, 8 %a_24 = lshr i32 %0, 8 @@ -25,18 +81,88 @@ entry: ret void } -; FUNC-LABEL: {{^}}i16_mad24: ; The order of A and B does not matter. -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] ; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 16 -; GCN: s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}} -; GCN: s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}} -; GCN: s_sext_i32_i16 [[EXT:s[0-9]]], [[MAD]] -; GCN: v_mov_b32_e32 v0, [[EXT]] define amdgpu_kernel void @i16_mad24(ptr addrspace(1) %out, i16 %a, i16 %b, i16 %c) { +; EG-LABEL: i16_mad24: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @12, KC0[], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 4, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_16 T1.X, T0.X, 40, #3 +; EG-NEXT: VTX_READ_16 T2.X, T0.X, 42, #3 +; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: MULLO_INT * T0.Y, T1.X, T2.X, +; EG-NEXT: ADD_INT * T0.W, PS, T0.X, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) +; +; CM-LABEL: i16_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 0, @12, KC0[], KC1[] +; CM-NEXT: TEX 2 @6 +; CM-NEXT: ALU 8, @13, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_16 T1.X, T0.X, 40, #3 +; CM-NEXT: VTX_READ_16 T2.X, T0.X, 42, #3 +; CM-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 13: +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Y, T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T1.X, T2.X, +; CM-NEXT: ADD_INT * T0.W, PV.Y, T0.X, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i16_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_load_dword s4, s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s2, 16 +; GCN-NEXT: s_mul_i32 s2, s4, s2 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_sext_i32_i16 s2, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: i16_mad24: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX8-NEXT: s_load_dword s8, s[4:5], 0x2c +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_mov_b32 s4, s0 +; GFX8-NEXT: s_lshr_b32 s0, s2, 16 +; GFX8-NEXT: s_mul_i32 s0, s8, s0 +; GFX8-NEXT: s_add_i32 s0, s0, s3 +; GFX8-NEXT: s_sext_i32_i16 s0, s0 +; GFX8-NEXT: s_mov_b32 s5, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm entry: %0 = mul i16 %a, %b %1 = add i16 %0, %c @@ -46,17 +172,85 @@ entry: } ; FIXME: Need to handle non-uniform case for function below (load without gep). -; FUNC-LABEL: {{^}}i8_mad24: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] ; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; GCN: s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}} -; GCN: s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}} -; GCN: s_sext_i32_i8 [[EXT:s[0-9]]], [[MAD]] -; GCN: v_mov_b32_e32 v0, [[EXT]] define amdgpu_kernel void @i8_mad24(ptr addrspace(1) %out, i8 %a, i8 %b, i8 %c) { +; EG-LABEL: i8_mad24: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 0, @12, KC0[], KC1[] +; EG-NEXT: TEX 2 @6 +; EG-NEXT: ALU 4, @13, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3 +; EG-NEXT: VTX_READ_8 T2.X, T0.X, 41, #3 +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 42, #3 +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 13: +; EG-NEXT: MULLO_INT * T0.Y, T1.X, T2.X, +; EG-NEXT: ADD_INT * T0.W, PS, T0.X, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) +; +; CM-LABEL: i8_mad24: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 0, @12, KC0[], KC1[] +; CM-NEXT: TEX 2 @6 +; CM-NEXT: ALU 8, @13, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3 +; CM-NEXT: VTX_READ_8 T2.X, T0.X, 41, #3 +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 42, #3 +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 13: +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Y, T1.X, T2.X, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.X, T2.X, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T1.X, T2.X, +; CM-NEXT: ADD_INT * T0.W, PV.Y, T0.X, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i8_mad24: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s2, s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s4, s2, 8 +; GCN-NEXT: s_lshr_b32 s5, s2, 16 +; GCN-NEXT: s_mul_i32 s2, s2, s4 +; GCN-NEXT: s_add_i32 s2, s2, s5 +; GCN-NEXT: s_sext_i32_i8 s4, s2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: i8_mad24: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dword s6, s[4:5], 0x2c +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s4, s6, 8 +; GFX8-NEXT: s_lshr_b32 s5, s6, 16 +; GFX8-NEXT: s_mul_i32 s4, s6, s4 +; GFX8-NEXT: s_add_i32 s4, s4, s5 +; GFX8-NEXT: s_sext_i32_i8 s4, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm entry: %0 = mul i8 %a, %b %1 = add i8 %0, %c @@ -72,11 +266,75 @@ entry: ; 24-bit mad pattern wasn't being matched. ; Check that the select instruction is not deleted. -; FUNC-LABEL: {{^}}i24_i32_i32_mad: -; EG: CNDE_INT -; SI: s_cselect -; GCN2: s_cselect define amdgpu_kernel void @i24_i32_i32_mad(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) { +; EG-LABEL: i24_i32_i32_mad: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: ASHR * T0.W, KC0[2].Z, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W, +; EG-NEXT: 34(4.764415e-44), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.X, PV.W, KC0[3].X, +; EG-NEXT: ADD_INT T0.X, PS, KC0[3].Y, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: i24_i32_i32_mad: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: ASHR * T0.W, KC0[2].Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W, +; CM-NEXT: 34(4.764415e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, KC0[3].X, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, KC0[3].X, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, KC0[3].X, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, KC0[3].X, +; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].Y, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i24_i32_i32_mad: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s2, s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s2, 8 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_cselect_b32 s2, s2, 34 +; GCN-NEXT: s_mul_i32 s2, s2, s6 +; GCN-NEXT: s_add_i32 s4, s2, s7 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: i24_i32_i32_mad: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dword s8, s[4:5], 0x2c +; GFX8-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_ashr_i32 s4, s8, 8 +; GFX8-NEXT: s_cmp_lg_u32 s6, 0 +; GFX8-NEXT: s_cselect_b32 s4, s4, 34 +; GFX8-NEXT: s_mul_i32 s4, s4, s6 +; GFX8-NEXT: s_add_i32 s4, s4, s7 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm entry: %0 = ashr i32 %a, 8 %1 = icmp ne i32 %c, 0 @@ -87,13 +345,139 @@ entry: ret void } -; FUNC-LABEL: {{^}}extra_and: -; SI-NOT: v_and -; SI: s_mul_i32 -; SI: s_mul_i32 -; SI: s_add_i32 -; SI: s_add_i32 define amdgpu_kernel void @extra_and(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) { +; EG-LABEL: extra_and: +; EG: ; %bb.0: ; %bb +; EG-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: LOOP_START_DX10 @7 +; EG-NEXT: ALU_PUSH_BEFORE 12, @16, KC0[], KC1[] +; EG-NEXT: JUMP @6 POP:1 +; EG-NEXT: LOOP_BREAK @6 +; EG-NEXT: POP @6 POP:1 +; EG-NEXT: END_LOOP @2 +; EG-NEXT: ALU 1, @29, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T1.W, literal.x, +; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; EG-NEXT: MOV * T3.W, PV.W, +; EG-NEXT: MOV T0.Z, KC0[2].Y, +; EG-NEXT: MOV T0.W, KC0[2].Z, +; EG-NEXT: MOV * T2.W, KC0[2].W, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: AND_INT T1.W, T1.W, literal.x, +; EG-NEXT: AND_INT * T4.W, T3.W, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: AND_INT T3.W, T3.W, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PS, PV.W, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W, +; EG-NEXT: ADD_INT T3.W, T2.W, PS, +; EG-NEXT: ADD_INT * T1.W, T0.W, T0.X, +; EG-NEXT: ADD_INT * T0.X, PS, PV.W, +; EG-NEXT: SETNE_INT * T4.W, PV.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; EG-NEXT: ALU clause starting at 29: +; EG-NEXT: LSHR * T1.X, T0.Z, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: extra_and: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @7 +; CM-NEXT: ALU_PUSH_BEFORE 17, @16, KC0[], KC1[] +; CM-NEXT: JUMP @6 POP:1 +; CM-NEXT: LOOP_BREAK @6 +; CM-NEXT: POP @6 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: ALU 1, @34, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T0.W, literal.x, +; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; CM-NEXT: MOV * T1.Z, PV.W, +; CM-NEXT: MOV T0.Y, KC0[2].Y, +; CM-NEXT: MOV T0.Z, KC0[2].Z, +; CM-NEXT: MOV * T1.W, KC0[2].W, +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: AND_INT T1.Y, T1.Z, literal.x, +; CM-NEXT: AND_INT T2.Z, T0.W, literal.x, +; CM-NEXT: AND_INT * T0.W, T1.Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT * T0.W, T1.Y, T2.Z, +; CM-NEXT: ADD_INT T1.Z, T1.W, PV.W, +; CM-NEXT: ADD_INT * T0.W, T0.Z, T0.X, +; CM-NEXT: ADD_INT * T0.X, PV.W, PV.Z, +; CM-NEXT: SETNE_INT * T2.W, PV.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; CM-NEXT: ALU clause starting at 34: +; CM-NEXT: LSHR * T1.X, T0.Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: extra_and: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s2, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: .LBB4_1: ; %bb4 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: s_and_b32 s3, s6, 0xffffff +; GCN-NEXT: s_and_b32 s6, s6, 0xffffff +; GCN-NEXT: s_and_b32 s2, s2, 0xffffff +; GCN-NEXT: s_mul_i32 s3, s3, s2 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s2, s0, s3 +; GCN-NEXT: s_add_i32 s6, s1, s6 +; GCN-NEXT: s_add_i32 s3, s2, s6 +; GCN-NEXT: s_cmp_lg_u32 s3, 8 +; GCN-NEXT: s_cbranch_scc1 .LBB4_1 +; GCN-NEXT: ; %bb.2: ; %bb18 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: extra_and: +; GFX8: ; %bb.0: ; %bb +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c +; GFX8-NEXT: s_mov_b32 s2, 0 +; GFX8-NEXT: s_mov_b32 s6, 0 +; GFX8-NEXT: .LBB4_1: ; %bb4 +; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX8-NEXT: s_and_b32 s3, s6, 0xffffff +; GFX8-NEXT: s_and_b32 s6, s6, 0xffffff +; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff +; GFX8-NEXT: s_mul_i32 s3, s3, s2 +; GFX8-NEXT: s_mul_i32 s6, s6, s2 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_add_i32 s2, s0, s3 +; GFX8-NEXT: s_add_i32 s6, s1, s6 +; GFX8-NEXT: s_add_i32 s3, s2, s6 +; GFX8-NEXT: s_cmp_lg_u32 s3, 8 +; GFX8-NEXT: s_cbranch_scc1 .LBB4_1 +; GFX8-NEXT: ; %bb.2: ; %bb18 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm bb: br label %bb4 @@ -119,13 +503,139 @@ bb18: ; preds = %bb4 ret void } -; FUNC-LABEL: {{^}}dont_remove_shift -; SI: s_lshr -; SI: s_mul_i32 -; SI: s_mul_i32 -; SI: s_add_i32 -; SI: s_add_i32 define amdgpu_kernel void @dont_remove_shift(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) { +; EG-LABEL: dont_remove_shift: +; EG: ; %bb.0: ; %bb +; EG-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; EG-NEXT: LOOP_START_DX10 @7 +; EG-NEXT: ALU_PUSH_BEFORE 12, @16, KC0[], KC1[] +; EG-NEXT: JUMP @6 POP:1 +; EG-NEXT: LOOP_BREAK @6 +; EG-NEXT: POP @6 POP:1 +; EG-NEXT: END_LOOP @2 +; EG-NEXT: ALU 1, @29, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 10: +; EG-NEXT: MOV * T1.W, literal.x, +; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; EG-NEXT: MOV * T3.W, PV.W, +; EG-NEXT: MOV T0.Z, KC0[2].Y, +; EG-NEXT: MOV T0.W, KC0[2].Z, +; EG-NEXT: MOV * T2.W, KC0[2].W, +; EG-NEXT: ALU clause starting at 16: +; EG-NEXT: LSHR T1.W, T1.W, literal.x, +; EG-NEXT: LSHR * T4.W, T3.W, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: LSHR T3.W, T3.W, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PS, PV.W, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W, +; EG-NEXT: ADD_INT T3.W, T2.W, PS, +; EG-NEXT: ADD_INT * T1.W, T0.W, T0.X, +; EG-NEXT: ADD_INT * T0.X, PS, PV.W, +; EG-NEXT: SETNE_INT * T4.W, PV.X, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; EG-NEXT: ALU clause starting at 29: +; EG-NEXT: LSHR * T1.X, T0.Z, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: dont_remove_shift: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @7 +; CM-NEXT: ALU_PUSH_BEFORE 17, @16, KC0[], KC1[] +; CM-NEXT: JUMP @6 POP:1 +; CM-NEXT: LOOP_BREAK @6 +; CM-NEXT: POP @6 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: ALU 1, @34, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 10: +; CM-NEXT: MOV * T0.W, literal.x, +; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00) +; CM-NEXT: MOV * T1.Z, PV.W, +; CM-NEXT: MOV T0.Y, KC0[2].Y, +; CM-NEXT: MOV T0.Z, KC0[2].Z, +; CM-NEXT: MOV * T1.W, KC0[2].W, +; CM-NEXT: ALU clause starting at 16: +; CM-NEXT: LSHR T1.Y, T1.Z, literal.x, +; CM-NEXT: LSHR T2.Z, T0.W, literal.x, +; CM-NEXT: LSHR * T0.W, T1.Z, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T2.Z, +; CM-NEXT: MULLO_INT T0.X (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.Y, T2.Z, +; CM-NEXT: MULLO_INT * T0.W, T1.Y, T2.Z, +; CM-NEXT: ADD_INT T1.Z, T1.W, PV.W, +; CM-NEXT: ADD_INT * T0.W, T0.Z, T0.X, +; CM-NEXT: ADD_INT * T0.X, PV.W, PV.Z, +; CM-NEXT: SETNE_INT * T2.W, PV.X, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; CM-NEXT: ALU clause starting at 34: +; CM-NEXT: LSHR * T1.X, T0.Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: dont_remove_shift: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s2, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: .LBB5_1: ; %bb4 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: s_lshr_b32 s3, s6, 8 +; GCN-NEXT: s_lshr_b32 s6, s6, 8 +; GCN-NEXT: s_lshr_b32 s2, s2, 8 +; GCN-NEXT: s_mul_i32 s3, s3, s2 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s2, s0, s3 +; GCN-NEXT: s_add_i32 s6, s1, s6 +; GCN-NEXT: s_add_i32 s3, s2, s6 +; GCN-NEXT: s_cmp_lg_u32 s3, 8 +; GCN-NEXT: s_cbranch_scc1 .LBB5_1 +; GCN-NEXT: ; %bb.2: ; %bb18 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm +; +; GFX8-LABEL: dont_remove_shift: +; GFX8: ; %bb.0: ; %bb +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c +; GFX8-NEXT: s_mov_b32 s2, 0 +; GFX8-NEXT: s_mov_b32 s6, 0 +; GFX8-NEXT: .LBB5_1: ; %bb4 +; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX8-NEXT: s_lshr_b32 s3, s6, 8 +; GFX8-NEXT: s_lshr_b32 s6, s6, 8 +; GFX8-NEXT: s_lshr_b32 s2, s2, 8 +; GFX8-NEXT: s_mul_i32 s3, s3, s2 +; GFX8-NEXT: s_mul_i32 s6, s6, s2 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_add_i32 s2, s0, s3 +; GFX8-NEXT: s_add_i32 s6, s1, s6 +; GFX8-NEXT: s_add_i32 s3, s2, s6 +; GFX8-NEXT: s_cmp_lg_u32 s3, 8 +; GFX8-NEXT: s_cbranch_scc1 .LBB5_1 +; GFX8-NEXT: ; %bb.2: ; %bb18 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm bb: br label %bb4 @@ -151,19 +661,234 @@ bb18: ; preds = %bb4 ret void } -; FUNC-LABEL: {{^}}i8_mad_sat_16: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16 -; SI: v_med3_i32 v{{[0-9]}}, [[EXT]], -; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; VI: v_max_i16_e32 [[MAX:v[0-9]]], 0xff80, [[MAD]] -; VI: v_min_i16_e32 {{v[0-9]}}, 0x7f, [[MAX]] define amdgpu_kernel void @i8_mad_sat_16(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(5) %idx) { +; EG-LABEL: i8_mad_sat_16: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 24, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_8 T3.X, T3.X, 0, #1 +; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X, +; EG-NEXT: ALU clause starting at 19: +; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X, +; EG-NEXT: ADD_INT * T3.X, KC0[3].X, T0.X, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T1.W, T3.X, 0.0, literal.x, +; EG-NEXT: MULLO_INT * T0.Y, PV.Z, PV.W, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PS, PV.W, +; EG-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; EG-NEXT: MAX_INT T0.W, PV.W, literal.x, +; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, T0.X, +; EG-NEXT: -128(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PS, literal.x, +; EG-NEXT: MIN_INT * T0.W, PV.W, literal.y, +; EG-NEXT: 3(4.203895e-45), 127(1.779649e-43) +; EG-NEXT: AND_INT T0.W, PS, literal.x, +; EG-NEXT: LSHL * T2.W, PV.W, literal.y, +; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45) +; EG-NEXT: LSHL T0.X, PV.W, PS, +; EG-NEXT: LSHL * T0.W, literal.x, PS, +; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; EG-NEXT: MOV T0.Y, 0.0, +; EG-NEXT: MOV * T0.Z, 0.0, +; EG-NEXT: LSHR * T1.X, T1.W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: i8_mad_sat_16: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 26, @21, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT MSKOR T1.XW, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_8 T3.X, T3.X, 0, #1 +; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X, +; CM-NEXT: ALU clause starting at 19: +; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X, +; CM-NEXT: ADD_INT * T3.X, KC0[2].Z, T0.X, +; CM-NEXT: ALU clause starting at 21: +; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x, +; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: BFE_INT * T0.W, T3.X, 0.0, literal.x, BS:VEC_201 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Z, T0.W, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.Z, T0.W, +; CM-NEXT: MULLO_INT T0.Z, T0.Z, T0.W, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Z, T0.W, +; CM-NEXT: ADD_INT * T0.W, PV.Z, T0.Y, +; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: MAX_INT T0.Z, PV.W, literal.x, +; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.X, +; CM-NEXT: -128(nan), 0(0.000000e+00) +; CM-NEXT: AND_INT T1.Z, PV.W, literal.x, +; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.y, +; CM-NEXT: 3(4.203895e-45), 127(1.779649e-43) +; CM-NEXT: AND_INT T0.Z, PV.W, literal.x, +; CM-NEXT: LSHL * T1.W, PV.Z, literal.y, +; CM-NEXT: 255(3.573311e-43), 3(4.203895e-45) +; CM-NEXT: LSHL T1.X, PV.Z, PV.W, +; CM-NEXT: LSHL * T1.W, literal.x, PV.W, +; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; CM-NEXT: MOV T1.Y, 0.0, +; CM-NEXT: MOV * T1.Z, 0.0, +; CM-NEXT: LSHR * T0.X, T0.W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i8_mad_sat_16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0 +; GCN-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1 +; GCN-NEXT: s_mov_b32 s22, -1 +; GCN-NEXT: s_mov_b32 s23, 0xe8f000 +; GCN-NEXT: s_add_u32 s20, s20, s11 +; GCN-NEXT: s_addc_u32 s21, s21, 0 +; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s9, s8, 4 +; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: buffer_load_dword v1, v1, s[20:23], 0 offen +; GCN-NEXT: buffer_load_dword v0, v0, s[20:23], 0 offen +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, 0 +; GCN-NEXT: s_mov_b64 s[14:15], s[10:11] +; GCN-NEXT: s_mov_b64 s[18:19], s[10:11] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[8:9], s[2:3] +; GCN-NEXT: s_mov_b64 s[12:13], s[4:5] +; GCN-NEXT: s_mov_b64 s[16:17], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[8:11], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v4, v[0:1], s[16:19], 0 addr64 +; GCN-NEXT: s_movk_i32 s2, 0xff80 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mad_u32_u24 v2, v2, v3, v4 +; GCN-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GCN-NEXT: v_mov_b32_e32 v3, 0x7f +; GCN-NEXT: v_med3_i32 v2, v2, s2, v3 +; GCN-NEXT: s_mov_b64 s[2:3], s[10:11] +; GCN-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 +; GCN-NEXT: s_endpgm +; +; SI-LABEL: i8_mad_sat_16: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0 +; SI-NEXT: s_load_dword s0, s[4:5], 0x44 +; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1 +; SI-NEXT: s_mov_b32 s90, -1 +; SI-NEXT: s_mov_b32 s91, 0xe80000 +; SI-NEXT: s_add_u32 s88, s88, s11 +; SI-NEXT: s_addc_u32 s89, s89, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_add_i32 s1, s0, 4 +; SI-NEXT: v_mov_b32_e32 v0, s0 +; SI-NEXT: buffer_load_dword v6, v0, s[88:91], 0 offen +; SI-NEXT: v_mov_b32_e32 v0, s1 +; SI-NEXT: buffer_load_dword v7, v0, s[88:91], 0 offen +; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s3 +; SI-NEXT: v_mov_b32_e32 v3, s5 +; SI-NEXT: v_mov_b32_e32 v5, s7 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v6 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc +; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v6 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc +; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v6 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; SI-NEXT: flat_load_sbyte v0, v[0:1] +; SI-NEXT: flat_load_sbyte v1, v[2:3] +; SI-NEXT: flat_load_sbyte v2, v[4:5] +; SI-NEXT: v_mov_b32_e32 v3, s1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_u16 v0, v1, v0, v2 +; SI-NEXT: v_max_i16_e32 v0, 0xff80, v0 +; SI-NEXT: v_min_i16_e32 v2, 0x7f, v0 +; SI-NEXT: v_add_u32_e32 v0, vcc, s0, v6 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v7, vcc +; SI-NEXT: flat_store_byte v[0:1], v2 +; SI-NEXT: s_endpgm +; +; VI-LABEL: i8_mad_sat_16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; VI-NEXT: s_load_dword s0, s[4:5], 0x44 +; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; VI-NEXT: s_mov_b32 s14, -1 +; VI-NEXT: s_mov_b32 s15, 0xe80000 +; VI-NEXT: s_add_u32 s12, s12, s11 +; VI-NEXT: s_addc_u32 s13, s13, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s0, 4 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_load_dword v6, v0, s[12:15], 0 offen +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: buffer_load_dword v7, v0, s[12:15], 0 offen +; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6 +; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; VI-NEXT: flat_load_sbyte v0, v[0:1] +; VI-NEXT: flat_load_sbyte v1, v[2:3] +; VI-NEXT: flat_load_sbyte v2, v[4:5] +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u16 v0, v1, v0, v2 +; VI-NEXT: v_max_i16_e32 v0, 0xff80, v0 +; VI-NEXT: v_min_i16_e32 v2, 0x7f, v0 +; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6 +; VI-NEXT: v_addc_u32_e32 v1, vcc, v3, v7, vcc +; VI-NEXT: flat_store_byte v[0:1], v2 +; VI-NEXT: s_endpgm entry: %retval.0.i = load i64, ptr addrspace(5) %idx %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 %retval.0.i @@ -187,16 +912,201 @@ entry: ret void } -; FUNC-LABEL: {{^}}i8_mad_32: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16 define amdgpu_kernel void @i8_mad_32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) { +; EG-LABEL: i8_mad_32: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 9, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X, +; EG-NEXT: ALU clause starting at 19: +; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X, +; EG-NEXT: ADD_INT * T0.X, KC0[3].X, T0.X, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T1.W, T0.X, 0.0, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PV.W, PV.Z, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PS, PV.W, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) +; +; CM-LABEL: i8_mad_32: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 12, @21, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X, +; CM-NEXT: ALU clause starting at 19: +; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X, +; CM-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, +; CM-NEXT: ALU clause starting at 21: +; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x, +; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_201 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.Y, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GCN-LABEL: i8_mad_32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0 +; GCN-NEXT: s_mov_b32 s25, SCRATCH_RSRC_DWORD1 +; GCN-NEXT: s_mov_b32 s26, -1 +; GCN-NEXT: s_mov_b32 s27, 0xe8f000 +; GCN-NEXT: s_add_u32 s24, s24, s11 +; GCN-NEXT: s_addc_u32 s25, s25, 0 +; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s9, s8, 4 +; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: buffer_load_dword v1, v1, s[24:27], 0 offen +; GCN-NEXT: buffer_load_dword v0, v0, s[24:27], 0 offen +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s14, 0 +; GCN-NEXT: s_mov_b32 s15, s11 +; GCN-NEXT: s_mov_b64 s[18:19], s[14:15] +; GCN-NEXT: s_mov_b64 s[22:23], s[14:15] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[12:13], s[2:3] +; GCN-NEXT: s_mov_b64 s[16:17], s[4:5] +; GCN-NEXT: s_mov_b64 s[20:21], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[16:19], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v0, v[0:1], s[20:23], 0 addr64 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_mov_b32 s8, s0 +; GCN-NEXT: s_mov_b32 s9, s1 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v2 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mad_u32_u24 v0, v1, v2, v0 +; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GCN-NEXT: buffer_store_dword v0, off, s[8:11], 0 +; GCN-NEXT: s_endpgm +; +; SI-LABEL: i8_mad_32: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0 +; SI-NEXT: s_load_dword s0, s[4:5], 0x44 +; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1 +; SI-NEXT: s_mov_b32 s90, -1 +; SI-NEXT: s_mov_b32 s91, 0xe80000 +; SI-NEXT: s_add_u32 s88, s88, s11 +; SI-NEXT: s_addc_u32 s89, s89, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_add_i32 s1, s0, 4 +; SI-NEXT: v_mov_b32_e32 v0, s0 +; SI-NEXT: buffer_load_dword v4, v0, s[88:91], 0 offen +; SI-NEXT: v_mov_b32_e32 v0, s1 +; SI-NEXT: buffer_load_dword v5, v0, s[88:91], 0 offen +; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s3 +; SI-NEXT: v_mov_b32_e32 v3, s5 +; SI-NEXT: v_mov_b32_e32 v6, s7 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; SI-NEXT: flat_load_sbyte v0, v[0:1] +; SI-NEXT: flat_load_sbyte v1, v[2:3] +; SI-NEXT: flat_load_sbyte v2, v[4:5] +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_u16 v0, v0, v1, v2 +; SI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: i8_mad_32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; VI-NEXT: s_load_dword s0, s[4:5], 0x44 +; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; VI-NEXT: s_mov_b32 s14, -1 +; VI-NEXT: s_mov_b32 s15, 0xe80000 +; VI-NEXT: s_add_u32 s12, s12, s11 +; VI-NEXT: s_addc_u32 s13, s13, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s0, 4 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_load_dword v4, v0, s[12:15], 0 offen +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: buffer_load_dword v5, v0, s[12:15], 0 offen +; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_mov_b32_e32 v6, s7 +; VI-NEXT: s_mov_b32 s3, 0xf000 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; VI-NEXT: flat_load_sbyte v0, v[0:1] +; VI-NEXT: flat_load_sbyte v1, v[2:3] +; VI-NEXT: flat_load_sbyte v2, v[4:5] +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u16 v0, v0, v1, v2 +; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; VI-NEXT: s_endpgm entry: %retval.0.i = load i64, ptr addrspace(5) %idx %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i @@ -215,16 +1125,207 @@ entry: ret void } -; FUNC-LABEL: {{^}}i8_mad_64: -; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] -; The result must be sign-extended -; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x -; EG: 8 -; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16 define amdgpu_kernel void @i8_mad_64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) { +; EG-LABEL: i8_mad_64: +; EG: ; %bb.0: ; %entry +; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 0 @8 +; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; EG-NEXT: TEX 1 @10 +; EG-NEXT: ALU 11, @21, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 8: +; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; EG-NEXT: Fetch clause starting at 10: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; EG-NEXT: ALU clause starting at 14: +; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X, +; EG-NEXT: ALU clause starting at 19: +; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X, +; EG-NEXT: ADD_INT * T0.X, KC0[3].X, T0.X, +; EG-NEXT: ALU clause starting at 21: +; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x, +; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_INT T1.W, T0.X, 0.0, literal.x, +; EG-NEXT: MULLO_INT * T0.X, PV.W, PV.Z, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PS, PV.W, +; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) +; EG-NEXT: ASHR * T0.Y, PV.X, literal.x, +; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) +; +; CM-LABEL: i8_mad_64: +; CM: ; %bb.0: ; %entry +; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 0 @8 +; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[] +; CM-NEXT: TEX 1 @10 +; CM-NEXT: ALU 13, @21, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 8: +; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 +; CM-NEXT: Fetch clause starting at 10: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 +; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1 +; CM-NEXT: ALU clause starting at 14: +; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W, +; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+, +; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X, +; CM-NEXT: ALU clause starting at 19: +; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X, +; CM-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, +; CM-NEXT: ALU clause starting at 21: +; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x, +; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212 +; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_201 +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z, +; CM-NEXT: ADD_INT * T0.W, PV.X, T0.Y, +; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; CM-NEXT: ASHR * T0.Y, PV.X, literal.y, +; CM-NEXT: 2(2.802597e-45), 31(4.344025e-44) +; +; GCN-LABEL: i8_mad_64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0 +; GCN-NEXT: s_mov_b32 s25, SCRATCH_RSRC_DWORD1 +; GCN-NEXT: s_mov_b32 s26, -1 +; GCN-NEXT: s_mov_b32 s27, 0xe8f000 +; GCN-NEXT: s_add_u32 s24, s24, s11 +; GCN-NEXT: s_addc_u32 s25, s25, 0 +; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s9, s8, 4 +; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: buffer_load_dword v1, v1, s[24:27], 0 offen +; GCN-NEXT: buffer_load_dword v0, v0, s[24:27], 0 offen +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s14, 0 +; GCN-NEXT: s_mov_b32 s15, s11 +; GCN-NEXT: s_mov_b64 s[18:19], s[14:15] +; GCN-NEXT: s_mov_b64 s[22:23], s[14:15] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[12:13], s[2:3] +; GCN-NEXT: s_mov_b64 s[16:17], s[4:5] +; GCN-NEXT: s_mov_b64 s[20:21], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[16:19], 0 addr64 +; GCN-NEXT: buffer_load_sbyte v0, v[0:1], s[20:23], 0 addr64 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_mov_b32 s8, s0 +; GCN-NEXT: s_mov_b32 s9, s1 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v2 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mad_u32_u24 v0, v1, v2, v0 +; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: s_endpgm +; +; SI-LABEL: i8_mad_64: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0 +; SI-NEXT: s_load_dword s0, s[4:5], 0x44 +; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1 +; SI-NEXT: s_mov_b32 s90, -1 +; SI-NEXT: s_mov_b32 s91, 0xe80000 +; SI-NEXT: s_add_u32 s88, s88, s11 +; SI-NEXT: s_addc_u32 s89, s89, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_add_i32 s1, s0, 4 +; SI-NEXT: v_mov_b32_e32 v0, s0 +; SI-NEXT: buffer_load_dword v4, v0, s[88:91], 0 offen +; SI-NEXT: v_mov_b32_e32 v0, s1 +; SI-NEXT: buffer_load_dword v5, v0, s[88:91], 0 offen +; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s3 +; SI-NEXT: v_mov_b32_e32 v3, s5 +; SI-NEXT: v_mov_b32_e32 v6, s7 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; SI-NEXT: flat_load_sbyte v0, v[0:1] +; SI-NEXT: flat_load_sbyte v1, v[2:3] +; SI-NEXT: flat_load_sbyte v2, v[4:5] +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_u16 v0, v0, v1, v2 +; SI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: i8_mad_64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; VI-NEXT: s_load_dword s0, s[4:5], 0x44 +; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; VI-NEXT: s_mov_b32 s14, -1 +; VI-NEXT: s_mov_b32 s15, 0xe80000 +; VI-NEXT: s_add_u32 s12, s12, s11 +; VI-NEXT: s_addc_u32 s13, s13, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s0, 4 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: buffer_load_dword v4, v0, s[12:15], 0 offen +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: buffer_load_dword v5, v0, s[12:15], 0 offen +; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_mov_b32_e32 v6, s7 +; VI-NEXT: s_mov_b32 s3, 0xf000 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 +; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; VI-NEXT: flat_load_sbyte v0, v[0:1] +; VI-NEXT: flat_load_sbyte v1, v[2:3] +; VI-NEXT: flat_load_sbyte v2, v[4:5] +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_mad_u16 v0, v0, v1, v2 +; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 +; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; VI-NEXT: s_endpgm entry: %retval.0.i = load i64, ptr addrspace(5) %idx %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i @@ -248,17 +1349,236 @@ entry: ; had a chance to form mul24. The mul combine would then see ; extractelement with no known bits and fail. All of the mul/add ; combos in this loop should form v_mad_u32_u24. - -; FUNC-LABEL: {{^}}mad24_known_bits_destroyed: -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 -; GCN: v_mad_u32_u24 define void @mad24_known_bits_destroyed(i32 %arg, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, i32 %arg4, i32 %arg5, i32 %arg6, ptr addrspace(1) %arg7, ptr addrspace(1) %arg8) #0 { +; EG-LABEL: mad24_known_bits_destroyed: +; EG: ; %bb.0: ; %bb +; EG-NEXT: ALU 21, @12, KC0[CB0:0-32], KC1[] +; EG-NEXT: LOOP_START_DX10 @11 +; EG-NEXT: ALU 8, @34, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 0 +; EG-NEXT: ALU 14, @43, KC0[], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 0 +; EG-NEXT: ALU_PUSH_BEFORE 3, @58, KC0[], KC1[] +; EG-NEXT: JUMP @10 POP:1 +; EG-NEXT: LOOP_BREAK @10 +; EG-NEXT: POP @10 POP:1 +; EG-NEXT: END_LOOP @2 +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 12: +; EG-NEXT: MOV * T0.W, KC0[5].X, +; EG-NEXT: MOV * T0.Z, KC0[4].W, +; EG-NEXT: MOV * T0.Y, KC0[4].Z, +; EG-NEXT: MOV T0.X, KC0[2].Y, +; EG-NEXT: AND_INT * T1.Y, KC0[4].X, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: AND_INT T1.Z, KC0[3].W, literal.x, +; EG-NEXT: AND_INT T1.W, KC0[3].Z, literal.x, +; EG-NEXT: MOV * T2.W, KC0[7].Y, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: LSHR T1.X, PS, literal.x, +; EG-NEXT: AND_INT T2.Y, KC0[6].Y, literal.y, +; EG-NEXT: MOV T2.Z, KC0[6].X, +; EG-NEXT: MOV * T2.W, KC0[5].W, +; EG-NEXT: 2(2.802597e-45), 16777215(2.350989e-38) +; EG-NEXT: MOV * T3.W, KC0[7].X, +; EG-NEXT: LSHR T2.X, PV.W, literal.x, +; EG-NEXT: MOV T3.Y, KC0[5].Z, +; EG-NEXT: MOV T3.Z, KC0[6].Z, +; EG-NEXT: MOV * T3.W, KC0[6].W, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: MOV * T4.W, KC0[4].Y, +; EG-NEXT: ALU clause starting at 34: +; EG-NEXT: MULLO_INT * T0.X, T0.X, T2.Y, +; EG-NEXT: ADD_INT * T4.W, PS, T3.Z, +; EG-NEXT: AND_INT * T4.W, PV.W, literal.x, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: MULLO_INT * T0.X, PV.W, T2.Y, +; EG-NEXT: MULLO_INT * T0.W, T0.W, T1.Y, +; EG-NEXT: MULLO_INT * T0.Z, T0.Z, T1.Z, +; EG-NEXT: MULLO_INT * T0.Y, T0.Y, T1.W, +; EG-NEXT: ADD_INT * T0.X, T0.X, T3.Z, +; EG-NEXT: ALU clause starting at 43: +; EG-NEXT: ADD_INT * T4.W, T0.Y, T3.Y, +; EG-NEXT: AND_INT T4.W, PV.W, literal.x, +; EG-NEXT: ADD_INT * T5.W, T0.Z, T2.W, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: AND_INT T0.Z, PS, literal.x, +; EG-NEXT: ADD_INT T0.W, T0.W, T2.Z, +; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: ADD_INT T0.Y, PS, T3.Y, +; EG-NEXT: AND_INT T0.W, PV.W, literal.x, +; EG-NEXT: MULLO_INT * T0.Z, PV.Z, T1.Z, +; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; EG-NEXT: ADD_INT T0.Z, PS, T2.W, +; EG-NEXT: MULLO_INT * T0.W, PV.W, T1.Y, +; EG-NEXT: ADD_INT * T0.W, PS, T2.Z, +; EG-NEXT: ALU clause starting at 58: +; EG-NEXT: ADD_INT * T3.W, T3.W, literal.x, +; EG-NEXT: -1(nan), 0(0.000000e+00) +; EG-NEXT: SETE_INT * T4.W, PV.W, 0.0, +; EG-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; +; CM-LABEL: mad24_known_bits_destroyed: +; CM: ; %bb.0: ; %bb +; CM-NEXT: ALU 22, @12, KC0[CB0:0-32], KC1[] +; CM-NEXT: LOOP_START_DX10 @11 +; CM-NEXT: ALU 23, @35, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T2.X +; CM-NEXT: ALU 23, @59, KC0[], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X +; CM-NEXT: ALU_PUSH_BEFORE 3, @83, KC0[], KC1[] +; CM-NEXT: JUMP @10 POP:1 +; CM-NEXT: LOOP_BREAK @10 +; CM-NEXT: POP @10 POP:1 +; CM-NEXT: END_LOOP @2 +; CM-NEXT: CF_END +; CM-NEXT: ALU clause starting at 12: +; CM-NEXT: MOV * T0.W, KC0[5].X, +; CM-NEXT: MOV * T0.Z, KC0[4].W, +; CM-NEXT: MOV * T0.Y, KC0[4].Z, +; CM-NEXT: MOV T0.X, KC0[2].Y, +; CM-NEXT: AND_INT * T1.Y, KC0[4].X, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: AND_INT T1.Z, KC0[3].W, literal.x, +; CM-NEXT: AND_INT * T1.W, KC0[3].Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: AND_INT T2.Y, KC0[6].Y, literal.x, +; CM-NEXT: MOV T2.Z, KC0[6].X, +; CM-NEXT: MOV * T2.W, KC0[7].Y, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: LSHR T1.X, PV.W, literal.x, +; CM-NEXT: MOV T3.Y, KC0[5].W, +; CM-NEXT: MOV T3.Z, KC0[5].Z, +; CM-NEXT: MOV * T2.W, KC0[7].X, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: LSHR T2.X, PV.W, literal.x, +; CM-NEXT: MOV T4.Y, KC0[6].Z, +; CM-NEXT: MOV T4.Z, KC0[6].W, +; CM-NEXT: MOV * T2.W, KC0[4].Y, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: ALU clause starting at 35: +; CM-NEXT: MULLO_INT T0.X, T0.X, T2.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.X, T2.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.X, T2.Y, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.X, T2.Y, +; CM-NEXT: ADD_INT * T2.W, PV.X, T4.Y, +; CM-NEXT: AND_INT * T2.W, PV.W, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X, T2.W, T2.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T2.W, T2.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T2.W, T2.Y, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T2.W, T2.Y, +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT * T0.W, T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Z, T1.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.Z, T1.Z, +; CM-NEXT: MULLO_INT T0.Z, T0.Z, T1.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Z, T1.Z, +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Y, T1.W, +; CM-NEXT: MULLO_INT T0.Y, T0.Y, T1.W, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.Y, T1.W, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Y, T1.W, +; CM-NEXT: ADD_INT * T0.X, T0.X, T4.Y, +; CM-NEXT: ALU clause starting at 59: +; CM-NEXT: ADD_INT * T2.W, T0.Y, T3.Z, +; CM-NEXT: ADD_INT T0.Z, T0.Z, T3.Y, +; CM-NEXT: AND_INT * T2.W, PV.W, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT T0.Y, T2.W, T1.W, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T2.W, T1.W, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T2.W, T1.W, +; CM-NEXT: ADD_INT T0.Y, PV.Y, T3.Z, +; CM-NEXT: ADD_INT T5.Z, T0.W, T2.Z, BS:VEC_021/SCL_122 +; CM-NEXT: AND_INT * T0.W, T0.Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z, +; CM-NEXT: MULLO_INT T0.Z, T0.W, T1.Z, +; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z, +; CM-NEXT: ADD_INT T0.Z, PV.Z, T3.Y, +; CM-NEXT: AND_INT * T0.W, T5.Z, literal.x, +; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00) +; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Y, +; CM-NEXT: MULLO_INT * T0.W, T0.W, T1.Y, +; CM-NEXT: ADD_INT * T0.W, PV.W, T2.Z, +; CM-NEXT: ALU clause starting at 83: +; CM-NEXT: ADD_INT * T4.Z, T4.Z, literal.x, +; CM-NEXT: -1(nan), 0(0.000000e+00) +; CM-NEXT: SETE_INT * T2.W, PV.Z, 0.0, +; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, +; +; GCN-LABEL: mad24_known_bits_destroyed: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, v0 +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v13 +; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v2 +; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v3 +; GCN-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; GCN-NEXT: s_mov_b64 s[8:9], 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: .LBB9_1: ; %bb19 +; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 +; GCN-NEXT: v_mad_u32_u24 v4, v5, v0, v14 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GCN-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GCN-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GCN-NEXT: v_add_i32_e32 v15, vcc, -1, v15 +; GCN-NEXT: v_mad_u32_u24 v5, v4, v0, v14 +; GCN-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GCN-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GCN-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 +; GCN-NEXT: buffer_store_dword v5, v[16:17], s[4:7], 0 addr64 +; GCN-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GCN-NEXT: buffer_store_dwordx4 v[5:8], v[18:19], s[4:7], 0 addr64 +; GCN-NEXT: s_andn2_b64 exec, exec, s[8:9] +; GCN-NEXT: s_cbranch_execnz .LBB9_1 +; GCN-NEXT: ; %bb.2: ; %bb18 +; GCN-NEXT: s_or_b64 exec, exec, s[8:9] +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: mad24_known_bits_destroyed: +; GFX8: ; %bb.0: ; %bb +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v5, v0 +; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v13 +; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v2 +; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3 +; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; GFX8-NEXT: s_mov_b64 s[4:5], 0 +; GFX8-NEXT: .LBB9_1: ; %bb19 +; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX8-NEXT: v_add_u32_e32 v15, vcc, -1, v15 +; GFX8-NEXT: v_mad_u32_u24 v4, v5, v0, v14 +; GFX8-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GFX8-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GFX8-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15 +; GFX8-NEXT: v_mad_u32_u24 v5, v4, v0, v14 +; GFX8-NEXT: v_mad_u32_u24 v6, v6, v1, v10 +; GFX8-NEXT: v_mad_u32_u24 v7, v7, v2, v11 +; GFX8-NEXT: v_mad_u32_u24 v8, v8, v3, v12 +; GFX8-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX8-NEXT: flat_store_dword v[16:17], v5 +; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[5:8] +; GFX8-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX8-NEXT: s_cbranch_execnz .LBB9_1 +; GFX8-NEXT: ; %bb.2: ; %bb18 +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] bb: %tmp = and i32 %arg4, 16777215 %tmp9 = extractelement <4 x i32> %arg1, i64 1 diff --git a/llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags_V1.ll b/llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags_V1.ll new file mode 100644 index 0000000..610ce4f --- /dev/null +++ b/llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags_V1.ll @@ -0,0 +1,18 @@ +; RUN: not opt -passes='print<dxil-root-signature>' %s -S -o - 2>&1 | FileCheck %s +; On Version 1, the only valid flag is DataVolatile (2). +target triple = "dxil-unknown-shadermodel6.0-compute" + + +; CHECK: error: Invalid value for RootDescriptorFlag: 4 +; CHECK-NOT: Root Signature Definitions +define void @main() #0 { +entry: + ret void +} +attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" } + + +!dx.rootsignatures = !{!2} ; list of function/root signature pairs +!2 = !{ ptr @main, !3, i32 1 } ; function, root signature +!3 = !{ !5 } ; list of root signature elements +!5 = !{ !"RootCBV", i32 0, i32 1, i32 2, i32 4 } diff --git a/llvm/test/CodeGen/DirectX/ContainerData/RootSignature-StaticSamplers-Invalid-Flag_V1.ll b/llvm/test/CodeGen/DirectX/ContainerData/RootSignature-StaticSamplers-Invalid-Flag_V1.ll new file mode 100644 index 0000000..76b60b8 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/ContainerData/RootSignature-StaticSamplers-Invalid-Flag_V1.ll @@ -0,0 +1,19 @@ +; RUN: not opt -passes='print<dxil-root-signature>' %s -S -o - 2>&1 | FileCheck %s + + +target triple = "dxil-unknown-shadermodel6.0-compute" + +; CHECK: error: Invalid value for Static Sampler Flag: 1 +; CHECK-NOT: Root Signature Definitions + +define void @main() #0 { +entry: + ret void +} +attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" } + + +!dx.rootsignatures = !{!2} ; list of function/root signature pairs +!2 = !{ ptr @main, !3, i32 1 } ; function, root signature +!3 = !{ !5 } ; list of root signature elements +!5 = !{ !"StaticSampler", i32 4, i32 2, i32 3, i32 5, float 0x3FF6CCCCC0000000, i32 9, i32 3, i32 2, float -1.280000e+02, float 1.280000e+02, i32 42, i32 0, i32 0, i32 1 } diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll new file mode 100644 index 0000000..a3127e8 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_predicated_io/predicated_io_generic.ll @@ -0,0 +1,36 @@ +; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_predicated_io %s -o - | FileCheck %s + +; CHECK-ERROR: LLVM ERROR: OpPredicated[Load/Store]INTEL +; CHECK-ERROR-SAME: instructions require the following SPIR-V extension: SPV_INTEL_predicated_io + +; CHECK-DAG: Capability PredicatedIOINTEL +; CHECK-DAG: Extension "SPV_INTEL_predicated_io" + +; CHECK-DAG: %[[Int32Ty:[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: %[[IntPtrTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[Int32Ty]] +; CHECK-DAG: %[[BoolTy:[0-9]+]] = OpTypeBool +; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid +; CHECK: %[[LoadPtr:[0-9]+]] = OpFunctionParameter %[[IntPtrTy]] +; CHECK: %[[StorePtr:[0-9]+]] = OpFunctionParameter %[[IntPtrTy]] +; CHECK: %[[DefaultVal:[0-9]+]] = OpFunctionParameter %[[Int32Ty]] +; CHECK: %[[StoreObj:[0-9]+]] = OpFunctionParameter %[[Int32Ty]] +; CHECK: %[[Predicate:[0-9]+]] = OpFunctionParameter %[[BoolTy]] +; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] +; CHECK: PredicatedLoadINTEL %[[Int32Ty]] %[[LoadPtr]] %[[Predicate]] %[[DefaultVal]] None +; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] +; CHECK: PredicatedStoreINTEL %[[StorePtr]] %[[StoreObj]] %[[Predicate]] None + +define spir_func void @foo(ptr addrspace(1) %load_pointer, ptr addrspace(1) %store_pointer, i32 %default_value, i32 %store_object, i1 zeroext %predicate) { +entry: + %1 = call spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1) %load_pointer, i1 %predicate, i32 %default_value) + %2 = call spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1) %load_pointer, i1 %predicate, i32 %default_value, i32 0) + call spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1) %store_pointer, i32 %store_object, i1 %predicate) + call spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1) %store_pointer, i32 %store_object, i1 %predicate, i32 0) + ret void +} + +declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibi(ptr addrspace(1), i1, i32) +declare spir_func i32 @_Z27__spirv_PredicatedLoadINTELPU3AS1Kibii(ptr addrspace(1), i1, i32, i32) +declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiib(ptr addrspace(1), i32, i1) +declare spir_func void @_Z28__spirv_PredicatedStoreINTELPU3AS1Kiibi(ptr addrspace(1), i32, i1, i32) diff --git a/llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll b/llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll index 52f57dc..a8d37be 100644 --- a/llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll @@ -434,7 +434,6 @@ entry: define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-LABEL: stest_f16i16: ; CHECK: .functype stest_f16i16 (f32, f32, f32, f32, f32, f32, f32, f32) -> (v128) -; CHECK-NEXT: .local v128, v128, v128 ; CHECK-NEXT: # %bb.0: # %entry ; CHECK-NEXT: local.get 5 ; CHECK-NEXT: call __truncsfhf2 @@ -474,15 +473,6 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: i32.trunc_sat_f32_s ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: v128.const 32767, 32767, 32767, 32767 -; CHECK-NEXT: local.tee 8 -; CHECK-NEXT: i32x4.min_s -; CHECK-NEXT: v128.const -32768, -32768, -32768, -32768 -; CHECK-NEXT: local.tee 9 -; CHECK-NEXT: i32x4.max_s -; CHECK-NEXT: v128.const 65535, 65535, 65535, 65535 -; CHECK-NEXT: local.tee 10 -; CHECK-NEXT: v128.and ; CHECK-NEXT: local.get 4 ; CHECK-NEXT: i32.trunc_sat_f32_s ; CHECK-NEXT: i32x4.splat @@ -495,13 +485,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) { ; CHECK-NEXT: local.get 7 ; CHECK-NEXT: i32.trunc_sat_f32_s ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: local.get 8 -; CHECK-NEXT: i32x4.min_s -; CHECK-NEXT: local.get 9 -; CHECK-NEXT: i32x4.max_s -; CHECK-NEXT: local.get 10 -; CHECK-NEXT: v128.and -; CHECK-NEXT: i16x8.narrow_i32x4_u +; CHECK-NEXT: i16x8.narrow_i32x4_s ; CHECK-NEXT: # fallthrough-return entry: %conv = fptosi <8 x half> %x to <8 x i32> @@ -516,7 +500,6 @@ entry: define <8 x i16> @utest_f16i16(<8 x half> %x) { ; CHECK-LABEL: utest_f16i16: ; CHECK: .functype utest_f16i16 (f32, f32, f32, f32, f32, f32, f32, f32) -> (v128) -; CHECK-NEXT: .local v128 ; CHECK-NEXT: # %bb.0: # %entry ; CHECK-NEXT: local.get 5 ; CHECK-NEXT: call __truncsfhf2 @@ -556,9 +539,6 @@ define <8 x i16> @utest_f16i16(<8 x half> %x) { ; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: i32.trunc_sat_f32_u ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: v128.const 65535, 65535, 65535, 65535 -; CHECK-NEXT: local.tee 8 -; CHECK-NEXT: i32x4.min_u ; CHECK-NEXT: local.get 4 ; CHECK-NEXT: i32.trunc_sat_f32_u ; CHECK-NEXT: i32x4.splat @@ -571,8 +551,6 @@ define <8 x i16> @utest_f16i16(<8 x half> %x) { ; CHECK-NEXT: local.get 7 ; CHECK-NEXT: i32.trunc_sat_f32_u ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: local.get 8 -; CHECK-NEXT: i32x4.min_u ; CHECK-NEXT: i16x8.narrow_i32x4_u ; CHECK-NEXT: # fallthrough-return entry: @@ -1861,7 +1839,6 @@ entry: define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-LABEL: stest_f16i16_mm: ; CHECK: .functype stest_f16i16_mm (f32, f32, f32, f32, f32, f32, f32, f32) -> (v128) -; CHECK-NEXT: .local v128, v128, v128 ; CHECK-NEXT: # %bb.0: # %entry ; CHECK-NEXT: local.get 5 ; CHECK-NEXT: call __truncsfhf2 @@ -1901,15 +1878,6 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: i32.trunc_sat_f32_s ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: v128.const 32767, 32767, 32767, 32767 -; CHECK-NEXT: local.tee 8 -; CHECK-NEXT: i32x4.min_s -; CHECK-NEXT: v128.const -32768, -32768, -32768, -32768 -; CHECK-NEXT: local.tee 9 -; CHECK-NEXT: i32x4.max_s -; CHECK-NEXT: v128.const 65535, 65535, 65535, 65535 -; CHECK-NEXT: local.tee 10 -; CHECK-NEXT: v128.and ; CHECK-NEXT: local.get 4 ; CHECK-NEXT: i32.trunc_sat_f32_s ; CHECK-NEXT: i32x4.splat @@ -1922,13 +1890,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { ; CHECK-NEXT: local.get 7 ; CHECK-NEXT: i32.trunc_sat_f32_s ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: local.get 8 -; CHECK-NEXT: i32x4.min_s -; CHECK-NEXT: local.get 9 -; CHECK-NEXT: i32x4.max_s -; CHECK-NEXT: local.get 10 -; CHECK-NEXT: v128.and -; CHECK-NEXT: i16x8.narrow_i32x4_u +; CHECK-NEXT: i16x8.narrow_i32x4_s ; CHECK-NEXT: # fallthrough-return entry: %conv = fptosi <8 x half> %x to <8 x i32> @@ -1941,7 +1903,6 @@ entry: define <8 x i16> @utest_f16i16_mm(<8 x half> %x) { ; CHECK-LABEL: utest_f16i16_mm: ; CHECK: .functype utest_f16i16_mm (f32, f32, f32, f32, f32, f32, f32, f32) -> (v128) -; CHECK-NEXT: .local v128 ; CHECK-NEXT: # %bb.0: # %entry ; CHECK-NEXT: local.get 5 ; CHECK-NEXT: call __truncsfhf2 @@ -1981,9 +1942,6 @@ define <8 x i16> @utest_f16i16_mm(<8 x half> %x) { ; CHECK-NEXT: call __extendhfsf2 ; CHECK-NEXT: i32.trunc_sat_f32_u ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: v128.const 65535, 65535, 65535, 65535 -; CHECK-NEXT: local.tee 8 -; CHECK-NEXT: i32x4.min_u ; CHECK-NEXT: local.get 4 ; CHECK-NEXT: i32.trunc_sat_f32_u ; CHECK-NEXT: i32x4.splat @@ -1996,8 +1954,6 @@ define <8 x i16> @utest_f16i16_mm(<8 x half> %x) { ; CHECK-NEXT: local.get 7 ; CHECK-NEXT: i32.trunc_sat_f32_u ; CHECK-NEXT: i32x4.replace_lane 3 -; CHECK-NEXT: local.get 8 -; CHECK-NEXT: i32x4.min_u ; CHECK-NEXT: i16x8.narrow_i32x4_u ; CHECK-NEXT: # fallthrough-return entry: diff --git a/llvm/test/CodeGen/WebAssembly/saturating-truncation.ll b/llvm/test/CodeGen/WebAssembly/saturating-truncation.ll new file mode 100644 index 0000000..f3f3ba9 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/saturating-truncation.ll @@ -0,0 +1,87 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 + +; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s + +target triple = "wasm32-unknown-unknown" + +declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>) #2 +declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>) #2 + +define <16 x i8> @i16_signed(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: i16_signed: +; CHECK: .functype i16_signed (v128, v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %bb2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i8x16.narrow_i16x8_s +; CHECK-NEXT: # fallthrough-return +bb2: + %0 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = tail call <16 x i16> @llvm.smax.v16i16(<16 x i16> %0, <16 x i16> splat (i16 -128)) + %2 = tail call <16 x i16> @llvm.smin.v16i16(<16 x i16> %1, <16 x i16> splat (i16 127)) + %3 = trunc nsw <16 x i16> %2 to <16 x i8> + ret <16 x i8> %3 + ret <16 x i8> %3 +} + +define <8 x i16> @i32_signed(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: i32_signed: +; CHECK: .functype i32_signed (v128, v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %bb2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i16x8.narrow_i32x4_s +; CHECK-NEXT: # fallthrough-return +bb2: + %0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %1 = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> %0, <8 x i32> splat (i32 -32768)) + %2 = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> %1, <8 x i32> splat (i32 32767)) + %3 = trunc nsw <8 x i32> %2 to <8 x i16> + ret <8 x i16> %3 +} + +define <8 x i16> @i32_signed_flipped(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: i32_signed_flipped: +; CHECK: .functype i32_signed_flipped (v128, v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %bb2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i16x8.narrow_i32x4_s +; CHECK-NEXT: # fallthrough-return +bb2: + %0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %1 = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> splat (i32 32767), <8 x i32> %0) + %2 = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> splat (i32 -32768), <8 x i32> %1) + %3 = trunc nsw <8 x i32> %2 to <8 x i16> + ret <8 x i16> %3 +} + +define <16 x i8> @i16_unsigned(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: i16_unsigned: +; CHECK: .functype i16_unsigned (v128, v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %bb2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i8x16.narrow_i16x8_u +; CHECK-NEXT: # fallthrough-return +bb2: + %0 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = tail call <16 x i16> @llvm.umin.v16i16(<16 x i16> %0, <16 x i16> splat (i16 255)) + %2 = trunc nuw <16 x i16> %1 to <16 x i8> + ret <16 x i8> %2 +} + +define <8 x i16> @i32_unsigned(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: i32_unsigned: +; CHECK: .functype i32_unsigned (v128, v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %bb2 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i16x8.narrow_i32x4_u +; CHECK-NEXT: # fallthrough-return +bb2: + %0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %1 = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> %0, <8 x i32> splat (i32 65535)) + %2 = trunc nsw <8 x i32> %1 to <8 x i16> + ret <8 x i16> %2 +} diff --git a/llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll b/llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll new file mode 100644 index 0000000..c302d41 --- /dev/null +++ b/llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll @@ -0,0 +1,11 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-linux-gnu -fast-isel -fast-isel-abort=1 < %s -o - | FileCheck %s + +define i64 @ptrtoaddr(ptr %p) { +; CHECK-LABEL: ptrtoaddr: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq + %addr = ptrtoaddr ptr %p to i64 + ret i64 %addr +} |