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-rw-r--r--llvm/test/CodeGen/SystemZ/args-22.ll1004
-rw-r--r--llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll11
-rw-r--r--llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll11
-rw-r--r--llvm/test/CodeGen/SystemZ/condfolding.ll28
-rw-r--r--llvm/test/CodeGen/SystemZ/inline-asm-flag-output-01.ll37
-rw-r--r--llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll4
-rw-r--r--llvm/test/CodeGen/SystemZ/stackmap.ll4
-rw-r--r--llvm/test/CodeGen/SystemZ/vec-load-element.ll4
-rw-r--r--llvm/test/CodeGen/SystemZ/vec-max-05.ll181
-rw-r--r--llvm/test/CodeGen/SystemZ/vec-min-05.ll181
-rw-r--r--llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll66
-rw-r--r--llvm/test/CodeGen/SystemZ/zos-target-flags.ll17
12 files changed, 1396 insertions, 152 deletions
diff --git a/llvm/test/CodeGen/SystemZ/args-22.ll b/llvm/test/CodeGen/SystemZ/args-22.ll
new file mode 100644
index 0000000..ba422b6
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/args-22.ll
@@ -0,0 +1,1004 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s --check-prefix=VECTOR
+;
+; Test passing IR struct arguments, which do not adhere to the SystemZ ABI but are
+; split up with each element passed like a separate argument.
+
+@Fnptr = external global ptr
+@Src = external global ptr
+@Dst = external global ptr
+
+%Ty0 = type {i128}
+define void @arg0(%Ty0 %A) {
+; CHECK-LABEL: arg0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r2)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg0:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r2), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vst %v0, 0(%r1), 3
+; VECTOR-NEXT: br %r14
+ store %Ty0 %A, ptr @Dst
+ ret void
+}
+
+define void @call0() {
+; CHECK-LABEL: call0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 8(%r1)
+; CHECK-NEXT: lg %r1, 0(%r1)
+; CHECK-NEXT: stg %r0, 168(%r15)
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: stg %r1, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call0:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -176
+; VECTOR-NEXT: .cfi_def_cfa_offset 336
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vl %v0, 0(%r1), 3
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: vst %v0, 160(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 288(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty0, ptr @Src
+ call void @Fnptr(%Ty0 %L)
+ ret void
+}
+
+define %Ty0 @ret0() {
+; CHECK-LABEL: ret0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lg %r0, 168(%r15)
+; CHECK-NEXT: lg %r1, 160(%r15)
+; CHECK-NEXT: stg %r0, 8(%r13)
+; CHECK-NEXT: stg %r1, 0(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret0:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -176
+; VECTOR-NEXT: .cfi_def_cfa_offset 336
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: vl %v0, 160(%r15), 3
+; VECTOR-NEXT: vst %v0, 0(%r13), 3
+; VECTOR-NEXT: lmg %r13, %r15, 280(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty0 @Fnptr()
+ ret %Ty0 %C
+}
+
+%Ty1 = type {i72}
+define void @arg1(%Ty1 %A) {
+; CHECK-LABEL: arg1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r2)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: stc %r0, 8(%r1)
+; CHECK-NEXT: sllg %r2, %r2, 56
+; CHECK-NEXT: rosbg %r2, %r0, 8, 63, 56
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg1:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r2), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vrepib %v1, 8
+; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
+; VECTOR-NEXT: vsrlb %v0, %v0, %v1
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
+; VECTOR-NEXT: br %r14
+ store %Ty1 %A, ptr @Dst
+ ret void
+}
+
+define void @call1() {
+; CHECK-LABEL: call1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 0(%r1)
+; CHECK-NEXT: sllg %r2, %r0, 8
+; CHECK-NEXT: ic %r2, 8(%r1)
+; CHECK-NEXT: srlg %r0, %r0, 56
+; CHECK-NEXT: stg %r2, 168(%r15)
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: stg %r0, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call1:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -176
+; VECTOR-NEXT: .cfi_def_cfa_offset 336
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vgbm %v0, 0
+; VECTOR-NEXT: vleb %v0, 8(%r1), 15
+; VECTOR-NEXT: vlrepg %v1, 0(%r1)
+; VECTOR-NEXT: vrepib %v2, 8
+; VECTOR-NEXT: vslb %v1, %v1, %v2
+; VECTOR-NEXT: vo %v0, %v0, %v1
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: vst %v0, 160(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 288(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty1, ptr @Src
+ call void @Fnptr(%Ty1 %L)
+ ret void
+}
+
+define %Ty1 @ret1() {
+; CHECK-LABEL: ret1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lg %r0, 160(%r15)
+; CHECK-NEXT: llgc %r1, 168(%r15)
+; CHECK-NEXT: stg %r0, 0(%r13)
+; CHECK-NEXT: stc %r1, 8(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret1:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -176
+; VECTOR-NEXT: .cfi_def_cfa_offset 336
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: vgbm %v0, 0
+; VECTOR-NEXT: vleb %v0, 168(%r15), 15
+; VECTOR-NEXT: vlrepg %v1, 160(%r15)
+; VECTOR-NEXT: vsteg %v1, 0(%r13), 1
+; VECTOR-NEXT: vsteb %v0, 8(%r13), 15
+; VECTOR-NEXT: lmg %r13, %r15, 280(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty1 @Fnptr()
+ ret %Ty1 %C
+}
+
+%Ty2 = type {i128, i128}
+define void @arg2(%Ty2 %A) {
+; CHECK-LABEL: arg2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r3)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r3, 0(%r3)
+; CHECK-NEXT: lg %r4, 8(%r2)
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: stg %r0, 24(%r1)
+; CHECK-NEXT: stg %r3, 16(%r1)
+; CHECK-NEXT: stg %r4, 8(%r1)
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg2:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r2), 3
+; VECTOR-NEXT: vl %v1, 0(%r3), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vst %v1, 16(%r1), 3
+; VECTOR-NEXT: vst %v0, 0(%r1), 3
+; VECTOR-NEXT: br %r14
+ store %Ty2 %A, ptr @Dst
+ ret void
+}
+
+define void @call2() {
+; CHECK-LABEL: call2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 24(%r1)
+; CHECK-NEXT: lg %r2, 16(%r1)
+; CHECK-NEXT: lg %r3, 8(%r1)
+; CHECK-NEXT: lg %r1, 0(%r1)
+; CHECK-NEXT: stg %r0, 168(%r15)
+; CHECK-NEXT: stg %r2, 160(%r15)
+; CHECK-NEXT: stg %r3, 184(%r15)
+; CHECK-NEXT: la %r2, 176(%r15)
+; CHECK-NEXT: la %r3, 160(%r15)
+; CHECK-NEXT: stg %r1, 176(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call2:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vl %v0, 0(%r1), 3
+; VECTOR-NEXT: vl %v1, 16(%r1), 3
+; VECTOR-NEXT: la %r2, 176(%r15)
+; VECTOR-NEXT: la %r3, 160(%r15)
+; VECTOR-NEXT: vst %v1, 160(%r15), 3
+; VECTOR-NEXT: vst %v0, 176(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty2, ptr @Src
+ call void @Fnptr(%Ty2 %L)
+ ret void
+}
+
+define %Ty2 @ret2() {
+; CHECK-LABEL: ret2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lg %r0, 176(%r15)
+; CHECK-NEXT: lg %r1, 184(%r15)
+; CHECK-NEXT: lg %r2, 160(%r15)
+; CHECK-NEXT: lg %r3, 168(%r15)
+; CHECK-NEXT: stg %r0, 16(%r13)
+; CHECK-NEXT: stg %r1, 24(%r13)
+; CHECK-NEXT: stg %r2, 0(%r13)
+; CHECK-NEXT: stg %r3, 8(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret2:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: vl %v0, 160(%r15), 3
+; VECTOR-NEXT: vl %v1, 176(%r15), 3
+; VECTOR-NEXT: vst %v1, 16(%r13), 3
+; VECTOR-NEXT: vst %v0, 0(%r13), 3
+; VECTOR-NEXT: lmg %r13, %r15, 296(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty2 @Fnptr()
+ ret %Ty2 %C
+}
+
+%Ty3 = type {i72, i128}
+define void @arg3(%Ty3 %A) {
+; CHECK-LABEL: arg3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r3)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r3, 0(%r3)
+; CHECK-NEXT: lg %r4, 8(%r2)
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: stg %r0, 24(%r1)
+; CHECK-NEXT: stg %r3, 16(%r1)
+; CHECK-NEXT: stc %r4, 8(%r1)
+; CHECK-NEXT: sllg %r0, %r2, 56
+; CHECK-NEXT: rosbg %r0, %r4, 8, 63, 56
+; CHECK-NEXT: stg %r0, 0(%r1)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg3:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r3), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vl %v1, 0(%r2), 3
+; VECTOR-NEXT: vsteb %v1, 8(%r1), 15
+; VECTOR-NEXT: vst %v0, 16(%r1), 3
+; VECTOR-NEXT: vrepib %v0, 8
+; VECTOR-NEXT: vsrlb %v0, %v1, %v0
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
+; VECTOR-NEXT: br %r14
+ store %Ty3 %A, ptr @Dst
+ ret void
+}
+
+define void @call3() {
+; CHECK-LABEL: call3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 0(%r1)
+; CHECK-NEXT: sllg %r2, %r0, 8
+; CHECK-NEXT: lg %r3, 24(%r1)
+; CHECK-NEXT: lg %r4, 16(%r1)
+; CHECK-NEXT: ic %r2, 8(%r1)
+; CHECK-NEXT: srlg %r0, %r0, 56
+; CHECK-NEXT: stg %r3, 168(%r15)
+; CHECK-NEXT: stg %r4, 160(%r15)
+; CHECK-NEXT: stg %r2, 184(%r15)
+; CHECK-NEXT: la %r2, 176(%r15)
+; CHECK-NEXT: la %r3, 160(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call3:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vgbm %v0, 0
+; VECTOR-NEXT: vleb %v0, 8(%r1), 15
+; VECTOR-NEXT: vlrepg %v1, 0(%r1)
+; VECTOR-NEXT: vrepib %v2, 8
+; VECTOR-NEXT: vslb %v1, %v1, %v2
+; VECTOR-NEXT: vo %v0, %v0, %v1
+; VECTOR-NEXT: vl %v1, 16(%r1), 3
+; VECTOR-NEXT: la %r2, 176(%r15)
+; VECTOR-NEXT: la %r3, 160(%r15)
+; VECTOR-NEXT: vst %v1, 160(%r15), 3
+; VECTOR-NEXT: vst %v0, 176(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty3, ptr @Src
+ call void @Fnptr(%Ty3 %L)
+ ret void
+}
+
+define %Ty3 @ret3() {
+; CHECK-LABEL: ret3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lg %r0, 176(%r15)
+; CHECK-NEXT: lg %r1, 184(%r15)
+; CHECK-NEXT: lg %r2, 160(%r15)
+; CHECK-NEXT: llgc %r3, 168(%r15)
+; CHECK-NEXT: stg %r0, 16(%r13)
+; CHECK-NEXT: stg %r1, 24(%r13)
+; CHECK-NEXT: stg %r2, 0(%r13)
+; CHECK-NEXT: stc %r3, 8(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret3:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: vgbm %v0, 0
+; VECTOR-NEXT: vleb %v0, 168(%r15), 15
+; VECTOR-NEXT: vlrepg %v1, 160(%r15)
+; VECTOR-NEXT: vl %v2, 176(%r15), 3
+; VECTOR-NEXT: vst %v2, 16(%r13), 3
+; VECTOR-NEXT: vsteg %v1, 0(%r13), 1
+; VECTOR-NEXT: vsteb %v0, 8(%r13), 15
+; VECTOR-NEXT: lmg %r13, %r15, 296(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty3 @Fnptr()
+ ret %Ty3 %C
+}
+
+%Ty4 = type {float, i8, i16, i32, i64, i128, i8}
+define void @arg4(%Ty4 %A) {
+; CHECK-LABEL: arg4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: l %r0, 164(%r15)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r14, 0(%r6)
+; CHECK-NEXT: lg %r13, 8(%r6)
+; CHECK-NEXT: stc %r0, 40(%r1)
+; CHECK-NEXT: stg %r5, 16(%r1)
+; CHECK-NEXT: st %r4, 8(%r1)
+; CHECK-NEXT: sth %r3, 6(%r1)
+; CHECK-NEXT: stc %r2, 4(%r1)
+; CHECK-NEXT: ste %f0, 0(%r1)
+; CHECK-NEXT: stg %r13, 32(%r1)
+; CHECK-NEXT: stg %r14, 24(%r1)
+; CHECK-NEXT: lmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg4:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v1, 0(%r6), 3
+; VECTOR-NEXT: l %r0, 164(%r15)
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: stc %r0, 40(%r1)
+; VECTOR-NEXT: stg %r5, 16(%r1)
+; VECTOR-NEXT: st %r4, 8(%r1)
+; VECTOR-NEXT: sth %r3, 6(%r1)
+; VECTOR-NEXT: stc %r2, 4(%r1)
+; VECTOR-NEXT: ste %f0, 0(%r1)
+; VECTOR-NEXT: vst %v1, 24(%r1), 3
+; VECTOR-NEXT: br %r14
+ store %Ty4 %A, ptr @Dst
+ ret void
+}
+
+define void @call4() {
+; CHECK-LABEL: call4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -184
+; CHECK-NEXT: .cfi_def_cfa_offset 344
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r5, 16(%r1)
+; CHECK-NEXT: l %r4, 8(%r1)
+; CHECK-NEXT: le %f0, 0(%r1)
+; CHECK-NEXT: lg %r0, 24(%r1)
+; CHECK-NEXT: lb %r14, 40(%r1)
+; CHECK-NEXT: lg %r13, 32(%r1)
+; CHECK-NEXT: lh %r3, 6(%r1)
+; CHECK-NEXT: lb %r2, 4(%r1)
+; CHECK-NEXT: st %r14, 164(%r15)
+; CHECK-NEXT: stg %r13, 176(%r15)
+; CHECK-NEXT: la %r6, 168(%r15)
+; CHECK-NEXT: stg %r0, 168(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r6, %r15, 232(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call4:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r6, %r15, 48(%r15)
+; VECTOR-NEXT: .cfi_offset %r6, -112
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -184
+; VECTOR-NEXT: .cfi_def_cfa_offset 344
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: lh %r3, 6(%r1)
+; VECTOR-NEXT: lb %r2, 4(%r1)
+; VECTOR-NEXT: lb %r0, 40(%r1)
+; VECTOR-NEXT: lg %r5, 16(%r1)
+; VECTOR-NEXT: l %r4, 8(%r1)
+; VECTOR-NEXT: lde %f0, 0(%r1)
+; VECTOR-NEXT: vl %v1, 24(%r1), 3
+; VECTOR-NEXT: la %r6, 168(%r15)
+; VECTOR-NEXT: st %r0, 164(%r15)
+; VECTOR-NEXT: vst %v1, 168(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r6, %r15, 232(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty4, ptr @Src
+ call void @Fnptr(%Ty4 %L)
+ ret void
+}
+
+define %Ty4 @ret4() {
+; CHECK-LABEL: ret4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -208
+; CHECK-NEXT: .cfi_def_cfa_offset 368
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lb %r0, 164(%r15)
+; CHECK-NEXT: lh %r1, 166(%r15)
+; CHECK-NEXT: lg %r2, 192(%r15)
+; CHECK-NEXT: lg %r3, 184(%r15)
+; CHECK-NEXT: le %f0, 160(%r15)
+; CHECK-NEXT: l %r4, 168(%r15)
+; CHECK-NEXT: lg %r5, 176(%r15)
+; CHECK-NEXT: lb %r14, 200(%r15)
+; CHECK-NEXT: ste %f0, 0(%r13)
+; CHECK-NEXT: st %r4, 8(%r13)
+; CHECK-NEXT: stg %r5, 16(%r13)
+; CHECK-NEXT: stc %r14, 40(%r13)
+; CHECK-NEXT: stg %r3, 24(%r13)
+; CHECK-NEXT: stg %r2, 32(%r13)
+; CHECK-NEXT: sth %r1, 6(%r13)
+; CHECK-NEXT: stc %r0, 4(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 312(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret4:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -208
+; VECTOR-NEXT: .cfi_def_cfa_offset 368
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lb %r0, 164(%r15)
+; VECTOR-NEXT: lh %r1, 166(%r15)
+; VECTOR-NEXT: lb %r4, 200(%r15)
+; VECTOR-NEXT: lde %f0, 160(%r15)
+; VECTOR-NEXT: l %r2, 168(%r15)
+; VECTOR-NEXT: lg %r3, 176(%r15)
+; VECTOR-NEXT: vl %v1, 184(%r15), 3
+; VECTOR-NEXT: stc %r4, 40(%r13)
+; VECTOR-NEXT: vst %v1, 24(%r13), 3
+; VECTOR-NEXT: stg %r3, 16(%r13)
+; VECTOR-NEXT: st %r2, 8(%r13)
+; VECTOR-NEXT: sth %r1, 6(%r13)
+; VECTOR-NEXT: stc %r0, 4(%r13)
+; VECTOR-NEXT: ste %f0, 0(%r13)
+; VECTOR-NEXT: lmg %r13, %r15, 312(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty4 @Fnptr()
+ ret %Ty4 %C
+}
+
+%Ty5 = type [4 x i128]
+define void @arg5(%Ty5 %A) {
+; CHECK-LABEL: arg5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: lg %r0, 0(%r2)
+; CHECK-NEXT: lg %r1, 8(%r2)
+; CHECK-NEXT: lg %r2, 0(%r3)
+; CHECK-NEXT: lg %r3, 8(%r3)
+; CHECK-NEXT: lg %r14, 8(%r5)
+; CHECK-NEXT: lgrl %r13, Dst@GOT
+; CHECK-NEXT: lg %r5, 0(%r5)
+; CHECK-NEXT: lg %r12, 8(%r4)
+; CHECK-NEXT: lg %r4, 0(%r4)
+; CHECK-NEXT: stg %r14, 56(%r13)
+; CHECK-NEXT: stg %r5, 48(%r13)
+; CHECK-NEXT: stg %r12, 40(%r13)
+; CHECK-NEXT: stg %r4, 32(%r13)
+; CHECK-NEXT: stg %r3, 24(%r13)
+; CHECK-NEXT: stg %r2, 16(%r13)
+; CHECK-NEXT: stg %r1, 8(%r13)
+; CHECK-NEXT: stg %r0, 0(%r13)
+; CHECK-NEXT: lmg %r12, %r15, 96(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg5:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r2), 3
+; VECTOR-NEXT: vl %v1, 0(%r3), 3
+; VECTOR-NEXT: vl %v2, 0(%r4), 3
+; VECTOR-NEXT: vl %v3, 0(%r5), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vst %v3, 48(%r1), 3
+; VECTOR-NEXT: vst %v2, 32(%r1), 3
+; VECTOR-NEXT: vst %v1, 16(%r1), 3
+; VECTOR-NEXT: vst %v0, 0(%r1), 3
+; VECTOR-NEXT: br %r14
+ store %Ty5 %A, ptr @Dst
+ ret void
+}
+
+define void @call5() {
+; CHECK-LABEL: call5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -224
+; CHECK-NEXT: .cfi_def_cfa_offset 384
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 0(%r1)
+; CHECK-NEXT: lg %r2, 8(%r1)
+; CHECK-NEXT: lg %r3, 16(%r1)
+; CHECK-NEXT: lg %r4, 24(%r1)
+; CHECK-NEXT: lg %r5, 56(%r1)
+; CHECK-NEXT: lg %r14, 48(%r1)
+; CHECK-NEXT: lg %r13, 40(%r1)
+; CHECK-NEXT: lg %r1, 32(%r1)
+; CHECK-NEXT: stg %r5, 168(%r15)
+; CHECK-NEXT: stg %r14, 160(%r15)
+; CHECK-NEXT: stg %r13, 184(%r15)
+; CHECK-NEXT: stg %r1, 176(%r15)
+; CHECK-NEXT: stg %r4, 200(%r15)
+; CHECK-NEXT: stg %r3, 192(%r15)
+; CHECK-NEXT: stg %r2, 216(%r15)
+; CHECK-NEXT: la %r2, 208(%r15)
+; CHECK-NEXT: la %r3, 192(%r15)
+; CHECK-NEXT: la %r4, 176(%r15)
+; CHECK-NEXT: la %r5, 160(%r15)
+; CHECK-NEXT: stg %r0, 208(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r13, %r15, 328(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call5:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -224
+; VECTOR-NEXT: .cfi_def_cfa_offset 384
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vl %v0, 0(%r1), 3
+; VECTOR-NEXT: vl %v1, 16(%r1), 3
+; VECTOR-NEXT: vl %v2, 32(%r1), 3
+; VECTOR-NEXT: vl %v3, 48(%r1), 3
+; VECTOR-NEXT: la %r2, 208(%r15)
+; VECTOR-NEXT: la %r3, 192(%r15)
+; VECTOR-NEXT: la %r4, 176(%r15)
+; VECTOR-NEXT: la %r5, 160(%r15)
+; VECTOR-NEXT: vst %v3, 160(%r15), 3
+; VECTOR-NEXT: vst %v2, 176(%r15), 3
+; VECTOR-NEXT: vst %v1, 192(%r15), 3
+; VECTOR-NEXT: vst %v0, 208(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 336(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty5, ptr @Src
+ call void @Fnptr(%Ty5 %L)
+ ret void
+}
+
+define %Ty5 @ret5() {
+; CHECK-LABEL: ret5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -224
+; CHECK-NEXT: .cfi_def_cfa_offset 384
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lg %r0, 168(%r15)
+; CHECK-NEXT: lg %r1, 160(%r15)
+; CHECK-NEXT: lg %r2, 184(%r15)
+; CHECK-NEXT: lg %r3, 176(%r15)
+; CHECK-NEXT: lg %r4, 208(%r15)
+; CHECK-NEXT: lg %r5, 216(%r15)
+; CHECK-NEXT: lg %r14, 192(%r15)
+; CHECK-NEXT: lg %r12, 200(%r15)
+; CHECK-NEXT: stg %r4, 48(%r13)
+; CHECK-NEXT: stg %r5, 56(%r13)
+; CHECK-NEXT: stg %r14, 32(%r13)
+; CHECK-NEXT: stg %r12, 40(%r13)
+; CHECK-NEXT: stg %r3, 16(%r13)
+; CHECK-NEXT: stg %r2, 24(%r13)
+; CHECK-NEXT: stg %r1, 0(%r13)
+; CHECK-NEXT: stg %r0, 8(%r13)
+; CHECK-NEXT: lmg %r12, %r15, 320(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret5:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -224
+; VECTOR-NEXT: .cfi_def_cfa_offset 384
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: vl %v0, 160(%r15), 3
+; VECTOR-NEXT: vl %v1, 176(%r15), 3
+; VECTOR-NEXT: vl %v2, 192(%r15), 3
+; VECTOR-NEXT: vl %v3, 208(%r15), 3
+; VECTOR-NEXT: vst %v3, 48(%r13), 3
+; VECTOR-NEXT: vst %v2, 32(%r13), 3
+; VECTOR-NEXT: vst %v1, 16(%r13), 3
+; VECTOR-NEXT: vst %v0, 0(%r13), 3
+; VECTOR-NEXT: lmg %r13, %r15, 328(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty5 @Fnptr()
+ ret %Ty5 %C
+}
+
+%Ty6 = type [2 x i72]
+define void @arg6(%Ty6 %A) {
+; CHECK-LABEL: arg6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r3)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r4, 8(%r2)
+; CHECK-NEXT: lg %r3, 0(%r3)
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: stc %r0, 24(%r1)
+; CHECK-NEXT: stc %r4, 8(%r1)
+; CHECK-NEXT: sllg %r3, %r3, 56
+; CHECK-NEXT: rosbg %r3, %r0, 8, 63, 56
+; CHECK-NEXT: stg %r3, 16(%r1)
+; CHECK-NEXT: sllg %r0, %r2, 56
+; CHECK-NEXT: rosbg %r0, %r4, 8, 63, 56
+; CHECK-NEXT: stg %r0, 0(%r1)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg6:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r2), 3
+; VECTOR-NEXT: vl %v1, 0(%r3), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vsteb %v1, 24(%r1), 15
+; VECTOR-NEXT: vrepib %v2, 8
+; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
+; VECTOR-NEXT: vsrlb %v1, %v1, %v2
+; VECTOR-NEXT: vsrlb %v0, %v0, %v2
+; VECTOR-NEXT: vsteg %v1, 16(%r1), 1
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
+; VECTOR-NEXT: br %r14
+ store %Ty6 %A, ptr @Dst
+ ret void
+}
+
+define void @call6() {
+; CHECK-LABEL: call6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 0(%r1)
+; CHECK-NEXT: lg %r2, 16(%r1)
+; CHECK-NEXT: sllg %r3, %r0, 8
+; CHECK-NEXT: sllg %r4, %r2, 8
+; CHECK-NEXT: ic %r4, 24(%r1)
+; CHECK-NEXT: ic %r3, 8(%r1)
+; CHECK-NEXT: srlg %r0, %r0, 56
+; CHECK-NEXT: srlg %r1, %r2, 56
+; CHECK-NEXT: stg %r4, 168(%r15)
+; CHECK-NEXT: stg %r1, 160(%r15)
+; CHECK-NEXT: stg %r3, 184(%r15)
+; CHECK-NEXT: la %r2, 176(%r15)
+; CHECK-NEXT: la %r3, 160(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call6:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vgbm %v1, 0
+; VECTOR-NEXT: vleb %v1, 8(%r1), 15
+; VECTOR-NEXT: vlrepg %v2, 0(%r1)
+; VECTOR-NEXT: vrepib %v3, 8
+; VECTOR-NEXT: vslb %v2, %v2, %v3
+; VECTOR-NEXT: vgbm %v0, 0
+; VECTOR-NEXT: vo %v1, %v1, %v2
+; VECTOR-NEXT: vleb %v0, 24(%r1), 15
+; VECTOR-NEXT: vlrepg %v2, 16(%r1)
+; VECTOR-NEXT: vslb %v2, %v2, %v3
+; VECTOR-NEXT: vo %v0, %v0, %v2
+; VECTOR-NEXT: la %r2, 176(%r15)
+; VECTOR-NEXT: la %r3, 160(%r15)
+; VECTOR-NEXT: vst %v0, 160(%r15), 3
+; VECTOR-NEXT: vst %v1, 176(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty6, ptr @Src
+ call void @Fnptr(%Ty6 %L)
+ ret void
+}
+
+define %Ty6 @ret6() {
+; CHECK-LABEL: ret6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lg %r0, 176(%r15)
+; CHECK-NEXT: llgc %r1, 184(%r15)
+; CHECK-NEXT: lg %r2, 160(%r15)
+; CHECK-NEXT: llgc %r3, 168(%r15)
+; CHECK-NEXT: stg %r0, 16(%r13)
+; CHECK-NEXT: stc %r1, 24(%r13)
+; CHECK-NEXT: stg %r2, 0(%r13)
+; CHECK-NEXT: stc %r3, 8(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: ret6:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
+; VECTOR-NEXT: .cfi_offset %r13, -56
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgr %r13, %r2
+; VECTOR-NEXT: la %r2, 160(%r15)
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: vgbm %v0, 0
+; VECTOR-NEXT: vgbm %v1, 0
+; VECTOR-NEXT: vleb %v1, 168(%r15), 15
+; VECTOR-NEXT: vleb %v0, 184(%r15), 15
+; VECTOR-NEXT: vlrepg %v2, 160(%r15)
+; VECTOR-NEXT: vlrepg %v3, 176(%r15)
+; VECTOR-NEXT: vsteg %v3, 16(%r13), 1
+; VECTOR-NEXT: vsteb %v0, 24(%r13), 15
+; VECTOR-NEXT: vsteg %v2, 0(%r13), 1
+; VECTOR-NEXT: vsteb %v1, 8(%r13), 15
+; VECTOR-NEXT: lmg %r13, %r15, 296(%r15)
+; VECTOR-NEXT: br %r14
+ %C = call %Ty6 @Fnptr()
+ ret %Ty6 %C
+}
+
+%Ty7 = type {i128}
+define void @arg7(%Ty7 %A, %Ty7 %B) {
+; CHECK-LABEL: arg7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r2)
+; CHECK-NEXT: lgrl %r1, Dst@GOT
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: lg %r4, 8(%r3)
+; CHECK-NEXT: lg %r3, 0(%r3)
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: stg %r4, 24(%r1)
+; CHECK-NEXT: stg %r3, 16(%r1)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: arg7:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: vl %v0, 0(%r3), 3
+; VECTOR-NEXT: vl %v1, 0(%r2), 3
+; VECTOR-NEXT: lgrl %r1, Dst@GOT
+; VECTOR-NEXT: vst %v1, 0(%r1), 3
+; VECTOR-NEXT: vst %v0, 16(%r1), 3
+; VECTOR-NEXT: br %r14
+ store %Ty7 %A, ptr @Dst
+ %D2 = getelementptr %Ty7, ptr @Dst, i32 1
+ store %Ty7 %B, ptr %D2
+ ret void
+}
+
+define void @call7() {
+; CHECK-LABEL: call7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-NEXT: lgrl %r1, Src@GOT
+; CHECK-NEXT: lg %r0, 24(%r1)
+; CHECK-NEXT: lg %r2, 16(%r1)
+; CHECK-NEXT: lg %r3, 8(%r1)
+; CHECK-NEXT: lg %r1, 0(%r1)
+; CHECK-NEXT: stg %r0, 168(%r15)
+; CHECK-NEXT: stg %r2, 160(%r15)
+; CHECK-NEXT: stg %r3, 184(%r15)
+; CHECK-NEXT: la %r2, 176(%r15)
+; CHECK-NEXT: la %r3, 160(%r15)
+; CHECK-NEXT: stg %r1, 176(%r15)
+; CHECK-NEXT: brasl %r14, Fnptr@PLT
+; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-NEXT: br %r14
+;
+; VECTOR-LABEL: call7:
+; VECTOR: # %bb.0:
+; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
+; VECTOR-NEXT: .cfi_offset %r14, -48
+; VECTOR-NEXT: .cfi_offset %r15, -40
+; VECTOR-NEXT: aghi %r15, -192
+; VECTOR-NEXT: .cfi_def_cfa_offset 352
+; VECTOR-NEXT: lgrl %r1, Src@GOT
+; VECTOR-NEXT: vl %v0, 0(%r1), 3
+; VECTOR-NEXT: vl %v1, 16(%r1), 3
+; VECTOR-NEXT: la %r2, 176(%r15)
+; VECTOR-NEXT: la %r3, 160(%r15)
+; VECTOR-NEXT: vst %v1, 160(%r15), 3
+; VECTOR-NEXT: vst %v0, 176(%r15), 3
+; VECTOR-NEXT: brasl %r14, Fnptr@PLT
+; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
+; VECTOR-NEXT: br %r14
+ %L = load %Ty7, ptr @Src
+ %S2 = getelementptr %Ty7, ptr @Src, i32 1
+ %L2 = load %Ty7, ptr %S2
+ call void @Fnptr(%Ty7 %L, %Ty7 %L2)
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll
index 1bfa055..f77abd9 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll
@@ -6,14 +6,15 @@ define float @f1(ptr %src, float %b) {
; CHECK-LABEL: f1:
; CHECK: le [[F:%f[0-9]+]], 0(%r2)
; CHECK: [[L:\.L.+]]:
-; CHECK: lgdr [[RI:%r[0-9]+]], [[F]]
-; CHECK: aebr [[F]], %f0
-; CHECK: lgdr [[RO:%r[0-9]+]], [[F]]
+; CHECK: ler [[COPY_F:%f[0-9]+]], [[F]]
+; CHECK-NEXT: aebr [[F]], %f0
+; CHECK-NEXT: lgdr [[RO:%r[0-9]+]], [[F]]
; CHECK: srlg [[RO]], [[RO]], 32
+; CHECK: lgdr [[RI:%r[0-9]+]], [[COPY_F]]
; CHECK: srlg [[RI]], [[RI]], 32
; CHECK: cs [[RI]], [[RO]], 0(%r2)
-; CHECK: sllg [[RI]], [[RI]], 32
-; CHECK: ldgr [[F]], [[RI]]
+; CHECK: sllg [[RO]], [[RI]], 32
+; CHECK: ldgr [[F]], [[RO]]
; CHECK: jl [[L]]
; CHECK: ler %f0, [[F]]
; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll
index 3f4ad31..ffe2569 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll
@@ -6,14 +6,15 @@ define float @f1(ptr %src, float %b) {
; CHECK-LABEL: f1:
; CHECK: le [[F:%f[0-9]+]], 0(%r2)
; CHECK: [[L:\.L.+]]:
-; CHECK: lgdr [[RI:%r[0-9]+]], [[F]]
-; CHECK: sebr [[F]], %f0
-; CHECK: lgdr [[RO:%r[0-9]+]], [[F]]
+; CHECK: ler [[COPY_F:%f[0-9]+]], [[F]]
+; CHECK-NEXT: sebr [[F]], %f0
+; CHECK-NEXT: lgdr [[RO:%r[0-9]+]], [[F]]
; CHECK: srlg [[RO]], [[RO]], 32
+; CHECK: lgdr [[RI:%r[0-9]+]], [[COPY_F]]
; CHECK: srlg [[RI]], [[RI]], 32
; CHECK: cs [[RI]], [[RO]], 0(%r2)
-; CHECK: sllg [[RI]], [[RI]], 32
-; CHECK: ldgr [[F]], [[RI]]
+; CHECK: sllg [[RO]], [[RI]], 32
+; CHECK: ldgr [[F]], [[RO]]
; CHECK: jl [[L]]
; CHECK: ler %f0, [[F]]
; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/condfolding.ll b/llvm/test/CodeGen/SystemZ/condfolding.ll
new file mode 100644
index 0000000..07d8a24
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/condfolding.ll
@@ -0,0 +1,28 @@
+; Test that a conditional branch with a discoverably trivial condition
+; does not result in an invalid conditional branch instruction.
+;
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
+; RUN: --stop-after=systemz-isel | FileCheck %s
+
+@g_1 = dso_local local_unnamed_addr global i64 0, align 8
+@g_2 = dso_local local_unnamed_addr global i32 0, align 4
+
+define dso_local void @f1() local_unnamed_addr #1 {
+entry:
+;CHECK-LABEL: f1
+;CHECK-NOT: BRC 14, 0, %bb.2
+ %0 = load i64, ptr @g_1, align 8
+ %tobool.not = icmp eq i64 %0, 0
+ %sub.i = select i1 %tobool.not, i8 4, i8 3
+ %conv1 = zext nneg i8 %sub.i to i32
+ store i32 %conv1, ptr @g_2, align 4
+ %.pr = load i32, ptr @g_2, align 4
+ %tobool5.not = icmp eq i32 %.pr, 0
+ br i1 %tobool5.not, label %for.cond, label %lbl_1
+
+lbl_1:
+ br label %lbl_1
+
+for.cond:
+ br label %for.cond
+}
diff --git a/llvm/test/CodeGen/SystemZ/inline-asm-flag-output-01.ll b/llvm/test/CodeGen/SystemZ/inline-asm-flag-output-01.ll
index 6b8746e..a86420e 100644
--- a/llvm/test/CodeGen/SystemZ/inline-asm-flag-output-01.ll
+++ b/llvm/test/CodeGen/SystemZ/inline-asm-flag-output-01.ll
@@ -736,3 +736,40 @@ exit:
ret void
}
+; Test INLINEASM defines CC.
+@wait_fence = global i32 0, align 4
+@bit_cc = global i32 0, align 4
+define void @test_inlineasm_define_cc() {
+; CHECK-LABEL: test_inlineasm_define_cc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, wait_fence@GOT
+; CHECK-NEXT: chsi 0(%r1), 0
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB29_1: # %while.body.lr.ph
+; CHECK-NEXT: lgrl %r1, bit_cc@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r1)
+; CHECK-NEXT: .LBB29_2: # %while.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: j .LBB29_2
+entry:
+ %0 = load i32, ptr @wait_fence, align 4
+ %tobool.not = icmp eq i32 %0, 0
+ br i1 %tobool.not, label %while.end, label %while.body.lr.ph
+
+while.body.lr.ph:
+ %1 = tail call i32 asm "", "={@cc}"()
+ %2 = icmp ult i32 %1, 4
+ tail call void @llvm.assume(i1 %2)
+ store i32 %1, ptr @bit_cc, align 4
+ br label %while.body
+
+while.body:
+ br label %while.body
+
+while.end:
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
index 678d9a9..ff9b6a3 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
+++ b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
@@ -22,10 +22,10 @@ define void @main(i16 %in) {
; CHECK-NEXT: locghile %r3, 1
; CHECK-NEXT: o %r0, 0(%r1)
; CHECK-NEXT: larl %r1, g_222
-; CHECK-NEXT: lghi %r5, 0
; CHECK-NEXT: dsgfr %r2, %r0
+; CHECK-NEXT: lghi %r3, 0
; CHECK-NEXT: stgrl %r2, g_39
-; CHECK-NEXT: stc %r5, 19(%r1)
+; CHECK-NEXT: stc %r3, 19(%r1)
; CHECK-NEXT: br %r14
%tmp = load i32, ptr @g_151, align 4
%tmp3 = or i32 %tmp, 1
diff --git a/llvm/test/CodeGen/SystemZ/stackmap.ll b/llvm/test/CodeGen/SystemZ/stackmap.ll
index 05b8de7..f414ea3 100644
--- a/llvm/test/CodeGen/SystemZ/stackmap.ll
+++ b/llvm/test/CodeGen/SystemZ/stackmap.ll
@@ -84,14 +84,14 @@
; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 65535
+; CHECK-NEXT: .long -1
; SmallConstant
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 65535
+; CHECK-NEXT: .long -1
; SmallConstant
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 0
diff --git a/llvm/test/CodeGen/SystemZ/vec-load-element.ll b/llvm/test/CodeGen/SystemZ/vec-load-element.ll
index 2baaed1..9bef279 100644
--- a/llvm/test/CodeGen/SystemZ/vec-load-element.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-load-element.ll
@@ -5,8 +5,8 @@
; CHECK-LABEL: .LBB0_1:
; CHECK-NOT: l %r
; CHECK-NOT: vlvgf
-; CHECK: pfd
-; CHECK: vlef
+; CHECK-DAG: pfd
+; CHECK-DAG: vlef
%type0 = type { i32, [400 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
@Mem = external global [150 x %type0], align 4
diff --git a/llvm/test/CodeGen/SystemZ/vec-max-05.ll b/llvm/test/CodeGen/SystemZ/vec-max-05.ll
index 09d40c7..ea4408f 100644
--- a/llvm/test/CodeGen/SystemZ/vec-max-05.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-max-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Test vector maximum on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
@@ -23,8 +24,9 @@ declare fp128 @llvm.maximum.f128(fp128, fp128)
; Test the fmax library function.
define double @f1(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f1:
-; CHECK: wfmaxdb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmaxdb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call double @fmax(double %val1, double %val2) readnone
ret double %ret
}
@@ -32,8 +34,9 @@ define double @f1(double %dummy, double %val1, double %val2) {
; Test the f64 maxnum intrinsic.
define double @f2(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f2:
-; CHECK: wfmaxdb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmaxdb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call double @llvm.maxnum.f64(double %val1, double %val2)
ret double %ret
}
@@ -41,8 +44,9 @@ define double @f2(double %dummy, double %val1, double %val2) {
; Test the f64 maximum intrinsic.
define double @f3(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f3:
-; CHECK: wfmaxdb %f0, %f2, %f4, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmaxdb %f0, %f2, %f4, 1
+; CHECK-NEXT: br %r14
%ret = call double @llvm.maximum.f64(double %val1, double %val2)
ret double %ret
}
@@ -50,9 +54,10 @@ define double @f3(double %dummy, double %val1, double %val2) {
; Test a f64 constant compare/select resulting in maxnum.
define double @f4(double %dummy, double %val) {
; CHECK-LABEL: f4:
-; CHECK: lzdr [[REG:%f[0-9]+]]
-; CHECK: wfmaxdb %f0, %f2, [[REG]], 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzdr %f0
+; CHECK-NEXT: wfmaxdb %f0, %f2, %f0, 4
+; CHECK-NEXT: br %r14
%cmp = fcmp ogt double %val, 0.0
%ret = select i1 %cmp, double %val, double 0.0
ret double %ret
@@ -61,30 +66,34 @@ define double @f4(double %dummy, double %val) {
; Test a f64 constant compare/select resulting in maximum.
define double @f5(double %dummy, double %val) {
; CHECK-LABEL: f5:
-; CHECK: ltdbr %f1, %f2
-; CHECK-NEXT: ldr %f0, %f2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ltdbr %f1, %f2
+; CHECK-NEXT: ldr %f0, %f2
+; CHECK-NEXT: bnler %r14
+; CHECK-NEXT: .LBB4_1:
+; CHECK-NEXT: lzdr %f0
+; CHECK-NEXT: br %r14
%cmp = fcmp ugt double %val, 0.0
%ret = select i1 %cmp, double %val, double 0.0
ret double %ret
}
; Test the v2f64 maxnum intrinsic.
-define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
- <2 x double> %val2) {
+define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1, <2 x double> %val2) {
; CHECK-LABEL: f6:
-; CHECK: vfmaxdb %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmaxdb %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
%ret = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %val1, <2 x double> %val2)
ret <2 x double> %ret
}
; Test the v2f64 maximum intrinsic.
-define <2 x double> @f7(<2 x double> %dummy, <2 x double> %val1,
- <2 x double> %val2) {
+define <2 x double> @f7(<2 x double> %dummy, <2 x double> %val1, <2 x double> %val2) {
; CHECK-LABEL: f7:
-; CHECK: vfmaxdb %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmaxdb %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
%ret = call <2 x double> @llvm.maximum.v2f64(<2 x double> %val1, <2 x double> %val2)
ret <2 x double> %ret
}
@@ -92,8 +101,9 @@ define <2 x double> @f7(<2 x double> %dummy, <2 x double> %val1,
; Test the fmaxf library function.
define float @f11(float %dummy, float %val1, float %val2) {
; CHECK-LABEL: f11:
-; CHECK: wfmaxsb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmaxsb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call float @fmaxf(float %val1, float %val2) readnone
ret float %ret
}
@@ -101,11 +111,28 @@ define float @f11(float %dummy, float %val1, float %val2) {
; Test the f16 maxnum intrinsic.
define half @f12_half(half %dummy, half %val1, half %val2) {
; CHECK-LABEL: f12_half:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: wfmaxsb %f0, %f0, %f9, 4
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Spill
+; CHECK-NEXT: std %f9, 160(%r15) # 8-byte Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: ldr %f0, %f4
+; CHECK-NEXT: ldr %f8, %f2
+; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
+; CHECK-NEXT: ldr %f9, %f0
+; CHECK-NEXT: ldr %f0, %f8
+; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
+; CHECK-NEXT: wfmaxsb %f0, %f0, %f9, 4
+; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
+; CHECK-NEXT: ld %f8, 168(%r15) # 8-byte Reload
+; CHECK-NEXT: ld %f9, 160(%r15) # 8-byte Reload
+; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-NEXT: br %r14
%ret = call half @llvm.maxnum.f16(half %val1, half %val2)
ret half %ret
}
@@ -113,8 +140,9 @@ define half @f12_half(half %dummy, half %val1, half %val2) {
; Test the f32 maxnum intrinsic.
define float @f12(float %dummy, float %val1, float %val2) {
; CHECK-LABEL: f12:
-; CHECK: wfmaxsb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmaxsb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call float @llvm.maxnum.f32(float %val1, float %val2)
ret float %ret
}
@@ -122,8 +150,9 @@ define float @f12(float %dummy, float %val1, float %val2) {
; Test the f32 maximum intrinsic.
define float @f13(float %dummy, float %val1, float %val2) {
; CHECK-LABEL: f13:
-; CHECK: wfmaxsb %f0, %f2, %f4, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmaxsb %f0, %f2, %f4, 1
+; CHECK-NEXT: br %r14
%ret = call float @llvm.maximum.f32(float %val1, float %val2)
ret float %ret
}
@@ -131,9 +160,10 @@ define float @f13(float %dummy, float %val1, float %val2) {
; Test a f32 constant compare/select resulting in maxnum.
define float @f14(float %dummy, float %val) {
; CHECK-LABEL: f14:
-; CHECK: lzer [[REG:%f[0-9]+]]
-; CHECK: wfmaxsb %f0, %f2, [[REG]], 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzer %f0
+; CHECK-NEXT: wfmaxsb %f0, %f2, %f0, 4
+; CHECK-NEXT: br %r14
%cmp = fcmp ogt float %val, 0.0
%ret = select i1 %cmp, float %val, float 0.0
ret float %ret
@@ -142,9 +172,13 @@ define float @f14(float %dummy, float %val) {
; Test a f32 constant compare/select resulting in maximum.
define float @f15(float %dummy, float %val) {
; CHECK-LABEL: f15:
-; CHECK: ltebr %f1, %f2
-; CHECK: ldr %f0, %f2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ltebr %f1, %f2
+; CHECK-NEXT: ldr %f0, %f2
+; CHECK-NEXT: bnler %r14
+; CHECK-NEXT: .LBB12_1:
+; CHECK-NEXT: lzer %f0
+; CHECK-NEXT: br %r14
%cmp = fcmp ugt float %val, 0.0
%ret = select i1 %cmp, float %val, float 0.0
ret float %ret
@@ -152,20 +186,22 @@ define float @f15(float %dummy, float %val) {
; Test the v4f32 maxnum intrinsic.
define <4 x float> @f16(<4 x float> %dummy, <4 x float> %val1,
- <4 x float> %val2) {
; CHECK-LABEL: f16:
-; CHECK: vfmaxsb %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmaxsb %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
+ <4 x float> %val2) {
%ret = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %val1, <4 x float> %val2)
ret <4 x float> %ret
}
; Test the v4f32 maximum intrinsic.
define <4 x float> @f17(<4 x float> %dummy, <4 x float> %val1,
- <4 x float> %val2) {
; CHECK-LABEL: f17:
-; CHECK: vfmaxsb %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmaxsb %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
+ <4 x float> %val2) {
%ret = call <4 x float> @llvm.maximum.v4f32(<4 x float> %val1, <4 x float> %val2)
ret <4 x float> %ret
}
@@ -173,11 +209,12 @@ define <4 x float> @f17(<4 x float> %dummy, <4 x float> %val1,
; Test the fmaxl library function.
define void @f21(ptr %ptr1, ptr %ptr2, ptr %dst) {
; CHECK-LABEL: f21:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
-; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
-; CHECK: vst [[RES]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: wfmaxxb %v0, %v0, %v1, 4
+; CHECK-NEXT: vst %v0, 0(%r4), 3
+; CHECK-NEXT: br %r14
%val1 = load fp128, ptr %ptr1
%val2 = load fp128, ptr %ptr2
%res = call fp128 @fmaxl(fp128 %val1, fp128 %val2) readnone
@@ -188,11 +225,12 @@ define void @f21(ptr %ptr1, ptr %ptr2, ptr %dst) {
; Test the f128 maxnum intrinsic.
define void @f22(ptr %ptr1, ptr %ptr2, ptr %dst) {
; CHECK-LABEL: f22:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
-; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
-; CHECK: vst [[RES]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: wfmaxxb %v0, %v0, %v1, 4
+; CHECK-NEXT: vst %v0, 0(%r4), 3
+; CHECK-NEXT: br %r14
%val1 = load fp128, ptr %ptr1
%val2 = load fp128, ptr %ptr2
%res = call fp128 @llvm.maxnum.f128(fp128 %val1, fp128 %val2)
@@ -203,11 +241,12 @@ define void @f22(ptr %ptr1, ptr %ptr2, ptr %dst) {
; Test the f128 maximum intrinsic.
define void @f23(ptr %ptr1, ptr %ptr2, ptr %dst) {
; CHECK-LABEL: f23:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
-; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 1
-; CHECK: vst [[RES]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: wfmaxxb %v0, %v0, %v1, 1
+; CHECK-NEXT: vst %v0, 0(%r4), 3
+; CHECK-NEXT: br %r14
%val1 = load fp128, ptr %ptr1
%val2 = load fp128, ptr %ptr2
%res = call fp128 @llvm.maximum.f128(fp128 %val1, fp128 %val2)
@@ -218,11 +257,12 @@ define void @f23(ptr %ptr1, ptr %ptr2, ptr %dst) {
; Test a f128 constant compare/select resulting in maxnum.
define void @f24(ptr %ptr, ptr %dst) {
; CHECK-LABEL: f24:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
-; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
-; CHECK: vst [[RES]], 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vzero %v1
+; CHECK-NEXT: wfmaxxb %v0, %v0, %v1, 4
+; CHECK-NEXT: vst %v0, 0(%r3), 3
+; CHECK-NEXT: br %r14
%val = load fp128, ptr %ptr
%cmp = fcmp ogt fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
@@ -233,11 +273,16 @@ define void @f24(ptr %ptr, ptr %dst) {
; Test a f128 constant compare/select resulting in maximum.
define void @f25(ptr %ptr, ptr %dst) {
; CHECK-LABEL: f25:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
-; CHECK: wfcxb [[REG1]], [[REG2]]
-; CHECK: vst [[RES]], 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vzero %v1
+; CHECK-NEXT: wfcxb %v0, %v1
+; CHECK-NEXT: jnle .LBB19_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: vzero %v0
+; CHECK-NEXT: .LBB19_2:
+; CHECK-NEXT: vst %v0, 0(%r3), 3
+; CHECK-NEXT: br %r14
%val = load fp128, ptr %ptr
%cmp = fcmp ugt fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
diff --git a/llvm/test/CodeGen/SystemZ/vec-min-05.ll b/llvm/test/CodeGen/SystemZ/vec-min-05.ll
index b7b288f..f1e7193 100644
--- a/llvm/test/CodeGen/SystemZ/vec-min-05.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-min-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Test vector minimum on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
@@ -23,8 +24,9 @@ declare fp128 @llvm.minimum.f128(fp128, fp128)
; Test the fmin library function.
define double @f1(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f1:
-; CHECK: wfmindb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmindb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call double @fmin(double %val1, double %val2) readnone
ret double %ret
}
@@ -32,8 +34,9 @@ define double @f1(double %dummy, double %val1, double %val2) {
; Test the f64 minnum intrinsic.
define double @f2(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f2:
-; CHECK: wfmindb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmindb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call double @llvm.minnum.f64(double %val1, double %val2)
ret double %ret
}
@@ -41,8 +44,9 @@ define double @f2(double %dummy, double %val1, double %val2) {
; Test the f64 minimum intrinsic.
define double @f3(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f3:
-; CHECK: wfmindb %f0, %f2, %f4, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfmindb %f0, %f2, %f4, 1
+; CHECK-NEXT: br %r14
%ret = call double @llvm.minimum.f64(double %val1, double %val2)
ret double %ret
}
@@ -50,9 +54,10 @@ define double @f3(double %dummy, double %val1, double %val2) {
; Test a f64 constant compare/select resulting in minnum.
define double @f4(double %dummy, double %val) {
; CHECK-LABEL: f4:
-; CHECK: lzdr [[REG:%f[0-9]+]]
-; CHECK: wfmindb %f0, %f2, [[REG]], 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzdr %f0
+; CHECK-NEXT: wfmindb %f0, %f2, %f0, 4
+; CHECK-NEXT: br %r14
%cmp = fcmp olt double %val, 0.0
%ret = select i1 %cmp, double %val, double 0.0
ret double %ret
@@ -61,30 +66,34 @@ define double @f4(double %dummy, double %val) {
; Test a f64 constant compare/select resulting in minimum.
define double @f5(double %dummy, double %val) {
; CHECK-LABEL: f5:
-; CHECK: ltdbr %f1, %f2
-; CHECK-NEXT: ldr %f0, %f2
-; CHECK: bnher %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ltdbr %f1, %f2
+; CHECK-NEXT: ldr %f0, %f2
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB4_1:
+; CHECK-NEXT: lzdr %f0
+; CHECK-NEXT: br %r14
%cmp = fcmp ult double %val, 0.0
%ret = select i1 %cmp, double %val, double 0.0
ret double %ret
}
; Test the v2f64 minnum intrinsic.
-define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
- <2 x double> %val2) {
+define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1, <2 x double> %val2) {
; CHECK-LABEL: f6:
-; CHECK: vfmindb %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmindb %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
%ret = call <2 x double> @llvm.minnum.v2f64(<2 x double> %val1, <2 x double> %val2)
ret <2 x double> %ret
}
; Test the v2f64 minimum intrinsic.
-define <2 x double> @f7(<2 x double> %dummy, <2 x double> %val1,
- <2 x double> %val2) {
+define <2 x double> @f7(<2 x double> %dummy, <2 x double> %val1, <2 x double> %val2) {
; CHECK-LABEL: f7:
-; CHECK: vfmindb %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmindb %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
%ret = call <2 x double> @llvm.minimum.v2f64(<2 x double> %val1, <2 x double> %val2)
ret <2 x double> %ret
}
@@ -92,8 +101,9 @@ define <2 x double> @f7(<2 x double> %dummy, <2 x double> %val1,
; Test the fminf library function.
define float @f11(float %dummy, float %val1, float %val2) {
; CHECK-LABEL: f11:
-; CHECK: wfminsb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfminsb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call float @fminf(float %val1, float %val2) readnone
ret float %ret
}
@@ -101,11 +111,28 @@ define float @f11(float %dummy, float %val1, float %val2) {
; Test the f16 minnum intrinsic.
define half @f12_half(half %dummy, half %val1, half %val2) {
; CHECK-LABEL: f12_half:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: wfminsb %f0, %f0, %f9, 4
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Spill
+; CHECK-NEXT: std %f9, 160(%r15) # 8-byte Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: ldr %f0, %f4
+; CHECK-NEXT: ldr %f8, %f2
+; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
+; CHECK-NEXT: ldr %f9, %f0
+; CHECK-NEXT: ldr %f0, %f8
+; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
+; CHECK-NEXT: wfminsb %f0, %f0, %f9, 4
+; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
+; CHECK-NEXT: ld %f8, 168(%r15) # 8-byte Reload
+; CHECK-NEXT: ld %f9, 160(%r15) # 8-byte Reload
+; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-NEXT: br %r14
%ret = call half @llvm.minnum.f16(half %val1, half %val2)
ret half %ret
}
@@ -113,8 +140,9 @@ define half @f12_half(half %dummy, half %val1, half %val2) {
; Test the f32 minnum intrinsic.
define float @f12(float %dummy, float %val1, float %val2) {
; CHECK-LABEL: f12:
-; CHECK: wfminsb %f0, %f2, %f4, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfminsb %f0, %f2, %f4, 4
+; CHECK-NEXT: br %r14
%ret = call float @llvm.minnum.f32(float %val1, float %val2)
ret float %ret
}
@@ -122,8 +150,9 @@ define float @f12(float %dummy, float %val1, float %val2) {
; Test the f32 minimum intrinsic.
define float @f13(float %dummy, float %val1, float %val2) {
; CHECK-LABEL: f13:
-; CHECK: wfminsb %f0, %f2, %f4, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: wfminsb %f0, %f2, %f4, 1
+; CHECK-NEXT: br %r14
%ret = call float @llvm.minimum.f32(float %val1, float %val2)
ret float %ret
}
@@ -131,9 +160,10 @@ define float @f13(float %dummy, float %val1, float %val2) {
; Test a f32 constant compare/select resulting in minnum.
define float @f14(float %dummy, float %val) {
; CHECK-LABEL: f14:
-; CHECK: lzer [[REG:%f[0-9]+]]
-; CHECK: wfminsb %f0, %f2, [[REG]], 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzer %f0
+; CHECK-NEXT: wfminsb %f0, %f2, %f0, 4
+; CHECK-NEXT: br %r14
%cmp = fcmp olt float %val, 0.0
%ret = select i1 %cmp, float %val, float 0.0
ret float %ret
@@ -142,9 +172,13 @@ define float @f14(float %dummy, float %val) {
; Test a f32 constant compare/select resulting in minimum.
define float @f15(float %dummy, float %val) {
; CHECK-LABEL: f15:
-; CHECK: ltebr %f1, %f2
-; CHECK: ldr %f0, %f2
-; CHECK: bnher %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ltebr %f1, %f2
+; CHECK-NEXT: ldr %f0, %f2
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB12_1:
+; CHECK-NEXT: lzer %f0
+; CHECK-NEXT: br %r14
%cmp = fcmp ult float %val, 0.0
%ret = select i1 %cmp, float %val, float 0.0
ret float %ret
@@ -152,20 +186,22 @@ define float @f15(float %dummy, float %val) {
; Test the v4f32 minnum intrinsic.
define <4 x float> @f16(<4 x float> %dummy, <4 x float> %val1,
- <4 x float> %val2) {
; CHECK-LABEL: f16:
-; CHECK: vfminsb %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfminsb %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
+ <4 x float> %val2) {
%ret = call <4 x float> @llvm.minnum.v4f32(<4 x float> %val1, <4 x float> %val2)
ret <4 x float> %ret
}
; Test the v4f32 minimum intrinsic.
define <4 x float> @f17(<4 x float> %dummy, <4 x float> %val1,
- <4 x float> %val2) {
; CHECK-LABEL: f17:
-; CHECK: vfminsb %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfminsb %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
+ <4 x float> %val2) {
%ret = call <4 x float> @llvm.minimum.v4f32(<4 x float> %val1, <4 x float> %val2)
ret <4 x float> %ret
}
@@ -173,11 +209,12 @@ define <4 x float> @f17(<4 x float> %dummy, <4 x float> %val1,
; Test the fminl library function.
define void @f21(ptr %ptr1, ptr %ptr2, ptr %dst) {
; CHECK-LABEL: f21:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
-; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
-; CHECK: vst [[RES]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: wfminxb %v0, %v0, %v1, 4
+; CHECK-NEXT: vst %v0, 0(%r4), 3
+; CHECK-NEXT: br %r14
%val1 = load fp128, ptr %ptr1
%val2 = load fp128, ptr %ptr2
%res = call fp128 @fminl(fp128 %val1, fp128 %val2) readnone
@@ -188,11 +225,12 @@ define void @f21(ptr %ptr1, ptr %ptr2, ptr %dst) {
; Test the f128 minnum intrinsic.
define void @f22(ptr %ptr1, ptr %ptr2, ptr %dst) {
; CHECK-LABEL: f22:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
-; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
-; CHECK: vst [[RES]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: wfminxb %v0, %v0, %v1, 4
+; CHECK-NEXT: vst %v0, 0(%r4), 3
+; CHECK-NEXT: br %r14
%val1 = load fp128, ptr %ptr1
%val2 = load fp128, ptr %ptr2
%res = call fp128 @llvm.minnum.f128(fp128 %val1, fp128 %val2)
@@ -203,11 +241,12 @@ define void @f22(ptr %ptr1, ptr %ptr2, ptr %dst) {
; Test the f128 minimum intrinsic.
define void @f23(ptr %ptr1, ptr %ptr2, ptr %dst) {
; CHECK-LABEL: f23:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
-; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 1
-; CHECK: vst [[RES]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: wfminxb %v0, %v0, %v1, 1
+; CHECK-NEXT: vst %v0, 0(%r4), 3
+; CHECK-NEXT: br %r14
%val1 = load fp128, ptr %ptr1
%val2 = load fp128, ptr %ptr2
%res = call fp128 @llvm.minimum.f128(fp128 %val1, fp128 %val2)
@@ -218,11 +257,12 @@ define void @f23(ptr %ptr1, ptr %ptr2, ptr %dst) {
; Test a f128 constant compare/select resulting in minnum.
define void @f24(ptr %ptr, ptr %dst) {
; CHECK-LABEL: f24:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
-; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
-; CHECK: vst [[RES]], 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vzero %v1
+; CHECK-NEXT: wfminxb %v0, %v0, %v1, 4
+; CHECK-NEXT: vst %v0, 0(%r3), 3
+; CHECK-NEXT: br %r14
%val = load fp128, ptr %ptr
%cmp = fcmp olt fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
@@ -233,11 +273,16 @@ define void @f24(ptr %ptr, ptr %dst) {
; Test a f128 constant compare/select resulting in minimum.
define void @f25(ptr %ptr, ptr %dst) {
; CHECK-LABEL: f25:
-; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
-; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
-; CHECK: wfcxb [[REG1]], [[REG2]]
-; CHECK: vst [[RES]], 0(%r3)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 0(%r2), 3
+; CHECK-NEXT: vzero %v1
+; CHECK-NEXT: wfcxb %v0, %v1
+; CHECK-NEXT: jnhe .LBB19_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: vzero %v0
+; CHECK-NEXT: .LBB19_2:
+; CHECK-NEXT: vst %v0, 0(%r3), 3
+; CHECK-NEXT: br %r14
%val = load fp128, ptr %ptr
%cmp = fcmp ult fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
new file mode 100644
index 0000000..511bc46
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
@@ -0,0 +1,66 @@
+; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+%struct.LargeStruct_t = type { [33 x i32] }
+
+@GlobLargeS = hidden global %struct.LargeStruct_t zeroinitializer, align 4
+@GlobInt = hidden global i32 0, align 4
+
+; === Check that function with small frame does not emit PPA1 Argument Area Length.
+define void @fSmallOutArgArea() {
+; CHECK-LABEL: L#EPM_fSmallOutArgArea_0 DS 0H
+; CHECK: * Bit 1: 1 = Leaf function
+; CHECK: * Bit 2: 0 = Does not use alloca
+; CHECK: DC XL4'00000008'
+; CHECK: fSmallOutArgArea DS 0H
+; CHECK: L#PPA1_fSmallOutArgArea_0 DS 0H
+; CHECK: * PPA1 Flags 3
+; CHECK: DC XL1'00'
+ ret void
+}
+
+; === Check that function with large frame does emit PPA1 Argument Area Length.
+define void @fLargeOutArgArea() {
+; CHECK-LABEL: L#EPM_fLargeOutArgArea_0 DS 0H
+; CHECK: * Bit 1: 0 = Non-leaf function
+; CHECK: * Bit 2: 0 = Does not use alloca
+; CHECK: DC XL4'00000220'
+; CHECK: fLargeOutArgArea DS 0H
+; CHECK: L#PPA1_fLargeOutArgArea_0 DS 0H
+; CHECK: * PPA1 Flags 3
+; CHECK: * Bit 1: 1 = Argument Area Length is in optional area
+; CHECK: DC XL1'40'
+; CHECK: * Argument Area Length
+; CHECK: DC XL4'00000140'
+ %1 = load [33 x i32], ptr @GlobLargeS, align 4
+ call void @fLargeParm([33 x i32] inreg %1)
+ ret void
+}
+
+; === Check that function with parameter does emit PPA1 Length/4 of parms
+define void @fLargeParm([33 x i64] inreg %arr) {
+; CHECK-LABEL: L#EPM_fLargeParm_0 DS 0H
+; CHECK: * Length/4 of Parms
+; CHECK: DC XL2'0042'
+ %1 = extractvalue [33 x i64] %arr, 1
+ call void @foo(i64 %1)
+ ret void
+}
+
+; === Check that function with alloca call does emit PPA1 Argument Area Length.
+define hidden void @fHasAlloca() {
+; CHECK-LABEL: L#EPM_fHasAlloca_0 DS 0H
+; CHECK: * Bit 2: 1 = Uses alloca
+; CHECK: fHasAlloca DS 0H
+; CHECK: L#PPA1_fHasAlloca_0 DS 0H
+; CHECK: * PPA1 Flags 3
+; CHECK: * Bit 1: 1 = Argument Area Length is in optional area
+; CHECK: DC XL1'40'
+; CHECK: * Argument Area Length
+; CHECK: DC XL4'00000040'
+ %p = alloca ptr, align 4
+ %1 = load i32, ptr @GlobInt, align 4
+ %2 = alloca i8, i32 %1, align 8
+ store ptr %2, ptr %p, align 4
+ ret void
+}
+
+declare void @foo(i64)
diff --git a/llvm/test/CodeGen/SystemZ/zos-target-flags.ll b/llvm/test/CodeGen/SystemZ/zos-target-flags.ll
new file mode 100644
index 0000000..968337d
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/zos-target-flags.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=s390x-ibm-zos -stop-after=systemz-isel --simplify-mir < %s | FileCheck %s
+
+
+declare i64 @calc(i64 noundef, ptr noundef)
+declare i64 @morework(i64 noundef)
+
+@i = external local_unnamed_addr global i64, align 8
+
+define i64 @work() {
+entry:
+; CHECK: %{{.*}}:addr64bit = ADA_ENTRY_VALUE target-flags(systemz-ada-datasymboladdr) @i,
+; CHECK: %{{.*}}:addr64bit = ADA_ENTRY_VALUE target-flags(systemz-ada-directfuncdesc) @calc,
+; CHECK: %{{.*}}:addr64bit = ADA_ENTRY_VALUE target-flags(systemz-ada-indirectfuncdesc) @morework,
+ %0 = load i64, ptr @i, align 8
+ %call = tail call i64 @calc(i64 noundef %0, ptr noundef nonnull @morework) #2
+ ret i64 %call
+}
generated by cgit v1.1 at 2026-01-08 05:47:01 +0000