diff options
36 files changed, 4497 insertions, 209 deletions
diff --git a/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp index d36cc3e..6e0c252 100644 --- a/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp +++ b/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp @@ -90,12 +90,10 @@ ClangTidyCheck::OptionsView::getLocalOrGlobal(StringRef LocalName) const { return std::nullopt; } -static std::optional<bool> getAsBool(StringRef Value, - const llvm::Twine &LookupName) { - +static std::optional<bool> getAsBool(StringRef Value) { if (std::optional<bool> Parsed = llvm::yaml::parseBool(Value)) return Parsed; - // To maintain backwards compatability, we support parsing numbers as + // To maintain backwards compatibility, we support parsing numbers as // booleans, even though its not supported in YAML. long long Number = 0; if (!Value.getAsInteger(10, Number)) @@ -107,7 +105,7 @@ template <> std::optional<bool> ClangTidyCheck::OptionsView::get<bool>(StringRef LocalName) const { if (std::optional<StringRef> ValueOr = get(LocalName)) { - if (auto Result = getAsBool(*ValueOr, NamePrefix + LocalName)) + if (auto Result = getAsBool(*ValueOr)) return Result; diagnoseBadBooleanOption(NamePrefix + LocalName, *ValueOr); } @@ -119,7 +117,7 @@ std::optional<bool> ClangTidyCheck::OptionsView::getLocalOrGlobal<bool>(StringRef LocalName) const { auto Iter = findPriorityOption(CheckOptions, NamePrefix, LocalName, Context); if (Iter != CheckOptions.end()) { - if (auto Result = getAsBool(Iter->getValue().Value, Iter->getKey())) + if (auto Result = getAsBool(Iter->getValue().Value)) return Result; diagnoseBadBooleanOption(Iter->getKey(), Iter->getValue().Value); } diff --git a/clang-tools-extra/clang-tidy/readability/CMakeLists.txt b/clang-tools-extra/clang-tidy/readability/CMakeLists.txt index 0d0641c..91e9354 100644 --- a/clang-tools-extra/clang-tidy/readability/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/readability/CMakeLists.txt @@ -49,6 +49,7 @@ add_clang_library(clangTidyReadabilityModule STATIC RedundantSmartptrGetCheck.cpp RedundantStringCStrCheck.cpp RedundantStringInitCheck.cpp + RedundantTypenameCheck.cpp ReferenceToConstructedTemporaryCheck.cpp SimplifyBooleanExprCheck.cpp SimplifySubscriptExprCheck.cpp diff --git a/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp b/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp index fcfac05..569302e 100644 --- a/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp @@ -52,6 +52,7 @@ #include "RedundantSmartptrGetCheck.h" #include "RedundantStringCStrCheck.h" #include "RedundantStringInitCheck.h" +#include "RedundantTypenameCheck.h" #include "ReferenceToConstructedTemporaryCheck.h" #include "SimplifyBooleanExprCheck.h" #include "SimplifySubscriptExprCheck.h" @@ -143,6 +144,8 @@ public: "readability-redundant-parentheses"); CheckFactories.registerCheck<RedundantPreprocessorCheck>( "readability-redundant-preprocessor"); + CheckFactories.registerCheck<RedundantTypenameCheck>( + "readability-redundant-typename"); CheckFactories.registerCheck<ReferenceToConstructedTemporaryCheck>( "readability-reference-to-constructed-temporary"); CheckFactories.registerCheck<SimplifySubscriptExprCheck>( diff --git a/clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.cpp b/clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.cpp new file mode 100644 index 0000000..e70fb39 --- /dev/null +++ b/clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.cpp @@ -0,0 +1,95 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "RedundantTypenameCheck.h" +#include "clang/AST/TypeLoc.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" +#include "clang/Basic/Diagnostic.h" +#include "clang/Lex/Lexer.h" +#include "clang/Sema/DeclSpec.h" + +using namespace clang::ast_matchers; + +namespace clang::tidy::readability { + +void RedundantTypenameCheck::registerMatchers(MatchFinder *Finder) { + Finder->addMatcher(typeLoc(unless(hasAncestor(decl(isInstantiated())))) + .bind("nonDependentTypeLoc"), + this); + + if (!getLangOpts().CPlusPlus20) + return; + + const auto InImplicitTypenameContext = anyOf( + hasParent(decl(anyOf( + typedefNameDecl(), templateTypeParmDecl(), nonTypeTemplateParmDecl(), + friendDecl(), fieldDecl(), + varDecl(hasDeclContext(anyOf(namespaceDecl(), translationUnitDecl())), + unless(parmVarDecl())), + parmVarDecl(hasParent(expr(requiresExpr()))), + parmVarDecl(hasParent(typeLoc(hasParent(decl( + anyOf(cxxMethodDecl(), hasParent(friendDecl()), + functionDecl(has(nestedNameSpecifier())), + cxxDeductionGuideDecl(hasDeclContext(recordDecl())))))))), + // Match return types. + functionDecl(unless(cxxConversionDecl()))))), + hasParent(expr(anyOf(cxxNamedCastExpr(), cxxNewExpr())))); + Finder->addMatcher( + typeLoc(InImplicitTypenameContext).bind("dependentTypeLoc"), this); +} + +void RedundantTypenameCheck::check(const MatchFinder::MatchResult &Result) { + const SourceLocation ElaboratedKeywordLoc = [&] { + if (const auto *NonDependentTypeLoc = + Result.Nodes.getNodeAs<TypeLoc>("nonDependentTypeLoc")) { + if (const auto TL = NonDependentTypeLoc->getAs<TypedefTypeLoc>()) + return TL.getElaboratedKeywordLoc(); + + if (const auto TL = NonDependentTypeLoc->getAs<TagTypeLoc>()) + return TL.getElaboratedKeywordLoc(); + + if (const auto TL = NonDependentTypeLoc + ->getAs<DeducedTemplateSpecializationTypeLoc>()) + return TL.getElaboratedKeywordLoc(); + + if (const auto TL = + NonDependentTypeLoc->getAs<TemplateSpecializationTypeLoc>()) + if (!TL.getType()->isDependentType()) + return TL.getElaboratedKeywordLoc(); + } else { + TypeLoc InnermostTypeLoc = + *Result.Nodes.getNodeAs<TypeLoc>("dependentTypeLoc"); + while (const TypeLoc Next = InnermostTypeLoc.getNextTypeLoc()) + InnermostTypeLoc = Next; + + if (const auto TL = InnermostTypeLoc.getAs<DependentNameTypeLoc>()) + return TL.getElaboratedKeywordLoc(); + + if (const auto TL = + InnermostTypeLoc.getAs<TemplateSpecializationTypeLoc>()) + return TL.getElaboratedKeywordLoc(); + } + + return SourceLocation(); + }(); + + if (ElaboratedKeywordLoc.isInvalid()) + return; + + if (Token ElaboratedKeyword; + Lexer::getRawToken(ElaboratedKeywordLoc, ElaboratedKeyword, + *Result.SourceManager, getLangOpts()) || + ElaboratedKeyword.getRawIdentifier() != "typename") + return; + + diag(ElaboratedKeywordLoc, "redundant 'typename'") + << FixItHint::CreateRemoval(ElaboratedKeywordLoc); +} + +} // namespace clang::tidy::readability diff --git a/clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.h b/clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.h new file mode 100644 index 0000000..8e86b0c --- /dev/null +++ b/clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.h @@ -0,0 +1,36 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_REDUNDANTTYPENAMECHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_REDUNDANTTYPENAMECHECK_H + +#include "../ClangTidyCheck.h" + +namespace clang::tidy::readability { + +/// Finds redundant uses of the `typename` keyword. +/// +/// For the user-facing documentation see: +/// https://clang.llvm.org/extra/clang-tidy/checks/readability/redundant-typename.html +class RedundantTypenameCheck : public ClangTidyCheck { +public: + RedundantTypenameCheck(StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context) {} + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus; + } + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + std::optional<TraversalKind> getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } +}; + +} // namespace clang::tidy::readability + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_REDUNDANTTYPENAMECHECK_H diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 8a0151f..061fb114 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -221,6 +221,11 @@ New checks Detect redundant parentheses. +- New :doc:`readability-redundant-typename + <clang-tidy/checks/readability/redundant-typename>` check. + + Finds redundant uses of the ``typename`` keyword. + New check aliases ^^^^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index a324d18..d3c89e4 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -410,6 +410,7 @@ Clang-Tidy Checks :doc:`readability-redundant-smartptr-get <readability/redundant-smartptr-get>`, "Yes" :doc:`readability-redundant-string-cstr <readability/redundant-string-cstr>`, "Yes" :doc:`readability-redundant-string-init <readability/redundant-string-init>`, "Yes" + :doc:`readability-redundant-typename <readability/redundant-typename>`, "Yes" :doc:`readability-reference-to-constructed-temporary <readability/reference-to-constructed-temporary>`, :doc:`readability-simplify-boolean-expr <readability/simplify-boolean-expr>`, "Yes" :doc:`readability-simplify-subscript-expr <readability/simplify-subscript-expr>`, "Yes" diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability/redundant-typename.rst b/clang-tools-extra/docs/clang-tidy/checks/readability/redundant-typename.rst new file mode 100644 index 0000000..3f3e5de --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/readability/redundant-typename.rst @@ -0,0 +1,31 @@ +.. title:: clang-tidy - readability-redundant-typename + +readability-redundant-typename +============================== + +Finds redundant uses of the ``typename`` keyword. + +``typename`` is redundant in two cases. First, before non-dependent names: + +.. code-block:: c++ + + /*typename*/ std::vector<int>::size_type size; + +And second, since C++20, before dependent names that appear in a context +where only a type is allowed (the following example shows just a few of them): + +.. code-block:: c++ + + template <typename T> + using trait = /*typename*/ T::type; + + template <typename T> + /*typename*/ T::underlying_type as_underlying(T n) { + return static_cast</*typename*/ T::underlying_type>(n); + } + + template <typename T> + struct S { + /*typename*/ T::type variable; + /*typename*/ T::type function(/*typename*/ T::type); + }; diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename-cxx98.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename-cxx98.cpp new file mode 100644 index 0000000..8329926 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename-cxx98.cpp @@ -0,0 +1,25 @@ +// RUN: %check_clang_tidy -std=c++98,c++03 %s readability-redundant-typename %t \ +// RUN: -- -- -fno-delayed-template-parsing + +struct NotDependent { + typedef int R; + template <typename = int> + struct T {}; +}; + +template <typename T> +typename T::R f() { + static_cast<typename T::R>(0); + + typename NotDependent::R NotDependentVar; + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: NotDependent::R NotDependentVar; + + typename NotDependent::T<int> V1; + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: NotDependent::T<int> V1; + + void notDependentFunctionDeclaration(typename NotDependent::R); + // CHECK-MESSAGES: :[[@LINE-1]]:40: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: void notDependentFunctionDeclaration(NotDependent::R); +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename.cpp new file mode 100644 index 0000000..2efafd1 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename.cpp @@ -0,0 +1,269 @@ +// RUN: %check_clang_tidy -std=c++11,c++14 %s readability-redundant-typename %t \ +// RUN: -- -- -fno-delayed-template-parsing +// RUN: %check_clang_tidy -std=c++17 -check-suffixes=,17 %s readability-redundant-typename %t \ +// RUN: -- -- -fno-delayed-template-parsing +// RUN: %check_clang_tidy -std=c++20-or-later -check-suffixes=,17,20 %s readability-redundant-typename %t \ +// RUN: -- -- -fno-delayed-template-parsing + +struct NotDependent { + using R = int; + struct S {}; + template <typename = int> + struct T {}; +}; + +auto f(typename NotDependent::S) + // CHECK-MESSAGES: :[[@LINE-1]]:8: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: auto f(NotDependent::S) + -> typename NotDependent::R + // CHECK-MESSAGES: :[[@LINE-1]]:6: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: -> NotDependent::R +{ + typename NotDependent::T<int> V1; + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: NotDependent::T<int> V1; + +#if __cplusplus >= 201703L + typename NotDependent::T V2; + // CHECK-MESSAGES-17: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-17: NotDependent::T V2; +#endif + + return typename NotDependent::R(); + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: redundant 'typename' [readability-redundant-typename] + // return NotDependent::R(); +} + +template < + typename T, + typename T::R V, + // CHECK-MESSAGES-20: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: T::R V, + typename U = typename T::R + // CHECK-MESSAGES-20: :[[@LINE-1]]:16: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: typename U = T::R +> +auto f() -> typename T::R +// CHECK-MESSAGES-20: :[[@LINE-1]]:13: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: auto f() -> T::R +{ + static_cast<typename T::R>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:15: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: static_cast<T::R>(0); + + dynamic_cast<typename T::R>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:16: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: dynamic_cast<T::R>(0); + + reinterpret_cast<typename T::R>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:20: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: reinterpret_cast<T::R>(0); + + const_cast<typename T::R>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:14: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: const_cast<T::R>(0); + + static_cast<typename T::R&>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:15: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: static_cast<T::R&>(0); + + dynamic_cast<typename T::R const volatile &&>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:16: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: dynamic_cast<T::R const volatile &&>(0); + + reinterpret_cast<const typename T::template M<42>::R *>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:26: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: reinterpret_cast<const T::template M<42>::R *>(0); + + const_cast<const typename T::R *const[100]>(0); + // CHECK-MESSAGES-20: :[[@LINE-1]]:20: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: const_cast<const T::R *const[100]>(0); + + (typename T::R)(0); + + alignof(typename T::R); + + new typename T::R(); + // CHECK-MESSAGES-20: :[[@LINE-1]]:7: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: new T::R(); + + // CHECK-MESSAGES-20: :[[@LINE+2]]:15: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: static_cast<decltype([] { + static_cast<typename decltype([] { + return typename T::R(); // Inner typename must stay. + })::R>(0); + + auto localFunctionDeclaration() -> typename T::R; + // CHECK-MESSAGES-20: :[[@LINE-1]]:38: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: auto localFunctionDeclaration() -> T::R; + + void (*PointerToFunction)(typename T::R); + void anotherLocalFunctionDeclaration(typename T::R); + + auto Lambda = [](typename T::R = typename T::R()) {}; + // CHECK-MESSAGES-20: :[[@LINE-1]]:20: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: auto Lambda = [](T::R = typename T::R()) {}; + + typename T::R DependentVar; + typename NotDependent::R NotDependentVar; + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES: NotDependent::R NotDependentVar; + + return typename T::R(); +} + +template <typename T> +using trait = const typename T::R ****; +// CHECK-MESSAGES-20: :[[@LINE-1]]:21: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: using trait = const T::R ****; + +template <typename T> +using t = typename T::template R<T>; +// CHECK-MESSAGES-20: :[[@LINE-1]]:11: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: using t = T::template R<T>; + +template <typename T> +trait<typename T::R> m(); + +#if __cplusplus >= 202002L + +template <typename T> +concept c = requires(typename T::R) { +// CHECK-MESSAGES-20: :[[@LINE-1]]:22: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: concept c = requires(T::R) { + typename T::R; +}; + +template <typename T> +requires c<typename T::R> +void b(); + +auto GenericLambda = []<typename T>(typename T::R = typename T::R()) {}; +// CHECK-MESSAGES-20: :[[@LINE-1]]:37: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: auto GenericLambda = []<typename T>(T::R = typename T::R()) {}; + +#endif // __cplusplus >= 202002L + +template <typename T, typename> +struct PartiallySpecializedType {}; + +template <typename T> +struct PartiallySpecializedType<T, typename T::R> {}; + +#if __cplusplus >= 201402L + +template <typename T> +typename T::R v = typename T::R(); +// CHECK-MESSAGES-20: :[[@LINE-1]]:1: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: T::R v = typename T::R(); + +#endif // __cplusplus >= 201402L + +template <typename T> +typename T::R f(); +// CHECK-MESSAGES-20: :[[@LINE-1]]:1: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: T::R f(); + +template <typename T> +void n(typename T::R *) {} + +template void n<NotDependent>(NotDependent::R *); + +namespace ns { + +template <typename T> +void f(typename T::R1, typename T::R2); + +} // namespace ns + +template <typename T> +void ns::f( + typename T::R1, + // CHECK-MESSAGES-20: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: T::R1, + typename T::R2 + // CHECK-MESSAGES-20: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: T::R2 +); + +template <typename... Ts> +void p(typename Ts::R...); + +template <typename T, typename... Ts> +class A { +public: + friend typename T::R; + // CHECK-MESSAGES-20: :[[@LINE-1]]:10: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: friend T::R; + + typedef typename T::R a; + // CHECK-MESSAGES-20: :[[@LINE-1]]:11: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: typedef T::R a; + + const typename T::R typedef b; + // CHECK-MESSAGES-20: :[[@LINE-1]]:9: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: const T::R typedef b; + + typename T::R v; + // CHECK-MESSAGES-20: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: T::R v; + + typename T::R + // CHECK-MESSAGES-20: :[[@LINE-1]]:3: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: T::R + g(typename T::R) {} + // CHECK-MESSAGES-20: :[[@LINE-1]]:5: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: g(T::R) {} + + void h(typename T::R = typename T::R()) {} + // CHECK-MESSAGES-20: :[[@LINE-1]]:10: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: void h(T::R = typename T::R()) {} + + void p(typename Ts::R...); + // CHECK-MESSAGES-20: :[[@LINE-1]]:10: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: void p(Ts::R...); + + friend void k(typename T::R) {} + // CHECK-MESSAGES-20: :[[@LINE-1]]:17: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: friend void k(T::R) {} + + template <typename> + struct Nested {}; + +#if __cplusplus >= 201703L + template <typename U> + Nested(U, const typename U::R *, typename U::R = typename U::R()) -> Nested<typename U::R>; + // CHECK-MESSAGES-20: :[[@LINE-1]]:19: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-MESSAGES-20: :[[@LINE-2]]:36: warning: redundant 'typename' [readability-redundant-typename] + // CHECK-FIXES-20: Nested(U, const U::R *, U::R = typename U::R()) -> Nested<typename U::R>; +#endif + + friend struct T::R; + using typename T::R; + enum E1 : typename T::R {}; + enum class E2 : typename T::R {}; + operator typename T::R(); + void m() { this->operator typename T::R(); } +#if __cplusplus >= 202002L + T::R n; + T::R q(T::R) {} +#endif +}; + +#if __cplusplus >= 201703L + +template <typename T, typename U = typename T::R> +// CHECK-MESSAGES-20: :[[@LINE-1]]:36: warning: redundant 'typename' [readability-redundant-typename] +// CHECK-FIXES-20: template <typename T, typename U = T::R> +A(T, typename T::R) -> A<typename T::R>; + +#endif + +#define TYPENAME_KEYWORD_IN_MACRO typename +TYPENAME_KEYWORD_IN_MACRO NotDependent::R Macro1; + +#define WHOLE_TYPE_IN_MACRO typename NotDependent::R +WHOLE_TYPE_IN_MACRO Macro2; + +#define WHOLE_DECLARATION_IN_MACRO typename NotDependent::R Macro3 +WHOLE_DECLARATION_IN_MACRO; diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h index 492863d..98e62de 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchers.h +++ b/clang/include/clang/ASTMatchers/ASTMatchers.h @@ -2763,6 +2763,20 @@ extern const internal::VariadicDynCastAllOfMatcher<Stmt, CXXDynamicCastExpr> extern const internal::VariadicDynCastAllOfMatcher<Stmt, CXXConstCastExpr> cxxConstCastExpr; +/// Matches any named cast expression. +/// +/// Example: Matches all four of the casts in +/// \code +/// struct S { virtual void f(); }; +/// S* p = nullptr; +/// S* ptr1 = static_cast<S*>(p); +/// S* ptr2 = reinterpret_cast<S*>(p); +/// S* ptr3 = dynamic_cast<S*>(p); +/// S* ptr4 = const_cast<S*>(p); +/// \endcode +extern const internal::VariadicDynCastAllOfMatcher<Stmt, CXXNamedCastExpr> + cxxNamedCastExpr; + /// Matches a C-style cast expression. /// /// Example: Matches (int) 2.2f in diff --git a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp index 1f0e007..42f124b 100644 --- a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp +++ b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp @@ -1009,6 +1009,8 @@ const internal::VariadicDynCastAllOfMatcher<Stmt, CXXDynamicCastExpr> cxxDynamicCastExpr; const internal::VariadicDynCastAllOfMatcher<Stmt, CXXConstCastExpr> cxxConstCastExpr; +const internal::VariadicDynCastAllOfMatcher<Stmt, CXXNamedCastExpr> + cxxNamedCastExpr; const internal::VariadicDynCastAllOfMatcher<Stmt, CStyleCastExpr> cStyleCastExpr; const internal::VariadicDynCastAllOfMatcher<Stmt, ExplicitCastExpr> diff --git a/libclc/clc/include/clc/integer/gentype.inc b/libclc/clc/include/clc/integer/gentype.inc index b2b603e..acca863 100644 --- a/libclc/clc/include/clc/integer/gentype.inc +++ b/libclc/clc/include/clc/integer/gentype.inc @@ -23,6 +23,7 @@ // to keep this file manageable. #define __CLC_GENSIZE 8 #define __CLC_SCALAR_GENTYPE char +#define __CLC_GEN_S #define __CLC_GENTYPE char #define __CLC_U_GENTYPE uchar @@ -93,6 +94,8 @@ #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE uchar +#undef __CLC_GEN_S +#define __CLC_GEN_U #define __CLC_GENTYPE uchar #define __CLC_U_GENTYPE uchar @@ -165,6 +168,8 @@ #define __CLC_GENSIZE 16 #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE short +#undef __CLC_GEN_U +#define __CLC_GEN_S #define __CLC_GENTYPE short #define __CLC_U_GENTYPE ushort @@ -235,6 +240,8 @@ #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE ushort +#undef __CLC_GEN_S +#define __CLC_GEN_U #define __CLC_GENTYPE ushort #define __CLC_U_GENTYPE ushort @@ -307,6 +314,8 @@ #define __CLC_GENSIZE 32 #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE int +#undef __CLC_GEN_U +#define __CLC_GEN_S #define __CLC_GENTYPE int #define __CLC_U_GENTYPE uint @@ -377,6 +386,8 @@ #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE uint +#undef __CLC_GEN_S +#define __CLC_GEN_U #define __CLC_GENTYPE uint #define __CLC_U_GENTYPE uint @@ -449,6 +460,8 @@ #define __CLC_GENSIZE 64 #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE long +#undef __CLC_GEN_U +#define __CLC_GEN_S #define __CLC_GENTYPE long #define __CLC_U_GENTYPE ulong @@ -519,6 +532,8 @@ #undef __CLC_SCALAR_GENTYPE #define __CLC_SCALAR_GENTYPE ulong +#undef __CLC_GEN_S +#define __CLC_GEN_U #define __CLC_GENTYPE ulong #define __CLC_U_GENTYPE ulong @@ -588,6 +603,8 @@ #undef __CLC_S_GENTYPE #undef __CLC_VECSIZE_OR_1 +#undef __CLC_GEN_U + #undef __CLC_GENSIZE #undef __CLC_SCALAR_GENTYPE #undef __CLC_BODY diff --git a/libclc/clc/lib/generic/integer/clc_abs.inc b/libclc/clc/lib/generic/integer/clc_abs.inc index 26ec0b2..81e92461 100644 --- a/libclc/clc/lib/generic/integer/clc_abs.inc +++ b/libclc/clc/lib/generic/integer/clc_abs.inc @@ -6,7 +6,14 @@ // //===----------------------------------------------------------------------===// +#ifdef __CLC_GEN_S + _CLC_OVERLOAD _CLC_DEF __CLC_U_GENTYPE __clc_abs(__CLC_GENTYPE x) { - return __builtin_astype((__CLC_GENTYPE)(x > (__CLC_GENTYPE)(0) ? x : -x), - __CLC_U_GENTYPE); + return __builtin_astype(__builtin_elementwise_abs(x), __CLC_U_GENTYPE); } + +#else + +_CLC_OVERLOAD _CLC_DEF __CLC_U_GENTYPE __clc_abs(__CLC_GENTYPE x) { return x; } + +#endif diff --git a/llvm/docs/YamlIO.rst b/llvm/docs/YamlIO.rst index 4f523cb..553e4a8 100644 --- a/llvm/docs/YamlIO.rst +++ b/llvm/docs/YamlIO.rst @@ -12,7 +12,7 @@ YAML is a human-readable data serialization language. The full YAML language spec can be read at `yaml.org <http://www.yaml.org/spec/1.2/spec.html#Introduction>`_. The simplest form of YAML is just "scalars", "mappings", and "sequences". A scalar is any number -or string. The pound/hash symbol (#) begins a comment line. A mapping is +or string. The pound/hash symbol (``#``) begins a comment line. A mapping is a set of key-value pairs where the key ends with a colon. For example: .. code-block:: yaml @@ -21,7 +21,7 @@ a set of key-value pairs where the key ends with a colon. For example: name: Tom hat-size: 7 -A sequence is a list of items where each item starts with a leading dash ('-'). +A sequence is a list of items where each item starts with a leading dash (``-``). For example: .. code-block:: yaml @@ -221,7 +221,7 @@ Similar errors are produced for other input not conforming to the schema. Scalars ======= -YAML scalars are just strings (i.e. not a sequence or mapping). The YAML I/O +YAML scalars are just strings (i.e., not a sequence or mapping). The YAML I/O library provides support for translating between YAML scalars and specific C++ types. @@ -230,19 +230,19 @@ Built-in types -------------- The following types have built-in support in YAML I/O: -* bool -* float -* double -* StringRef -* std::string -* int64_t -* int32_t -* int16_t -* int8_t -* uint64_t -* uint32_t -* uint16_t -* uint8_t +* ``bool`` +* ``float`` +* ``double`` +* ``StringRef`` +* ``std::string`` +* ``int64_t`` +* ``int32_t`` +* ``int16_t`` +* ``int8_t`` +* ``uint64_t`` +* ``uint32_t`` +* ``uint16_t`` +* ``uint8_t`` That is, you can use those types in fields of ``MappingTraits`` or as the element type in a sequence. When reading, YAML I/O will validate that the string found @@ -264,7 +264,7 @@ operators to and from the base type. For example: LLVM_YAML_STRONG_TYPEDEF(uint32_t, MyFooFlags) LLVM_YAML_STRONG_TYPEDEF(uint32_t, MyBarFlags) -This generates two classes MyFooFlags and MyBarFlags which you can use in your +This generates two classes ``MyFooFlags`` and ``MyBarFlags`` which you can use in your native data structures instead of ``uint32_t``. They are implicitly converted to and from ``uint32_t``. The point of creating these unique types is that you can now specify traits on them to get different YAML conversions. @@ -275,12 +275,12 @@ An example use of a unique type is that YAML I/O provides fixed-sized unsigned integers that are written with YAML I/O as hexadecimal instead of the decimal format used by the built-in integer types: -* Hex64 -* Hex32 -* Hex16 -* Hex8 +* ``Hex64`` +* ``Hex32`` +* ``Hex16`` +* ``Hex8`` -You can use ``llvm::yaml::Hex32`` instead of ``uint32_t`` and the only difference will +You can use ``llvm::yaml::Hex32`` instead of ``uint32_t``. The only difference will be that when YAML I/O writes out that type it will be formatted in hexadecimal. @@ -356,8 +356,8 @@ had the following bit flags defined: LLVM_YAML_STRONG_TYPEDEF(uint32_t, MyFlags) -To support reading and writing of MyFlags, you specialize ``ScalarBitSetTraits<>`` -on MyFlags and provide the bit values and their names. +To support reading and writing of ``MyFlags``, you specialize ``ScalarBitSetTraits<>`` +on ``MyFlags`` and provide the bit values and their names. .. code-block:: c++ @@ -441,7 +441,7 @@ Custom Scalar Sometimes, for readability, a scalar needs to be formatted in a custom way. For instance, your internal data structure may use an integer for time (seconds since some epoch), but in YAML it would be much nicer to express that integer in -some time format (e.g. 4-May-2012 10:30pm). YAML I/O has a way to support +some time format (e.g., ``4-May-2012 10:30pm``). YAML I/O has a way to support custom formatting and parsing of scalar types by specializing ``ScalarTraits<>`` on your data type. When writing, YAML I/O will provide the native type and your specialization must create a temporary ``llvm::StringRef``. When reading, @@ -523,8 +523,8 @@ An example of a custom type with an appropriate specialization of Mappings ======== -To be translated to or from a YAML mapping for your type T you must specialize -``llvm::yaml::MappingTraits`` on T and implement the "void mapping(IO &io, T&)" +To be translated to or from a YAML mapping for your type ``T``, you must specialize +``llvm::yaml::MappingTraits`` on ``T`` and implement the ``void mapping(IO &io, T&)`` method. If your native data structures use pointers to a class everywhere, you can specialize on the class pointer. Examples: @@ -685,13 +685,13 @@ normalized instance is stack allocated. In these cases, the utility template ``MappingNormalizationHeap<>`` can be used instead. It just like ``MappingNormalization<>`` except that it heap allocates the normalized object when reading YAML. It never destroys the normalized object. The ``denormalize()`` -method can this return "this". +method can this return ``this``. Default values -------------- Within a ``mapping()`` method, calls to ``io.mapRequired()`` mean that that key is -required to exist when parsing YAML documents, otherwise YAML I/O will issue an +required to exist when parsing YAML documents; otherwise, YAML I/O will issue an error. On the other hand, keys registered with ``io.mapOptional()`` are allowed to not @@ -708,7 +708,7 @@ does not have that key. There is one important difference between those two ways (default constructor and third parameter to ``mapOptional()``). When YAML I/O generates a YAML document, if the ``mapOptional()`` third parameter is used, if the actual value being written -is the same as (using ==) the default value, then that key/value is not written. +is the same as (using ``==``) the default value, then that key/value is not written. Order of Keys @@ -772,7 +772,7 @@ not. This is similar to something having no syntax errors, but still having semantic errors. To support semantic-level checking, YAML I/O allows an optional ``validate()`` method in a MappingTraits template specialization. -When parsing YAML, the ``validate()`` method is call *after* all key/values in +When parsing YAML, the ``validate()`` method is called *after* all key/values in the map have been processed. Any error message returned by the ``validate()`` method during input will be printed just like a syntax error would be printed. When writing YAML, the ``validate()`` method is called *before* the YAML @@ -833,8 +833,8 @@ configuration. Sequence ======== -To be translated to or from a YAML sequence for your type T you must specialize -``llvm::yaml::SequenceTraits`` on T and implement two methods: +To be translated to or from a YAML sequence for your type ``T``, you must specialize +``llvm::yaml::SequenceTraits`` on ``T`` and implement two methods: ``size_t size(IO &io, T&)`` and ``T::value_type& element(IO &io, T&, size_t indx)``. For example: @@ -857,7 +857,7 @@ a reference to that new allocated space. Flow Sequence ------------- A YAML "flow sequence" is a sequence that when written to YAML it uses the -inline notation (e.g [ foo, bar ] ). To specify that a sequence type should +inline notation (e.g., ``[ foo, bar ]`` ). To specify that a sequence type should be written in YAML as a flow sequence, your SequenceTraits specialization should add ``static constexpr bool flow = true;``. For instance: @@ -872,9 +872,9 @@ add ``static constexpr bool flow = true;``. For instance: static constexpr bool flow = true; }; -With the above, if you used MyList as the data type in your native data +With the above, if you used ``MyList`` as the data type in your native data structures, then when converted to YAML, a flow sequence of integers -will be used (e.g. [ 10, -3, 4 ]). +will be used (e.g., ``[ 10, -3, 4 ]``). Flow sequences are subject to line wrapping according to the Output object configuration. @@ -900,8 +900,8 @@ Document List ============= YAML allows you to define multiple "documents" in a single YAML file. Each -new document starts with a left aligned "---" token. The end of all documents -is denoted with a left aligned "..." token. Many users of YAML will never +new document starts with a left aligned ``---`` token. The end of all documents +is denoted with a left aligned ``...`` token. Many users of YAML will never have need for multiple documents. The top level node in their YAML schema will be a mapping or sequence. For those cases, the following is not needed. But for cases where you do want multiple documents, you can specify a @@ -955,7 +955,7 @@ to write your native data as YAML. One thing to recall is that a YAML file can contain multiple "documents". If the top level data structure you are streaming as YAML is a mapping, scalar, or sequence, then ``Output`` assumes you are generating one document and wraps the mapping output -with "``---``" and trailing "``...``". +with ``---`` and trailing ``...``. The ``WrapColumn`` parameter will cause the flow mappings and sequences to line-wrap when they go over the supplied column. Pass 0 to completely @@ -981,8 +981,8 @@ The above could produce output like: On the other hand, if the top level data structure you are streaming as YAML has a ``DocumentListTraits`` specialization, then Output walks through each element -of your DocumentList and generates a "---" before the start of each element -and ends with a "...". +of your DocumentList and generates a ``---`` before the start of each element +and ends with a ``...``. .. code-block:: c++ @@ -1022,7 +1022,7 @@ pointer: Once you have an ``Input`` object, you can use the C++ stream operator to read the document(s). If you expect there might be multiple YAML documents in one file, you'll need to specialize ``DocumentListTraits`` on a list of your -document type and stream in that document list type. Otherwise you can +document type and stream in that document list type. Otherwise, you can just stream in the document type. Also, you can check if there was any syntax errors in the YAML by calling the ``error()`` method on the ``Input`` object. For example: diff --git a/llvm/include/llvm/ADT/DirectedGraph.h b/llvm/include/llvm/ADT/DirectedGraph.h index fb6b180..fe7c9e5 100644 --- a/llvm/include/llvm/ADT/DirectedGraph.h +++ b/llvm/include/llvm/ADT/DirectedGraph.h @@ -80,18 +80,6 @@ public: explicit DGNode(EdgeType &E) : Edges() { Edges.insert(&E); } DGNode() = default; - explicit DGNode(const DGNode<NodeType, EdgeType> &N) : Edges(N.Edges) {} - DGNode(DGNode<NodeType, EdgeType> &&N) : Edges(std::move(N.Edges)) {} - - DGNode<NodeType, EdgeType> &operator=(const DGNode<NodeType, EdgeType> &N) { - Edges = N.Edges; - return *this; - } - DGNode<NodeType, EdgeType> &operator=(const DGNode<NodeType, EdgeType> &&N) { - Edges = std::move(N.Edges); - return *this; - } - /// Static polymorphism: delegate implementation (via isEqualTo) to the /// derived class. friend bool operator==(const NodeType &M, const NodeType &N) { diff --git a/llvm/include/llvm/DebugInfo/PDB/PDBTypes.h b/llvm/include/llvm/DebugInfo/PDB/PDBTypes.h index a64a2e8..c919b5f 100644 --- a/llvm/include/llvm/DebugInfo/PDB/PDBTypes.h +++ b/llvm/include/llvm/DebugInfo/PDB/PDBTypes.h @@ -597,17 +597,10 @@ struct Variant { } // end namespace pdb } // end namespace llvm -namespace std { - -template <> struct hash<llvm::pdb::PDB_SymType> { - using argument_type = llvm::pdb::PDB_SymType; - using result_type = std::size_t; - - result_type operator()(const argument_type &Arg) const { +template <> struct std::hash<llvm::pdb::PDB_SymType> { + std::size_t operator()(const llvm::pdb::PDB_SymType &Arg) const { return std::hash<int>()(static_cast<int>(Arg)); } }; -} // end namespace std - #endif // LLVM_DEBUGINFO_PDB_PDBTYPES_H diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index ec16995..7be1b65 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -59,6 +59,11 @@ def ExceptionModelIsNotNone : RuntimeLibcallPredicate< [{ExceptionModel != ExceptionHandling::None}] >; +def ExceptionModelHasUnwindResume : RuntimeLibcallPredicate< + [{ExceptionModel != ExceptionHandling::None && + ExceptionModel != ExceptionHandling::SjLj}] +>; + def ExceptionModelIsSjLj : RuntimeLibcallPredicate< [{ExceptionModel == ExceptionHandling::SjLj}] >; @@ -1153,8 +1158,10 @@ def __ssp_canary_word : RuntimeLibcallImpl<STACK_CHECK_GUARD>; //===----------------------------------------------------------------------===// defvar ExceptionModelCalls = (add - LibcallImpls<(add DefaultExceptionHandlingLibcalls), + LibcallImpls<(add __cxa_end_cleanup), ExceptionModelIsNotNone>, + LibcallImpls<(add _Unwind_Resume), + ExceptionModelHasUnwindResume>, LibcallImpls<(add SjLjExceptionHandlingLibcalls), ExceptionModelIsSjLj> ); @@ -1396,8 +1403,10 @@ defset list<RuntimeLibcallImpl> WinArm64ECSjLjExceptionHandlingLibcalls = { } defvar ExceptionModelCallsArm64EC = (add - LibcallImpls<(add WinArm64ECDefaultExceptionHandlingLibcalls), + LibcallImpls<(add arm64ec___cxa_end_cleanup), ExceptionModelIsNotNone>, + LibcallImpls<(add arm64ec__Unwind_Resume), + ExceptionModelHasUnwindResume>, LibcallImpls<(add WinArm64ECSjLjExceptionHandlingLibcalls), ExceptionModelIsSjLj> ); @@ -1499,6 +1508,41 @@ def __aeabi_ddiv : RuntimeLibcallImpl<DIV_F64>; // CallingConv::ARM_AAPCS def __aeabi_dmul : RuntimeLibcallImpl<MUL_F64>; // CallingConv::ARM_AAPCS def __aeabi_dsub : RuntimeLibcallImpl<SUB_F64>; // CallingConv::ARM_AAPCS +defvar AEABIOverrides = [ + __eqsf2, __eqdf2, + __nesf2, __nedf2, + __ltsf2, __ltdf2, + __lesf2, __ledf2, + __gesf2, __gedf2, + __gtsf2, __gtdf2, + __unordsf2, __unorddf2, + + __addsf3, __adddf3, + __divsf3, __divdf3, + __mulsf3, __muldf3, + __subsf3, __subdf3, + + __fixdfsi, __fixunsdfsi, + __fixdfdi, __fixunsdfdi, + __fixsfsi, __fixunssfsi, + __fixsfdi, __fixunssfdi, + + __floatsidf, __floatunsidf, + __floatdidf, __floatundidf, + __floatsisf, __floatunsisf, + __floatdisf, __floatundisf, + + __muldi3, __ashldi3, + __lshrdi3, __ashrdi3, + + __divsi3, __udivsi3 + + // Half conversion cases are a mess and handled separately. + // __truncdfsf2, __truncdfhf2, + // __extendsfdf2, + // __truncsfhf2, __extendhfsf2 +]; + // Double-precision floating-point comparison helper functions // RTABI chapter 4.1.2, Table 3 def __aeabi_dcmpeq__oeq : RuntimeLibcallImpl<OEQ_F64, "__aeabi_dcmpeq">; // CallingConv::ARM_AAPCS, CmpInst::ICMP_NE @@ -1784,7 +1828,8 @@ def ARMSystemLibrary : SystemRuntimeLibrary<isARMOrThumb, (add (sub WinDefaultLibcallImpls, ARMLibgccHalfConvertCalls, GNUEABIHalfConvertCalls, - ARMDoubleToHalfCalls), + ARMDoubleToHalfCalls, + AEABIOverrides), LibcallImpls<(add __powisf2, __powidf2), isNotOSMSVCRT>, LibmHasFrexpF32, LibmHasLdexpF32, LibmHasFrexpF128, LibmHasLdexpF128, @@ -1803,6 +1848,11 @@ def ARMSystemLibrary GNUEABIHalfConvertCalls, ARMDoubleToHalfCalls, + LibcallImpls<(add AEABIOverrides), + RuntimeLibcallPredicate<[{ + (!hasAEABILibcalls(TT) || !isAAPCS_ABI(TT, ABIName)) && + !TT.isOSWindows() + }]>>, // Use divmod compiler-rt calls for iOS 5.0 and later. LibcallImpls<(add __divmodsi4, __udivmodsi4), RuntimeLibcallPredicate<[{TT.isOSBinFormatMachO() && @@ -2443,6 +2493,11 @@ def _aullrem : RuntimeLibcallImpl<UREM_I64>; def _allmul : RuntimeLibcallImpl<MUL_I64>; } +// FIXME: Should have utility function to filter by known provider. +defvar WindowsDivRemMulLibcallOverrides = [ + __divdi3, __udivdi3, __moddi3, __umoddi3, __muldi3 +]; + //===----------------------------------------------------------------------===// // X86 Runtime Libcalls //===----------------------------------------------------------------------===// @@ -2464,7 +2519,7 @@ defvar X86_F128_Libcalls = LibcallImpls<(add LibmF128Libcalls, LibmF128FiniteLib defvar SinCosF32F64Libcalls = LibcallImpls<(add sincosf, sincos), hasSinCos_f32_f64>; defvar X86CommonLibcalls = - (add WinDefaultLibcallImpls, + (add (sub WinDefaultLibcallImpls, WindowsDivRemMulLibcallOverrides), DarwinSinCosStret, DarwinExp10, X86_F128_Libcalls, LibmHasSinCosF80, // FIXME: Depends on long double @@ -2487,10 +2542,15 @@ defvar Windows32DivRemMulCalls = LibcallsWithCC<(add WindowsDivRemMulLibcalls), X86_STDCALL, RuntimeLibcallPredicate<"TT.isWindowsMSVCEnvironment() || TT.isWindowsItaniumEnvironment()">>; +defvar NotWindows32DivRemMulCalls = + LibcallImpls<(add WindowsDivRemMulLibcallOverrides), + RuntimeLibcallPredicate<"!TT.isWindowsMSVCEnvironment() && !TT.isWindowsItaniumEnvironment()">>; + def X86_32SystemLibrary : SystemRuntimeLibrary<isX86_32, (add X86CommonLibcalls, - Windows32DivRemMulCalls)>; + NotWindows32DivRemMulCalls, + Windows32DivRemMulCalls)>; def X86_64SystemLibrary : SystemRuntimeLibrary<isX86_64, diff --git a/llvm/include/llvm/Support/Program.h b/llvm/include/llvm/Support/Program.h index da5685d..53c2e75 100644 --- a/llvm/include/llvm/Support/Program.h +++ b/llvm/include/llvm/Support/Program.h @@ -45,7 +45,7 @@ typedef procid_t process_t; /// This struct encapsulates information about a process. struct ProcessInfo { - enum : procid_t { InvalidPid = 0 }; + static constexpr procid_t InvalidPid = 0; procid_t Pid; /// The process identifier. process_t Process; /// Platform-dependent process object. diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 7adb25d..e27a9b1 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -2982,6 +2982,10 @@ void LoopAccessInfo::collectStridedAccess(Value *MemAccess) { if (!StrideExpr) return; + if (auto *Unknown = dyn_cast<SCEVUnknown>(StrideExpr)) + if (isa<UndefValue>(Unknown->getValue())) + return; + LLVM_DEBUG(dbgs() << "LAA: Found a strided access that is a candidate for " "versioning:"); LLVM_DEBUG(dbgs() << " Ptr: " << *Ptr << " Stride: " << *StrideExpr << "\n"); diff --git a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp index 93ae548..7bef3a8 100644 --- a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp +++ b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp @@ -86,10 +86,7 @@ template <> struct llvm::DenseMapInfo<VariableID> { using VarLocInsertPt = PointerUnion<const Instruction *, const DbgRecord *>; template <> struct std::hash<VarLocInsertPt> { - using argument_type = VarLocInsertPt; - using result_type = std::size_t; - - result_type operator()(const argument_type &Arg) const { + std::size_t operator()(const VarLocInsertPt &Arg) const { return std::hash<void *>()(Arg.getOpaqueValue()); } }; diff --git a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp index 137ff89..f13554f 100644 --- a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp +++ b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp @@ -47,6 +47,8 @@ public: StringRef getPassName() const override { return AARCH64_BRANCH_TARGETS_NAME; } private: + const AArch64Subtarget *Subtarget; + void addBTI(MachineBasicBlock &MBB, bool CouldCall, bool CouldJump, bool NeedsWinCFI); }; @@ -75,6 +77,8 @@ bool AArch64BranchTargets::runOnMachineFunction(MachineFunction &MF) { << "********** Function: " << MF.getName() << '\n'); const Function &F = MF.getFunction(); + Subtarget = &MF.getSubtarget<AArch64Subtarget>(); + // LLVM does not consider basic blocks which are the targets of jump tables // to be address-taken (the address can't escape anywhere else), but they are // used for indirect branches, so need BTI instructions. @@ -100,9 +104,8 @@ bool AArch64BranchTargets::runOnMachineFunction(MachineFunction &MF) { // a BTI, and pointing the indirect branch at that. For non-ELF targets we // can't rely on that, so we assume that `CouldCall` is _always_ true due // to the risk of long-branch thunks at link time. - if (&MBB == &*MF.begin() && - (!MF.getSubtarget<AArch64Subtarget>().isTargetELF() || - (F.hasAddressTaken() || !F.hasLocalLinkage()))) + if (&MBB == &*MF.begin() && (!Subtarget->isTargetELF() || + (F.hasAddressTaken() || !F.hasLocalLinkage()))) CouldCall = true; // If the block itself is address-taken, it could be indirectly branched @@ -132,9 +135,6 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall, << (CouldCall ? "c" : "") << " to " << MBB.getName() << "\n"); - const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( - MBB.getParent()->getSubtarget().getInstrInfo()); - unsigned HintNum = 32; if (CouldCall) HintNum |= 2; @@ -162,6 +162,8 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall, MBBI->getOpcode() == AArch64::PACIBSP)) return; + const AArch64InstrInfo *TII = Subtarget->getInstrInfo(); + // Insert BTI exactly at the first executable instruction. const DebugLoc DL = MBB.findDebugLoc(MBBI); MachineInstr *BTI = BuildMI(MBB, MBBI, DL, TII->get(AArch64::HINT)) diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index 1e607f4..f63981b 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -1871,7 +1871,7 @@ bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) { } bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); + TII = MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); bool Modified = false; for (auto &MBB : MF) diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index c76689f..0f7b34c 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -644,10 +644,10 @@ bool AArch64FrameLowering::hasReservedCallFrame( MachineBasicBlock::iterator AArch64FrameLowering::eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const AArch64InstrInfo *TII = - static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); - const AArch64TargetLowering *TLI = - MF.getSubtarget<AArch64Subtarget>().getTargetLowering(); + + const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); + const AArch64InstrInfo *TII = Subtarget.getInstrInfo(); + const AArch64TargetLowering *TLI = Subtarget.getTargetLowering(); [[maybe_unused]] MachineFrameInfo &MFI = MF.getFrameInfo(); DebugLoc DL = I->getDebugLoc(); unsigned Opc = I->getOpcode(); @@ -1319,8 +1319,8 @@ StackOffset AArch64FrameLowering::getStackOffset(const MachineFunction &MF, // TODO: This function currently does not work for scalable vectors. int AArch64FrameLowering::getSEHFrameIndexOffset(const MachineFunction &MF, int FI) const { - const auto *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getSubtarget().getRegisterInfo()); + const AArch64RegisterInfo *RegInfo = + MF.getSubtarget<AArch64Subtarget>().getRegisterInfo(); int ObjectOffset = MF.getFrameInfo().getObjectOffset(FI); return RegInfo->getLocalAddressRegister(MF) == AArch64::FP ? getFPOffset(MF, ObjectOffset).getFixed() @@ -1343,10 +1343,9 @@ StackOffset AArch64FrameLowering::resolveFrameOffsetReference( TargetStackID::Value StackID, Register &FrameReg, bool PreferFP, bool ForSimm) const { const auto &MFI = MF.getFrameInfo(); - const auto *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getSubtarget().getRegisterInfo()); - const auto *AFI = MF.getInfo<AArch64FunctionInfo>(); const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>(); + const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); + const auto *AFI = MF.getInfo<AArch64FunctionInfo>(); int64_t FPOffset = getFPOffset(MF, ObjectOffset).getFixed(); int64_t Offset = getStackOffset(MF, ObjectOffset).getFixed(); @@ -1466,7 +1465,7 @@ StackOffset AArch64FrameLowering::resolveFrameOffsetReference( return FPOffset; } FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() - : (unsigned)AArch64::SP; + : MCRegister(AArch64::SP); return SPOffset; } @@ -1589,8 +1588,8 @@ static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, namespace { struct RegPairInfo { - unsigned Reg1 = AArch64::NoRegister; - unsigned Reg2 = AArch64::NoRegister; + Register Reg1; + Register Reg2; int FrameIdx; int Offset; enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; @@ -1598,21 +1597,21 @@ struct RegPairInfo { RegPairInfo() = default; - bool isPaired() const { return Reg2 != AArch64::NoRegister; } + bool isPaired() const { return Reg2.isValid(); } bool isScalable() const { return Type == PPR || Type == ZPR; } }; } // end anonymous namespace -unsigned findFreePredicateReg(BitVector &SavedRegs) { +MCRegister findFreePredicateReg(BitVector &SavedRegs) { for (unsigned PReg = AArch64::P8; PReg <= AArch64::P15; ++PReg) { if (SavedRegs.test(PReg)) { unsigned PNReg = PReg - AArch64::P0 + AArch64::PN0; - return PNReg; + return MCRegister(PNReg); } } - return AArch64::NoRegister; + return MCRegister(); } // The multivector LD/ST are available only for SME or SVE2p1 targets @@ -1930,8 +1929,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( } bool PTrueCreated = false; for (const RegPairInfo &RPI : llvm::reverse(RegPairs)) { - unsigned Reg1 = RPI.Reg1; - unsigned Reg2 = RPI.Reg2; + Register Reg1 = RPI.Reg1; + Register Reg2 = RPI.Reg2; unsigned StrOpc; // Issue sequence of spills for cs regs. The first spill may be converted @@ -1967,7 +1966,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( break; } - unsigned X0Scratch = AArch64::NoRegister; + Register X0Scratch; auto RestoreX0 = make_scope_exit([&] { if (X0Scratch != AArch64::NoRegister) BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), AArch64::X0) @@ -2009,11 +2008,15 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( } } - LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); - if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); - dbgs() << ") -> fi#(" << RPI.FrameIdx; - if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1; - dbgs() << ")\n"); + LLVM_DEBUG({ + dbgs() << "CSR spill: (" << printReg(Reg1, TRI); + if (RPI.isPaired()) + dbgs() << ", " << printReg(Reg2, TRI); + dbgs() << ") -> fi#(" << RPI.FrameIdx; + if (RPI.isPaired()) + dbgs() << ", " << RPI.FrameIdx + 1; + dbgs() << ")\n"; + }); assert((!NeedsWinCFI || !(Reg1 == AArch64::LR && Reg2 == AArch64::FP)) && "Windows unwdinding requires a consecutive (FP,LR) pair"); @@ -2143,8 +2146,8 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( bool PTrueCreated = false; for (const RegPairInfo &RPI : RegPairs) { - unsigned Reg1 = RPI.Reg1; - unsigned Reg2 = RPI.Reg2; + Register Reg1 = RPI.Reg1; + Register Reg2 = RPI.Reg2; // Issue sequence of restores for cs regs. The last restore may be converted // to a post-increment load later by emitEpilogue if the callee-save stack @@ -2176,11 +2179,15 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( case RegPairInfo::VG: continue; } - LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI); - if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); - dbgs() << ") -> fi#(" << RPI.FrameIdx; - if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1; - dbgs() << ")\n"); + LLVM_DEBUG({ + dbgs() << "CSR restore: (" << printReg(Reg1, TRI); + if (RPI.isPaired()) + dbgs() << ", " << printReg(Reg2, TRI); + dbgs() << ") -> fi#(" << RPI.FrameIdx; + if (RPI.isPaired()) + dbgs() << ", " << RPI.FrameIdx + 1; + dbgs() << ")\n"; + }); // Windows unwind codes require consecutive registers if registers are // paired. Make the switch here, so that the code below will save (x,x+1) @@ -2435,8 +2442,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); - const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getSubtarget().getRegisterInfo()); + const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); unsigned UnspilledCSGPR = AArch64::NoRegister; unsigned UnspilledCSGPRPaired = AArch64::NoRegister; @@ -2444,9 +2450,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, MachineFrameInfo &MFI = MF.getFrameInfo(); const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); - unsigned BasePointerReg = RegInfo->hasBasePointer(MF) - ? RegInfo->getBaseRegister() - : (unsigned)AArch64::NoRegister; + MCRegister BasePointerReg = + RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() : MCRegister(); unsigned ExtraCSSpill = 0; bool HasUnpairedGPR64 = false; @@ -2456,7 +2461,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, // Figure out which callee-saved registers to save/restore. for (unsigned i = 0; CSRegs[i]; ++i) { - const unsigned Reg = CSRegs[i]; + const MCRegister Reg = CSRegs[i]; // Add the base pointer register to SavedRegs if it is callee-save. if (Reg == BasePointerReg) @@ -2470,7 +2475,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, } bool RegUsed = SavedRegs.test(Reg); - unsigned PairedReg = AArch64::NoRegister; + MCRegister PairedReg; const bool RegIsGPR64 = AArch64::GPR64RegClass.contains(Reg); if (RegIsGPR64 || AArch64::FPR64RegClass.contains(Reg) || AArch64::FPR128RegClass.contains(Reg)) { @@ -2522,8 +2527,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); // Find a suitable predicate register for the multi-vector spill/fill // instructions. - unsigned PnReg = findFreePredicateReg(SavedRegs); - if (PnReg != AArch64::NoRegister) + MCRegister PnReg = findFreePredicateReg(SavedRegs); + if (PnReg.isValid()) AFI->setPredicateRegForFillSpill(PnReg); // If no free callee-save has been found assign one. if (!AFI->getPredicateRegForFillSpill() && @@ -2558,7 +2563,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, unsigned PPRCSStackSize = 0; const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); for (unsigned Reg : SavedRegs.set_bits()) { - auto *RC = TRI->getMinimalPhysRegClass(Reg); + auto *RC = TRI->getMinimalPhysRegClass(MCRegister(Reg)); assert(RC && "expected register class!"); auto SpillSize = TRI->getSpillSize(*RC); bool IsZPR = AArch64::ZPRRegClass.contains(Reg); @@ -2600,7 +2605,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, LLVM_DEBUG({ dbgs() << "*** determineCalleeSaves\nSaved CSRs:"; for (unsigned Reg : SavedRegs.set_bits()) - dbgs() << ' ' << printReg(Reg, RegInfo); + dbgs() << ' ' << printReg(MCRegister(Reg), RegInfo); dbgs() << "\n"; }); diff --git a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp index d67182d..03dd1cd 100644 --- a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp +++ b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp @@ -649,7 +649,7 @@ bool AArch64LowerHomogeneousPE::runOnMBB(MachineBasicBlock &MBB) { } bool AArch64LowerHomogeneousPE::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); + TII = MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); bool Modified = false; for (auto &MBB : MF) diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 79975b0..5bfb19d9 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -620,7 +620,7 @@ AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { return RC; } -unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } +MCRegister AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h index 47d76f3..3b0f4f6 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -124,7 +124,7 @@ public: bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; bool hasBasePointer(const MachineFunction &MF) const; - unsigned getBaseRegister() const; + MCRegister getBaseRegister() const; bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override; diff --git a/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp b/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp index d695f26..b4a4f4c 100644 --- a/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp +++ b/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp @@ -33,6 +33,7 @@ //===----------------------------------------------------------------------===// #include "AArch64InstrInfo.h" +#include "AArch64Subtarget.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringRef.h" @@ -49,8 +50,8 @@ #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCSchedule.h" #include "llvm/Pass.h" -#include <unordered_map> #include <map> +#include <unordered_map> using namespace llvm; @@ -67,7 +68,7 @@ namespace { struct AArch64SIMDInstrOpt : public MachineFunctionPass { static char ID; - const TargetInstrInfo *TII; + const AArch64InstrInfo *TII; MachineRegisterInfo *MRI; TargetSchedModel SchedModel; @@ -694,13 +695,9 @@ bool AArch64SIMDInstrOpt::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - TII = MF.getSubtarget().getInstrInfo(); MRI = &MF.getRegInfo(); - const TargetSubtargetInfo &ST = MF.getSubtarget(); - const AArch64InstrInfo *AAII = - static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); - if (!AAII) - return false; + const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>(); + TII = ST.getInstrInfo(); SchedModel.init(&ST); if (!SchedModel.hasInstrSchedModel()) return false; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 5c3e26e..4cd51d6 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1114,7 +1114,6 @@ bool AArch64InstPrinter::printSyslAlias(const MCInst *MI, } else return false; - std::string Str; llvm::transform(Name, Name.begin(), ::tolower); O << '\t' << Ins << '\t' << Reg.str() << ", " << Name; diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 53633ea..8198173 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -92,6 +92,8 @@ private: void emitFence(AtomicOrdering FenceOrdering, SyncScope::ID FenceSSID, MachineIRBuilder &MIB) const; bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const; + bool selectIntrinsicWithSideEffects(MachineInstr &I, + MachineIRBuilder &MIB) const; ComplexRendererFns selectShiftMask(MachineOperand &Root, unsigned ShiftWidth) const; @@ -714,6 +716,88 @@ static unsigned selectRegImmLoadStoreOp(unsigned GenericOpc, unsigned OpSize) { return GenericOpc; } +bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( + MachineInstr &I, MachineIRBuilder &MIB) const { + // Find the intrinsic ID. + unsigned IntrinID = cast<GIntrinsic>(I).getIntrinsicID(); + // Select the instruction. + switch (IntrinID) { + default: + return false; + case Intrinsic::riscv_vlm: + case Intrinsic::riscv_vle: + case Intrinsic::riscv_vle_mask: + case Intrinsic::riscv_vlse: + case Intrinsic::riscv_vlse_mask: { + bool IsMasked = IntrinID == Intrinsic::riscv_vle_mask || + IntrinID == Intrinsic::riscv_vlse_mask; + bool IsStrided = IntrinID == Intrinsic::riscv_vlse || + IntrinID == Intrinsic::riscv_vlse_mask; + LLT VT = MRI->getType(I.getOperand(0).getReg()); + unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); + + // Result vector + const Register DstReg = I.getOperand(0).getReg(); + + // Sources + bool HasPassthruOperand = IntrinID != Intrinsic::riscv_vlm; + unsigned CurOp = 2; + SmallVector<SrcOp, 4> SrcOps; // Source registers. + + // Passthru + if (HasPassthruOperand) { + auto PassthruReg = I.getOperand(CurOp++).getReg(); + SrcOps.push_back(PassthruReg); + } else { + SrcOps.push_back(Register(RISCV::NoRegister)); + } + + // Base Pointer + auto PtrReg = I.getOperand(CurOp++).getReg(); + SrcOps.push_back(PtrReg); + + // Stride + if (IsStrided) { + auto StrideReg = I.getOperand(CurOp++).getReg(); + SrcOps.push_back(StrideReg); + } + + // Mask + if (IsMasked) { + auto MaskReg = I.getOperand(CurOp++).getReg(); + SrcOps.push_back(MaskReg); + } + + RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(getMVTForLLT(VT)); + const RISCV::VLEPseudo *P = + RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW, + static_cast<unsigned>(LMUL)); + + auto PseudoMI = MIB.buildInstr(P->Pseudo, {DstReg}, SrcOps); + + // Select VL + auto VLOpFn = renderVLOp(I.getOperand(CurOp++)); + for (auto &RenderFn : *VLOpFn) + RenderFn(PseudoMI); + + // SEW + PseudoMI.addImm(Log2SEW); + + // Policy + uint64_t Policy = RISCVVType::MASK_AGNOSTIC; + if (IsMasked) + Policy = I.getOperand(CurOp++).getImm(); + PseudoMI.addImm(Policy); + + // Memref + PseudoMI.cloneMemRefs(I); + + I.eraseFromParent(); + return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + } + } +} + bool RISCVInstructionSelector::select(MachineInstr &MI) { MachineIRBuilder MIB(MI); @@ -984,6 +1068,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { return constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI); } + case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + return selectIntrinsicWithSideEffects(MI, MIB); default: return false; } diff --git a/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll b/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll index 6eed0ec..4c2a9c3 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll @@ -54,6 +54,100 @@ exit: ret void } +; Same as @test_inbounds_gep_used_in_predicated_block, but also storing the +; pointer values in the header. +define void @test_inbounds_gep_used_in_predicated_block_stored_value_operand(ptr %A, i64 %n, ptr noalias %B) { +; CHECK-LABEL: 'test_inbounds_gep_used_in_predicated_block_stored_value_operand' +; CHECK-NEXT: loop.header: +; CHECK-NEXT: Memory dependences are safe +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %loop.header + +loop.header: + %i = phi i64 [ 0, %entry ], [ %i.next, %loop.latch ] + %offset.0 = phi i64 [ 0, %entry ], [ %offset.0.next, %loop.latch ] + %offset.1 = phi i64 [ 0, %entry ], [ %offset.1.next, %loop.latch ] + %idx.0 = getelementptr inbounds i8, ptr %A, i64 %offset.0 + %idx.1 = getelementptr inbounds i8, ptr %A, i64 %offset.1 + %mask = and i64 %i, 3 + %cond = icmp eq i64 %mask, 0 + store ptr %idx.0, ptr %B + store ptr %idx.1, ptr %B + br i1 %cond, label %if.then, label %loop.latch + +if.then: + store i8 2, ptr %idx.0 + store i8 1, ptr %idx.1 + br label %loop.latch + +loop.latch: + %i.next = add nuw nsw i64 %i, 1 + %offset.0.next = add i64 %offset.0, 4611686018427387905 ; 2^62 + 1 + %offset.1.next = add i64 %offset.1, 4611686018427387906 ; 2^62 + 2 + %cond.exit = icmp eq i64 %i.next, 100 + br i1 %cond.exit, label %exit, label %loop.header + +exit: + ret void +} + +; Same as @test_inbounds_gep_used_in_predicated_block_non_memop_user, but with +; extra GEP users in the header. +define void @test_inbounds_gep_used_in_predicated_block_non_memop_user(ptr %A, i64 %n) { +; CHECK-LABEL: 'test_inbounds_gep_used_in_predicated_block_non_memop_user' +; CHECK-NEXT: loop.header: +; CHECK-NEXT: Memory dependences are safe +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %loop.header + +loop.header: + %i = phi i64 [ 0, %entry ], [ %i.next, %loop.latch ] + %offset.0 = phi i64 [ 0, %entry ], [ %offset.0.next, %loop.latch ] + %offset.1 = phi i64 [ 0, %entry ], [ %offset.1.next, %loop.latch ] + %idx.0 = getelementptr inbounds i8, ptr %A, i64 %offset.0 + %idx.1 = getelementptr inbounds i8, ptr %A, i64 %offset.1 + %mask = and i64 %i, 3 + %cond = icmp eq i64 %mask, 0 + %gep.idx.0 = getelementptr inbounds i8, ptr %idx.0, i8 1 + %gep.idx.1 = getelementptr inbounds i8, ptr %idx.1, i8 1 + br i1 %cond, label %if.then, label %loop.latch + +if.then: + store i8 2, ptr %idx.0 + store i8 1, ptr %idx.1 + br label %loop.latch + +loop.latch: + %i.next = add nuw nsw i64 %i, 1 + %offset.0.next = add i64 %offset.0, 4611686018427387905 ; 2^62 + 1 + %offset.1.next = add i64 %offset.1, 4611686018427387906 ; 2^62 + 2 + %cond.exit = icmp eq i64 %i.next, 100 + br i1 %cond.exit, label %exit, label %loop.header + +exit: + store i32 0, ptr %gep.idx.0 + store i32 0, ptr %gep.idx.1 + ret void +} + define void @test_header_existing(ptr %src, ptr %dst, i64 %start) { ; CHECK-LABEL: 'test_header_existing' ; CHECK-NEXT: loop.header: diff --git a/llvm/test/CodeGen/AArch64/sme-support-routines-calling-convention.ll b/llvm/test/CodeGen/AArch64/sme-support-routines-calling-convention.ll index 63c6533..a5b7612 100644 --- a/llvm/test/CodeGen/AArch64/sme-support-routines-calling-convention.ll +++ b/llvm/test/CodeGen/AArch64/sme-support-routines-calling-convention.ll @@ -64,6 +64,6 @@ define i64 @test_sme_calling_convention_x2() nounwind { ret i64 %pstate.sm } -declare void @__arm_tpidr2_save() -declare i64 @__arm_get_current_vg() -declare {i64, i64} @__arm_sme_state() +declare aarch64_sme_preservemost_from_x0 void @__arm_tpidr2_save() +declare aarch64_sme_preservemost_from_x1 i64 @__arm_get_current_vg() +declare aarch64_sme_preservemost_from_x2 {i64, i64} @__arm_sme_state() diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll new file mode 100644 index 0000000..3a74bcd --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll @@ -0,0 +1,1596 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \ +; RUN: -global-isel -verify-machineinstrs -target-abi=ilp32d | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \ +; RUN: -global-isel -verify-machineinstrs -target-abi=lp64d | FileCheck %s + +declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64( + <vscale x 1 x i64>, + ptr, + iXLen); + +define <vscale x 1 x i64> @intrinsic_vle_v_nxv1i64_nxv1i64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64( + <vscale x 1 x i64> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x i64> %a +} + +declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64( + <vscale x 1 x i64>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i64> @intrinsic_vle_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64( + <vscale x 1 x i64> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x i64> %a +} + +declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64( + <vscale x 2 x i64>, + ptr, + iXLen); + +define <vscale x 2 x i64> @intrinsic_vle_v_nxv2i64_nxv2i64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64( + <vscale x 2 x i64> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x i64> %a +} + +declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64( + <vscale x 2 x i64>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i64> @intrinsic_vle_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64( + <vscale x 2 x i64> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x i64> %a +} + +declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64( + <vscale x 4 x i64>, + ptr, + iXLen); + +define <vscale x 4 x i64> @intrinsic_vle_v_nxv4i64_nxv4i64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64( + <vscale x 4 x i64> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x i64> %a +} + +declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64( + <vscale x 4 x i64>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i64> @intrinsic_vle_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64( + <vscale x 4 x i64> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x i64> %a +} + +declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64( + <vscale x 8 x i64>, + ptr, + iXLen); + +define <vscale x 8 x i64> @intrinsic_vle_v_nxv8i64_nxv8i64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64( + <vscale x 8 x i64> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x i64> %a +} + +declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64( + <vscale x 8 x i64>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i64> @intrinsic_vle_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64( + <vscale x 8 x i64> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x i64> %a +} + +declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64( + <vscale x 1 x double>, + ptr, + iXLen); + +define <vscale x 1 x double> @intrinsic_vle_v_nxv1f64_nxv1f64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64( + <vscale x 1 x double> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x double> %a +} + +declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64( + <vscale x 1 x double>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x double> @intrinsic_vle_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64( + <vscale x 1 x double> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x double> %a +} + +declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64( + <vscale x 2 x double>, + ptr, + iXLen); + +define <vscale x 2 x double> @intrinsic_vle_v_nxv2f64_nxv2f64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64( + <vscale x 2 x double> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x double> %a +} + +declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64( + <vscale x 2 x double>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x double> @intrinsic_vle_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64( + <vscale x 2 x double> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x double> %a +} + +declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64( + <vscale x 4 x double>, + ptr, + iXLen); + +define <vscale x 4 x double> @intrinsic_vle_v_nxv4f64_nxv4f64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64( + <vscale x 4 x double> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x double> %a +} + +declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64( + <vscale x 4 x double>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x double> @intrinsic_vle_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64( + <vscale x 4 x double> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x double> %a +} + +declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64( + <vscale x 8 x double>, + ptr, + iXLen); + +define <vscale x 8 x double> @intrinsic_vle_v_nxv8f64_nxv8f64(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64( + <vscale x 8 x double> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x double> %a +} + +declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64( + <vscale x 8 x double>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x double> @intrinsic_vle_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64( + <vscale x 8 x double> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x double> %a +} + +declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32( + <vscale x 1 x i32>, + ptr, + iXLen); + +define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32( + <vscale x 1 x i32> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x i32> %a +} + +declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32( + <vscale x 1 x i32>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32( + <vscale x 1 x i32> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x i32> %a +} + +declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32( + <vscale x 2 x i32>, + ptr, + iXLen); + +define <vscale x 2 x i32> @intrinsic_vle_v_nxv2i32_nxv2i32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32( + <vscale x 2 x i32> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x i32> %a +} + +declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32( + <vscale x 2 x i32>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i32> @intrinsic_vle_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32( + <vscale x 2 x i32> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x i32> %a +} + +declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32( + <vscale x 4 x i32>, + ptr, + iXLen); + +define <vscale x 4 x i32> @intrinsic_vle_v_nxv4i32_nxv4i32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32( + <vscale x 4 x i32> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x i32> %a +} + +declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32( + <vscale x 4 x i32>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i32> @intrinsic_vle_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32( + <vscale x 4 x i32> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x i32> %a +} + +declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32( + <vscale x 8 x i32>, + ptr, + iXLen); + +define <vscale x 8 x i32> @intrinsic_vle_v_nxv8i32_nxv8i32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32( + <vscale x 8 x i32> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x i32> %a +} + +declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32( + <vscale x 8 x i32>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i32> @intrinsic_vle_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32( + <vscale x 8 x i32> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x i32> %a +} + +declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32( + <vscale x 16 x i32>, + ptr, + iXLen); + +define <vscale x 16 x i32> @intrinsic_vle_v_nxv16i32_nxv16i32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32( + <vscale x 16 x i32> poison, + ptr %0, + iXLen %1) + + ret <vscale x 16 x i32> %a +} + +declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32( + <vscale x 16 x i32>, + ptr, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x i32> @intrinsic_vle_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32( + <vscale x 16 x i32> %0, + ptr %1, + <vscale x 16 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 16 x i32> %a +} + +declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32( + <vscale x 1 x float>, + ptr, + iXLen); + +define <vscale x 1 x float> @intrinsic_vle_v_nxv1f32_nxv1f32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32( + <vscale x 1 x float> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x float> %a +} + +declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32( + <vscale x 1 x float>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x float> @intrinsic_vle_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32( + <vscale x 1 x float> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x float> %a +} + +declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32( + <vscale x 2 x float>, + ptr, + iXLen); + +define <vscale x 2 x float> @intrinsic_vle_v_nxv2f32_nxv2f32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32( + <vscale x 2 x float> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x float> %a +} + +declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32( + <vscale x 2 x float>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x float> @intrinsic_vle_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32( + <vscale x 2 x float> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x float> %a +} + +declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32( + <vscale x 4 x float>, + ptr, + iXLen); + +define <vscale x 4 x float> @intrinsic_vle_v_nxv4f32_nxv4f32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32( + <vscale x 4 x float> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x float> %a +} + +declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32( + <vscale x 4 x float>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x float> @intrinsic_vle_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32( + <vscale x 4 x float> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x float> %a +} + +declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32( + <vscale x 8 x float>, + ptr, + iXLen); + +define <vscale x 8 x float> @intrinsic_vle_v_nxv8f32_nxv8f32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32( + <vscale x 8 x float> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x float> %a +} + +declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32( + <vscale x 8 x float>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x float> @intrinsic_vle_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32( + <vscale x 8 x float> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x float> %a +} + +declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32( + <vscale x 16 x float>, + ptr, + iXLen); + +define <vscale x 16 x float> @intrinsic_vle_v_nxv16f32_nxv16f32(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32( + <vscale x 16 x float> poison, + ptr %0, + iXLen %1) + + ret <vscale x 16 x float> %a +} + +declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32( + <vscale x 16 x float>, + ptr, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x float> @intrinsic_vle_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32( + <vscale x 16 x float> %0, + ptr %1, + <vscale x 16 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 16 x float> %a +} + +declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16( + <vscale x 1 x i16>, + ptr, + iXLen); + +define <vscale x 1 x i16> @intrinsic_vle_v_nxv1i16_nxv1i16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16( + <vscale x 1 x i16> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x i16> %a +} + +declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16( + <vscale x 1 x i16>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i16> @intrinsic_vle_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16( + <vscale x 1 x i16> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x i16> %a +} + +declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16( + <vscale x 2 x i16>, + ptr, + iXLen); + +define <vscale x 2 x i16> @intrinsic_vle_v_nxv2i16_nxv2i16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16( + <vscale x 2 x i16> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x i16> %a +} + +declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16( + <vscale x 2 x i16>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i16> @intrinsic_vle_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16( + <vscale x 2 x i16> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x i16> %a +} + +declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16( + <vscale x 4 x i16>, + ptr, + iXLen); + +define <vscale x 4 x i16> @intrinsic_vle_v_nxv4i16_nxv4i16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16( + <vscale x 4 x i16> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x i16> %a +} + +declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16( + <vscale x 4 x i16>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i16> @intrinsic_vle_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16( + <vscale x 4 x i16> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x i16> %a +} + +declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16( + <vscale x 8 x i16>, + ptr, + iXLen); + +define <vscale x 8 x i16> @intrinsic_vle_v_nxv8i16_nxv8i16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16( + <vscale x 8 x i16> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x i16> %a +} + +declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16( + <vscale x 8 x i16>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i16> @intrinsic_vle_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16( + <vscale x 8 x i16> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x i16> %a +} + +declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16( + <vscale x 16 x i16>, + ptr, + iXLen); + +define <vscale x 16 x i16> @intrinsic_vle_v_nxv16i16_nxv16i16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16( + <vscale x 16 x i16> poison, + ptr %0, + iXLen %1) + + ret <vscale x 16 x i16> %a +} + +declare <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16( + <vscale x 16 x i16>, + ptr, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x i16> @intrinsic_vle_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16( + <vscale x 16 x i16> %0, + ptr %1, + <vscale x 16 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 16 x i16> %a +} + +declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16( + <vscale x 32 x i16>, + ptr, + iXLen); + +define <vscale x 32 x i16> @intrinsic_vle_v_nxv32i16_nxv32i16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16( + <vscale x 32 x i16> poison, + ptr %0, + iXLen %1) + + ret <vscale x 32 x i16> %a +} + +declare <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16( + <vscale x 32 x i16>, + ptr, + <vscale x 32 x i1>, + iXLen, + iXLen); + +define <vscale x 32 x i16> @intrinsic_vle_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16( + <vscale x 32 x i16> %0, + ptr %1, + <vscale x 32 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 32 x i16> %a +} + +declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16( + <vscale x 1 x half>, + ptr, + iXLen); + +define <vscale x 1 x half> @intrinsic_vle_v_nxv1f16_nxv1f16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16( + <vscale x 1 x half> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x half> %a +} + +declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16( + <vscale x 1 x half>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x half> @intrinsic_vle_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16( + <vscale x 1 x half> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x half> %a +} + +declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16( + <vscale x 2 x half>, + ptr, + iXLen); + +define <vscale x 2 x half> @intrinsic_vle_v_nxv2f16_nxv2f16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16( + <vscale x 2 x half> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x half> %a +} + +declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16( + <vscale x 2 x half>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x half> @intrinsic_vle_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16( + <vscale x 2 x half> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x half> %a +} + +declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16( + <vscale x 4 x half>, + ptr, + iXLen); + +define <vscale x 4 x half> @intrinsic_vle_v_nxv4f16_nxv4f16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16( + <vscale x 4 x half> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x half> %a +} + +declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16( + <vscale x 4 x half>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x half> @intrinsic_vle_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16( + <vscale x 4 x half> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x half> %a +} + +declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16( + <vscale x 8 x half>, + ptr, + iXLen); + +define <vscale x 8 x half> @intrinsic_vle_v_nxv8f16_nxv8f16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16( + <vscale x 8 x half> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x half> %a +} + +declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16( + <vscale x 8 x half>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x half> @intrinsic_vle_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16( + <vscale x 8 x half> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x half> %a +} + +declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16( + <vscale x 16 x half>, + ptr, + iXLen); + +define <vscale x 16 x half> @intrinsic_vle_v_nxv16f16_nxv16f16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16( + <vscale x 16 x half> poison, + ptr %0, + iXLen %1) + + ret <vscale x 16 x half> %a +} + +declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16( + <vscale x 16 x half>, + ptr, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x half> @intrinsic_vle_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16( + <vscale x 16 x half> %0, + ptr %1, + <vscale x 16 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 16 x half> %a +} + +declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16( + <vscale x 32 x half>, + ptr, + iXLen); + +define <vscale x 32 x half> @intrinsic_vle_v_nxv32f16_nxv32f16(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16( + <vscale x 32 x half> poison, + ptr %0, + iXLen %1) + + ret <vscale x 32 x half> %a +} + +declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16( + <vscale x 32 x half>, + ptr, + <vscale x 32 x i1>, + iXLen, + iXLen); + +define <vscale x 32 x half> @intrinsic_vle_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16( + <vscale x 32 x half> %0, + ptr %1, + <vscale x 32 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 32 x half> %a +} + +declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8( + <vscale x 1 x i8>, + ptr, + iXLen); + +define <vscale x 1 x i8> @intrinsic_vle_v_nxv1i8_nxv1i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8( + <vscale x 1 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 1 x i8> %a +} + +declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8( + <vscale x 1 x i8>, + ptr, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i8> @intrinsic_vle_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8( + <vscale x 1 x i8> %0, + ptr %1, + <vscale x 1 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 1 x i8> %a +} + +declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8( + <vscale x 2 x i8>, + ptr, + iXLen); + +define <vscale x 2 x i8> @intrinsic_vle_v_nxv2i8_nxv2i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8( + <vscale x 2 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 2 x i8> %a +} + +declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8( + <vscale x 2 x i8>, + ptr, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i8> @intrinsic_vle_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8( + <vscale x 2 x i8> %0, + ptr %1, + <vscale x 2 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 2 x i8> %a +} + +declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8( + <vscale x 4 x i8>, + ptr, + iXLen); + +define <vscale x 4 x i8> @intrinsic_vle_v_nxv4i8_nxv4i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8( + <vscale x 4 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 4 x i8> %a +} + +declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8( + <vscale x 4 x i8>, + ptr, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i8> @intrinsic_vle_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8( + <vscale x 4 x i8> %0, + ptr %1, + <vscale x 4 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 4 x i8> %a +} + +declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8( + <vscale x 8 x i8>, + ptr, + iXLen); + +define <vscale x 8 x i8> @intrinsic_vle_v_nxv8i8_nxv8i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8( + <vscale x 8 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 8 x i8> %a +} + +declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8( + <vscale x 8 x i8>, + ptr, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i8> @intrinsic_vle_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8( + <vscale x 8 x i8> %0, + ptr %1, + <vscale x 8 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 8 x i8> %a +} + +declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8( + <vscale x 16 x i8>, + ptr, + iXLen); + +define <vscale x 16 x i8> @intrinsic_vle_v_nxv16i8_nxv16i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8( + <vscale x 16 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 16 x i8> %a +} + +declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8( + <vscale x 16 x i8>, + ptr, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x i8> @intrinsic_vle_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8( + <vscale x 16 x i8> %0, + ptr %1, + <vscale x 16 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 16 x i8> %a +} + +declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8( + <vscale x 32 x i8>, + ptr, + iXLen); + +define <vscale x 32 x i8> @intrinsic_vle_v_nxv32i8_nxv32i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8( + <vscale x 32 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 32 x i8> %a +} + +declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8( + <vscale x 32 x i8>, + ptr, + <vscale x 32 x i1>, + iXLen, + iXLen); + +define <vscale x 32 x i8> @intrinsic_vle_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8( + <vscale x 32 x i8> %0, + ptr %1, + <vscale x 32 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 32 x i8> %a +} + +declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8( + <vscale x 64 x i8>, + ptr, + iXLen); + +define <vscale x 64 x i8> @intrinsic_vle_v_nxv64i8_nxv64i8(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8( + <vscale x 64 x i8> poison, + ptr %0, + iXLen %1) + + ret <vscale x 64 x i8> %a +} + +declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8( + <vscale x 64 x i8>, + ptr, + <vscale x 64 x i1>, + iXLen, + iXLen); + +define <vscale x 64 x i8> @intrinsic_vle_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i1> %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8( + <vscale x 64 x i8> %0, + ptr %1, + <vscale x 64 x i1> %2, + iXLen %3, iXLen 1) + + ret <vscale x 64 x i8> %a +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll new file mode 100644 index 0000000..1227963 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll @@ -0,0 +1,96 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -global-isel -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -global-isel -verify-machineinstrs | FileCheck %s + +declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(ptr, iXLen); + +define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(ptr %0, iXLen %1) + ret <vscale x 1 x i1> %a +} + +declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(ptr, iXLen); + +define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(ptr %0, iXLen %1) + ret <vscale x 2 x i1> %a +} + +declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(ptr, iXLen); + +define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(ptr %0, iXLen %1) + ret <vscale x 4 x i1> %a +} + +declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(ptr, iXLen); + +define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(ptr %0, iXLen %1) + ret <vscale x 8 x i1> %a +} + +declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(ptr, iXLen); + +define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(ptr %0, iXLen %1) + ret <vscale x 16 x i1> %a +} + +declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(ptr, iXLen); + +define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(ptr %0, iXLen %1) + ret <vscale x 32 x i1> %a +} + +declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(ptr, iXLen); + +define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(ptr %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vlm_v_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma +; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: ret +entry: + %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(ptr %0, iXLen %1) + ret <vscale x 64 x i1> %a +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll new file mode 100644 index 0000000..14abfa1 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll @@ -0,0 +1,1744 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \ +; RUN: -global-isel -verify-machineinstrs -target-abi=ilp32d | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \ +; RUN: -global-isel -verify-machineinstrs -target-abi=lp64d | FileCheck %s + +declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64( + <vscale x 1 x i64>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x i64> @intrinsic_vlse_v_nxv1i64_nxv1i64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64( + <vscale x 1 x i64> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x i64> %a +} + +declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64( + <vscale x 1 x i64>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i64> @intrinsic_vlse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64( + <vscale x 1 x i64> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x i64> %a +} + +declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64( + <vscale x 2 x i64>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x i64> @intrinsic_vlse_v_nxv2i64_nxv2i64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64( + <vscale x 2 x i64> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x i64> %a +} + +declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64( + <vscale x 2 x i64>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i64> @intrinsic_vlse_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64( + <vscale x 2 x i64> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x i64> %a +} + +declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64( + <vscale x 4 x i64>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x i64> @intrinsic_vlse_v_nxv4i64_nxv4i64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64( + <vscale x 4 x i64> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x i64> %a +} + +declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64( + <vscale x 4 x i64>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i64> @intrinsic_vlse_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64( + <vscale x 4 x i64> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x i64> %a +} + +declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64( + <vscale x 8 x i64>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x i64> @intrinsic_vlse_v_nxv8i64_nxv8i64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64( + <vscale x 8 x i64> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x i64> %a +} + +declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64( + <vscale x 8 x i64>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i64> @intrinsic_vlse_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64( + <vscale x 8 x i64> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x i64> %a +} + +declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64( + <vscale x 1 x double>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x double> @intrinsic_vlse_v_nxv1f64_nxv1f64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64( + <vscale x 1 x double> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x double> %a +} + +declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64( + <vscale x 1 x double>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x double> @intrinsic_vlse_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64( + <vscale x 1 x double> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x double> %a +} + +declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64( + <vscale x 2 x double>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x double> @intrinsic_vlse_v_nxv2f64_nxv2f64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64( + <vscale x 2 x double> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x double> %a +} + +declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64( + <vscale x 2 x double>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x double> @intrinsic_vlse_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64( + <vscale x 2 x double> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x double> %a +} + +declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64( + <vscale x 4 x double>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x double> @intrinsic_vlse_v_nxv4f64_nxv4f64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64( + <vscale x 4 x double> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x double> %a +} + +declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64( + <vscale x 4 x double>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x double> @intrinsic_vlse_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64( + <vscale x 4 x double> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x double> %a +} + +declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64( + <vscale x 8 x double>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x double> @intrinsic_vlse_v_nxv8f64_nxv8f64(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64( + <vscale x 8 x double> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x double> %a +} + +declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64( + <vscale x 8 x double>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x double> @intrinsic_vlse_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64( + <vscale x 8 x double> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x double> %a +} + +declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32( + <vscale x 1 x i32>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32( + <vscale x 1 x i32> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x i32> %a +} + +declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32( + <vscale x 1 x i32>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32( + <vscale x 1 x i32> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x i32> %a +} + +declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32( + <vscale x 2 x i32>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x i32> @intrinsic_vlse_v_nxv2i32_nxv2i32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32( + <vscale x 2 x i32> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x i32> %a +} + +declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32( + <vscale x 2 x i32>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i32> @intrinsic_vlse_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32( + <vscale x 2 x i32> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x i32> %a +} + +declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32( + <vscale x 4 x i32>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x i32> @intrinsic_vlse_v_nxv4i32_nxv4i32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32( + <vscale x 4 x i32> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x i32> %a +} + +declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32( + <vscale x 4 x i32>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i32> @intrinsic_vlse_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32( + <vscale x 4 x i32> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x i32> %a +} + +declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32( + <vscale x 8 x i32>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x i32> @intrinsic_vlse_v_nxv8i32_nxv8i32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32( + <vscale x 8 x i32> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x i32> %a +} + +declare <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32( + <vscale x 8 x i32>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i32> @intrinsic_vlse_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32( + <vscale x 8 x i32> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x i32> %a +} + +declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32( + <vscale x 16 x i32>, + ptr, + iXLen, + iXLen); + +define <vscale x 16 x i32> @intrinsic_vlse_v_nxv16i32_nxv16i32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32( + <vscale x 16 x i32> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 16 x i32> %a +} + +declare <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32( + <vscale x 16 x i32>, + ptr, + iXLen, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x i32> @intrinsic_vlse_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32( + <vscale x 16 x i32> %0, + ptr %1, + iXLen %2, + <vscale x 16 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 16 x i32> %a +} + +declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32( + <vscale x 1 x float>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x float> @intrinsic_vlse_v_nxv1f32_nxv1f32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32( + <vscale x 1 x float> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x float> %a +} + +declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32( + <vscale x 1 x float>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x float> @intrinsic_vlse_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32( + <vscale x 1 x float> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x float> %a +} + +declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32( + <vscale x 2 x float>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x float> @intrinsic_vlse_v_nxv2f32_nxv2f32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32( + <vscale x 2 x float> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x float> %a +} + +declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32( + <vscale x 2 x float>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x float> @intrinsic_vlse_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32( + <vscale x 2 x float> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x float> %a +} + +declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32( + <vscale x 4 x float>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x float> @intrinsic_vlse_v_nxv4f32_nxv4f32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32( + <vscale x 4 x float> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x float> %a +} + +declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32( + <vscale x 4 x float>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x float> @intrinsic_vlse_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32( + <vscale x 4 x float> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x float> %a +} + +declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32( + <vscale x 8 x float>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x float> @intrinsic_vlse_v_nxv8f32_nxv8f32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32( + <vscale x 8 x float> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x float> %a +} + +declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32( + <vscale x 8 x float>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x float> @intrinsic_vlse_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32( + <vscale x 8 x float> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x float> %a +} + +declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32( + <vscale x 16 x float>, + ptr, + iXLen, + iXLen); + +define <vscale x 16 x float> @intrinsic_vlse_v_nxv16f32_nxv16f32(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32( + <vscale x 16 x float> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 16 x float> %a +} + +declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32( + <vscale x 16 x float>, + ptr, + iXLen, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x float> @intrinsic_vlse_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32( + <vscale x 16 x float> %0, + ptr %1, + iXLen %2, + <vscale x 16 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 16 x float> %a +} + +declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16( + <vscale x 1 x i16>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x i16> @intrinsic_vlse_v_nxv1i16_nxv1i16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16( + <vscale x 1 x i16> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x i16> %a +} + +declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16( + <vscale x 1 x i16>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i16> @intrinsic_vlse_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16( + <vscale x 1 x i16> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x i16> %a +} + +declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16( + <vscale x 2 x i16>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x i16> @intrinsic_vlse_v_nxv2i16_nxv2i16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16( + <vscale x 2 x i16> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x i16> %a +} + +declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16( + <vscale x 2 x i16>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i16> @intrinsic_vlse_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16( + <vscale x 2 x i16> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x i16> %a +} + +declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16( + <vscale x 4 x i16>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x i16> @intrinsic_vlse_v_nxv4i16_nxv4i16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16( + <vscale x 4 x i16> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x i16> %a +} + +declare <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16( + <vscale x 4 x i16>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i16> @intrinsic_vlse_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16( + <vscale x 4 x i16> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x i16> %a +} + +declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16( + <vscale x 8 x i16>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x i16> @intrinsic_vlse_v_nxv8i16_nxv8i16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16( + <vscale x 8 x i16> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x i16> %a +} + +declare <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16( + <vscale x 8 x i16>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i16> @intrinsic_vlse_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16( + <vscale x 8 x i16> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x i16> %a +} + +declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16( + <vscale x 16 x i16>, + ptr, + iXLen, + iXLen); + +define <vscale x 16 x i16> @intrinsic_vlse_v_nxv16i16_nxv16i16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16( + <vscale x 16 x i16> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 16 x i16> %a +} + +declare <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16( + <vscale x 16 x i16>, + ptr, + iXLen, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x i16> @intrinsic_vlse_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16( + <vscale x 16 x i16> %0, + ptr %1, + iXLen %2, + <vscale x 16 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 16 x i16> %a +} + +declare <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16( + <vscale x 32 x i16>, + ptr, + iXLen, + iXLen); + +define <vscale x 32 x i16> @intrinsic_vlse_v_nxv32i16_nxv32i16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16( + <vscale x 32 x i16> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 32 x i16> %a +} + +declare <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16( + <vscale x 32 x i16>, + ptr, + iXLen, + <vscale x 32 x i1>, + iXLen, + iXLen); + +define <vscale x 32 x i16> @intrinsic_vlse_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16( + <vscale x 32 x i16> %0, + ptr %1, + iXLen %2, + <vscale x 32 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 32 x i16> %a +} + +declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16( + <vscale x 1 x half>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x half> @intrinsic_vlse_v_nxv1f16_nxv1f16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16( + <vscale x 1 x half> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x half> %a +} + +declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16( + <vscale x 1 x half>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x half> @intrinsic_vlse_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16( + <vscale x 1 x half> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x half> %a +} + +declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16( + <vscale x 2 x half>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x half> @intrinsic_vlse_v_nxv2f16_nxv2f16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16( + <vscale x 2 x half> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x half> %a +} + +declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16( + <vscale x 2 x half>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x half> @intrinsic_vlse_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16( + <vscale x 2 x half> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x half> %a +} + +declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16( + <vscale x 4 x half>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x half> @intrinsic_vlse_v_nxv4f16_nxv4f16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16( + <vscale x 4 x half> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x half> %a +} + +declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16( + <vscale x 4 x half>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x half> @intrinsic_vlse_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16( + <vscale x 4 x half> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x half> %a +} + +declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16( + <vscale x 8 x half>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x half> @intrinsic_vlse_v_nxv8f16_nxv8f16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16( + <vscale x 8 x half> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x half> %a +} + +declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16( + <vscale x 8 x half>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x half> @intrinsic_vlse_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16( + <vscale x 8 x half> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x half> %a +} + +declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16( + <vscale x 16 x half>, + ptr, + iXLen, + iXLen); + +define <vscale x 16 x half> @intrinsic_vlse_v_nxv16f16_nxv16f16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16( + <vscale x 16 x half> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 16 x half> %a +} + +declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16( + <vscale x 16 x half>, + ptr, + iXLen, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x half> @intrinsic_vlse_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16( + <vscale x 16 x half> %0, + ptr %1, + iXLen %2, + <vscale x 16 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 16 x half> %a +} + +declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16( + <vscale x 32 x half>, + ptr, + iXLen, + iXLen); + +define <vscale x 32 x half> @intrinsic_vlse_v_nxv32f16_nxv32f16(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16( + <vscale x 32 x half> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 32 x half> %a +} + +declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16( + <vscale x 32 x half>, + ptr, + iXLen, + <vscale x 32 x i1>, + iXLen, + iXLen); + +define <vscale x 32 x half> @intrinsic_vlse_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16( + <vscale x 32 x half> %0, + ptr %1, + iXLen %2, + <vscale x 32 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 32 x half> %a +} + +declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8( + <vscale x 1 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 1 x i8> @intrinsic_vlse_v_nxv1i8_nxv1i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8( + <vscale x 1 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 1 x i8> %a +} + +declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8( + <vscale x 1 x i8>, + ptr, + iXLen, + <vscale x 1 x i1>, + iXLen, + iXLen); + +define <vscale x 1 x i8> @intrinsic_vlse_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8( + <vscale x 1 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 1 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 1 x i8> %a +} + +declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8( + <vscale x 2 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 2 x i8> @intrinsic_vlse_v_nxv2i8_nxv2i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8( + <vscale x 2 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 2 x i8> %a +} + +declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8( + <vscale x 2 x i8>, + ptr, + iXLen, + <vscale x 2 x i1>, + iXLen, + iXLen); + +define <vscale x 2 x i8> @intrinsic_vlse_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8( + <vscale x 2 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 2 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 2 x i8> %a +} + +declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8( + <vscale x 4 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 4 x i8> @intrinsic_vlse_v_nxv4i8_nxv4i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8( + <vscale x 4 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 4 x i8> %a +} + +declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8( + <vscale x 4 x i8>, + ptr, + iXLen, + <vscale x 4 x i1>, + iXLen, + iXLen); + +define <vscale x 4 x i8> @intrinsic_vlse_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8( + <vscale x 4 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 4 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 4 x i8> %a +} + +declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8( + <vscale x 8 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 8 x i8> @intrinsic_vlse_v_nxv8i8_nxv8i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8( + <vscale x 8 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 8 x i8> %a +} + +declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8( + <vscale x 8 x i8>, + ptr, + iXLen, + <vscale x 8 x i1>, + iXLen, + iXLen); + +define <vscale x 8 x i8> @intrinsic_vlse_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8( + <vscale x 8 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 8 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 8 x i8> %a +} + +declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8( + <vscale x 16 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 16 x i8> @intrinsic_vlse_v_nxv16i8_nxv16i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8( + <vscale x 16 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 16 x i8> %a +} + +declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8( + <vscale x 16 x i8>, + ptr, + iXLen, + <vscale x 16 x i1>, + iXLen, + iXLen); + +define <vscale x 16 x i8> @intrinsic_vlse_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8( + <vscale x 16 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 16 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 16 x i8> %a +} + +declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8( + <vscale x 32 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 32 x i8> @intrinsic_vlse_v_nxv32i8_nxv32i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8( + <vscale x 32 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 32 x i8> %a +} + +declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8( + <vscale x 32 x i8>, + ptr, + iXLen, + <vscale x 32 x i1>, + iXLen, + iXLen); + +define <vscale x 32 x i8> @intrinsic_vlse_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8( + <vscale x 32 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 32 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 32 x i8> %a +} + +declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8( + <vscale x 64 x i8>, + ptr, + iXLen, + iXLen); + +define <vscale x 64 x i8> @intrinsic_vlse_v_nxv64i8_nxv64i8(ptr %0, iXLen %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: ret +entry: + %a = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8( + <vscale x 64 x i8> poison, + ptr %0, + iXLen %1, + iXLen %2) + + ret <vscale x 64 x i8> %a +} + +declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8( + <vscale x 64 x i8>, + ptr, + iXLen, + <vscale x 64 x i1>, + iXLen, + iXLen); + +define <vscale x 64 x i8> @intrinsic_vlse_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, iXLen %2, <vscale x 64 x i1> %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: ret +entry: + %a = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8( + <vscale x 64 x i8> %0, + ptr %1, + iXLen %2, + <vscale x 64 x i1> %3, + iXLen %4, iXLen 1) + + ret <vscale x 64 x i8> %a +} diff --git a/llvm/test/Transforms/LoopVectorize/version-mem-access.ll b/llvm/test/Transforms/LoopVectorize/version-mem-access.ll index 7bf4fbd..91b3099 100644 --- a/llvm/test/Transforms/LoopVectorize/version-mem-access.ll +++ b/llvm/test/Transforms/LoopVectorize/version-mem-access.ll @@ -1,6 +1,5 @@ -; RUN: opt -passes=loop-vectorize -enable-mem-access-versioning -force-vector-width=2 -force-vector-interleave=1 < %s -S | FileCheck %s - -target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph:" --version 6 +; RUN: opt -passes=loop-vectorize -enable-mem-access-versioning -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck %s ; Check that we version this loop with speculating the value 1 for symbolic ; strides. This also checks that the symbolic stride information is correctly @@ -8,50 +7,60 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" ; vectorize because we couldn't determine the array bounds for the required ; memchecks. -; CHECK-LABEL: test -define void @test(ptr %A, i64 %AStride, - ptr %B, i32 %BStride, - ptr %C, i64 %CStride, i32 %N) { +define void @test(ptr noalias %A, i64 %AStride, ptr noalias %B, i32 %BStride, ptr noalias %C, i64 %CStride) { +; CHECK-LABEL: define void @test( +; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[ASTRIDE:%.*]], ptr noalias [[B:%.*]], i32 [[BSTRIDE:%.*]], ptr noalias [[C:%.*]], i64 [[CSTRIDE:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] +; CHECK: [[VECTOR_SCEVCHECK]]: +; CHECK-NEXT: [[IDENT_CHECK1:%.*]] = icmp ne i32 [[BSTRIDE]], 1 +; CHECK-NEXT: [[IDENT_CHECK2:%.*]] = icmp ne i64 [[CSTRIDE]], 1 +; CHECK-NEXT: [[DIFF_CHECK6:%.*]] = icmp ne i64 [[ASTRIDE]], 1 +; CHECK-NEXT: [[DIFF_CHECK:%.*]] = or i1 [[IDENT_CHECK1]], [[IDENT_CHECK2]] +; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK6]] +; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INDEX]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP5]] +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]] +; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i32>, ptr [[TMP7]], align 4 +; CHECK-NEXT: [[TMP8:%.*]] = mul nsw <2 x i32> [[WIDE_LOAD7]], [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] +; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr [[TMP9]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br [[EXIT:label %.*]] +; CHECK: [[SCALAR_PH]]: +; entry: - %cmp13 = icmp eq i32 %N, 0 - br i1 %cmp13, label %for.end, label %for.body.preheader - -; CHECK-DAG: icmp ne i64 %AStride, 1 -; CHECK-DAG: icmp ne i32 %BStride, 1 -; CHECK-DAG: icmp ne i64 %CStride, 1 -; CHECK: or -; CHECK: or -; CHECK: br - -; CHECK: vector.body -; CHECK: load <2 x i32> + br label %loop -for.body.preheader: - br label %for.body - -for.body: - %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] - %iv.trunc = trunc i64 %indvars.iv to i32 +loop: + %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] + %iv.trunc = trunc i64 %iv to i32 %mul = mul i32 %iv.trunc, %BStride %mul64 = zext i32 %mul to i64 - %arrayidx = getelementptr inbounds i32, ptr %B, i64 %mul64 - %0 = load i32, ptr %arrayidx, align 4 - %mul2 = mul nsw i64 %indvars.iv, %CStride - %arrayidx3 = getelementptr inbounds i32, ptr %C, i64 %mul2 - %1 = load i32, ptr %arrayidx3, align 4 + %gep.x = getelementptr inbounds i32, ptr %B, i64 %mul64 + %0 = load i32, ptr %gep.x, align 4 + %mul2 = mul nsw i64 %iv, %CStride + %gep.c = getelementptr inbounds i32, ptr %C, i64 %mul2 + %1 = load i32, ptr %gep.c, align 4 %mul4 = mul nsw i32 %1, %0 - %mul3 = mul nsw i64 %indvars.iv, %AStride - %arrayidx7 = getelementptr inbounds i32, ptr %A, i64 %mul3 - store i32 %mul4, ptr %arrayidx7, align 4 - %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - %lftr.wideiv = trunc i64 %indvars.iv.next to i32 - %exitcond = icmp eq i32 %lftr.wideiv, %N - br i1 %exitcond, label %for.end.loopexit, label %for.body - -for.end.loopexit: - br label %for.end - -for.end: + %mul3 = mul nsw i64 %iv, %AStride + %gep.a = getelementptr inbounds i32, ptr %A, i64 %mul3 + store i32 %mul4, ptr %gep.a, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv.next, 100 + br i1 %ec, label %exit, label %loop + +exit: ret void } @@ -59,36 +68,150 @@ for.end: ; replacing the symbolic stride '%conv'. ; PR18480 -; CHECK-LABEL: fn1 -; CHECK: load <2 x double> - define void @fn1(ptr noalias %x, ptr noalias %c, double %a) { +; CHECK-LABEL: define void @fn1( +; CHECK-SAME: ptr noalias [[X:%.*]], ptr noalias [[C:%.*]], double [[A:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[CONV:%.*]] = fptosi double [[A]] to i32 +; CHECK-NEXT: [[CONV2:%.*]] = add i32 [[CONV]], 4 +; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[CONV2]], 0 +; CHECK-NEXT: br i1 [[CMP8]], label %[[LOOP_PREHEADER:.*]], [[EXIT:label %.*]] +; CHECK: [[LOOP_PREHEADER]]: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[CONV2]] to i64 +; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] +; CHECK: [[VECTOR_SCEVCHECK]]: +; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[CONV]], 1 +; CHECK-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDEX]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[TMP2]] +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP3]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds double, ptr [[C]], i64 [[INDEX]] +; CHECK-NEXT: store <2 x double> [[WIDE_LOAD]], ptr [[TMP4]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4 +; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br label %[[SCALAR_PH]] +; CHECK: [[SCALAR_PH]]: +; entry: %conv = fptosi double %a to i32 %conv2 = add i32 %conv, 4 %cmp8 = icmp sgt i32 %conv2, 0 - br i1 %cmp8, label %for.body.preheader, label %for.end + br i1 %cmp8, label %loop, label %exit -for.body.preheader: - br label %for.body - -for.body: - %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] - %0 = trunc i64 %indvars.iv to i32 +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %0 = trunc i64 %iv to i32 %mul = mul nsw i32 %0, %conv - %idxprom = sext i32 %mul to i64 - %arrayidx = getelementptr inbounds double, ptr %x, i64 %idxprom - %1 = load double, ptr %arrayidx, align 8 - %arrayidx3 = getelementptr inbounds double, ptr %c, i64 %indvars.iv - store double %1, ptr %arrayidx3, align 8 - %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - %lftr.wideiv = trunc i64 %indvars.iv.next to i32 - %exitcond = icmp eq i32 %lftr.wideiv, %conv2 - br i1 %exitcond, label %for.end.loopexit, label %for.body + %mul.ext = sext i32 %mul to i64 + %gep.x = getelementptr inbounds double, ptr %x, i64 %mul.ext + %1 = load double, ptr %gep.x, align 8 + %gep.c = getelementptr inbounds double, ptr %c, i64 %iv + store double %1, ptr %gep.c, align 8 + %iv.next = add nuw nsw i64 %iv, 1 + %iv.trunc = trunc i64 %iv.next to i32 + %ec = icmp eq i32 %iv.trunc, %conv2 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +; Make sure we do not crash when the stride is poison. +; Test for https://github.com/llvm/llvm-project/issues/162922. +define void @stride_poison(ptr %dst) mustprogress { +; CHECK-LABEL: define void @stride_poison( +; CHECK-SAME: ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 poison, i64 1) +; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 99, [[UMAX]] +; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 2 +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 2 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] +; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], poison +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], poison +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], poison +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], poison +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP4]] +; CHECK-NEXT: store i8 0, ptr [[TMP5]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP6]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH:.*]] +; CHECK: [[SCALAR_PH]]: +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.dst = getelementptr i8, ptr %dst, i64 %iv + store i8 0, ptr %gep.dst, align 1 + %iv.next = add nuw nsw i64 %iv, poison + %ec = icmp samesign ult i64 %iv, 100 + br i1 %ec, label %loop, label %exit + +exit: + ret void +} + +; Make sure we do not crash when the stride is undef. +define void @stride_undef(ptr %dst) mustprogress { +; CHECK-LABEL: define void @stride_undef( +; CHECK-SAME: ptr [[DST:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 undef, i64 1) +; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 99, [[UMAX]] +; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 2 +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 2 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] +; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], undef +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], undef +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], undef +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP4]] +; CHECK-NEXT: store i8 0, ptr [[TMP5]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP6]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH:.*]] +; CHECK: [[SCALAR_PH]]: +; +entry: + br label %loop -for.end.loopexit: - br label %for.end +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.dst = getelementptr i8, ptr %dst, i64 %iv + store i8 0, ptr %gep.dst, align 1 + %iv.next = add nuw nsw i64 %iv, undef + %ec = icmp samesign ult i64 %iv, 100 + br i1 %ec, label %loop, label %exit -for.end: +exit: ret void } |