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-rw-r--r--llvm/test/CodeGen/RISCV/rv32p.ll709
-rw-r--r--llvm/test/CodeGen/RISCV/rv64p.ll677
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/sf_vfbfexp16e.ll191
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/sf_vfexp16e.ll191
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/sf_vfexp32e.ll160
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/sf_vfexpa.ll335
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/sf_vfexpa64e.ll125
7 files changed, 2388 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
new file mode 100644
index 0000000..4eee880a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -0,0 +1,709 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define i32 @ctlz_i32(i32 %a) nounwind {
+; CHECK-LABEL: ctlz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+
+define i64 @ctlz_i64(i64 %a) nounwind {
+; CHECK-LABEL: ctlz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bnez a1, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: addi a0, a0, 32
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: clz a0, a1
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define i32 @cttz_i32(i32 %a) nounwind {
+; CHECK-LABEL: cttz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i64 @cttz_i64(i64 %a) nounwind {
+; CHECK-LABEL: cttz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: or a2, a0, a1
+; CHECK-NEXT: beqz a2, .LBB3_3
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: bnez a0, .LBB3_4
+; CHECK-NEXT: # %bb.2: # %cond.false
+; CHECK-NEXT: addi a0, a1, -1
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: j .LBB3_5
+; CHECK-NEXT: .LBB3_3:
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_4:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: .LBB3_5: # %cond.false
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+define i32 @sextb_i32(i32 %a) nounwind {
+; CHECK-LABEL: sextb_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 24
+ %shr = ashr exact i32 %shl, 24
+ ret i32 %shr
+}
+
+define i64 @sextb_i64(i64 %a) nounwind {
+; CHECK-LABEL: sextb_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: srai a1, a0, 31
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 56
+ %shr = ashr exact i64 %shl, 56
+ ret i64 %shr
+}
+
+define i32 @sexth_i32(i32 %a) nounwind {
+; CHECK-LABEL: sexth_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 16
+ %shr = ashr exact i32 %shl, 16
+ ret i32 %shr
+}
+
+define i64 @sexth_i64(i64 %a) nounwind {
+; CHECK-LABEL: sexth_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: srai a1, a0, 31
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 48
+ %shr = ashr exact i64 %shl, 48
+ ret i64 %shr
+}
+
+define i32 @min_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: min_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: min a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp slt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @min_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: min_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: slt a4, a1, a3
+; CHECK-NEXT: beqz a4, .LBB9_3
+; CHECK-NEXT: j .LBB9_4
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: bnez a4, .LBB9_4
+; CHECK-NEXT: .LBB9_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB9_4:
+; CHECK-NEXT: ret
+ %cmp = icmp slt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define i32 @max_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: max_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: max a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @max_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: max_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB11_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: slt a4, a3, a1
+; CHECK-NEXT: beqz a4, .LBB11_3
+; CHECK-NEXT: j .LBB11_4
+; CHECK-NEXT: .LBB11_2:
+; CHECK-NEXT: sltu a4, a2, a0
+; CHECK-NEXT: bnez a4, .LBB11_4
+; CHECK-NEXT: .LBB11_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB11_4:
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define i32 @minu_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: minu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @minu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: minu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB13_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: beqz a4, .LBB13_3
+; CHECK-NEXT: j .LBB13_4
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: bnez a4, .LBB13_4
+; CHECK-NEXT: .LBB13_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB13_4:
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define i32 @maxu_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: maxu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: maxu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: maxu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB15_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a3, a1
+; CHECK-NEXT: beqz a4, .LBB15_3
+; CHECK-NEXT: j .LBB15_4
+; CHECK-NEXT: .LBB15_2:
+; CHECK-NEXT: sltu a4, a2, a0
+; CHECK-NEXT: bnez a4, .LBB15_4
+; CHECK-NEXT: .LBB15_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB15_4:
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+declare i32 @llvm.abs.i32(i32, i1 immarg)
+
+define i32 @abs_i32(i32 %x) {
+; CHECK-LABEL: abs_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: abs a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 @abs_i64(i64 %x) {
+; CHECK-LABEL: abs_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bgez a1, .LBB17_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: snez a2, a0
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: neg a1, a1
+; CHECK-NEXT: sub a1, a1, a2
+; CHECK-NEXT: .LBB17_2:
+; CHECK-NEXT: ret
+ %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+ ret i64 %abs
+}
+
+define i32 @zexth_i32(i32 %a) nounwind {
+; CHECK-LABEL: zexth_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 16
+; CHECK-NEXT: srli a0, a0, 16
+; CHECK-NEXT: ret
+ %and = and i32 %a, 65535
+ ret i32 %and
+}
+
+define i64 @zexth_i64(i64 %a) nounwind {
+; CHECK-LABEL: zexth_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 16
+; CHECK-NEXT: srli a0, a0, 16
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+ %and = and i64 %a, 65535
+ ret i64 %and
+}
+
+declare i32 @llvm.bswap.i32(i32)
+
+define i32 @bswap_i32(i32 %a) nounwind {
+; CHECK-LABEL: bswap_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: ret
+ %1 = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %1
+}
+
+declare i64 @llvm.bswap.i64(i64)
+
+define i64 @bswap_i64(i64 %a) {
+; CHECK-LABEL: bswap_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a2, a1
+; CHECK-NEXT: rev8 a1, a0
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.bswap.i64(i64 %a)
+ ret i64 %1
+}
+
+define i32 @srai_slli(i16 signext %0) {
+; CHECK-LABEL: srai_slli:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 25
+; CHECK-NEXT: srai a0, a0, 31
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 15
+ %3 = sext i16 %sext to i32
+ ret i32 %3
+}
+
+define i32 @srai_slli2(i16 signext %0) {
+; CHECK-LABEL: srai_slli2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 25
+; CHECK-NEXT: srai a0, a0, 30
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 14
+ %3 = sext i16 %sext to i32
+ ret i32 %3
+}
+define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sub_if_uge_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: zext.b a2, a0
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: zext.b a0, a0
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i8 %x, %y
+ %select = select i1 %cmp, i8 0, i8 %y
+ %sub = sub nuw i8 %x, %select
+ ret i8 %sub
+}
+
+define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: sub_if_uge_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: and a1, a1, a2
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i16 %x, %y
+ %select = select i1 %cmp, i16 0, i16 %y
+ %sub = sub nuw i16 %x, %select
+ ret i16 %sub
+}
+
+define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB27_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: j .LBB27_3
+; CHECK-NEXT: .LBB27_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: .LBB27_3:
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: sub a1, a1, a3
+; CHECK-NEXT: sub a1, a1, a4
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, %y
+ %select = select i1 %cmp, i64 0, i64 %y
+ %sub = sub nuw i64 %x, %select
+ ret i64 %sub
+}
+
+define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lw a3, 4(a1)
+; CHECK-NEXT: lw a4, 8(a1)
+; CHECK-NEXT: lw a5, 12(a1)
+; CHECK-NEXT: lw a6, 4(a2)
+; CHECK-NEXT: lw t0, 12(a2)
+; CHECK-NEXT: lw a7, 8(a2)
+; CHECK-NEXT: beq a5, t0, .LBB28_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu t1, a5, t0
+; CHECK-NEXT: j .LBB28_3
+; CHECK-NEXT: .LBB28_2:
+; CHECK-NEXT: sltu t1, a4, a7
+; CHECK-NEXT: .LBB28_3:
+; CHECK-NEXT: lw a1, 0(a1)
+; CHECK-NEXT: lw a2, 0(a2)
+; CHECK-NEXT: beq a3, a6, .LBB28_5
+; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: sltu t2, a3, a6
+; CHECK-NEXT: j .LBB28_6
+; CHECK-NEXT: .LBB28_5:
+; CHECK-NEXT: sltu t2, a1, a2
+; CHECK-NEXT: .LBB28_6:
+; CHECK-NEXT: xor t3, a5, t0
+; CHECK-NEXT: xor t4, a4, a7
+; CHECK-NEXT: or t3, t4, t3
+; CHECK-NEXT: beqz t3, .LBB28_8
+; CHECK-NEXT: # %bb.7:
+; CHECK-NEXT: mv t2, t1
+; CHECK-NEXT: .LBB28_8:
+; CHECK-NEXT: addi t3, t2, -1
+; CHECK-NEXT: and t2, t3, t0
+; CHECK-NEXT: and t0, t3, a2
+; CHECK-NEXT: and t1, t3, a6
+; CHECK-NEXT: sltu a2, a1, t0
+; CHECK-NEXT: and a7, t3, a7
+; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: beq a3, t1, .LBB28_10
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: sltu a6, a3, t1
+; CHECK-NEXT: .LBB28_10:
+; CHECK-NEXT: sub t3, a4, a7
+; CHECK-NEXT: sltu a4, a4, a7
+; CHECK-NEXT: sub a5, a5, t2
+; CHECK-NEXT: sub a3, a3, t1
+; CHECK-NEXT: sub a1, a1, t0
+; CHECK-NEXT: sltu a7, t3, a6
+; CHECK-NEXT: sub a5, a5, a4
+; CHECK-NEXT: sub a4, t3, a6
+; CHECK-NEXT: sub a3, a3, a2
+; CHECK-NEXT: sub a2, a5, a7
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: sw a3, 4(a0)
+; CHECK-NEXT: sw a4, 8(a0)
+; CHECK-NEXT: sw a2, 12(a0)
+; CHECK-NEXT: ret
+ %cmp = icmp ult i128 %x, %y
+ %select = select i1 %cmp, i128 0, i128 %y
+ %sub = sub nuw i128 %x, %select
+ ret i128 %sub
+}
+
+define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a2, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: sll a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %shl = shl i32 %sub, %select
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: minu a2, a0, a2
+; CHECK-NEXT: bltu a0, a1, .LBB30_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: li a0, 4
+; CHECK-NEXT: sll a0, a2, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB30_2:
+; CHECK-NEXT: li a0, 2
+; CHECK-NEXT: sll a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %select2 = select i1 %cmp, i32 2, i32 4
+ %shl = shl i32 %sub, %select2
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: xori a3, a3, 1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: sw a3, 0(a2)
+; CHECK-NEXT: ret
+ %cmp = icmp uge i32 %x, %y
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %select = select i1 %cmp, i32 %y, i32 0
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i8 @sub_if_uge_C_i8(i8 zeroext %x) {
+; CHECK-LABEL: sub_if_uge_C_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -13
+; CHECK-NEXT: zext.b a1, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i8 %x, 12
+ %sub = add i8 %x, -13
+ %conv4 = select i1 %cmp, i8 %sub, i8 %x
+ ret i8 %conv4
+}
+
+define i16 @sub_if_uge_C_i16(i16 zeroext %x) {
+; CHECK-LABEL: sub_if_uge_C_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -251
+; CHECK-NEXT: slli a1, a1, 16
+; CHECK-NEXT: srli a1, a1, 16
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i16 %x, 250
+ %sub = add i16 %x, -251
+ %conv4 = select i1 %cmp, i16 %sub, i16 %x
+ ret i16 %conv4
+}
+
+define i32 @sub_if_uge_C_i32(i32 signext %x) {
+; CHECK-LABEL: sub_if_uge_C_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i64 @sub_if_uge_C_i64(i64 %x) {
+; CHECK-LABEL: sub_if_uge_C_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a2, 1
+; CHECK-NEXT: beq a1, a2, .LBB35_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltiu a2, a1, 2
+; CHECK-NEXT: xori a2, a2, 1
+; CHECK-NEXT: j .LBB35_3
+; CHECK-NEXT: .LBB35_2:
+; CHECK-NEXT: lui a2, 172127
+; CHECK-NEXT: addi a2, a2, 511
+; CHECK-NEXT: sltu a2, a2, a0
+; CHECK-NEXT: .LBB35_3:
+; CHECK-NEXT: neg a2, a2
+; CHECK-NEXT: andi a3, a2, -2
+; CHECK-NEXT: add a1, a1, a3
+; CHECK-NEXT: lui a3, 876449
+; CHECK-NEXT: addi a3, a3, -512
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: sltu a0, a2, a0
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %x, 4999999999
+ %sub = add i64 %x, -5000000000
+ %cond = select i1 %cmp, i64 %sub, i64 %x
+ ret i64 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
+; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: lui a3, 1048560
+; CHECK-NEXT: addi a2, a2, -16
+; CHECK-NEXT: addi a3, a3, 15
+; CHECK-NEXT: sltu a2, a2, a0
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: minu a0, a3, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
+; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 1048560
+; CHECK-NEXT: addi a2, a2, 15
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %sub = add i32 %x, -65521
+ store i32 %sub, ptr %z, align 4
+ %cmp = icmp ugt i32 %x, 65520
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_swapped_i32(i32 %x) {
+; CHECK-LABEL: sub_if_uge_C_swapped_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, 65521
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %x, i32 %sub
+ ret i32 %cond
+}
+
+define i7 @sub_if_uge_C_nsw_i7(i7 %a) {
+; CHECK-LABEL: sub_if_uge_C_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ugt i7 %x, -18
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %add, i7 %x
+ ret i7 %s
+}
+
+define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {
+; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ult i7 %x, -17
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %x, i7 %add
+ ret i7 %s
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
new file mode 100644
index 0000000..cb07f94
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -0,0 +1,677 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define signext i32 @ctlz_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: ctlz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+define signext i32 @log2_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: log2_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: li a1, 31
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+ %2 = sub i32 31, %1
+ ret i32 %2
+}
+
+define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: log2_ceil_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = sub i32 %a, 1
+ %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
+ %3 = sub i32 32, %2
+ ret i32 %3
+}
+
+define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: findLastSet_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clzw a1, a0
+; CHECK-NEXT: snez a0, a0
+; CHECK-NEXT: xori a1, a1, 31
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
+ %2 = xor i32 31, %1
+ %3 = icmp eq i32 %a, 0
+ %4 = select i1 %3, i32 -1, i32 %2
+ ret i32 %4
+}
+
+define i32 @ctlz_lshr_i32(i32 signext %a) {
+; CHECK-LABEL: ctlz_lshr_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srliw a0, a0, 1
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: ret
+ %1 = lshr i32 %a, 1
+ %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
+ ret i32 %2
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+
+define i64 @ctlz_i64(i64 %a) nounwind {
+; CHECK-LABEL: ctlz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define signext i32 @cttz_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: cttz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB6_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: cttz_zero_undef_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
+ ret i32 %1
+}
+
+define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: findFirstSet_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a2, a0
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: snez a0, a0
+; CHECK-NEXT: clzw a1, a1
+; CHECK-NEXT: sub a2, a2, a1
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: or a0, a0, a2
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
+ %2 = icmp eq i32 %a, 0
+ %3 = select i1 %2, i32 -1, i32 %1
+ ret i32 %3
+}
+
+define signext i32 @ffs_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: ffs_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a2, a0
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: li a2, 33
+; CHECK-NEXT: seqz a0, a0
+; CHECK-NEXT: clzw a1, a1
+; CHECK-NEXT: sub a2, a2, a1
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
+ %2 = add i32 %1, 1
+ %3 = icmp eq i32 %a, 0
+ %4 = select i1 %3, i32 0, i32 %2
+ ret i32 %4
+}
+
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i64 @cttz_i64(i64 %a) nounwind {
+; CHECK-LABEL: cttz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB10_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB10_2:
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+define signext i32 @sextb_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: sextb_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 24
+ %shr = ashr exact i32 %shl, 24
+ ret i32 %shr
+}
+
+define i64 @sextb_i64(i64 %a) nounwind {
+; CHECK-LABEL: sextb_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 56
+ %shr = ashr exact i64 %shl, 56
+ ret i64 %shr
+}
+
+define signext i32 @sexth_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: sexth_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 16
+ %shr = ashr exact i32 %shl, 16
+ ret i32 %shr
+}
+
+define i64 @sexth_i64(i64 %a) nounwind {
+; CHECK-LABEL: sexth_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 48
+ %shr = ashr exact i64 %shl, 48
+ ret i64 %shr
+}
+
+define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: min_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: min a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp slt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @min_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: min_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: min a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp slt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: max_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: max a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @max_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: max_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: max a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: minu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @minu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: minu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: maxu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: maxu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: maxu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: maxu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+declare i32 @llvm.abs.i32(i32, i1 immarg)
+
+define i32 @abs_i32(i32 %x) {
+; CHECK-LABEL: abs_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a0, a0
+; CHECK-NEXT: abs a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+define signext i32 @abs_i32_sext(i32 signext %x) {
+; CHECK-LABEL: abs_i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: abs a0, a0
+; CHECK-NEXT: sext.w a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 @abs_i64(i64 %x) {
+; CHECK-LABEL: abs_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: abs a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+ ret i64 %abs
+}
+
+declare i32 @llvm.bswap.i32(i32)
+
+define signext i32 @bswap_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: bswap_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: srai a0, a0, 32
+; CHECK-NEXT: ret
+ %1 = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %1
+}
+
+; Similar to bswap_i32 but the result is not sign extended.
+define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {
+; CHECK-LABEL: bswap_i32_nosext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: srli a0, a0, 32
+; CHECK-NEXT: sw a0, 0(a1)
+; CHECK-NEXT: ret
+ %1 = tail call i32 @llvm.bswap.i32(i32 %a)
+ store i32 %1, ptr %x
+ ret void
+}
+
+declare i64 @llvm.bswap.i64(i64)
+
+define i64 @bswap_i64(i64 %a) {
+; CHECK-LABEL: bswap_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.bswap.i64(i64 %a)
+ ret i64 %1
+}
+
+define i64 @srai_slli(i16 signext %0) {
+; CHECK-LABEL: srai_slli:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 57
+; CHECK-NEXT: srai a0, a0, 63
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 15
+ %3 = sext i16 %sext to i64
+ ret i64 %3
+}
+
+define i64 @srai_slli2(i16 signext %0) {
+; CHECK-LABEL: srai_slli2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 57
+; CHECK-NEXT: srai a0, a0, 62
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 14
+ %3 = sext i16 %sext to i64
+ ret i64 %3
+}
+
+define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 {
+; CHECK-LABEL: func0000000000000001:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: slli a1, a1, 59
+; CHECK-NEXT: srai a1, a1, 63
+; CHECK-NEXT: addw a0, a1, a0
+; CHECK-NEXT: ret
+entry:
+ %2 = shl i8 %1, 3
+ %3 = ashr i8 %2, 7
+ %4 = sext i8 %3 to i32
+ %5 = add nsw i32 %4, %0
+ ret i32 %5
+}
+
+define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sub_if_uge_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: zext.b a2, a0
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: zext.b a0, a0
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i8 %x, %y
+ %select = select i1 %cmp, i8 0, i8 %y
+ %sub = sub nuw i8 %x, %select
+ ret i8 %sub
+}
+
+define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: sub_if_uge_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: and a1, a1, a2
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i16 %x, %y
+ %select = select i1 %cmp, i16 0, i16 %y
+ %sub = sub nuw i16 %x, %select
+ ret i16 %sub
+}
+
+define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a0
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, %y
+ %select = select i1 %cmp, i64 0, i64 %y
+ %sub = sub nuw i64 %x, %select
+ ret i64 %sub
+}
+
+define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB36_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: j .LBB36_3
+; CHECK-NEXT: .LBB36_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: .LBB36_3:
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: sub a1, a1, a3
+; CHECK-NEXT: sub a1, a1, a4
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ult i128 %x, %y
+ %select = select i1 %cmp, i128 0, i128 %y
+ %sub = sub nuw i128 %x, %select
+ ret i128 %sub
+}
+
+define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: sltu a2, a3, a2
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %shl = shl i32 %sub, %select
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: minu a0, a3, a0
+; CHECK-NEXT: bltu a3, a2, .LBB38_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: li a1, 4
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB38_2:
+; CHECK-NEXT: li a1, 2
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %select2 = select i1 %cmp, i32 2, i32 4
+ %shl = shl i32 %sub, %select2
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, ptr %z) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: subw a1, a0, a1
+; CHECK-NEXT: xori a3, a3, 1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: sw a3, 0(a2)
+; CHECK-NEXT: ret
+ %cmp = icmp uge i32 %x, %y
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %select = select i1 %cmp, i32 %y, i32 0
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i8 @sub_if_uge_C_i8(i8 zeroext %x) {
+; CHECK-LABEL: sub_if_uge_C_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -13
+; CHECK-NEXT: zext.b a1, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i8 %x, 12
+ %sub = add i8 %x, -13
+ %conv4 = select i1 %cmp, i8 %sub, i8 %x
+ ret i8 %conv4
+}
+
+define i16 @sub_if_uge_C_i16(i16 zeroext %x) {
+; CHECK-LABEL: sub_if_uge_C_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -251
+; CHECK-NEXT: slli a1, a1, 48
+; CHECK-NEXT: srli a1, a1, 48
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i16 %x, 250
+ %sub = add i16 %x, -251
+ %conv4 = select i1 %cmp, i16 %sub, i16 %x
+ ret i16 %conv4
+}
+
+define i32 @sub_if_uge_C_i32(i32 signext %x) {
+; CHECK-LABEL: sub_if_uge_C_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: addw a1, a0, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i64 @sub_if_uge_C_i64(i64 %x) {
+; CHECK-LABEL: sub_if_uge_C_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1046192
+; CHECK-NEXT: addi a1, a1, -761
+; CHECK-NEXT: slli a1, a1, 9
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %x, 4999999999
+ %sub = add i64 %x, -5000000000
+ %cond = select i1 %cmp, i64 %sub, i64 %x
+ ret i64 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
+; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: lui a3, 1048560
+; CHECK-NEXT: addi a2, a2, -16
+; CHECK-NEXT: addi a3, a3, 15
+; CHECK-NEXT: sltu a2, a2, a0
+; CHECK-NEXT: addw a3, a0, a3
+; CHECK-NEXT: minu a0, a3, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
+; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 1048560
+; CHECK-NEXT: addi a2, a2, 15
+; CHECK-NEXT: addw a2, a0, a2
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %sub = add i32 %x, -65521
+ store i32 %sub, ptr %z, align 4
+ %cmp = icmp ugt i32 %x, 65520
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {
+; CHECK-LABEL: sub_if_uge_C_swapped_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: addw a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, 65521
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %x, i32 %sub
+ ret i32 %cond
+}
+
+define i7 @sub_if_uge_C_nsw_i7(i7 %a) {
+; CHECK-LABEL: sub_if_uge_C_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ugt i7 %x, -18
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %add, i7 %x
+ ret i7 %s
+}
+
+define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {
+; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ult i7 %x, -17
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %x, i7 %add
+ ret i7 %s
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfbfexp16e.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfbfexp16e.ll
new file mode 100644
index 0000000..5c0c6c1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfbfexp16e.ll
@@ -0,0 +1,191 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+xsfvfbfexp16e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+xsfvfbfexp16e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x bfloat> @intrinsic_sf_vfexp_v_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv1bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16(
+ <vscale x 1 x bfloat> poison,
+ <vscale x 1 x bfloat> %0,
+ iXLen %1)
+
+ ret <vscale x 1 x bfloat> %a
+}
+
+define <vscale x 2 x bfloat> @intrinsic_sf_vfexp_v_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv2bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16(
+ <vscale x 2 x bfloat> poison,
+ <vscale x 2 x bfloat> %0,
+ iXLen %1)
+
+ ret <vscale x 2 x bfloat> %a
+}
+
+define <vscale x 4 x bfloat> @intrinsic_sf_vfexp_v_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv4bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16(
+ <vscale x 4 x bfloat> poison,
+ <vscale x 4 x bfloat> %0,
+ iXLen %1)
+
+ ret <vscale x 4 x bfloat> %a
+}
+
+define <vscale x 8 x bfloat> @intrinsic_sf_vfexp_v_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv8bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16(
+ <vscale x 8 x bfloat> poison,
+ <vscale x 8 x bfloat> %0,
+ iXLen %1)
+
+ ret <vscale x 8 x bfloat> %a
+}
+
+define <vscale x 16 x bfloat> @intrinsic_sf_vfexp_v_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv16bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16(
+ <vscale x 16 x bfloat> poison,
+ <vscale x 16 x bfloat> %0,
+ iXLen %1)
+
+ ret <vscale x 16 x bfloat> %a
+}
+
+define <vscale x 32 x bfloat> @intrinsic_sf_vfexp_v_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv32bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16(
+ <vscale x 32 x bfloat> poison,
+ <vscale x 32 x bfloat> %0,
+ iXLen %1)
+
+ ret <vscale x 32 x bfloat> %a
+}
+
+define <vscale x 1 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv1bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16(
+ <vscale x 1 x bfloat> %0,
+ <vscale x 1 x bfloat> %1,
+ <vscale x 1 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 1 x bfloat> %a
+}
+
+define <vscale x 2 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv2bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16(
+ <vscale x 2 x bfloat> %0,
+ <vscale x 2 x bfloat> %1,
+ <vscale x 2 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 2 x bfloat> %a
+}
+
+define <vscale x 4 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv4bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16(
+ <vscale x 4 x bfloat> %0,
+ <vscale x 4 x bfloat> %1,
+ <vscale x 4 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 4 x bfloat> %a
+}
+
+define <vscale x 8 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv8bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16(
+ <vscale x 8 x bfloat> %0,
+ <vscale x 8 x bfloat> %1,
+ <vscale x 8 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 8 x bfloat> %a
+}
+
+define <vscale x 16 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv16bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv16bf16(
+ <vscale x 16 x bfloat> %0,
+ <vscale x 16 x bfloat> %1,
+ <vscale x 16 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 16 x bfloat> %a
+}
+
+define <vscale x 32 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv32bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv32bf16(
+ <vscale x 32 x bfloat> %0,
+ <vscale x 32 x bfloat> %1,
+ <vscale x 32 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 32 x bfloat> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfexp16e.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfexp16e.ll
new file mode 100644
index 0000000..2d97f73
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfexp16e.ll
@@ -0,0 +1,191 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvfexp16e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvfexp16e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x half> @intrinsic_sf_vfexp_v_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16(
+ <vscale x 1 x half> poison,
+ <vscale x 1 x half> %0,
+ iXLen %1)
+
+ ret <vscale x 1 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_sf_vfexp_v_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16(
+ <vscale x 2 x half> poison,
+ <vscale x 2 x half> %0,
+ iXLen %1)
+
+ ret <vscale x 2 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_sf_vfexp_v_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16(
+ <vscale x 4 x half> poison,
+ <vscale x 4 x half> %0,
+ iXLen %1)
+
+ ret <vscale x 4 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_sf_vfexp_v_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16(
+ <vscale x 8 x half> poison,
+ <vscale x 8 x half> %0,
+ iXLen %1)
+
+ ret <vscale x 8 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_sf_vfexp_v_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16(
+ <vscale x 16 x half> poison,
+ <vscale x 16 x half> %0,
+ iXLen %1)
+
+ ret <vscale x 16 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_sf_vfexp_v_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv32f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16(
+ <vscale x 32 x half> poison,
+ <vscale x 32 x half> %0,
+ iXLen %1)
+
+ ret <vscale x 32 x half> %a
+}
+
+define <vscale x 1 x half> @intrinsic_sf_vfexp_mask_v_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16(
+ <vscale x 1 x half> %0,
+ <vscale x 1 x half> %1,
+ <vscale x 1 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 1 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_sf_vfexp_mask_v_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16(
+ <vscale x 2 x half> %0,
+ <vscale x 2 x half> %1,
+ <vscale x 2 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 2 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_sf_vfexp_mask_v_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16(
+ <vscale x 4 x half> %0,
+ <vscale x 4 x half> %1,
+ <vscale x 4 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 4 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_sf_vfexp_mask_v_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16(
+ <vscale x 8 x half> %0,
+ <vscale x 8 x half> %1,
+ <vscale x 8 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 8 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_sf_vfexp_mask_v_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16(
+ <vscale x 16 x half> %0,
+ <vscale x 16 x half> %1,
+ <vscale x 16 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 16 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_sf_vfexp_mask_v_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv32f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.mask.nxv32f16(
+ <vscale x 32 x half> %0,
+ <vscale x 32 x half> %1,
+ <vscale x 32 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 32 x half> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfexp32e.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfexp32e.ll
new file mode 100644
index 0000000..46dce14
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfexp32e.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvfexp32e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvfexp32e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x float> @intrinsic_sf_vfexp_v_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32(
+ <vscale x 1 x float> poison,
+ <vscale x 1 x float> %0,
+ iXLen %1)
+
+ ret <vscale x 1 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_sf_vfexp_v_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32(
+ <vscale x 2 x float> poison,
+ <vscale x 2 x float> %0,
+ iXLen %1)
+
+ ret <vscale x 2 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_sf_vfexp_v_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32(
+ <vscale x 4 x float> poison,
+ <vscale x 4 x float> %0,
+ iXLen %1)
+
+ ret <vscale x 4 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_sf_vfexp_v_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32(
+ <vscale x 8 x float> poison,
+ <vscale x 8 x float> %0,
+ iXLen %1)
+
+ ret <vscale x 8 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_sf_vfexp_v_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv16f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: sf.vfexp.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32(
+ <vscale x 16 x float> poison,
+ <vscale x 16 x float> %0,
+ iXLen %1)
+
+ ret <vscale x 16 x float> %a
+}
+
+define <vscale x 1 x float> @intrinsic_sf_vfexp_mask_v_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32(
+ <vscale x 1 x float> %0,
+ <vscale x 1 x float> %1,
+ <vscale x 1 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 1 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_sf_vfexp_mask_v_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32(
+ <vscale x 2 x float> %0,
+ <vscale x 2 x float> %1,
+ <vscale x 2 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 2 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_sf_vfexp_mask_v_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32(
+ <vscale x 4 x float> %0,
+ <vscale x 4 x float> %1,
+ <vscale x 4 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 4 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_sf_vfexp_mask_v_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32(
+ <vscale x 8 x float> %0,
+ <vscale x 8 x float> %1,
+ <vscale x 8 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 8 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_sf_vfexp_mask_v_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %m, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv16f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
+; CHECK-NEXT: sf.vfexp.v v8, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32(
+ <vscale x 16 x float> %0,
+ <vscale x 16 x float> %1,
+ <vscale x 16 x i1> %m,
+ iXLen %2, iXLen 0)
+
+ ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa.ll
new file mode 100644
index 0000000..d3d10d2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa.ll
@@ -0,0 +1,335 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64f,+zvfh,+xsfvfexpa \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64f,+zvfh,+xsfvfexpa \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x float> @test_intrinsic_sf_vfexpa_v_nxv1f32(<vscale x 1 x float> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32(
+ <vscale x 1 x float> poison,
+ <vscale x 1 x float> %0,
+ iXLen %1)
+ ret <vscale x 1 x float> %f
+}
+
+define <vscale x 2 x float> @test_intrinsic_sf_vfexpa_v_nxv2f32(<vscale x 2 x float> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32(
+ <vscale x 2 x float> poison,
+ <vscale x 2 x float> %0,
+ iXLen %1)
+ ret <vscale x 2 x float> %f
+}
+
+define <vscale x 4 x float> @test_intrinsic_sf_vfexpa_v_nxv4f32(<vscale x 4 x float> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32(
+ <vscale x 4 x float> poison,
+ <vscale x 4 x float> %0,
+ iXLen %1)
+ ret <vscale x 4 x float> %f
+}
+
+define <vscale x 8 x float> @test_intrinsic_sf_vfexpa_v_nxv8f32(<vscale x 8 x float> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32(
+ <vscale x 8 x float> poison,
+ <vscale x 8 x float> %0,
+ iXLen %1)
+ ret <vscale x 8 x float> %f
+}
+
+define <vscale x 16 x float> @test_intrinsic_sf_vfexpa_v_nxv16f32(<vscale x 16 x float> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv16f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32(
+ <vscale x 16 x float> poison,
+ <vscale x 16 x float> %0,
+ iXLen %1)
+ ret <vscale x 16 x float> %f
+}
+
+define <vscale x 1 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.mask.nxv1f32(
+ <vscale x 1 x float> %0,
+ <vscale x 1 x float> %1,
+ <vscale x 1 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 1 x float> %f
+}
+
+define <vscale x 2 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.mask.nxv2f32(
+ <vscale x 2 x float> %0,
+ <vscale x 2 x float> %1,
+ <vscale x 2 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 2 x float> %f
+}
+
+define <vscale x 4 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.mask.nxv4f32(
+ <vscale x 4 x float> %0,
+ <vscale x 4 x float> %1,
+ <vscale x 4 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 4 x float> %f
+}
+
+define <vscale x 8 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.mask.nxv8f32(
+ <vscale x 8 x float> %0,
+ <vscale x 8 x float> %1,
+ <vscale x 8 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 8 x float> %f
+}
+
+define <vscale x 16 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv16f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.mask.nxv16f32(
+ <vscale x 16 x float> %0,
+ <vscale x 16 x float> %1,
+ <vscale x 16 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 16 x float> %f
+}
+
+define <vscale x 1 x half> @test_intrinsic_sf_vfexpa_v_nxv1f16(<vscale x 1 x half> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16(
+ <vscale x 1 x half> poison,
+ <vscale x 1 x half> %0,
+ iXLen %1)
+ ret <vscale x 1 x half> %f
+}
+
+define <vscale x 2 x half> @test_intrinsic_sf_vfexpa_v_nxv2f16(<vscale x 2 x half> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16(
+ <vscale x 2 x half> poison,
+ <vscale x 2 x half> %0,
+ iXLen %1)
+ ret <vscale x 2 x half> %f
+}
+
+define <vscale x 4 x half> @test_intrinsic_sf_vfexpa_v_nxv4f16(<vscale x 4 x half> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16(
+ <vscale x 4 x half> poison,
+ <vscale x 4 x half> %0,
+ iXLen %1)
+ ret <vscale x 4 x half> %f
+}
+
+define <vscale x 8 x half> @test_intrinsic_sf_vfexpa_v_nxv8f16(<vscale x 8 x half> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16(
+ <vscale x 8 x half> poison,
+ <vscale x 8 x half> %0,
+ iXLen %1)
+ ret <vscale x 8 x half> %f
+}
+
+define <vscale x 16 x half> @test_intrinsic_sf_vfexpa_v_nxv16f16(<vscale x 16 x half> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16(
+ <vscale x 16 x half> poison,
+ <vscale x 16 x half> %0,
+ iXLen %1)
+ ret <vscale x 16 x half> %f
+}
+
+define <vscale x 32 x half> @test_intrinsic_sf_vfexpa_v_nxv32f16(<vscale x 32 x half> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv32f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16(
+ <vscale x 32 x half> poison,
+ <vscale x 32 x half> %0,
+ iXLen %1)
+ ret <vscale x 32 x half> %f
+}
+
+define <vscale x 1 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16(
+ <vscale x 1 x half> %0,
+ <vscale x 1 x half> %1,
+ <vscale x 1 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 1 x half> %f
+}
+
+define <vscale x 2 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.mask.nxv2f16(
+ <vscale x 2 x half> %0,
+ <vscale x 2 x half> %1,
+ <vscale x 2 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 2 x half> %f
+}
+
+define <vscale x 4 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.mask.nxv4f16(
+ <vscale x 4 x half> %0,
+ <vscale x 4 x half> %1,
+ <vscale x 4 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 4 x half> %f
+}
+
+define <vscale x 8 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.mask.nxv8f16(
+ <vscale x 8 x half> %0,
+ <vscale x 8 x half> %1,
+ <vscale x 8 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 8 x half> %f
+}
+
+define <vscale x 16 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.mask.nxv16f16(
+ <vscale x 16 x half> %0,
+ <vscale x 16 x half> %1,
+ <vscale x 16 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 16 x half> %f
+}
+
+define <vscale x 32 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv32f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.mask.nxv32f16(
+ <vscale x 32 x half> %0,
+ <vscale x 32 x half> %1,
+ <vscale x 32 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 32 x half> %f
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa64e.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa64e.ll
new file mode 100644
index 0000000..3de0e93
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa64e.ll
@@ -0,0 +1,125 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfvfexpa64e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfvfexpa64e \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x double> @test_intrinsic_sf_vfexpa_v_nxv1f64(<vscale x 1 x double> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64(
+ <vscale x 1 x double> poison,
+ <vscale x 1 x double> %0,
+ iXLen %1)
+ ret <vscale x 1 x double> %f
+}
+
+define <vscale x 2 x double> @test_intrinsic_sf_vfexpa_v_nxv2f64(<vscale x 2 x double> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64(
+ <vscale x 2 x double> poison,
+ <vscale x 2 x double> %0,
+ iXLen %1)
+ ret <vscale x 2 x double> %f
+}
+
+define <vscale x 4 x double> @test_intrinsic_sf_vfexpa_v_nxv4f64(<vscale x 4 x double> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64(
+ <vscale x 4 x double> poison,
+ <vscale x 4 x double> %0,
+ iXLen %1)
+ ret <vscale x 4 x double> %f
+}
+
+define <vscale x 8 x double> @test_intrinsic_sf_vfexpa_v_nxv8f64(<vscale x 8 x double> %0, iXLen %1) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: sf.vfexpa.v v8, v8
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64(
+ <vscale x 8 x double> poison,
+ <vscale x 8 x double> %0,
+ iXLen %1)
+ ret <vscale x 8 x double> %f
+}
+
+define <vscale x 1 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64(
+ <vscale x 1 x double> %0,
+ <vscale x 1 x double> %1,
+ <vscale x 1 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 1 x double> %f
+}
+
+define <vscale x 2 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64(
+ <vscale x 2 x double> %0,
+ <vscale x 2 x double> %1,
+ <vscale x 2 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 2 x double> %f
+}
+
+define <vscale x 4 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64(
+ <vscale x 4 x double> %0,
+ <vscale x 4 x double> %1,
+ <vscale x 4 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 4 x double> %f
+}
+
+define <vscale x 8 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %m, iXLen %vl) {
+; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
+; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t
+; CHECK-NEXT: ret
+entry:
+ %f = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64(
+ <vscale x 8 x double> %0,
+ <vscale x 8 x double> %1,
+ <vscale x 8 x i1> %m,
+ iXLen %vl,
+ iXLen 0)
+ ret <vscale x 8 x double> %f
+}
generated by cgit v1.1 at 2025-10-25 19:00:53 +0000