diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
3 files changed, 767 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/min-max.ll b/llvm/test/CodeGen/RISCV/min-max.ll index acde8ad..e7f6899 100644 --- a/llvm/test/CodeGen/RISCV/min-max.ll +++ b/llvm/test/CodeGen/RISCV/min-max.ll @@ -5,6 +5,12 @@ ; RUN: FileCheck %s --check-prefixes=ZBB,RV32ZBB ; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | \ ; RUN: FileCheck %s --check-prefixes=ZBB,RV64ZBB +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s | \ +; RUN: FileCheck %s --check-prefixes=XQCI +; RUN: llc < %s -mtriple=riscv32 -mattr=+short-forward-branch-opt | \ +; RUN: FileCheck %s --check-prefixes=RV32I-SFB +; RUN: llc < %s -mtriple=riscv64 -mattr=+short-forward-branch-opt | \ +; RUN: FileCheck %s --check-prefixes=RV64I-SFB ; Basic tests. @@ -23,6 +29,27 @@ define signext i8 @smax_i8(i8 signext %a, i8 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: max a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smax_i8: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvge a0, a1, a0, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_i8: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: blt a1, a0, .LBB0_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB0_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_i8: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a1, a0, .LBB0_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB0_2: +; RV64I-SFB-NEXT: ret %c = call i8 @llvm.smax.i8(i8 %a, i8 %b) ret i8 %c } @@ -42,6 +69,27 @@ define signext i16 @smax_i16(i16 signext %a, i16 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: max a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smax_i16: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvge a0, a1, a0, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_i16: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: blt a1, a0, .LBB1_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB1_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_i16: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a1, a0, .LBB1_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB1_2: +; RV64I-SFB-NEXT: ret %c = call i16 @llvm.smax.i16(i16 %a, i16 %b) ret i16 %c } @@ -61,6 +109,27 @@ define signext i32 @smax_i32(i32 signext %a, i32 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: max a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smax_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvge a0, a1, a0, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: blt a1, a0, .LBB2_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB2_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a1, a0, .LBB2_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB2_2: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smax.i32(i32 %a, i32 %b) ret i32 %c } @@ -112,6 +181,41 @@ define i64 @smax_i64(i64 %a, i64 %b) { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: max a0, a0, a1 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: smax_i64: +; XQCI: # %bb.0: +; XQCI-NEXT: sltu a4, a2, a0 +; XQCI-NEXT: slt a5, a3, a1 +; XQCI-NEXT: qc.mveq a5, a1, a3, a4 +; XQCI-NEXT: qc.mveqi a0, a5, 0, a2 +; XQCI-NEXT: qc.mveqi a1, a5, 0, a3 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_i64: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: sltu a4, a2, a0 +; RV32I-SFB-NEXT: slt a5, a3, a1 +; RV32I-SFB-NEXT: bne a1, a3, .LBB3_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a5, a4 +; RV32I-SFB-NEXT: .LBB3_2: +; RV32I-SFB-NEXT: bnez a5, .LBB3_4 +; RV32I-SFB-NEXT: # %bb.3: +; RV32I-SFB-NEXT: mv a0, a2 +; RV32I-SFB-NEXT: .LBB3_4: +; RV32I-SFB-NEXT: bnez a5, .LBB3_6 +; RV32I-SFB-NEXT: # %bb.5: +; RV32I-SFB-NEXT: mv a1, a3 +; RV32I-SFB-NEXT: .LBB3_6: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_i64: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a1, a0, .LBB3_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB3_2: +; RV64I-SFB-NEXT: ret %c = call i64 @llvm.smax.i64(i64 %a, i64 %b) ret i64 %c } @@ -131,6 +235,27 @@ define signext i8 @smin_i8(i8 signext %a, i8 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: min a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smin_i8: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvge a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_i8: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: blt a0, a1, .LBB4_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB4_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_i8: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a0, a1, .LBB4_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB4_2: +; RV64I-SFB-NEXT: ret %c = call i8 @llvm.smin.i8(i8 %a, i8 %b) ret i8 %c } @@ -150,6 +275,27 @@ define signext i16 @smin_i16(i16 signext %a, i16 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: min a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smin_i16: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvge a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_i16: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: blt a0, a1, .LBB5_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB5_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_i16: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a0, a1, .LBB5_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB5_2: +; RV64I-SFB-NEXT: ret %c = call i16 @llvm.smin.i16(i16 %a, i16 %b) ret i16 %c } @@ -169,6 +315,27 @@ define signext i32 @smin_i32(i32 signext %a, i32 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: min a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smin_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvge a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: blt a0, a1, .LBB6_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB6_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a0, a1, .LBB6_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB6_2: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smin.i32(i32 %a, i32 %b) ret i32 %c } @@ -220,6 +387,41 @@ define i64 @smin_i64(i64 %a, i64 %b) { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: min a0, a0, a1 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: smin_i64: +; XQCI: # %bb.0: +; XQCI-NEXT: sltu a4, a0, a2 +; XQCI-NEXT: slt a5, a1, a3 +; XQCI-NEXT: qc.mveq a5, a1, a3, a4 +; XQCI-NEXT: qc.mveqi a0, a5, 0, a2 +; XQCI-NEXT: qc.mveqi a1, a5, 0, a3 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_i64: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: sltu a4, a0, a2 +; RV32I-SFB-NEXT: slt a5, a1, a3 +; RV32I-SFB-NEXT: bne a1, a3, .LBB7_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a5, a4 +; RV32I-SFB-NEXT: .LBB7_2: +; RV32I-SFB-NEXT: bnez a5, .LBB7_4 +; RV32I-SFB-NEXT: # %bb.3: +; RV32I-SFB-NEXT: mv a0, a2 +; RV32I-SFB-NEXT: .LBB7_4: +; RV32I-SFB-NEXT: bnez a5, .LBB7_6 +; RV32I-SFB-NEXT: # %bb.5: +; RV32I-SFB-NEXT: mv a1, a3 +; RV32I-SFB-NEXT: .LBB7_6: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_i64: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: blt a0, a1, .LBB7_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB7_2: +; RV64I-SFB-NEXT: ret %c = call i64 @llvm.smin.i64(i64 %a, i64 %b) ret i64 %c } @@ -239,6 +441,27 @@ define i8 @umax_i8(i8 zeroext %a, i8 zeroext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: maxu a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: umax_i8: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvgeu a0, a1, a0, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_i8: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: bltu a1, a0, .LBB8_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB8_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_i8: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a1, a0, .LBB8_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB8_2: +; RV64I-SFB-NEXT: ret %c = call i8 @llvm.umax.i8(i8 %a, i8 %b) ret i8 %c } @@ -258,6 +481,27 @@ define i16 @umax_i16(i16 zeroext %a, i16 zeroext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: maxu a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: umax_i16: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvgeu a0, a1, a0, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_i16: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: bltu a1, a0, .LBB9_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB9_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_i16: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a1, a0, .LBB9_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB9_2: +; RV64I-SFB-NEXT: ret %c = call i16 @llvm.umax.i16(i16 %a, i16 %b) ret i16 %c } @@ -277,6 +521,27 @@ define signext i32 @umax_i32(i32 signext %a, i32 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: maxu a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: umax_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvgeu a0, a1, a0, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: bltu a1, a0, .LBB10_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB10_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a1, a0, .LBB10_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB10_2: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.umax.i32(i32 %a, i32 %b) ret i32 %c } @@ -328,6 +593,41 @@ define i64 @umax_i64(i64 %a, i64 %b) { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: maxu a0, a0, a1 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: umax_i64: +; XQCI: # %bb.0: +; XQCI-NEXT: sltu a4, a2, a0 +; XQCI-NEXT: sltu a5, a3, a1 +; XQCI-NEXT: qc.mveq a5, a1, a3, a4 +; XQCI-NEXT: qc.mveqi a0, a5, 0, a2 +; XQCI-NEXT: qc.mveqi a1, a5, 0, a3 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_i64: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: sltu a4, a2, a0 +; RV32I-SFB-NEXT: sltu a5, a3, a1 +; RV32I-SFB-NEXT: bne a1, a3, .LBB11_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a5, a4 +; RV32I-SFB-NEXT: .LBB11_2: +; RV32I-SFB-NEXT: bnez a5, .LBB11_4 +; RV32I-SFB-NEXT: # %bb.3: +; RV32I-SFB-NEXT: mv a0, a2 +; RV32I-SFB-NEXT: .LBB11_4: +; RV32I-SFB-NEXT: bnez a5, .LBB11_6 +; RV32I-SFB-NEXT: # %bb.5: +; RV32I-SFB-NEXT: mv a1, a3 +; RV32I-SFB-NEXT: .LBB11_6: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_i64: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a1, a0, .LBB11_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB11_2: +; RV64I-SFB-NEXT: ret %c = call i64 @llvm.umax.i64(i64 %a, i64 %b) ret i64 %c } @@ -347,6 +647,27 @@ define zeroext i8 @umin_i8(i8 zeroext %a, i8 zeroext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: minu a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: umin_i8: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvgeu a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umin_i8: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: bltu a0, a1, .LBB12_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB12_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umin_i8: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a0, a1, .LBB12_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB12_2: +; RV64I-SFB-NEXT: ret %c = call i8 @llvm.umin.i8(i8 %a, i8 %b) ret i8 %c } @@ -366,6 +687,27 @@ define zeroext i16 @umin_i16(i16 zeroext %a, i16 zeroext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: minu a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: umin_i16: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvgeu a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umin_i16: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: bltu a0, a1, .LBB13_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB13_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umin_i16: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a0, a1, .LBB13_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB13_2: +; RV64I-SFB-NEXT: ret %c = call i16 @llvm.umin.i16(i16 %a, i16 %b) ret i16 %c } @@ -385,6 +727,27 @@ define signext i32 @umin_i32(i32 signext %a, i32 signext %b) { ; ZBB: # %bb.0: ; ZBB-NEXT: minu a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: umin_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.mvgeu a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umin_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: bltu a0, a1, .LBB14_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB14_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umin_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a0, a1, .LBB14_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB14_2: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.umin.i32(i32 %a, i32 %b) ret i32 %c } @@ -436,6 +799,41 @@ define i64 @umin_i64(i64 %a, i64 %b) { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: minu a0, a0, a1 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: umin_i64: +; XQCI: # %bb.0: +; XQCI-NEXT: sltu a4, a0, a2 +; XQCI-NEXT: sltu a5, a1, a3 +; XQCI-NEXT: qc.mveq a5, a1, a3, a4 +; XQCI-NEXT: qc.mveqi a0, a5, 0, a2 +; XQCI-NEXT: qc.mveqi a1, a5, 0, a3 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umin_i64: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: sltu a4, a0, a2 +; RV32I-SFB-NEXT: sltu a5, a1, a3 +; RV32I-SFB-NEXT: bne a1, a3, .LBB15_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a5, a4 +; RV32I-SFB-NEXT: .LBB15_2: +; RV32I-SFB-NEXT: bnez a5, .LBB15_4 +; RV32I-SFB-NEXT: # %bb.3: +; RV32I-SFB-NEXT: mv a0, a2 +; RV32I-SFB-NEXT: .LBB15_4: +; RV32I-SFB-NEXT: bnez a5, .LBB15_6 +; RV32I-SFB-NEXT: # %bb.5: +; RV32I-SFB-NEXT: mv a1, a3 +; RV32I-SFB-NEXT: .LBB15_6: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umin_i64: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: bltu a0, a1, .LBB15_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB15_2: +; RV64I-SFB-NEXT: ret %c = call i64 @llvm.umin.i64(i64 %a, i64 %b) ret i64 %c } @@ -450,6 +848,18 @@ define signext i32 @smin_same_op_i32(i32 signext %a) { ; ZBB-LABEL: smin_same_op_i32: ; ZBB: # %bb.0: ; ZBB-NEXT: ret +; +; XQCI-LABEL: smin_same_op_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_same_op_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_same_op_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smin.i32(i32 %a, i32 %a) ret i32 %c } @@ -462,6 +872,18 @@ define signext i32 @smax_same_op_i32(i32 signext %a) { ; ZBB-LABEL: smax_same_op_i32: ; ZBB: # %bb.0: ; ZBB-NEXT: ret +; +; XQCI-LABEL: smax_same_op_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_same_op_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_same_op_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smax.i32(i32 %a, i32 %a) ret i32 %c } @@ -474,6 +896,18 @@ define signext i32 @umin_same_op_i32(i32 signext %a) { ; ZBB-LABEL: umin_same_op_i32: ; ZBB: # %bb.0: ; ZBB-NEXT: ret +; +; XQCI-LABEL: umin_same_op_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umin_same_op_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umin_same_op_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.umin.i32(i32 %a, i32 %a) ret i32 %c } @@ -486,6 +920,18 @@ define signext i32 @umax_same_op_i32(i32 signext %a) { ; ZBB-LABEL: umax_same_op_i32: ; ZBB: # %bb.0: ; ZBB-NEXT: ret +; +; XQCI-LABEL: umax_same_op_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_same_op_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_same_op_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.umax.i32(i32 %a, i32 %a) ret i32 %c } @@ -510,6 +956,19 @@ define signext i32 @smin_undef_i32() { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: li a0, 0 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: smin_undef_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_undef_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_undef_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a0, 0 +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smin.i32(i32 undef, i32 undef) ret i32 %c } @@ -532,6 +991,19 @@ define signext i32 @smax_undef_i32() { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: li a0, 0 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: smax_undef_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_undef_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_undef_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a0, 0 +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smax.i32(i32 undef, i32 undef) ret i32 %c } @@ -554,6 +1026,19 @@ define signext i32 @umin_undef_i32() { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: li a0, 0 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: umin_undef_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umin_undef_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umin_undef_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a0, 0 +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.umin.i32(i32 undef, i32 undef) ret i32 %c } @@ -576,6 +1061,19 @@ define signext i32 @umax_undef_i32() { ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: li a0, 0 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: umax_undef_i32: +; XQCI: # %bb.0: +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_undef_i32: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_undef_i32: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a0, 0 +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.umax.i32(i32 undef, i32 undef) ret i32 %c } @@ -595,6 +1093,29 @@ define signext i32 @smax_i32_pos_constant(i32 signext %a) { ; ZBB-NEXT: li a1, 10 ; ZBB-NEXT: max a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smax_i32_pos_constant: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.lilti a0, a0, 11, 10 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_i32_pos_constant: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: li a1, 10 +; RV32I-SFB-NEXT: blt a1, a0, .LBB24_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB24_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_i32_pos_constant: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a1, 10 +; RV64I-SFB-NEXT: blt a1, a0, .LBB24_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB24_2: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smax.i32(i32 %a, i32 10) ret i32 %c } @@ -616,6 +1137,33 @@ define signext i32 @smax_i32_pos_constant_trailing_zeros(i32 signext %a) { ; ZBB-NEXT: li a1, 16 ; ZBB-NEXT: max a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smax_i32_pos_constant_trailing_zeros: +; XQCI: # %bb.0: +; XQCI-NEXT: andi a1, a0, -8 +; XQCI-NEXT: li a0, 16 +; XQCI-NEXT: qc.mvlt a0, a0, a1, a1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smax_i32_pos_constant_trailing_zeros: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: andi a1, a0, -8 +; RV32I-SFB-NEXT: li a0, 16 +; RV32I-SFB-NEXT: bge a0, a1, .LBB25_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB25_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smax_i32_pos_constant_trailing_zeros: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: andi a1, a0, -8 +; RV64I-SFB-NEXT: li a0, 16 +; RV64I-SFB-NEXT: bge a0, a1, .LBB25_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB25_2: +; RV64I-SFB-NEXT: ret %b = and i32 %a, -8 %c = call i32 @llvm.smax.i32(i32 %b, i32 16) %d = and i32 %c, -4 @@ -635,6 +1183,29 @@ define signext i32 @smin_i32_negone(i32 signext %a) { ; ZBB-NEXT: li a1, -1 ; ZBB-NEXT: min a0, a0, a1 ; ZBB-NEXT: ret +; +; XQCI-LABEL: smin_i32_negone: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.ligei a0, a0, 0, -1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_i32_negone: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: li a1, -1 +; RV32I-SFB-NEXT: bltz a0, .LBB26_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a1 +; RV32I-SFB-NEXT: .LBB26_2: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_i32_negone: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a1, -1 +; RV64I-SFB-NEXT: bltz a0, .LBB26_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB26_2: +; RV64I-SFB-NEXT: ret %c = call i32 @llvm.smin.i32(i32 %a, i32 -1) ret i32 %c } @@ -672,6 +1243,34 @@ define i64 @smin_i64_negone(i64 %a) { ; RV64ZBB-NEXT: li a1, -1 ; RV64ZBB-NEXT: min a0, a0, a1 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: smin_i64_negone: +; XQCI: # %bb.0: +; XQCI-NEXT: qc.ligei a0, a1, 0, -1 +; XQCI-NEXT: qc.ligei a1, a1, 0, -1 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: smin_i64_negone: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: li a2, -1 +; RV32I-SFB-NEXT: bltz a1, .LBB27_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a0, a2 +; RV32I-SFB-NEXT: .LBB27_2: +; RV32I-SFB-NEXT: bltz a1, .LBB27_4 +; RV32I-SFB-NEXT: # %bb.3: +; RV32I-SFB-NEXT: mv a1, a2 +; RV32I-SFB-NEXT: .LBB27_4: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: smin_i64_negone: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a1, -1 +; RV64I-SFB-NEXT: bltz a0, .LBB27_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB27_2: +; RV64I-SFB-NEXT: ret %c = call i64 @llvm.smin.i64(i64 %a, i64 -1) ret i64 %c } @@ -720,6 +1319,41 @@ define i64 @umax_i64_one(i64 %a, i64 %b) { ; RV64ZBB-NEXT: li a1, 1 ; RV64ZBB-NEXT: maxu a0, a0, a1 ; RV64ZBB-NEXT: ret +; +; XQCI-LABEL: umax_i64_one: +; XQCI: # %bb.0: +; XQCI-NEXT: mv a2, a1 +; XQCI-NEXT: qc.selectinei a2, 0, a0, 1 +; XQCI-NEXT: qc.liltui a0, a0, 2, 1 +; XQCI-NEXT: qc.mvnei a0, a1, 0, a2 +; XQCI-NEXT: ret +; +; RV32I-SFB-LABEL: umax_i64_one: +; RV32I-SFB: # %bb.0: +; RV32I-SFB-NEXT: li a2, 1 +; RV32I-SFB-NEXT: li a3, 1 +; RV32I-SFB-NEXT: beqz a1, .LBB28_2 +; RV32I-SFB-NEXT: # %bb.1: +; RV32I-SFB-NEXT: mv a3, a0 +; RV32I-SFB-NEXT: .LBB28_2: +; RV32I-SFB-NEXT: bnez a0, .LBB28_4 +; RV32I-SFB-NEXT: # %bb.3: +; RV32I-SFB-NEXT: mv a0, a2 +; RV32I-SFB-NEXT: .LBB28_4: +; RV32I-SFB-NEXT: beqz a1, .LBB28_6 +; RV32I-SFB-NEXT: # %bb.5: +; RV32I-SFB-NEXT: mv a0, a3 +; RV32I-SFB-NEXT: .LBB28_6: +; RV32I-SFB-NEXT: ret +; +; RV64I-SFB-LABEL: umax_i64_one: +; RV64I-SFB: # %bb.0: +; RV64I-SFB-NEXT: li a1, 1 +; RV64I-SFB-NEXT: bnez a0, .LBB28_2 +; RV64I-SFB-NEXT: # %bb.1: +; RV64I-SFB-NEXT: mv a0, a1 +; RV64I-SFB-NEXT: .LBB28_2: +; RV64I-SFB-NEXT: ret %c = call i64 @llvm.umax.i64(i64 %a, i64 1) ret i64 %c } diff --git a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll new file mode 100644 index 0000000..c19e93d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll @@ -0,0 +1,76 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -O1 -mtriple=riscv64 -mattr=+v < %s | FileCheck %s + +define i32 @pr134424(i64 %input_value, i32 %base_value, i1 %cond_flag1, i1 %cond_flag2, i1 %cond_flag3) { +; CHECK-LABEL: pr134424: +; CHECK: # %bb.0: # %for.body.us.preheader.i +; CHECK-NEXT: andi a3, a3, 1 +; CHECK-NEXT: andi a5, a2, 1 +; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, ma +; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-NEXT: vmv.v.i v0, 14 +; CHECK-NEXT: mv a2, a1 +; CHECK-NEXT: bnez a5, .LBB0_2 +; CHECK-NEXT: # %bb.1: # %for.body.us.preheader.i +; CHECK-NEXT: li a2, 1 +; CHECK-NEXT: .LBB0_2: # %for.body.us.preheader.i +; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: andi a4, a4, 1 +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: bnez a3, .LBB0_4 +; CHECK-NEXT: # %bb.3: # %for.body.us.preheader.i +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: .LBB0_4: # %for.body.us.preheader.i +; CHECK-NEXT: vmsle.vi v0, v8, 0 +; CHECK-NEXT: sext.w a2, a2 +; CHECK-NEXT: bnez a4, .LBB0_6 +; CHECK-NEXT: # %bb.5: # %for.body.us.preheader.i +; CHECK-NEXT: li a1, 1 +; CHECK-NEXT: .LBB0_6: # %for.body.us.preheader.i +; CHECK-NEXT: sext.w a0, a0 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: vredmin.vs v8, v8, v8 +; CHECK-NEXT: vmv.x.s a3, v8 +; CHECK-NEXT: sext.w a1, a1 +; CHECK-NEXT: bge a3, a2, .LBB0_11 +; CHECK-NEXT: # %bb.7: # %for.body.us.preheader.i +; CHECK-NEXT: bge a0, a1, .LBB0_12 +; CHECK-NEXT: .LBB0_8: # %for.body.us.preheader.i +; CHECK-NEXT: blt a3, a0, .LBB0_10 +; CHECK-NEXT: .LBB0_9: # %for.body.us.preheader.i +; CHECK-NEXT: mv a3, a0 +; CHECK-NEXT: .LBB0_10: # %for.body.us.preheader.i +; CHECK-NEXT: sw a3, 0(zero) +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB0_11: # %for.body.us.preheader.i +; CHECK-NEXT: mv a3, a2 +; CHECK-NEXT: blt a0, a1, .LBB0_8 +; CHECK-NEXT: .LBB0_12: # %for.body.us.preheader.i +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: bge a3, a0, .LBB0_9 +; CHECK-NEXT: j .LBB0_10 +for.body.us.preheader.i: + %partial_vector = insertelement <4 x i64> zeroinitializer, i64 %input_value, i64 1 + %comparison_vector = shufflevector <4 x i64> %partial_vector, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 1, i32 1> + %comparison_result = icmp sle <4 x i64> %comparison_vector, zeroinitializer + %selected_value1 = select i1 %cond_flag1, i32 %base_value, i32 1 + %selected_value2 = select i1 %cond_flag2, i32 %base_value, i32 1 + %selected_value3 = select i1 %cond_flag3, i32 %base_value, i32 1 + %bool_to_int = zext <4 x i1> %comparison_result to <4 x i32> + %extended_vector = shufflevector <4 x i32> %bool_to_int, <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison> + %vector_min = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %extended_vector) + %min1 = call i32 @llvm.smin.i32(i32 %vector_min, i32 %selected_value1) + %min2 = call i32 @llvm.smin.i32(i32 %selected_value2, i32 %selected_value3) + %final_min = call i32 @llvm.smin.i32(i32 %min1, i32 %min2) + store i32 %final_min, ptr null, align 4 + ret i32 0 +} + diff --git a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir new file mode 100644 index 0000000..aeab8f6 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir @@ -0,0 +1,57 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer -o - %s | FileCheck %s + +--- +name: pr71023 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: pr71023 + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $v8, $v10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; CHECK-NEXT: undef [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_2:vrn8m1 = PseudoVMV_V_I_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_6:vrn8m1 = COPY undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2 + ; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: early-clobber [[PseudoVMV_V_I_M1_]].sub_vrm1_0:vrn8m1 = PseudoVRGATHER_VI_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_0, [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, 0, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSSEG6E8_V_M1_MASK [[PseudoVMV_V_I_M1_]].sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, undef [[DEF]], killed undef $v0, 0, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1) + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.3(0x40000000), %bb.1(0x40000000) + liveins: $x10, $v8, $v10 + %0:gpr = IMPLICIT_DEF + %1:vrnov0 = PseudoVMV_V_I_M1 undef %1, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + %2:vrnov0 = IMPLICIT_DEF + undef %3.sub_vrm1_0:vrn6m1nov0 = COPY undef %1 + %3.sub_vrm1_3:vrn6m1nov0 = COPY %2 + %3.sub_vrm1_4:vrn6m1nov0 = COPY undef %1 + BNE undef %0, $x0, %bb.3 + PseudoBR %bb.1 + bb.1: + successors: %bb.3(0x40000000), %bb.2(0x40000000) + BNE killed undef %0, $x0, %bb.3 + PseudoBR %bb.2 + bb.2: + successors: %bb.3(0x80000000) + bb.3: + %4:vr = IMPLICIT_DEF + early-clobber %4:vr = PseudoVRGATHER_VI_M1 undef %4, killed %1, 0, 0, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + undef %5.sub_vrm1_0:vrn6m1 = COPY killed %4 + %5.sub_vrm1_5:vrn6m1 = COPY killed %2 + PseudoVSSEG6E8_V_M1_MASK killed %5, undef %0, killed undef $v0, 0, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1) + PseudoRET +... |