diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
38 files changed, 1298 insertions, 751 deletions
diff --git a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll index 38b1074..ac04be4 100644 --- a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll +++ b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll @@ -6,9 +6,11 @@ ; CHECK-LABEL: Pass Arguments: ; CHECK-NEXT: Target Library Information +; CHECK-NEXT: Runtime Library Function Analysis ; CHECK-NEXT: Target Pass Configuration ; CHECK-NEXT: Machine Module Information ; CHECK-NEXT: Target Transform Information +; CHECK-NEXT: Library Function Lowering Analysis ; CHECK-NEXT: Create Garbage Collector Module Metadata ; CHECK-NEXT: Assumption Cache Tracker ; CHECK-NEXT: Profile summary info diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll index 7cbb1a1..fd8fd5f 100644 --- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll +++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll @@ -5,9 +5,11 @@ ; REQUIRES: asserts ; CHECK-LABEL: Pass Arguments: ; CHECK-NEXT: Target Library Information +; CHECK-NEXT: Runtime Library Function Analysis ; CHECK-NEXT: Target Pass Configuration ; CHECK-NEXT: Machine Module Information ; CHECK-NEXT: Target Transform Information +; CHECK-NEXT: Library Function Lowering Analysis ; CHECK-NEXT: Assumption Cache Tracker ; CHECK-NEXT: Type-Based Alias Analysis ; CHECK-NEXT: Scoped NoAlias Alias Analysis diff --git a/llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll b/llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll index e67d031..4ec54fa 100644 --- a/llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll +++ b/llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll @@ -8,15 +8,14 @@ ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \ ; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s -; The addition of vector `A` with vector of 1s currently uses `vspltisw` to generate vector of 1s followed by add operation. +; Optimized version which `xxleqv` and `vsubu` to generate vector of -1s to leverage the identity A - (-1) = A + 1. ; Function for the vector type v2i64 `a + {1, 1}` define <2 x i64> @test_v2i64(<2 x i64> %a) { ; CHECK-LABEL: test_v2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vspltisw v3, 1 -; CHECK-NEXT: vupklsw v3, v3 -; CHECK-NEXT: vaddudm v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vsubudm v2, v2, v3 ; CHECK-NEXT: blr entry: %add = add <2 x i64> %a, splat (i64 1) @@ -27,8 +26,8 @@ entry: define <4 x i32> @test_v4i32(<4 x i32> %a) { ; CHECK-LABEL: test_v4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vspltisw v3, 1 -; CHECK-NEXT: vadduwm v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vsubuwm v2, v2, v3 ; CHECK-NEXT: blr entry: %add = add <4 x i32> %a, splat (i32 1) @@ -39,8 +38,8 @@ entry: define <8 x i16> @test_v8i16(<8 x i16> %a) { ; CHECK-LABEL: test_v8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vspltish v3, 1 -; CHECK-NEXT: vadduhm v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vsubuhm v2, v2, v3 ; CHECK-NEXT: blr entry: %add = add <8 x i16> %a, splat (i16 1) @@ -51,8 +50,8 @@ entry: define <16 x i8> @test_16i8(<16 x i8> %a) { ; CHECK-LABEL: test_16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxspltib v3, 1 -; CHECK-NEXT: vaddubm v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vsububm v2, v2, v3 ; CHECK-NEXT: blr entry: %add = add <16 x i8> %a, splat (i8 1) diff --git a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll index 3eef8d5..682c2b7 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll @@ -8,22 +8,22 @@ define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: renamable $r11 = ADDI %fixed-stack.0, 0 ; CHECK-NEXT: STW killed renamable $r4, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0) - ; CHECK-NEXT: STW killed renamable $r6, 8, %fixed-stack.0 :: (store (s32)) - ; CHECK-NEXT: STW killed renamable $r7, 12, %fixed-stack.0 :: (store (s32)) - ; CHECK-NEXT: STW killed renamable $r8, 16, %fixed-stack.0 :: (store (s32)) - ; CHECK-NEXT: STW killed renamable $r9, 20, %fixed-stack.0 :: (store (s32)) - ; CHECK-NEXT: STW killed renamable $r10, 24, %fixed-stack.0 :: (store (s32)) + ; CHECK-NEXT: STW killed renamable $r5, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4) + ; CHECK-NEXT: STW killed renamable $r6, 8, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 8) + ; CHECK-NEXT: STW killed renamable $r7, 12, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 12) + ; CHECK-NEXT: STW killed renamable $r8, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16) + ; CHECK-NEXT: STW killed renamable $r9, 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20) + ; CHECK-NEXT: STW killed renamable $r10, 24, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 24) ; CHECK-NEXT: STW renamable $r11, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1) ; CHECK-NEXT: STW killed renamable $r11, 0, %stack.1.arg2 :: (store (s32) into %ir.arg2) ; CHECK-NEXT: renamable $r4 = ADDI %fixed-stack.0, 4 ; CHECK-NEXT: STW renamable $r4, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1) - ; CHECK-NEXT: renamable $r6 = LWZ 0, %fixed-stack.0 :: (load (s32) from %ir.argp.cur) + ; CHECK-NEXT: renamable $r5 = LWZ 0, %fixed-stack.0 :: (load (s32) from %ir.argp.cur) ; CHECK-NEXT: STW killed renamable $r4, 0, %stack.1.arg2 :: (store (s32) into %ir.arg2) ; CHECK-NEXT: renamable $r4 = LWZ 0, %fixed-stack.0 :: (load (s32) from %ir.argp.cur2) - ; CHECK-NEXT: renamable $r3 = nsw ADD4 killed renamable $r6, killed renamable $r3 + ; CHECK-NEXT: renamable $r3 = nsw ADD4 killed renamable $r5, killed renamable $r3 ; CHECK-NEXT: renamable $r4 = RLWINM killed renamable $r4, 1, 0, 30 ; CHECK-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4 - ; CHECK-NEXT: STW killed renamable $r5, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4) ; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 entry: %arg1 = alloca ptr, align 4 @@ -115,12 +115,12 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr { ; CHECK-NEXT: liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0 - ; CHECK-NEXT: STW killed renamable $r7, 8, %fixed-stack.0 :: (store (s32), align 8) + ; CHECK-NEXT: STW killed renamable $r7, 8, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 8, align 8) ; CHECK-NEXT: STW renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16) ; CHECK-NEXT: STW renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4) - ; CHECK-NEXT: STW killed renamable $r8, 12, %fixed-stack.0 :: (store (s32)) + ; CHECK-NEXT: STW killed renamable $r8, 12, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 12) ; CHECK-NEXT: STW killed renamable $r9, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16, align 16) - ; CHECK-NEXT: STW killed renamable $r10, 20, %fixed-stack.0 :: (store (s32)) + ; CHECK-NEXT: STW killed renamable $r10, 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20) ; CHECK-NEXT: STW renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1) ; CHECK-NEXT: STW killed renamable $r3, 0, %stack.1.arg2 :: (store (s32) into %ir.arg2) ; CHECK-NEXT: STW renamable $r5, 0, %stack.2 :: (store (s32) into %stack.2, align 8) diff --git a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll index 6ec56ff..9cf1e45 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll @@ -7,21 +7,21 @@ define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr { ; CHECK-NEXT: addi 11, 1, 28 ; CHECK-NEXT: stw 4, 28(1) ; CHECK-NEXT: addi 4, 1, 32 -; CHECK-NEXT: stw 6, 36(1) +; CHECK-NEXT: stw 5, 32(1) ; CHECK-NEXT: stw 11, -4(1) ; CHECK-NEXT: stw 11, -8(1) ; CHECK-NEXT: stw 4, -4(1) -; CHECK-NEXT: lwz 6, 28(1) +; CHECK-NEXT: lwz 5, 28(1) ; CHECK-NEXT: stw 4, -8(1) -; CHECK-NEXT: add 3, 6, 3 +; CHECK-NEXT: add 3, 5, 3 ; CHECK-NEXT: lwz 4, 28(1) ; CHECK-NEXT: slwi 4, 4, 1 -; CHECK-NEXT: stw 7, 40(1) +; CHECK-NEXT: stw 6, 36(1) ; CHECK-NEXT: add 3, 3, 4 +; CHECK-NEXT: stw 7, 40(1) ; CHECK-NEXT: stw 8, 44(1) ; CHECK-NEXT: stw 9, 48(1) ; CHECK-NEXT: stw 10, 52(1) -; CHECK-NEXT: stw 5, 32(1) ; CHECK-NEXT: blr entry: %arg1 = alloca ptr, align 4 diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll index e3eb864..600ad2e 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll @@ -17,11 +17,11 @@ define <4 x i32> @callee(i32 %count, ...) { ; CHECK: [[COPY6:%[0-9]+]]:gprc = COPY $r4 ; CHECK: STW [[COPY6]], 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0) ; CHECK: STW [[COPY5]], 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4) - ; CHECK: STW [[COPY4]], 8, %fixed-stack.0 :: (store (s32)) - ; CHECK: STW [[COPY3]], 12, %fixed-stack.0 :: (store (s32)) - ; CHECK: STW [[COPY2]], 16, %fixed-stack.0 :: (store (s32)) - ; CHECK: STW [[COPY1]], 20, %fixed-stack.0 :: (store (s32)) - ; CHECK: STW [[COPY]], 24, %fixed-stack.0 :: (store (s32)) + ; CHECK: STW [[COPY4]], 8, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 8) + ; CHECK: STW [[COPY3]], 12, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 12) + ; CHECK: STW [[COPY2]], 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16) + ; CHECK: STW [[COPY1]], 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20) + ; CHECK: STW [[COPY]], 24, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 24) ; CHECK: LIFETIME_START %stack.0.arg_list ; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 0 ; CHECK: STW killed [[ADDI]], 0, %stack.0.arg_list :: (store (s32) into %ir.arg_list) diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll index 4d7c6fb..dc62e18 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll @@ -7,23 +7,23 @@ define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr { ; CHECK-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: renamable $x11 = ADDI8 %fixed-stack.0, 0 - ; CHECK-NEXT: STD killed renamable $x6, 16, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x7, 24, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x8, 32, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x9, 40, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x10, 48, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD renamable $x11, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) - ; CHECK-NEXT: renamable $x6 = LD 0, %stack.1.arg2 :: (load (s64) from %ir.arg2) - ; CHECK-NEXT: renamable $x7 = disjoint ADDI8 %fixed-stack.0, 4 - ; CHECK-NEXT: renamable $r8 = LWZ 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK-NEXT: renamable $x9 = ADDI8 renamable $x6, 4 ; CHECK-NEXT: STD killed renamable $x4, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0) ; CHECK-NEXT: STD killed renamable $x5, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8) + ; CHECK-NEXT: STD killed renamable $x6, 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16) + ; CHECK-NEXT: STD killed renamable $x7, 24, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 24) + ; CHECK-NEXT: STD killed renamable $x8, 32, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 32) + ; CHECK-NEXT: STD killed renamable $x9, 40, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 40) + ; CHECK-NEXT: STD killed renamable $x10, 48, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 48) + ; CHECK-NEXT: STD renamable $x11, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) + ; CHECK-NEXT: renamable $x4 = LD 0, %stack.1.arg2 :: (load (s64) from %ir.arg2) + ; CHECK-NEXT: renamable $x5 = disjoint ADDI8 %fixed-stack.0, 4 ; CHECK-NEXT: STD killed renamable $x11, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1) - ; CHECK-NEXT: STD killed renamable $x7, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1) - ; CHECK-NEXT: STD killed renamable $x9, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) - ; CHECK-NEXT: renamable $r4 = LWZ 0, killed renamable $x6 :: (load (s32)) - ; CHECK-NEXT: renamable $r3 = nsw ADD4 killed renamable $r8, renamable $r3, implicit killed $x3 + ; CHECK-NEXT: STD killed renamable $x5, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1) + ; CHECK-NEXT: renamable $r5 = LWZ 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: renamable $x6 = ADDI8 renamable $x4, 4 + ; CHECK-NEXT: STD killed renamable $x6, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) + ; CHECK-NEXT: renamable $r4 = LWZ 0, killed renamable $x4 :: (load (s32)) + ; CHECK-NEXT: renamable $r3 = nsw ADD4 killed renamable $r5, renamable $r3, implicit killed $x3 ; CHECK-NEXT: renamable $r4 = RLWINM killed renamable $r4, 1, 0, 30 ; CHECK-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4, implicit-def $x3 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 @@ -101,22 +101,22 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr { ; CHECK-NEXT: liveins: $f1, $x4, $x5, $x6, $x7, $x8, $x9, $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: renamable $x3 = ADDI8 %fixed-stack.0, 0 - ; CHECK-NEXT: STD killed renamable $x6, 16, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x7, 24, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x8, 32, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x9, 40, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD killed renamable $x10, 48, %fixed-stack.0 :: (store (s64)) - ; CHECK-NEXT: STD renamable $x3, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) - ; CHECK-NEXT: renamable $x6 = LD 0, %stack.1.arg2 :: (load (s64) from %ir.arg2) - ; CHECK-NEXT: renamable $x7 = ADDI8 %fixed-stack.0, 8 ; CHECK-NEXT: STD killed renamable $x4, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0) + ; CHECK-NEXT: STD killed renamable $x5, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8) + ; CHECK-NEXT: STD killed renamable $x6, 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16) + ; CHECK-NEXT: STD killed renamable $x7, 24, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 24) + ; CHECK-NEXT: STD killed renamable $x8, 32, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 32) + ; CHECK-NEXT: STD killed renamable $x9, 40, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 40) + ; CHECK-NEXT: STD killed renamable $x10, 48, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 48) + ; CHECK-NEXT: STD renamable $x3, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) + ; CHECK-NEXT: renamable $x4 = LD 0, %stack.1.arg2 :: (load (s64) from %ir.arg2) + ; CHECK-NEXT: renamable $x5 = ADDI8 %fixed-stack.0, 8 ; CHECK-NEXT: STD killed renamable $x3, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1) - ; CHECK-NEXT: STD killed renamable $x7, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1) + ; CHECK-NEXT: STD killed renamable $x5, 0, %stack.0.arg1 :: (store (s64) into %ir.arg1) ; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64)) - ; CHECK-NEXT: renamable $x3 = ADDI8 renamable $x6, 8 - ; CHECK-NEXT: STD killed renamable $x5, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8) + ; CHECK-NEXT: renamable $x3 = ADDI8 renamable $x4, 8 ; CHECK-NEXT: STD killed renamable $x3, 0, %stack.1.arg2 :: (store (s64) into %ir.arg2) - ; CHECK-NEXT: renamable $f2 = LFD 0, killed renamable $x6 :: (load (s64)) + ; CHECK-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (load (s64)) ; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm ; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll index 87f46fe..e77f635 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll @@ -5,24 +5,24 @@ define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr { ; CHECK-LABEL: int_va_arg: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi 11, 1, 56 ; CHECK-NEXT: std 4, 56(1) -; CHECK-NEXT: addi 4, 1, 56 -; CHECK-NEXT: std 4, -16(1) +; CHECK-NEXT: addi 4, 1, 60 +; CHECK-NEXT: std 11, -16(1) +; CHECK-NEXT: std 11, -8(1) ; CHECK-NEXT: std 4, -8(1) ; CHECK-NEXT: ld 4, -16(1) -; CHECK-NEXT: std 5, 64(1) -; CHECK-NEXT: addi 5, 1, 60 -; CHECK-NEXT: std 5, -8(1) -; CHECK-NEXT: addi 5, 4, 4 ; CHECK-NEXT: std 6, 72(1) +; CHECK-NEXT: addi 6, 4, 4 +; CHECK-NEXT: std 5, 64(1) ; CHECK-NEXT: std 7, 80(1) ; CHECK-NEXT: std 8, 88(1) ; CHECK-NEXT: std 9, 96(1) ; CHECK-NEXT: std 10, 104(1) -; CHECK-NEXT: std 5, -16(1) -; CHECK-NEXT: lwz 11, 56(1) +; CHECK-NEXT: std 6, -16(1) +; CHECK-NEXT: lwz 5, 56(1) ; CHECK-NEXT: lwz 4, 0(4) -; CHECK-NEXT: add 3, 11, 3 +; CHECK-NEXT: add 3, 5, 3 ; CHECK-NEXT: slwi 4, 4, 1 ; CHECK-NEXT: add 3, 3, 4 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll index 3349709..434f35f 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll @@ -17,11 +17,11 @@ define <4 x i32> @callee(i32 signext %count, ...) { ; CHECK: [[COPY6:%[0-9]+]]:g8rc = COPY $x4 ; CHECK: STD [[COPY6]], 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0) ; CHECK: STD [[COPY5]], 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8) - ; CHECK: STD [[COPY4]], 16, %fixed-stack.0 :: (store (s64)) - ; CHECK: STD [[COPY3]], 24, %fixed-stack.0 :: (store (s64)) - ; CHECK: STD [[COPY2]], 32, %fixed-stack.0 :: (store (s64)) - ; CHECK: STD [[COPY1]], 40, %fixed-stack.0 :: (store (s64)) - ; CHECK: STD [[COPY]], 48, %fixed-stack.0 :: (store (s64)) + ; CHECK: STD [[COPY4]], 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16) + ; CHECK: STD [[COPY3]], 24, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 24) + ; CHECK: STD [[COPY2]], 32, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 32) + ; CHECK: STD [[COPY1]], 40, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 40) + ; CHECK: STD [[COPY]], 48, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 48) ; CHECK: LIFETIME_START %stack.0.arg_list ; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 %fixed-stack.0, 0 ; CHECK: STD killed [[ADDI8_]], 0, %stack.0.arg_list :: (store (s64) into %ir.arg_list) diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll index 0024acf..63b9f5c 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll @@ -15,7 +15,7 @@ define double @callee(i32 signext %count, <4 x i32> %vsi, double %next, ...) { ; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x8 ; CHECK: STD [[COPY2]], 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0) ; CHECK: STD [[COPY1]], 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8) - ; CHECK: STD [[COPY]], 16, %fixed-stack.0 :: (store (s64)) + ; CHECK: STD [[COPY]], 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16) ; CHECK: LIFETIME_START %stack.0.arg_list ; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 %fixed-stack.0, 0 ; CHECK: STD killed [[ADDI8_]], 0, %stack.0.arg_list :: (store (s64) into %ir.arg_list) diff --git a/llvm/test/CodeGen/PowerPC/amo-enable.ll b/llvm/test/CodeGen/PowerPC/amo-enable.ll new file mode 100644 index 0000000..33739cc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/amo-enable.ll @@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s \ +; RUN: | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \ +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-BE + +define void @test_us_lwat(ptr noundef %ptr, i32 noundef %value, ptr nocapture %resp) { +; CHECK-LABEL: test_us_lwat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mr r7, r4 +; CHECK-NEXT: lwat r6, r3, 0 +; CHECK-NEXT: stw r6, 0(r5) +; CHECK-NEXT: blr +; +; CHECK-BE-LABEL: test_us_lwat: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: mr r7, r4 +; CHECK-BE-NEXT: lwat r6, r3, 0 +; CHECK-BE-NEXT: stw r6, 0(r5) +; CHECK-BE-NEXT: blr +entry: + %0 = tail call i32 @llvm.ppc.amo.lwat(ptr %ptr, i32 %value, i32 0) + store i32 %0, ptr %resp, align 4 + ret void +} + +define void @test_us_ldat(ptr noundef %ptr, i64 noundef %value, ptr nocapture %resp) { +; CHECK-LABEL: test_us_ldat: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mr r7, r4 +; CHECK-NEXT: ldat r6, r3, 3 +; CHECK-NEXT: std r6, 0(r5) +; CHECK-NEXT: blr +; +; CHECK-BE-LABEL: test_us_ldat: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: mr r7, r4 +; CHECK-BE-NEXT: ldat r6, r3, 3 +; CHECK-BE-NEXT: std r6, 0(r5) +; CHECK-BE-NEXT: blr +entry: + %0 = tail call i64 @llvm.ppc.amo.ldat(ptr %ptr, i64 %value, i32 3) + store i64 %0, ptr %resp, align 8 + ret void +} + +declare i64 @llvm.ppc.amo.ldat(ptr, i64, i32 immarg) +declare i32 @llvm.ppc.amo.lwat(ptr, i32, i32 immarg) + diff --git a/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll b/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll index 530169f..00a77f9 100644 --- a/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll +++ b/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll @@ -212,33 +212,37 @@ define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind { ; CHECK-NEXT: std r30, 48(r1) # 8-byte Folded Spill ; CHECK-NEXT: andi. r3, r3, 1 ; CHECK-NEXT: li r3, -1 -; CHECK-NEXT: li r4, 0 ; CHECK-NEXT: li r30, 0 ; CHECK-NEXT: crmove 4*cr2+lt, gt ; CHECK-NEXT: std r29, 40(r1) # 8-byte Folded Spill ; CHECK-NEXT: b .LBB3_2 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB3_1: # %if.end116 ; CHECK-NEXT: # ; CHECK-NEXT: bl callee ; CHECK-NEXT: nop ; CHECK-NEXT: mr r3, r29 -; CHECK-NEXT: li r4, 0 -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB3_2: # %while.body5.i -; CHECK-NEXT: # -; CHECK-NEXT: addi r4, r4, -1 -; CHECK-NEXT: cmpwi r4, 0 -; CHECK-NEXT: bgt cr0, .LBB3_2 -; CHECK-NEXT: # %bb.3: # %while.cond12.preheader.i -; CHECK-NEXT: # +; CHECK-NEXT: .LBB3_2: # %cond.end.i.i +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB3_3 Depth 2 ; CHECK-NEXT: lwz r29, 0(r3) +; CHECK-NEXT: li r5, 0 +; CHECK-NEXT: extsw r4, r29 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB3_3: # %while.body5.i +; CHECK-NEXT: # Parent Loop BB3_2 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: addi r5, r5, -1 +; CHECK-NEXT: cmpwi r5, 0 +; CHECK-NEXT: bgt cr0, .LBB3_3 +; CHECK-NEXT: # %bb.4: # %while.cond12.preheader.i +; CHECK-NEXT: # ; CHECK-NEXT: bc 12, 4*cr2+lt, .LBB3_1 -; CHECK-NEXT: # %bb.4: # %for.cond99.preheader +; CHECK-NEXT: # %bb.5: # %for.cond99.preheader ; CHECK-NEXT: # -; CHECK-NEXT: extsw r4, r29 ; CHECK-NEXT: ld r5, 0(r3) -; CHECK-NEXT: stw r3, 0(r3) ; CHECK-NEXT: sldi r4, r4, 2 +; CHECK-NEXT: stw r3, 0(r3) ; CHECK-NEXT: stwx r30, r5, r4 ; CHECK-NEXT: b .LBB3_1 ; @@ -252,33 +256,37 @@ define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind { ; CHECK-BE-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: andi. r3, r3, 1 ; CHECK-BE-NEXT: li r3, -1 -; CHECK-BE-NEXT: li r4, 0 ; CHECK-BE-NEXT: li r30, 0 ; CHECK-BE-NEXT: crmove 4*cr2+lt, gt ; CHECK-BE-NEXT: std r29, 56(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: b .LBB3_2 +; CHECK-BE-NEXT: .p2align 4 ; CHECK-BE-NEXT: .LBB3_1: # %if.end116 ; CHECK-BE-NEXT: # ; CHECK-BE-NEXT: bl callee ; CHECK-BE-NEXT: nop ; CHECK-BE-NEXT: mr r3, r29 -; CHECK-BE-NEXT: li r4, 0 -; CHECK-BE-NEXT: .p2align 4 -; CHECK-BE-NEXT: .LBB3_2: # %while.body5.i -; CHECK-BE-NEXT: # -; CHECK-BE-NEXT: addi r4, r4, -1 -; CHECK-BE-NEXT: cmpwi r4, 0 -; CHECK-BE-NEXT: bgt cr0, .LBB3_2 -; CHECK-BE-NEXT: # %bb.3: # %while.cond12.preheader.i -; CHECK-BE-NEXT: # +; CHECK-BE-NEXT: .LBB3_2: # %cond.end.i.i +; CHECK-BE-NEXT: # =>This Loop Header: Depth=1 +; CHECK-BE-NEXT: # Child Loop BB3_3 Depth 2 ; CHECK-BE-NEXT: lwz r29, 0(r3) +; CHECK-BE-NEXT: li r5, 0 +; CHECK-BE-NEXT: extsw r4, r29 +; CHECK-BE-NEXT: .p2align 5 +; CHECK-BE-NEXT: .LBB3_3: # %while.body5.i +; CHECK-BE-NEXT: # Parent Loop BB3_2 Depth=1 +; CHECK-BE-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-BE-NEXT: addi r5, r5, -1 +; CHECK-BE-NEXT: cmpwi r5, 0 +; CHECK-BE-NEXT: bgt cr0, .LBB3_3 +; CHECK-BE-NEXT: # %bb.4: # %while.cond12.preheader.i +; CHECK-BE-NEXT: # ; CHECK-BE-NEXT: bc 12, 4*cr2+lt, .LBB3_1 -; CHECK-BE-NEXT: # %bb.4: # %for.cond99.preheader +; CHECK-BE-NEXT: # %bb.5: # %for.cond99.preheader ; CHECK-BE-NEXT: # -; CHECK-BE-NEXT: extsw r4, r29 ; CHECK-BE-NEXT: ld r5, 0(r3) -; CHECK-BE-NEXT: stw r3, 0(r3) ; CHECK-BE-NEXT: sldi r4, r4, 2 +; CHECK-BE-NEXT: stw r3, 0(r3) ; CHECK-BE-NEXT: stwx r30, r5, r4 ; CHECK-BE-NEXT: b .LBB3_1 ; @@ -292,28 +300,32 @@ define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind { ; CHECK-P9-NEXT: std r0, 80(r1) ; CHECK-P9-NEXT: std r30, 48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: li r3, -1 -; CHECK-P9-NEXT: li r4, 0 ; CHECK-P9-NEXT: li r30, 0 ; CHECK-P9-NEXT: std r29, 40(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: crmove 4*cr2+lt, gt ; CHECK-P9-NEXT: b .LBB3_2 +; CHECK-P9-NEXT: .p2align 4 ; CHECK-P9-NEXT: .LBB3_1: # %if.end116 ; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: bl callee ; CHECK-P9-NEXT: nop ; CHECK-P9-NEXT: mr r3, r29 +; CHECK-P9-NEXT: .LBB3_2: # %cond.end.i.i +; CHECK-P9-NEXT: # =>This Loop Header: Depth=1 +; CHECK-P9-NEXT: # Child Loop BB3_3 Depth 2 +; CHECK-P9-NEXT: lwz r29, 0(r3) ; CHECK-P9-NEXT: li r4, 0 -; CHECK-P9-NEXT: .p2align 4 -; CHECK-P9-NEXT: .LBB3_2: # %while.body5.i -; CHECK-P9-NEXT: # +; CHECK-P9-NEXT: .p2align 5 +; CHECK-P9-NEXT: .LBB3_3: # %while.body5.i +; CHECK-P9-NEXT: # Parent Loop BB3_2 Depth=1 +; CHECK-P9-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-P9-NEXT: addi r4, r4, -1 ; CHECK-P9-NEXT: cmpwi r4, 0 -; CHECK-P9-NEXT: bgt cr0, .LBB3_2 -; CHECK-P9-NEXT: # %bb.3: # %while.cond12.preheader.i +; CHECK-P9-NEXT: bgt cr0, .LBB3_3 +; CHECK-P9-NEXT: # %bb.4: # %while.cond12.preheader.i ; CHECK-P9-NEXT: # -; CHECK-P9-NEXT: lwz r29, 0(r3) ; CHECK-P9-NEXT: bc 12, 4*cr2+lt, .LBB3_1 -; CHECK-P9-NEXT: # %bb.4: # %for.cond99.preheader +; CHECK-P9-NEXT: # %bb.5: # %for.cond99.preheader ; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: ld r4, 0(r3) ; CHECK-P9-NEXT: extswsli r5, r29, 2 @@ -331,28 +343,32 @@ define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind { ; CHECK-P9-BE-NEXT: std r0, 96(r1) ; CHECK-P9-BE-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P9-BE-NEXT: li r3, -1 -; CHECK-P9-BE-NEXT: li r4, 0 ; CHECK-P9-BE-NEXT: li r30, 0 ; CHECK-P9-BE-NEXT: std r29, 56(r1) # 8-byte Folded Spill ; CHECK-P9-BE-NEXT: crmove 4*cr2+lt, gt ; CHECK-P9-BE-NEXT: b .LBB3_2 +; CHECK-P9-BE-NEXT: .p2align 4 ; CHECK-P9-BE-NEXT: .LBB3_1: # %if.end116 ; CHECK-P9-BE-NEXT: # ; CHECK-P9-BE-NEXT: bl callee ; CHECK-P9-BE-NEXT: nop ; CHECK-P9-BE-NEXT: mr r3, r29 +; CHECK-P9-BE-NEXT: .LBB3_2: # %cond.end.i.i +; CHECK-P9-BE-NEXT: # =>This Loop Header: Depth=1 +; CHECK-P9-BE-NEXT: # Child Loop BB3_3 Depth 2 +; CHECK-P9-BE-NEXT: lwz r29, 0(r3) ; CHECK-P9-BE-NEXT: li r4, 0 -; CHECK-P9-BE-NEXT: .p2align 4 -; CHECK-P9-BE-NEXT: .LBB3_2: # %while.body5.i -; CHECK-P9-BE-NEXT: # +; CHECK-P9-BE-NEXT: .p2align 5 +; CHECK-P9-BE-NEXT: .LBB3_3: # %while.body5.i +; CHECK-P9-BE-NEXT: # Parent Loop BB3_2 Depth=1 +; CHECK-P9-BE-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-P9-BE-NEXT: addi r4, r4, -1 ; CHECK-P9-BE-NEXT: cmpwi r4, 0 -; CHECK-P9-BE-NEXT: bgt cr0, .LBB3_2 -; CHECK-P9-BE-NEXT: # %bb.3: # %while.cond12.preheader.i +; CHECK-P9-BE-NEXT: bgt cr0, .LBB3_3 +; CHECK-P9-BE-NEXT: # %bb.4: # %while.cond12.preheader.i ; CHECK-P9-BE-NEXT: # -; CHECK-P9-BE-NEXT: lwz r29, 0(r3) ; CHECK-P9-BE-NEXT: bc 12, 4*cr2+lt, .LBB3_1 -; CHECK-P9-BE-NEXT: # %bb.4: # %for.cond99.preheader +; CHECK-P9-BE-NEXT: # %bb.5: # %for.cond99.preheader ; CHECK-P9-BE-NEXT: # ; CHECK-P9-BE-NEXT: ld r4, 0(r3) ; CHECK-P9-BE-NEXT: extswsli r5, r29, 2 diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll index a99c25a..39cf136 100644 --- a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll +++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll @@ -301,22 +301,13 @@ define <4 x float> @v4f32_minimum(<4 x float> %a, <4 x float> %b) { ; VSX-NEXT: xvcmpeqsp 1, 35, 35 ; VSX-NEXT: xvcmpeqsp 2, 34, 34 ; VSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; VSX-NEXT: xxleqv 36, 36, 36 -; VSX-NEXT: xvminsp 0, 34, 35 -; VSX-NEXT: vslw 4, 4, 4 ; VSX-NEXT: addi 3, 3, .LCPI4_0@toc@l ; VSX-NEXT: xxlnor 1, 1, 1 ; VSX-NEXT: xxlnor 2, 2, 2 -; VSX-NEXT: vcmpequw 5, 2, 4 +; VSX-NEXT: xvminsp 0, 34, 35 ; VSX-NEXT: xxlor 1, 2, 1 ; VSX-NEXT: lxvd2x 2, 0, 3 -; VSX-NEXT: xxsel 0, 0, 2, 1 -; VSX-NEXT: xxlxor 2, 2, 2 -; VSX-NEXT: xvcmpeqsp 2, 0, 2 -; VSX-NEXT: xxsel 1, 0, 34, 37 -; VSX-NEXT: vcmpequw 2, 3, 4 -; VSX-NEXT: xxsel 1, 1, 35, 34 -; VSX-NEXT: xxsel 34, 0, 1, 2 +; VSX-NEXT: xxsel 34, 0, 2, 1 ; VSX-NEXT: blr ; ; AIX-LABEL: v4f32_minimum: @@ -324,21 +315,12 @@ define <4 x float> @v4f32_minimum(<4 x float> %a, <4 x float> %b) { ; AIX-NEXT: xvcmpeqsp 1, 35, 35 ; AIX-NEXT: xvcmpeqsp 2, 34, 34 ; AIX-NEXT: ld 3, L..C4(2) # %const.0 -; AIX-NEXT: xxleqv 36, 36, 36 ; AIX-NEXT: xvminsp 0, 34, 35 -; AIX-NEXT: vslw 4, 4, 4 ; AIX-NEXT: xxlnor 1, 1, 1 ; AIX-NEXT: xxlnor 2, 2, 2 -; AIX-NEXT: vcmpequw 5, 2, 4 ; AIX-NEXT: xxlor 1, 2, 1 ; AIX-NEXT: lxvw4x 2, 0, 3 -; AIX-NEXT: xxsel 0, 0, 2, 1 -; AIX-NEXT: xxlxor 2, 2, 2 -; AIX-NEXT: xvcmpeqsp 2, 0, 2 -; AIX-NEXT: xxsel 1, 0, 34, 37 -; AIX-NEXT: vcmpequw 2, 3, 4 -; AIX-NEXT: xxsel 1, 1, 35, 34 -; AIX-NEXT: xxsel 34, 0, 1, 2 +; AIX-NEXT: xxsel 34, 0, 2, 1 ; AIX-NEXT: blr entry: %m = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b) @@ -377,16 +359,9 @@ define <4 x float> @v4f32_maximum(<4 x float> %a, <4 x float> %b) { ; VSX-NEXT: xxlnor 1, 1, 1 ; VSX-NEXT: xxlnor 2, 2, 2 ; VSX-NEXT: xvmaxsp 0, 34, 35 -; VSX-NEXT: xxlxor 36, 36, 36 -; VSX-NEXT: vcmpequw 5, 2, 4 ; VSX-NEXT: xxlor 1, 2, 1 ; VSX-NEXT: lxvd2x 2, 0, 3 -; VSX-NEXT: xxsel 0, 0, 2, 1 -; VSX-NEXT: xvcmpeqsp 2, 0, 36 -; VSX-NEXT: xxsel 1, 0, 34, 37 -; VSX-NEXT: vcmpequw 2, 3, 4 -; VSX-NEXT: xxsel 1, 1, 35, 34 -; VSX-NEXT: xxsel 34, 0, 1, 2 +; VSX-NEXT: xxsel 34, 0, 2, 1 ; VSX-NEXT: blr ; ; AIX-LABEL: v4f32_maximum: @@ -395,18 +370,11 @@ define <4 x float> @v4f32_maximum(<4 x float> %a, <4 x float> %b) { ; AIX-NEXT: xvcmpeqsp 2, 34, 34 ; AIX-NEXT: ld 3, L..C5(2) # %const.0 ; AIX-NEXT: xvmaxsp 0, 34, 35 -; AIX-NEXT: xxlxor 36, 36, 36 ; AIX-NEXT: xxlnor 1, 1, 1 ; AIX-NEXT: xxlnor 2, 2, 2 -; AIX-NEXT: vcmpequw 5, 2, 4 ; AIX-NEXT: xxlor 1, 2, 1 ; AIX-NEXT: lxvw4x 2, 0, 3 -; AIX-NEXT: xxsel 0, 0, 2, 1 -; AIX-NEXT: xvcmpeqsp 2, 0, 36 -; AIX-NEXT: xxsel 1, 0, 34, 37 -; AIX-NEXT: vcmpequw 2, 3, 4 -; AIX-NEXT: xxsel 1, 1, 35, 34 -; AIX-NEXT: xxsel 34, 0, 1, 2 +; AIX-NEXT: xxsel 34, 0, 2, 1 ; AIX-NEXT: blr entry: %m = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b) @@ -493,47 +461,28 @@ define <2 x double> @v2f64_minimum(<2 x double> %a, <2 x double> %b) { ; VSX-LABEL: v2f64_minimum: ; VSX: # %bb.0: # %entry ; VSX-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; VSX-NEXT: xvcmpeqdp 36, 35, 35 -; VSX-NEXT: xvcmpeqdp 37, 34, 34 -; VSX-NEXT: addi 3, 3, .LCPI6_0@toc@l -; VSX-NEXT: xxlnor 36, 36, 36 -; VSX-NEXT: xxlnor 37, 37, 37 ; VSX-NEXT: xvmindp 0, 34, 35 +; VSX-NEXT: xvcmpeqdp 35, 35, 35 +; VSX-NEXT: addi 3, 3, .LCPI6_0@toc@l +; VSX-NEXT: xvcmpeqdp 34, 34, 34 +; VSX-NEXT: xxlnor 35, 35, 35 +; VSX-NEXT: xxlnor 34, 34, 34 ; VSX-NEXT: lxvd2x 2, 0, 3 -; VSX-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; VSX-NEXT: xxlor 1, 37, 36 -; VSX-NEXT: addi 3, 3, .LCPI6_1@toc@l -; VSX-NEXT: lxvd2x 36, 0, 3 -; VSX-NEXT: vcmpequd 5, 2, 4 -; VSX-NEXT: xxsel 0, 0, 2, 1 -; VSX-NEXT: xxlxor 2, 2, 2 -; VSX-NEXT: xxsel 1, 0, 34, 37 -; VSX-NEXT: vcmpequd 2, 3, 4 -; VSX-NEXT: xxsel 1, 1, 35, 34 -; VSX-NEXT: xvcmpeqdp 34, 0, 2 -; VSX-NEXT: xxsel 34, 0, 1, 34 +; VSX-NEXT: xxlor 1, 34, 35 +; VSX-NEXT: xxsel 34, 0, 2, 1 ; VSX-NEXT: blr ; ; AIX-LABEL: v2f64_minimum: ; AIX: # %bb.0: # %entry ; AIX-NEXT: ld 3, L..C6(2) # %const.0 -; AIX-NEXT: xvcmpeqdp 36, 35, 35 -; AIX-NEXT: xvcmpeqdp 37, 34, 34 -; AIX-NEXT: lxvd2x 2, 0, 3 -; AIX-NEXT: ld 3, L..C7(2) # %const.1 -; AIX-NEXT: xxlnor 36, 36, 36 -; AIX-NEXT: xxlnor 37, 37, 37 ; AIX-NEXT: xvmindp 0, 34, 35 -; AIX-NEXT: xxlor 1, 37, 36 -; AIX-NEXT: lxvd2x 36, 0, 3 -; AIX-NEXT: vcmpequd 5, 2, 4 -; AIX-NEXT: xxsel 0, 0, 2, 1 -; AIX-NEXT: xxlxor 2, 2, 2 -; AIX-NEXT: xxsel 1, 0, 34, 37 -; AIX-NEXT: vcmpequd 2, 3, 4 -; AIX-NEXT: xxsel 1, 1, 35, 34 -; AIX-NEXT: xvcmpeqdp 34, 0, 2 -; AIX-NEXT: xxsel 34, 0, 1, 34 +; AIX-NEXT: xvcmpeqdp 35, 35, 35 +; AIX-NEXT: lxvd2x 2, 0, 3 +; AIX-NEXT: xvcmpeqdp 34, 34, 34 +; AIX-NEXT: xxlnor 35, 35, 35 +; AIX-NEXT: xxlnor 34, 34, 34 +; AIX-NEXT: xxlor 1, 34, 35 +; AIX-NEXT: xxsel 34, 0, 2, 1 ; AIX-NEXT: blr entry: %m = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b) @@ -618,42 +567,28 @@ define <2 x double> @v2f64_maximum(<2 x double> %a, <2 x double> %b) { ; VSX-LABEL: v2f64_maximum: ; VSX: # %bb.0: # %entry ; VSX-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; VSX-NEXT: xvcmpeqdp 36, 35, 35 -; VSX-NEXT: xvcmpeqdp 37, 34, 34 -; VSX-NEXT: addi 3, 3, .LCPI7_0@toc@l -; VSX-NEXT: xxlnor 36, 36, 36 -; VSX-NEXT: xxlnor 37, 37, 37 ; VSX-NEXT: xvmaxdp 0, 34, 35 +; VSX-NEXT: xvcmpeqdp 35, 35, 35 +; VSX-NEXT: addi 3, 3, .LCPI7_0@toc@l +; VSX-NEXT: xvcmpeqdp 34, 34, 34 +; VSX-NEXT: xxlnor 35, 35, 35 +; VSX-NEXT: xxlnor 34, 34, 34 ; VSX-NEXT: lxvd2x 2, 0, 3 -; VSX-NEXT: xxlor 1, 37, 36 -; VSX-NEXT: xxlxor 36, 36, 36 -; VSX-NEXT: vcmpequd 5, 2, 4 -; VSX-NEXT: xxsel 0, 0, 2, 1 -; VSX-NEXT: xxsel 1, 0, 34, 37 -; VSX-NEXT: vcmpequd 2, 3, 4 -; VSX-NEXT: xxsel 1, 1, 35, 34 -; VSX-NEXT: xvcmpeqdp 34, 0, 36 -; VSX-NEXT: xxsel 34, 0, 1, 34 +; VSX-NEXT: xxlor 1, 34, 35 +; VSX-NEXT: xxsel 34, 0, 2, 1 ; VSX-NEXT: blr ; ; AIX-LABEL: v2f64_maximum: ; AIX: # %bb.0: # %entry -; AIX-NEXT: ld 3, L..C8(2) # %const.0 -; AIX-NEXT: xvcmpeqdp 36, 35, 35 -; AIX-NEXT: xvcmpeqdp 37, 34, 34 -; AIX-NEXT: lxvd2x 2, 0, 3 -; AIX-NEXT: xxlnor 36, 36, 36 -; AIX-NEXT: xxlnor 37, 37, 37 +; AIX-NEXT: ld 3, L..C7(2) # %const.0 ; AIX-NEXT: xvmaxdp 0, 34, 35 -; AIX-NEXT: xxlor 1, 37, 36 -; AIX-NEXT: xxlxor 36, 36, 36 -; AIX-NEXT: vcmpequd 5, 2, 4 -; AIX-NEXT: xxsel 0, 0, 2, 1 -; AIX-NEXT: xxsel 1, 0, 34, 37 -; AIX-NEXT: vcmpequd 2, 3, 4 -; AIX-NEXT: xxsel 1, 1, 35, 34 -; AIX-NEXT: xvcmpeqdp 34, 0, 36 -; AIX-NEXT: xxsel 34, 0, 1, 34 +; AIX-NEXT: xvcmpeqdp 35, 35, 35 +; AIX-NEXT: lxvd2x 2, 0, 3 +; AIX-NEXT: xvcmpeqdp 34, 34, 34 +; AIX-NEXT: xxlnor 35, 35, 35 +; AIX-NEXT: xxlnor 34, 34, 34 +; AIX-NEXT: xxlor 1, 34, 35 +; AIX-NEXT: xxsel 34, 0, 2, 1 ; AIX-NEXT: blr entry: %m = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b) diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll index 12078ad..383dcdb 100644 --- a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll +++ b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -mtriple=ppc32-- | FileCheck %s --check-prefixes=CHECK,CHECK32,CHECK32_32 ; RUN: llc < %s -mtriple=ppc32-- -mcpu=ppc64 | FileCheck %s --check-prefixes=CHECK,CHECK32,CHECK32_64 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s --check-prefixes=CHECK,CHECK64 +; RUN: llc < %s -mcpu=future -mtriple=powerpc64le-- | FileCheck %s --check-prefix=FUTURE declare i8 @llvm.fshl.i8(i8, i8, i8) declare i16 @llvm.fshl.i16(i16, i16, i16) @@ -24,6 +25,13 @@ define i8 @rotl_i8_const_shift(i8 %x) { ; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28 ; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotl_i8_const_shift: +; FUTURE: # %bb.0: +; FUTURE-NEXT: rotlwi 4, 3, 27 +; FUTURE-NEXT: rlwimi 4, 3, 3, 0, 28 +; FUTURE-NEXT: mr 3, 4 +; FUTURE-NEXT: blr %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3) ret i8 %f } @@ -43,6 +51,11 @@ define i64 @rotl_i64_const_shift(i64 %x) { ; CHECK64: # %bb.0: ; CHECK64-NEXT: rotldi 3, 3, 3 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotl_i64_const_shift: +; FUTURE: # %bb.0: +; FUTURE-NEXT: rotldi 3, 3, 3 +; FUTURE-NEXT: blr %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3) ret i64 %f } @@ -60,6 +73,17 @@ define i16 @rotl_i16(i16 %x, i16 %z) { ; CHECK-NEXT: srw 4, 5, 4 ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotl_i16: +; FUTURE: # %bb.0: +; FUTURE-NEXT: clrlwi 6, 4, 28 +; FUTURE-NEXT: neg 4, 4 +; FUTURE-NEXT: clrlwi 5, 3, 16 +; FUTURE-NEXT: clrlwi 4, 4, 28 +; FUTURE-NEXT: slw 3, 3, 6 +; FUTURE-NEXT: srw 4, 5, 4 +; FUTURE-NEXT: or 3, 3, 4 +; FUTURE-NEXT: blr %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z) ret i16 %f } @@ -69,6 +93,11 @@ define i32 @rotl_i32(i32 %x, i32 %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: rotlw 3, 3, 4 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotl_i32: +; FUTURE: # %bb.0: +; FUTURE-NEXT: rotlw 3, 3, 4 +; FUTURE-NEXT: blr %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z) ret i32 %f } @@ -100,6 +129,11 @@ define i64 @rotl_i64(i64 %x, i64 %z) { ; CHECK64: # %bb.0: ; CHECK64-NEXT: rotld 3, 3, 4 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotl_i64: +; FUTURE: # %bb.0: +; FUTURE-NEXT: rotld 3, 3, 4 +; FUTURE-NEXT: blr %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z) ret i64 %f } @@ -124,6 +158,11 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) { ; CHECK64: # %bb.0: ; CHECK64-NEXT: vrlw 2, 2, 3 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotl_v4i32: +; FUTURE: # %bb.0: +; FUTURE-NEXT: xvrlw 34, 34, 35 +; FUTURE-NEXT: blr %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z) ret <4 x i32> %f } @@ -150,6 +189,12 @@ define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) { ; CHECK64-NEXT: vspltisw 3, 3 ; CHECK64-NEXT: vrlw 2, 2, 3 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotl_v4i32_const_shift: +; FUTURE: # %bb.0: +; FUTURE-NEXT: vspltisw 3, 3 +; FUTURE-NEXT: xvrlw 34, 34, 35 +; FUTURE-NEXT: blr %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) ret <4 x i32> %f } @@ -163,6 +208,13 @@ define i8 @rotr_i8_const_shift(i8 %x) { ; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26 ; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotr_i8_const_shift: +; FUTURE: # %bb.0: +; FUTURE-NEXT: rotlwi 4, 3, 29 +; FUTURE-NEXT: rlwimi 4, 3, 5, 0, 26 +; FUTURE-NEXT: mr 3, 4 +; FUTURE-NEXT: blr %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3) ret i8 %f } @@ -172,6 +224,11 @@ define i32 @rotr_i32_const_shift(i32 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: rotlwi 3, 3, 29 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotr_i32_const_shift: +; FUTURE: # %bb.0: +; FUTURE-NEXT: rotlwi 3, 3, 29 +; FUTURE-NEXT: blr %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3) ret i32 %f } @@ -189,6 +246,17 @@ define i16 @rotr_i16(i16 %x, i16 %z) { ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: or 3, 5, 3 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotr_i16: +; FUTURE: # %bb.0: +; FUTURE-NEXT: clrlwi 6, 4, 28 +; FUTURE-NEXT: neg 4, 4 +; FUTURE-NEXT: clrlwi 5, 3, 16 +; FUTURE-NEXT: clrlwi 4, 4, 28 +; FUTURE-NEXT: srw 5, 5, 6 +; FUTURE-NEXT: slw 3, 3, 4 +; FUTURE-NEXT: or 3, 5, 3 +; FUTURE-NEXT: blr %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z) ret i16 %f } @@ -199,6 +267,12 @@ define i32 @rotr_i32(i32 %x, i32 %z) { ; CHECK-NEXT: neg 4, 4 ; CHECK-NEXT: rotlw 3, 3, 4 ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotr_i32: +; FUTURE: # %bb.0: +; FUTURE-NEXT: neg 4, 4 +; FUTURE-NEXT: rotlw 3, 3, 4 +; FUTURE-NEXT: blr %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z) ret i32 %f } @@ -231,6 +305,12 @@ define i64 @rotr_i64(i64 %x, i64 %z) { ; CHECK64-NEXT: neg 4, 4 ; CHECK64-NEXT: rotld 3, 3, 4 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotr_i64: +; FUTURE: # %bb.0: +; FUTURE-NEXT: neg 4, 4 +; FUTURE-NEXT: rotld 3, 3, 4 +; FUTURE-NEXT: blr %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z) ret i64 %f } @@ -263,6 +343,12 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) { ; CHECK64-NEXT: vsubuwm 3, 4, 3 ; CHECK64-NEXT: vrlw 2, 2, 3 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotr_v4i32: +; FUTURE: # %bb.0: +; FUTURE-NEXT: vnegw 3, 3 +; FUTURE-NEXT: xvrlw 34, 34, 35 +; FUTURE-NEXT: blr %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z) ret <4 x i32> %f } @@ -293,6 +379,12 @@ define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) { ; CHECK64-NEXT: vsubuwm 3, 4, 3 ; CHECK64-NEXT: vrlw 2, 2, 3 ; CHECK64-NEXT: blr +; +; FUTURE-LABEL: rotr_v4i32_const_shift: +; FUTURE: # %bb.0: +; FUTURE-NEXT: xxspltiw 0, 29 +; FUTURE-NEXT: xvrlw 34, 34, 0 +; FUTURE-NEXT: blr %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) ret <4 x i32> %f } @@ -301,6 +393,10 @@ define i32 @rotl_i32_shift_by_bitwidth(i32 %x) { ; CHECK-LABEL: rotl_i32_shift_by_bitwidth: ; CHECK: # %bb.0: ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotl_i32_shift_by_bitwidth: +; FUTURE: # %bb.0: +; FUTURE-NEXT: blr %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32) ret i32 %f } @@ -309,6 +405,10 @@ define i32 @rotr_i32_shift_by_bitwidth(i32 %x) { ; CHECK-LABEL: rotr_i32_shift_by_bitwidth: ; CHECK: # %bb.0: ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotr_i32_shift_by_bitwidth: +; FUTURE: # %bb.0: +; FUTURE-NEXT: blr %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32) ret i32 %f } @@ -317,6 +417,10 @@ define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) { ; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth: ; CHECK: # %bb.0: ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotl_v4i32_shift_by_bitwidth: +; FUTURE: # %bb.0: +; FUTURE-NEXT: blr %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>) ret <4 x i32> %f } @@ -325,6 +429,10 @@ define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) { ; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth: ; CHECK: # %bb.0: ; CHECK-NEXT: blr +; +; FUTURE-LABEL: rotr_v4i32_shift_by_bitwidth: +; FUTURE: # %bb.0: +; FUTURE-NEXT: blr %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>) ret <4 x i32> %f } diff --git a/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll b/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll index 55482a0..826e306 100644 --- a/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll +++ b/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll @@ -70,27 +70,27 @@ define void @_Z3fooPfS_Pi(ptr noalias nocapture noundef %_a, ptr noalias nocaptu ; AIX32-NEXT: # %bb.2: # %for.body.preheader.new ; AIX32-NEXT: xxspltib 0, 6 ; AIX32-NEXT: addi 12, 4, -8 -; AIX32-NEXT: addi 9, 3, -8 +; AIX32-NEXT: addi 8, 3, -8 ; AIX32-NEXT: rlwinm 7, 5, 0, 1, 30 -; AIX32-NEXT: li 8, 0 -; AIX32-NEXT: li 10, 8 -; AIX32-NEXT: li 11, 12 +; AIX32-NEXT: li 9, 8 +; AIX32-NEXT: li 10, 12 +; AIX32-NEXT: li 11, 0 ; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB0_3: # %for.body ; AIX32-NEXT: # -; AIX32-NEXT: lxvwsx 1, 12, 10 +; AIX32-NEXT: lxvwsx 1, 12, 9 ; AIX32-NEXT: addic 6, 6, 2 -; AIX32-NEXT: addze 8, 8 +; AIX32-NEXT: addze 11, 11 ; AIX32-NEXT: xor 0, 6, 7 -; AIX32-NEXT: or. 0, 0, 8 +; AIX32-NEXT: or. 0, 0, 11 ; AIX32-NEXT: xxland 1, 1, 0 ; AIX32-NEXT: xscvspdpn 1, 1 -; AIX32-NEXT: stfsu 1, 8(9) -; AIX32-NEXT: lxvwsx 1, 12, 11 +; AIX32-NEXT: stfsu 1, 8(8) +; AIX32-NEXT: lxvwsx 1, 12, 10 ; AIX32-NEXT: addi 12, 12, 8 ; AIX32-NEXT: xxland 1, 1, 0 ; AIX32-NEXT: xscvspdpn 1, 1 -; AIX32-NEXT: stfs 1, 4(9) +; AIX32-NEXT: stfs 1, 4(8) ; AIX32-NEXT: bne 0, L..BB0_3 ; AIX32-NEXT: L..BB0_4: # %for.cond.cleanup.loopexit.unr-lcssa ; AIX32-NEXT: andi. 5, 5, 1 diff --git a/llvm/test/CodeGen/PowerPC/llvm.sincos.ll b/llvm/test/CodeGen/PowerPC/llvm.sincos.ll index aaf81ff..5b4e91c 100644 --- a/llvm/test/CodeGen/PowerPC/llvm.sincos.ll +++ b/llvm/test/CodeGen/PowerPC/llvm.sincos.ll @@ -26,30 +26,6 @@ define { ppc_fp128, ppc_fp128 } @test_sincos_ppcf128(ppc_fp128 %a) { ret { ppc_fp128, ppc_fp128 } %result } -define { ppc_fp128, ppc_fp128 } @test_sincospi_ppcf128(ppc_fp128 %a) { -; CHECK-LABEL: test_sincospi_ppcf128: -; CHECK: # %bb.0: -; CHECK-NEXT: mflr r0 -; CHECK-NEXT: stdu r1, -64(r1) -; CHECK-NEXT: std r0, 80(r1) -; CHECK-NEXT: .cfi_def_cfa_offset 64 -; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: addi r5, r1, 48 -; CHECK-NEXT: addi r6, r1, 32 -; CHECK-NEXT: bl sincospil -; CHECK-NEXT: nop -; CHECK-NEXT: lfd f1, 48(r1) -; CHECK-NEXT: lfd f2, 56(r1) -; CHECK-NEXT: lfd f3, 32(r1) -; CHECK-NEXT: lfd f4, 40(r1) -; CHECK-NEXT: addi r1, r1, 64 -; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 -; CHECK-NEXT: blr - %result = call { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %a) - ret { ppc_fp128, ppc_fp128 } %result -} - ; FIXME: This could be made a tail call with the default expansion of llvm.sincos. define void @test_sincos_ppcf128_void_tail_call(ppc_fp128 %a, ptr noalias %out_sin, ptr noalias %out_cos) { ; CHECK-LABEL: test_sincos_ppcf128_void_tail_call: @@ -73,29 +49,6 @@ define void @test_sincos_ppcf128_void_tail_call(ppc_fp128 %a, ptr noalias %out_s ret void } -; FIXME: This could be made a tail call with the default expansion of llvm.sincospi. -define void @test_sincospi_ppcf128_void_tail_call(ppc_fp128 %a, ptr noalias %out_sin, ptr noalias %out_cos) { -; CHECK-LABEL: test_sincospi_ppcf128_void_tail_call: -; CHECK: # %bb.0: -; CHECK-NEXT: mflr r0 -; CHECK-NEXT: stdu r1, -32(r1) -; CHECK-NEXT: std r0, 48(r1) -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: bl sincospil -; CHECK-NEXT: nop -; CHECK-NEXT: addi r1, r1, 32 -; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 -; CHECK-NEXT: blr - %result = tail call { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %a) - %result.0 = extractvalue { ppc_fp128, ppc_fp128 } %result, 0 - %result.1 = extractvalue { ppc_fp128, ppc_fp128 } %result, 1 - store ppc_fp128 %result.0, ptr %out_sin, align 16 - store ppc_fp128 %result.1, ptr %out_cos, align 16 - ret void -} - ; NOTE: This would need a struct-return library call for llvm.sincos to become a tail call. define { ppc_fp128, ppc_fp128 } @test_sincos_ppcf128_tail_call(ppc_fp128 %a) { ; CHECK-LABEL: test_sincos_ppcf128_tail_call: @@ -120,28 +73,3 @@ define { ppc_fp128, ppc_fp128 } @test_sincos_ppcf128_tail_call(ppc_fp128 %a) { %result = tail call { ppc_fp128, ppc_fp128 } @llvm.sincos.ppcf128(ppc_fp128 %a) ret { ppc_fp128, ppc_fp128 } %result } - -; NOTE: This would need a struct-return library call for llvm.sincospi to become a tail call. -define { ppc_fp128, ppc_fp128 } @test_sincospi_ppcf128_tail_call(ppc_fp128 %a) { -; CHECK-LABEL: test_sincospi_ppcf128_tail_call: -; CHECK: # %bb.0: -; CHECK-NEXT: mflr r0 -; CHECK-NEXT: stdu r1, -64(r1) -; CHECK-NEXT: std r0, 80(r1) -; CHECK-NEXT: .cfi_def_cfa_offset 64 -; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: addi r5, r1, 48 -; CHECK-NEXT: addi r6, r1, 32 -; CHECK-NEXT: bl sincospil -; CHECK-NEXT: nop -; CHECK-NEXT: lfd f1, 48(r1) -; CHECK-NEXT: lfd f2, 56(r1) -; CHECK-NEXT: lfd f3, 32(r1) -; CHECK-NEXT: lfd f4, 40(r1) -; CHECK-NEXT: addi r1, r1, 64 -; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 -; CHECK-NEXT: blr - %result = tail call { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %a) - ret { ppc_fp128, ppc_fp128 } %result -} diff --git a/llvm/test/CodeGen/PowerPC/llvm.sincospi.ll b/llvm/test/CodeGen/PowerPC/llvm.sincospi.ll new file mode 100644 index 0000000..75e7559 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/llvm.sincospi.ll @@ -0,0 +1,21 @@ +; RUN: not llc -mtriple=powerpc64le-gnu-linux -filetype=null %s 2>&1 | FileCheck %s + +; CHECK: error: no libcall available for fsincospi +define { half, half } @test_sincospi_f16(half %a) #0 { + %result = call { half, half } @llvm.sincospi.f16(half %a) + ret { half, half } %result +} + +; CHECK: error: no libcall available for fsincospi +define { float, float } @test_sincospi_f32(float %a) #0 { + %result = call { float, float } @llvm.sincospi.f32(float %a) + ret { float, float } %result +} + +; CHECK: error: no libcall available for fsincospi +define { double, double } @test_sincospi_f64(double %a) #0 { + %result = call { double, double } @llvm.sincospi.f64(double %a) + ret { double, double } %result +} + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/llvm.sincospi.ppcfp128.ll b/llvm/test/CodeGen/PowerPC/llvm.sincospi.ppcfp128.ll new file mode 100644 index 0000000..c332f44 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/llvm.sincospi.ppcfp128.ll @@ -0,0 +1,26 @@ +; XFAIL: * +; UNSUPPORTED: expensive_checks +; FIXME: asserts +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-gnu-linux -filetype=null -enable-legalize-types-checking=0 \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names %s + +define { ppc_fp128, ppc_fp128 } @test_sincospi_ppcf128(ppc_fp128 %a) { + %result = call { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %a) + ret { ppc_fp128, ppc_fp128 } %result +} + +; FIXME: This could be made a tail call with the default expansion of llvm.sincospi. +define void @test_sincospi_ppcf128_void_tail_call(ppc_fp128 %a, ptr noalias %out_sin, ptr noalias %out_cos) { + %result = tail call { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %a) + %result.0 = extractvalue { ppc_fp128, ppc_fp128 } %result, 0 + %result.1 = extractvalue { ppc_fp128, ppc_fp128 } %result, 1 + store ppc_fp128 %result.0, ptr %out_sin, align 16 + store ppc_fp128 %result.1, ptr %out_cos, align 16 + ret void +} + +; NOTE: This would need a struct-return library call for llvm.sincospi to become a tail call. +define { ppc_fp128, ppc_fp128 } @test_sincospi_ppcf128_tail_call(ppc_fp128 %a) { + %result = tail call { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %a) + ret { ppc_fp128, ppc_fp128 } %result +} diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll index 1da40d4..8d4dce1 100644 --- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll +++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll @@ -35,18 +35,12 @@ define signext i32 @zeroEqualityTest02(ptr %x, ptr %y) { define signext i32 @zeroEqualityTest01(ptr %x, ptr %y) { ; CHECK-LABEL: zeroEqualityTest01: ; CHECK: # %bb.0: -; CHECK-NEXT: ld 5, 0(3) -; CHECK-NEXT: ld 6, 0(4) -; CHECK-NEXT: cmpld 5, 6 -; CHECK-NEXT: bne 0, .LBB1_2 -; CHECK-NEXT: # %bb.1: # %loadbb1 -; CHECK-NEXT: ld 5, 8(3) -; CHECK-NEXT: ld 4, 8(4) -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: cmpld 5, 4 -; CHECK-NEXT: beqlr 0 -; CHECK-NEXT: .LBB1_2: # %res_block -; CHECK-NEXT: li 3, 1 +; CHECK-NEXT: lxvd2x 34, 0, 4 +; CHECK-NEXT: lxvd2x 35, 0, 3 +; CHECK-NEXT: vcmpequb. 2, 3, 2 +; CHECK-NEXT: mfocrf 3, 2 +; CHECK-NEXT: not 3, 3 +; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr %x, ptr %y, i64 16) %not.tobool = icmp ne i32 %call, 0 @@ -85,7 +79,7 @@ define signext i32 @zeroEqualityTest03(ptr %x, ptr %y) { ; Validate with > 0 define signext i32 @zeroEqualityTest04() { ; CHECK-LABEL: zeroEqualityTest04: -; CHECK: # %bb.0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr @zeroEqualityTest02.buffer1, ptr @zeroEqualityTest02.buffer2, i64 16) @@ -97,7 +91,7 @@ define signext i32 @zeroEqualityTest04() { ; Validate with < 0 define signext i32 @zeroEqualityTest05() { ; CHECK-LABEL: zeroEqualityTest05: -; CHECK: # %bb.0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr @zeroEqualityTest03.buffer1, ptr @zeroEqualityTest03.buffer2, i64 16) @@ -109,7 +103,7 @@ define signext i32 @zeroEqualityTest05() { ; Validate with memcmp()?: define signext i32 @equalityFoldTwoConstants() { ; CHECK-LABEL: equalityFoldTwoConstants: -; CHECK: # %bb.0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr @zeroEqualityTest04.buffer1, ptr @zeroEqualityTest04.buffer2, i64 16) @@ -121,24 +115,13 @@ define signext i32 @equalityFoldTwoConstants() { define signext i32 @equalityFoldOneConstant(ptr %X) { ; CHECK-LABEL: equalityFoldOneConstant: ; CHECK: # %bb.0: -; CHECK-NEXT: li 5, 1 -; CHECK-NEXT: ld 4, 0(3) -; CHECK-NEXT: rldic 5, 5, 32, 31 -; CHECK-NEXT: cmpld 4, 5 -; CHECK-NEXT: bne 0, .LBB6_2 -; CHECK-NEXT: # %bb.1: # %loadbb1 -; CHECK-NEXT: lis 5, -32768 -; CHECK-NEXT: ld 4, 8(3) -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: ori 5, 5, 1 -; CHECK-NEXT: rldic 5, 5, 1, 30 -; CHECK-NEXT: cmpld 4, 5 -; CHECK-NEXT: beq 0, .LBB6_3 -; CHECK-NEXT: .LBB6_2: # %res_block -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: .LBB6_3: # %endblock -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 +; CHECK-NEXT: lxvd2x 34, 0, 3 +; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l +; CHECK-NEXT: lxvd2x 35, 0, 3 +; CHECK-NEXT: vcmpequb. 2, 2, 3 +; CHECK-NEXT: mfocrf 3, 2 +; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr @zeroEqualityTest04.buffer1, ptr %X, i64 16) %not.tobool = icmp eq i32 %call, 0 diff --git a/llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll b/llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll index f5483ad..7dfaac1 100644 --- a/llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll +++ b/llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll @@ -14,110 +14,38 @@ define dso_local signext range(i32 0, 2) i32 @cmpeq16(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b) { ; CHECK-AIX32-P8-LABEL: cmpeq16: ; CHECK-AIX32-P8: # %bb.0: # %entry -; CHECK-AIX32-P8-NEXT: lwz r5, 4(r3) -; CHECK-AIX32-P8-NEXT: lwz r6, 0(r3) -; CHECK-AIX32-P8-NEXT: lwz r7, 4(r4) -; CHECK-AIX32-P8-NEXT: lwz r8, 0(r4) -; CHECK-AIX32-P8-NEXT: xor r6, r6, r8 -; CHECK-AIX32-P8-NEXT: xor r5, r5, r7 -; CHECK-AIX32-P8-NEXT: or. r5, r5, r6 -; CHECK-AIX32-P8-NEXT: bne cr0, L..BB0_2 -; CHECK-AIX32-P8-NEXT: # %bb.1: # %loadbb1 -; CHECK-AIX32-P8-NEXT: lwz r5, 12(r3) -; CHECK-AIX32-P8-NEXT: lwz r3, 8(r3) -; CHECK-AIX32-P8-NEXT: lwz r6, 12(r4) -; CHECK-AIX32-P8-NEXT: lwz r4, 8(r4) -; CHECK-AIX32-P8-NEXT: xor r3, r3, r4 -; CHECK-AIX32-P8-NEXT: xor r4, r5, r6 -; CHECK-AIX32-P8-NEXT: or. r3, r4, r3 -; CHECK-AIX32-P8-NEXT: li r3, 0 -; CHECK-AIX32-P8-NEXT: beq cr0, L..BB0_3 -; CHECK-AIX32-P8-NEXT: L..BB0_2: # %res_block -; CHECK-AIX32-P8-NEXT: li r3, 1 -; CHECK-AIX32-P8-NEXT: L..BB0_3: # %endblock -; CHECK-AIX32-P8-NEXT: cntlzw r3, r3 -; CHECK-AIX32-P8-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-AIX32-P8-NEXT: lxvw4x vs34, 0, r4 +; CHECK-AIX32-P8-NEXT: lxvw4x vs35, 0, r3 +; CHECK-AIX32-P8-NEXT: vcmpequb. v2, v3, v2 +; CHECK-AIX32-P8-NEXT: mfocrf r3, 2 +; CHECK-AIX32-P8-NEXT: rlwinm r3, r3, 25, 31, 31 ; CHECK-AIX32-P8-NEXT: blr ; ; CHECK-AIX32-P10-LABEL: cmpeq16: ; CHECK-AIX32-P10: # %bb.0: # %entry -; CHECK-AIX32-P10-NEXT: lwz r5, 4(r3) -; CHECK-AIX32-P10-NEXT: lwz r6, 0(r3) -; CHECK-AIX32-P10-NEXT: lwz r7, 4(r4) -; CHECK-AIX32-P10-NEXT: xor r5, r5, r7 -; CHECK-AIX32-P10-NEXT: lwz r8, 0(r4) -; CHECK-AIX32-P10-NEXT: xor r6, r6, r8 -; CHECK-AIX32-P10-NEXT: or. r5, r5, r6 -; CHECK-AIX32-P10-NEXT: bne cr0, L..BB0_2 -; CHECK-AIX32-P10-NEXT: # %bb.1: # %loadbb1 -; CHECK-AIX32-P10-NEXT: lwz r5, 12(r3) -; CHECK-AIX32-P10-NEXT: lwz r3, 8(r3) -; CHECK-AIX32-P10-NEXT: lwz r6, 12(r4) -; CHECK-AIX32-P10-NEXT: lwz r4, 8(r4) -; CHECK-AIX32-P10-NEXT: xor r3, r3, r4 -; CHECK-AIX32-P10-NEXT: xor r4, r5, r6 -; CHECK-AIX32-P10-NEXT: or. r3, r4, r3 -; CHECK-AIX32-P10-NEXT: li r3, 0 -; CHECK-AIX32-P10-NEXT: beq cr0, L..BB0_3 -; CHECK-AIX32-P10-NEXT: L..BB0_2: # %res_block -; CHECK-AIX32-P10-NEXT: li r3, 1 -; CHECK-AIX32-P10-NEXT: L..BB0_3: # %endblock -; CHECK-AIX32-P10-NEXT: cntlzw r3, r3 -; CHECK-AIX32-P10-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-AIX32-P10-NEXT: lxv vs34, 0(r4) +; CHECK-AIX32-P10-NEXT: lxv vs35, 0(r3) +; CHECK-AIX32-P10-NEXT: vcmpequb. v2, v3, v2 +; CHECK-AIX32-P10-NEXT: setbc r3, 4*cr6+lt ; CHECK-AIX32-P10-NEXT: blr ; ; CHECK-LINUX32-P8-LABEL: cmpeq16: ; CHECK-LINUX32-P8: # %bb.0: # %entry -; CHECK-LINUX32-P8-NEXT: lwz r5, 0(r3) -; CHECK-LINUX32-P8-NEXT: lwz r6, 4(r3) -; CHECK-LINUX32-P8-NEXT: lwz r7, 0(r4) -; CHECK-LINUX32-P8-NEXT: lwz r8, 4(r4) -; CHECK-LINUX32-P8-NEXT: xor r6, r6, r8 -; CHECK-LINUX32-P8-NEXT: xor r5, r5, r7 -; CHECK-LINUX32-P8-NEXT: or. r5, r5, r6 -; CHECK-LINUX32-P8-NEXT: bne cr0, .LBB0_2 -; CHECK-LINUX32-P8-NEXT: # %bb.1: # %loadbb1 -; CHECK-LINUX32-P8-NEXT: lwz r5, 8(r3) -; CHECK-LINUX32-P8-NEXT: lwz r3, 12(r3) -; CHECK-LINUX32-P8-NEXT: lwz r6, 8(r4) -; CHECK-LINUX32-P8-NEXT: lwz r4, 12(r4) -; CHECK-LINUX32-P8-NEXT: xor r3, r3, r4 -; CHECK-LINUX32-P8-NEXT: xor r4, r5, r6 -; CHECK-LINUX32-P8-NEXT: or. r3, r4, r3 -; CHECK-LINUX32-P8-NEXT: li r3, 0 -; CHECK-LINUX32-P8-NEXT: beq cr0, .LBB0_3 -; CHECK-LINUX32-P8-NEXT: .LBB0_2: # %res_block -; CHECK-LINUX32-P8-NEXT: li r3, 1 -; CHECK-LINUX32-P8-NEXT: .LBB0_3: # %endblock -; CHECK-LINUX32-P8-NEXT: cntlzw r3, r3 -; CHECK-LINUX32-P8-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-LINUX32-P8-NEXT: lxvd2x vs0, 0, r4 +; CHECK-LINUX32-P8-NEXT: xxswapd vs34, vs0 +; CHECK-LINUX32-P8-NEXT: lxvd2x vs0, 0, r3 +; CHECK-LINUX32-P8-NEXT: xxswapd vs35, vs0 +; CHECK-LINUX32-P8-NEXT: vcmpequb. v2, v3, v2 +; CHECK-LINUX32-P8-NEXT: mfocrf r3, 2 +; CHECK-LINUX32-P8-NEXT: rlwinm r3, r3, 25, 31, 31 ; CHECK-LINUX32-P8-NEXT: blr ; ; CHECK-LINUX32-P10-LABEL: cmpeq16: ; CHECK-LINUX32-P10: # %bb.0: # %entry -; CHECK-LINUX32-P10-NEXT: lwz r5, 0(r3) -; CHECK-LINUX32-P10-NEXT: lwz r6, 4(r3) -; CHECK-LINUX32-P10-NEXT: lwz r7, 0(r4) -; CHECK-LINUX32-P10-NEXT: xor r5, r5, r7 -; CHECK-LINUX32-P10-NEXT: lwz r8, 4(r4) -; CHECK-LINUX32-P10-NEXT: xor r6, r6, r8 -; CHECK-LINUX32-P10-NEXT: or. r5, r5, r6 -; CHECK-LINUX32-P10-NEXT: bne cr0, .LBB0_2 -; CHECK-LINUX32-P10-NEXT: # %bb.1: # %loadbb1 -; CHECK-LINUX32-P10-NEXT: lwz r5, 8(r3) -; CHECK-LINUX32-P10-NEXT: lwz r3, 12(r3) -; CHECK-LINUX32-P10-NEXT: lwz r6, 8(r4) -; CHECK-LINUX32-P10-NEXT: lwz r4, 12(r4) -; CHECK-LINUX32-P10-NEXT: xor r3, r3, r4 -; CHECK-LINUX32-P10-NEXT: xor r4, r5, r6 -; CHECK-LINUX32-P10-NEXT: or. r3, r4, r3 -; CHECK-LINUX32-P10-NEXT: li r3, 0 -; CHECK-LINUX32-P10-NEXT: beq cr0, .LBB0_3 -; CHECK-LINUX32-P10-NEXT: .LBB0_2: # %res_block -; CHECK-LINUX32-P10-NEXT: li r3, 1 -; CHECK-LINUX32-P10-NEXT: .LBB0_3: # %endblock -; CHECK-LINUX32-P10-NEXT: cntlzw r3, r3 -; CHECK-LINUX32-P10-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-LINUX32-P10-NEXT: lxv vs34, 0(r4) +; CHECK-LINUX32-P10-NEXT: lxv vs35, 0(r3) +; CHECK-LINUX32-P10-NEXT: vcmpequb. v2, v3, v2 +; CHECK-LINUX32-P10-NEXT: setbc r3, 4*cr6+lt ; CHECK-LINUX32-P10-NEXT: blr entry: %bcmp = tail call i32 @bcmp(ptr noundef nonnull dereferenceable(16) %a, ptr noundef nonnull dereferenceable(16) %b, i32 16) diff --git a/llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll b/llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll index 216b763..bd703b9 100644 --- a/llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll +++ b/llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll @@ -14,78 +14,36 @@ define dso_local signext range(i32 0, 2) i32 @cmpeq16(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b) { ; CHECK-AIX64-32-P8-LABEL: cmpeq16: ; CHECK-AIX64-32-P8: # %bb.0: # %entry -; CHECK-AIX64-32-P8-NEXT: ld r5, 0(r3) -; CHECK-AIX64-32-P8-NEXT: ld r6, 0(r4) -; CHECK-AIX64-32-P8-NEXT: cmpld r5, r6 -; CHECK-AIX64-32-P8-NEXT: bne cr0, L..BB0_2 -; CHECK-AIX64-32-P8-NEXT: # %bb.1: # %loadbb1 -; CHECK-AIX64-32-P8-NEXT: ld r5, 8(r3) -; CHECK-AIX64-32-P8-NEXT: ld r4, 8(r4) -; CHECK-AIX64-32-P8-NEXT: li r3, 0 -; CHECK-AIX64-32-P8-NEXT: cmpld r5, r4 -; CHECK-AIX64-32-P8-NEXT: beq cr0, L..BB0_3 -; CHECK-AIX64-32-P8-NEXT: L..BB0_2: # %res_block -; CHECK-AIX64-32-P8-NEXT: li r3, 1 -; CHECK-AIX64-32-P8-NEXT: L..BB0_3: # %endblock -; CHECK-AIX64-32-P8-NEXT: cntlzw r3, r3 -; CHECK-AIX64-32-P8-NEXT: srwi r3, r3, 5 +; CHECK-AIX64-32-P8-NEXT: lxvw4x vs34, 0, r4 +; CHECK-AIX64-32-P8-NEXT: lxvw4x vs35, 0, r3 +; CHECK-AIX64-32-P8-NEXT: vcmpequb. v2, v3, v2 +; CHECK-AIX64-32-P8-NEXT: mfocrf r3, 2 +; CHECK-AIX64-32-P8-NEXT: rlwinm r3, r3, 25, 31, 31 ; CHECK-AIX64-32-P8-NEXT: blr ; ; CHECK-AIX64-32-P10-LABEL: cmpeq16: ; CHECK-AIX64-32-P10: # %bb.0: # %entry -; CHECK-AIX64-32-P10-NEXT: ld r5, 0(r3) -; CHECK-AIX64-32-P10-NEXT: ld r6, 0(r4) -; CHECK-AIX64-32-P10-NEXT: cmpld r5, r6 -; CHECK-AIX64-32-P10-NEXT: bne cr0, L..BB0_2 -; CHECK-AIX64-32-P10-NEXT: # %bb.1: # %loadbb1 -; CHECK-AIX64-32-P10-NEXT: ld r5, 8(r3) -; CHECK-AIX64-32-P10-NEXT: ld r4, 8(r4) -; CHECK-AIX64-32-P10-NEXT: li r3, 0 -; CHECK-AIX64-32-P10-NEXT: cmpld r5, r4 -; CHECK-AIX64-32-P10-NEXT: beq cr0, L..BB0_3 -; CHECK-AIX64-32-P10-NEXT: L..BB0_2: # %res_block -; CHECK-AIX64-32-P10-NEXT: li r3, 1 -; CHECK-AIX64-32-P10-NEXT: L..BB0_3: # %endblock -; CHECK-AIX64-32-P10-NEXT: cntlzw r3, r3 -; CHECK-AIX64-32-P10-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-AIX64-32-P10-NEXT: lxv vs34, 0(r4) +; CHECK-AIX64-32-P10-NEXT: lxv vs35, 0(r3) +; CHECK-AIX64-32-P10-NEXT: vcmpequb. v2, v3, v2 +; CHECK-AIX64-32-P10-NEXT: setbc r3, 4*cr6+lt ; CHECK-AIX64-32-P10-NEXT: blr ; ; CHECK-LINUX64-P8-LABEL: cmpeq16: ; CHECK-LINUX64-P8: # %bb.0: # %entry -; CHECK-LINUX64-P8-NEXT: ld r5, 0(r3) -; CHECK-LINUX64-P8-NEXT: ld r6, 0(r4) -; CHECK-LINUX64-P8-NEXT: cmpld r5, r6 -; CHECK-LINUX64-P8-NEXT: bne cr0, .LBB0_2 -; CHECK-LINUX64-P8-NEXT: # %bb.1: # %loadbb1 -; CHECK-LINUX64-P8-NEXT: ld r5, 8(r3) -; CHECK-LINUX64-P8-NEXT: ld r4, 8(r4) -; CHECK-LINUX64-P8-NEXT: li r3, 0 -; CHECK-LINUX64-P8-NEXT: cmpld r5, r4 -; CHECK-LINUX64-P8-NEXT: beq cr0, .LBB0_3 -; CHECK-LINUX64-P8-NEXT: .LBB0_2: # %res_block -; CHECK-LINUX64-P8-NEXT: li r3, 1 -; CHECK-LINUX64-P8-NEXT: .LBB0_3: # %endblock -; CHECK-LINUX64-P8-NEXT: cntlzw r3, r3 -; CHECK-LINUX64-P8-NEXT: srwi r3, r3, 5 +; CHECK-LINUX64-P8-NEXT: lxvd2x vs34, 0, r4 +; CHECK-LINUX64-P8-NEXT: lxvd2x vs35, 0, r3 +; CHECK-LINUX64-P8-NEXT: vcmpequb. v2, v3, v2 +; CHECK-LINUX64-P8-NEXT: mfocrf r3, 2 +; CHECK-LINUX64-P8-NEXT: rlwinm r3, r3, 25, 31, 31 ; CHECK-LINUX64-P8-NEXT: blr ; ; CHECK-LINUX64-P10-LABEL: cmpeq16: ; CHECK-LINUX64-P10: # %bb.0: # %entry -; CHECK-LINUX64-P10-NEXT: ld r5, 0(r3) -; CHECK-LINUX64-P10-NEXT: ld r6, 0(r4) -; CHECK-LINUX64-P10-NEXT: cmpld r5, r6 -; CHECK-LINUX64-P10-NEXT: bne cr0, .LBB0_2 -; CHECK-LINUX64-P10-NEXT: # %bb.1: # %loadbb1 -; CHECK-LINUX64-P10-NEXT: ld r5, 8(r3) -; CHECK-LINUX64-P10-NEXT: ld r4, 8(r4) -; CHECK-LINUX64-P10-NEXT: li r3, 0 -; CHECK-LINUX64-P10-NEXT: cmpld r5, r4 -; CHECK-LINUX64-P10-NEXT: beq cr0, .LBB0_3 -; CHECK-LINUX64-P10-NEXT: .LBB0_2: # %res_block -; CHECK-LINUX64-P10-NEXT: li r3, 1 -; CHECK-LINUX64-P10-NEXT: .LBB0_3: # %endblock -; CHECK-LINUX64-P10-NEXT: cntlzw r3, r3 -; CHECK-LINUX64-P10-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-LINUX64-P10-NEXT: lxv vs34, 0(r4) +; CHECK-LINUX64-P10-NEXT: lxv vs35, 0(r3) +; CHECK-LINUX64-P10-NEXT: vcmpequb. v2, v3, v2 +; CHECK-LINUX64-P10-NEXT: setbc r3, 4*cr6+lt ; CHECK-LINUX64-P10-NEXT: blr entry: %bcmp = tail call i32 @bcmp(ptr noundef nonnull dereferenceable(16) %a, ptr noundef nonnull dereferenceable(16) %b, i64 16) diff --git a/llvm/test/CodeGen/PowerPC/memcmpIR.ll b/llvm/test/CodeGen/PowerPC/memcmpIR.ll index b57d2b5..974b8bd 100644 --- a/llvm/test/CodeGen/PowerPC/memcmpIR.ll +++ b/llvm/test/CodeGen/PowerPC/memcmpIR.ll @@ -4,48 +4,19 @@ define signext i32 @test1(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) { entry: ; CHECK-LABEL: @test1( - ; CHECK-LABEL: res_block:{{.*}} - ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64 - ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1 - ; CHECK-NEXT: br label %endblock - - ; CHECK-LABEL: loadbb:{{.*}} - ; CHECK: [[LOAD1:%[0-9]+]] = load i64, ptr - ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr - ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]]) - ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]]) - ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[BSWAP1]], [[BSWAP2]] - ; CHECK-NEXT: br i1 [[ICMP]], label %loadbb1, label %res_block - - ; CHECK-LABEL: loadbb1:{{.*}} - ; CHECK-NEXT: [[GEP1:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8 - ; CHECK-NEXT: [[GEP2:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8 - ; CHECK-NEXT: [[LOAD1:%[0-9]+]] = load i64, ptr [[GEP1]] - ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr [[GEP2]] - ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]]) - ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]]) - ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[BSWAP1]], [[BSWAP2]] - ; CHECK-NEXT: br i1 [[ICMP]], label %endblock, label %res_block - + ; CHECK: [[LOAD0:%[0-9]+]] = load i128, ptr %buffer1, align 1 + ; CHECK-NEXT: [[LOAD1:%[0-9]+]] = load i128, ptr %buffer2, align 1 + ; CHECK-NEXT: [[CALL1:%[0-9]+]] = call i128 @llvm.bswap.i128(i128 [[LOAD0]]) + ; CHECK-NEXT: [[CALL2:%[0-9]+]] = call i128 @llvm.bswap.i128(i128 [[LOAD1]]) + ; CHECK-NEXT: [[CALL3:%[0-9]+]] = call i32 @llvm.ucmp.i32.i128(i128 [[CALL1]], i128 [[CALL2]]) + ; CHECK-NEXT: ret i32 [[CALL3]] + + ; CHECK-BE-LABEL: @test1( - ; CHECK-BE-LABEL: res_block:{{.*}} - ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64 - ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1 - ; CHECK-BE-NEXT: br label %endblock - - ; CHECK-BE-LABEL: loadbb:{{.*}} - ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i64, ptr - ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr - ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[LOAD1]], [[LOAD2]] - ; CHECK-BE-NEXT: br i1 [[ICMP]], label %loadbb1, label %res_block - - ; CHECK-BE-LABEL: loadbb1:{{.*}} - ; CHECK-BE-NEXT: [[GEP1:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8 - ; CHECK-BE-NEXT: [[GEP2:%[0-9]+]] = getelementptr i8, ptr {{.*}}, i64 8 - ; CHECK-BE-NEXT: [[LOAD1:%[0-9]+]] = load i64, ptr [[GEP1]] - ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr [[GEP2]] - ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[LOAD1]], [[LOAD2]] - ; CHECK-BE-NEXT: br i1 [[ICMP]], label %endblock, label %res_block + ; CHECK-BE: [[LOAD0:%[0-9]+]] = load i128, ptr %buffer1, align 1 + ; CHECK-BE-NEXT: [[LOAD1:%[0-9]+]] = load i128, ptr %buffer2, align 1 + ; CHECK-BE-NEXT: [[CALL0:%[0-9]+]] = call i32 @llvm.ucmp.i32.i128(i128 [[LOAD0]], i128 [[LOAD1]]) + ; CHECK-BE-NEXT: ret i32 [[CALL0]] %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 16) ret i32 %call @@ -156,7 +127,7 @@ entry: define signext i32 @test4(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) { entry: - %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 65) + %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 129) ret i32 %call } diff --git a/llvm/test/CodeGen/PowerPC/milicode32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll index ddadd01..b69b997 100644 --- a/llvm/test/CodeGen/PowerPC/milicode32.ll +++ b/llvm/test/CodeGen/PowerPC/milicode32.ll @@ -68,7 +68,41 @@ entry: ret i32 %call } +define i32 @strlen_test_fp_strict(ptr noundef %str) nounwind { +; CHECK-AIX-32-P9-LABEL: strlen_test_fp_strict: +; CHECK-AIX-32-P9: # %bb.0: # %entry +; CHECK-AIX-32-P9-NEXT: mflr r0 +; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1) +; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1) +; CHECK-AIX-32-P9-NEXT: stw r3, 60(r1) +; CHECK-AIX-32-P9-NEXT: bl .___strlen[PR] +; CHECK-AIX-32-P9-NEXT: nop +; CHECK-AIX-32-P9-NEXT: addi r1, r1, 64 +; CHECK-AIX-32-P9-NEXT: lwz r0, 8(r1) +; CHECK-AIX-32-P9-NEXT: mtlr r0 +; CHECK-AIX-32-P9-NEXT: blr +; +; CHECK-LINUX32-P9-LABEL: strlen_test_fp_strict: +; CHECK-LINUX32-P9: # %bb.0: # %entry +; CHECK-LINUX32-P9-NEXT: mflr r0 +; CHECK-LINUX32-P9-NEXT: stwu r1, -16(r1) +; CHECK-LINUX32-P9-NEXT: stw r0, 20(r1) +; CHECK-LINUX32-P9-NEXT: stw r3, 12(r1) +; CHECK-LINUX32-P9-NEXT: bl strlen +; CHECK-LINUX32-P9-NEXT: lwz r0, 20(r1) +; CHECK-LINUX32-P9-NEXT: addi r1, r1, 16 +; CHECK-LINUX32-P9-NEXT: mtlr r0 +; CHECK-LINUX32-P9-NEXT: blr +entry: + %str.addr = alloca ptr, align 4 + store ptr %str, ptr %str.addr, align 4 + %0 = load ptr, ptr %str.addr, align 4 + %call = call i32 @strlen(ptr noundef %0) #0 + ret i32 %call +} + declare i32 @strlen(ptr noundef) nounwind +attributes #0 = { strictfp } define ptr @test_memmove(ptr noundef %destination, ptr noundef %source, i32 noundef %num) #0 { ; CHECK-AIX-32-P9-LABEL: test_memmove: diff --git a/llvm/test/CodeGen/PowerPC/milicode64.ll b/llvm/test/CodeGen/PowerPC/milicode64.ll index f7814a4..2dbf414 100644 --- a/llvm/test/CodeGen/PowerPC/milicode64.ll +++ b/llvm/test/CodeGen/PowerPC/milicode64.ll @@ -156,7 +156,7 @@ define ptr @test_memmove(ptr noundef %destination, ptr noundef %source, i64 noun ; CHECK-AIX-64-P9-NEXT: std r3, 128(r1) ; CHECK-AIX-64-P9-NEXT: std r4, 120(r1) ; CHECK-AIX-64-P9-NEXT: std r5, 112(r1) -; CHECK-AIX-64-P9-NEXT: bl .memmove[PR] +; CHECK-AIX-64-P9-NEXT: bl .___memmove64[PR] ; CHECK-AIX-64-P9-NEXT: nop ; CHECK-AIX-64-P9-NEXT: mr r3, r31 ; CHECK-AIX-64-P9-NEXT: ld r31, 136(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir index dc20a15..638b533 100644 --- a/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir +++ b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir @@ -1,5 +1,4 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# REQUIRES: asserts # RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ # RUN: -run-pass ppc-mi-peepholes %s -o - | FileCheck %s --check-prefix=ALL # RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ diff --git a/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll b/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll index 7d61177..2f7d227 100644 --- a/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll @@ -162,16 +162,16 @@ define <4 x float> @shuffle5(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x ; BE-ENABLE-NEXT: vextublx 3, 3, 2 ; BE-ENABLE-NEXT: xxmrghw 0, 1, 0 ; BE-ENABLE-NEXT: andi. 3, 3, 255 -; BE-ENABLE-NEXT: xxlor 1, 0, 0 +; BE-ENABLE-NEXT: xxlor 35, 0, 0 ; BE-ENABLE-NEXT: beq 0, .LBB4_2 ; BE-ENABLE-NEXT: # %bb.1: # %exit -; BE-ENABLE-NEXT: xvaddsp 34, 0, 1 +; BE-ENABLE-NEXT: xvaddsp 34, 35, 0 ; BE-ENABLE-NEXT: blr ; BE-ENABLE-NEXT: .LBB4_2: # %second -; BE-ENABLE-NEXT: xxmrglw 1, 36, 37 -; BE-ENABLE-NEXT: xxmrghw 2, 36, 37 -; BE-ENABLE-NEXT: xxmrghw 1, 2, 1 -; BE-ENABLE-NEXT: xvaddsp 34, 0, 1 +; BE-ENABLE-NEXT: xxmrglw 0, 36, 37 +; BE-ENABLE-NEXT: xxmrghw 1, 36, 37 +; BE-ENABLE-NEXT: xxmrghw 0, 1, 0 +; BE-ENABLE-NEXT: xvaddsp 34, 35, 0 ; BE-ENABLE-NEXT: blr entry: %shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll index 4bf572b..5042169 100644 --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -164,7 +164,7 @@ define double @foof_fmf(double %a, float %b) nounwind { ; CHECK-P9-NEXT: xsmuldp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b) - %y = fpext float %x to double + %y = fpext arcp float %x to double %r = fdiv contract reassoc arcp double %a, %y ret double %r } diff --git a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll index c0f3b60..5cd96ec 100644 --- a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll +++ b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll @@ -49,12 +49,11 @@ entry: define i1 @test_saddo_i32(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: test_saddo_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: add 5, 3, 4 -; CHECK-NEXT: cmpwi 1, 4, 0 -; CHECK-NEXT: cmpw 5, 3 -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: creqv 20, 4, 0 -; CHECK-NEXT: isel 3, 0, 3, 20 +; CHECK-NEXT: xor 5, 3, 4 +; CHECK-NEXT: add 4, 3, 4 +; CHECK-NEXT: xor 3, 4, 3 +; CHECK-NEXT: andc 3, 3, 5 +; CHECK-NEXT: srwi 3, 3, 31 ; CHECK-NEXT: blr entry: %res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) nounwind @@ -65,12 +64,11 @@ entry: define i1 @test_saddo_i64(i64 %a, i64 %b) nounwind { ; CHECK-LABEL: test_saddo_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: add 5, 3, 4 -; CHECK-NEXT: cmpdi 1, 4, 0 -; CHECK-NEXT: cmpd 5, 3 -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: creqv 20, 4, 0 -; CHECK-NEXT: isel 3, 0, 3, 20 +; CHECK-NEXT: xor 5, 3, 4 +; CHECK-NEXT: add 4, 3, 4 +; CHECK-NEXT: xor 3, 4, 3 +; CHECK-NEXT: andc 3, 3, 5 +; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: blr entry: %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind diff --git a/llvm/test/CodeGen/PowerPC/scalar-min-max.ll b/llvm/test/CodeGen/PowerPC/scalar-min-max.ll index 5f637e3..7feeba8 100644 --- a/llvm/test/CodeGen/PowerPC/scalar-min-max.ll +++ b/llvm/test/CodeGen/PowerPC/scalar-min-max.ll @@ -5,6 +5,7 @@ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: --check-prefix=P8 + define dso_local float @testfmax(float %a, float %b) local_unnamed_addr { ; P9-LABEL: testfmax: ; P9: # %bb.0: # %entry @@ -24,19 +25,19 @@ entry: ret float %cond } -define dso_local double @testdmax(double %a, double %b) local_unnamed_addr { -; P9-LABEL: testdmax: -; P9: # %bb.0: # %entry -; P9-NEXT: xsmaxcdp f1, f1, f2 -; P9-NEXT: blr +define double @testdmax(double %a, double %b) local_unnamed_addr { +; NO-FAST-P9-LABEL: testdmax: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxcdp f1, f1, f2 +; NO-FAST-P9-NEXT: blr ; -; P8-LABEL: testdmax: -; P8: # %bb.0: # %entry -; P8-NEXT: xscmpudp cr0, f1, f2 -; P8-NEXT: bgtlr cr0 -; P8-NEXT: # %bb.1: # %entry -; P8-NEXT: fmr f1, f2 -; P8-NEXT: blr +; NO-FAST-P8-LABEL: testdmax: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2 +; NO-FAST-P8-NEXT: bgtlr cr0 +; NO-FAST-P8-NEXT: # %bb.1: # %entry +; NO-FAST-P8-NEXT: fmr f1, f2 +; NO-FAST-P8-NEXT: blr entry: %cmp = fcmp ogt double %a, %b %cond = select i1 %cmp, double %a, double %b @@ -82,62 +83,242 @@ entry: } define dso_local float @testfmax_fast(float %a, float %b) local_unnamed_addr { -; P9-LABEL: testfmax_fast: -; P9: # %bb.0: # %entry -; P9-NEXT: xsmaxdp f1, f1, f2 -; P9-NEXT: blr +; NO-FAST-P9-LABEL: testfmax_fast: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P9-NEXT: blr ; -; P8-LABEL: testfmax_fast: -; P8: # %bb.0: # %entry -; P8-NEXT: xsmaxdp f1, f1, f2 -; P8-NEXT: blr +; NO-FAST-P8-LABEL: testfmax_fast: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P8-NEXT: blr entry: %cmp = fcmp nnan ninf ogt float %a, %b %cond = select nnan nsz i1 %cmp, float %a, float %b ret float %cond } define dso_local double @testdmax_fast(double %a, double %b) local_unnamed_addr { -; P9-LABEL: testdmax_fast: -; P9: # %bb.0: # %entry -; P9-NEXT: xsmaxdp f1, f1, f2 -; P9-NEXT: blr +; NO-FAST-P9-LABEL: testdmax_fast: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P9-NEXT: blr ; -; P8-LABEL: testdmax_fast: -; P8: # %bb.0: # %entry -; P8-NEXT: xsmaxdp f1, f1, f2 -; P8-NEXT: blr +; NO-FAST-P8-LABEL: testdmax_fast: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P8-NEXT: blr entry: %cmp = fcmp nnan ninf ogt double %a, %b %cond = select nnan nsz i1 %cmp, double %a, double %b ret double %cond } define dso_local float @testfmin_fast(float %a, float %b) local_unnamed_addr { -; P9-LABEL: testfmin_fast: -; P9: # %bb.0: # %entry -; P9-NEXT: xsmindp f1, f1, f2 -; P9-NEXT: blr +; NO-FAST-P9-LABEL: testfmin_fast: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P9-NEXT: blr ; -; P8-LABEL: testfmin_fast: -; P8: # %bb.0: # %entry -; P8-NEXT: xsmindp f1, f1, f2 -; P8-NEXT: blr +; NO-FAST-P8-LABEL: testfmin_fast: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P8-NEXT: blr entry: %cmp = fcmp nnan ninf olt float %a, %b %cond = select nnan nsz i1 %cmp, float %a, float %b ret float %cond } define dso_local double @testdmin_fast(double %a, double %b) local_unnamed_addr { -; P9-LABEL: testdmin_fast: -; P9: # %bb.0: # %entry -; P9-NEXT: xsmindp f1, f1, f2 -; P9-NEXT: blr +; NO-FAST-P9-LABEL: testdmin_fast: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P9-NEXT: blr ; -; P8-LABEL: testdmin_fast: -; P8: # %bb.0: # %entry -; P8-NEXT: xsmindp f1, f1, f2 -; P8-NEXT: blr +; NO-FAST-P8-LABEL: testdmin_fast: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P8-NEXT: blr entry: %cmp = fcmp nnan ninf olt double %a, %b %cond = select nnan nsz i1 %cmp, double %a, double %b ret double %cond } + +define float @testfminnum(float %a, float %b) { +; NO-FAST-P9-LABEL: testfminnum: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testfminnum: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call float @llvm.minnum.f32(float %a, float %b) + ret float %0 +} + +define float @testfmaxnum(float %a, float %b) { +; NO-FAST-P9-LABEL: testfmaxnum: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testfmaxnum: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call float @llvm.maxnum.f32(float %a, float %b) + ret float %0 +} + +define float @testfcanonicalize(float %a) { +; NO-FAST-P9-LABEL: testfcanonicalize: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxdp f1, f1, f1 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testfcanonicalize: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmaxdp f1, f1, f1 +; NO-FAST-P8-NEXT: blr +entry: + %canonicalize = tail call float @llvm.canonicalize.f32(float %a) + ret float %canonicalize +} + +define double @testdminnum(double %a, double %b) { +; NO-FAST-P9-LABEL: testdminnum: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testdminnum: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmindp f1, f1, f2 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call double @llvm.minnum.f64(double %a, double %b) + ret double %0 +} + +define double @testdmaxnum(double %a, double %b) { +; NO-FAST-P9-LABEL: testdmaxnum: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testdmaxnum: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmaxdp f1, f1, f2 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call double @llvm.maxnum.f64(double %a, double %b) + ret double %0 +} + +define double @testdcanonicalize(double %a) { +; NO-FAST-P9-LABEL: testdcanonicalize: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xsmaxdp f1, f1, f1 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testdcanonicalize: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xsmaxdp f1, f1, f1 +; NO-FAST-P8-NEXT: blr +entry: + %canonicalize = tail call double @llvm.canonicalize.f64(double %a) + ret double %canonicalize +} + +define <4 x float> @testfminnum_v4f32(<4 x float> %a, <4 x float> %b) { +; NO-FAST-P9-LABEL: testfminnum_v4f32: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xvminsp vs34, vs34, vs35 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testfminnum_v4f32: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xvminsp vs34, vs34, vs35 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %0 +} + +define <4 x float> @testfmaxnum_v4f32(<4 x float> %a, <4 x float> %b) { +; NO-FAST-P9-LABEL: testfmaxnum_v4f32: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xvmaxsp vs34, vs34, vs35 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testfmaxnum_v4f32: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xvmaxsp vs34, vs34, vs35 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %0 +} + +define <4 x float> @testfcanonicalize_v4f32(<4 x float> %a) { +; NO-FAST-P9-LABEL: testfcanonicalize_v4f32: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xvmaxsp vs34, vs34, vs34 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testfcanonicalize_v4f32: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xvmaxsp vs34, vs34, vs34 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call <4 x float> @llvm.canonicalize.v4f32(<4 x float> %a) + ret <4 x float> %0 +} + +define <2 x double> @testdminnum_v2f64(<2 x double> %a, <2 x double> %b) { +; NO-FAST-P9-LABEL: testdminnum_v2f64: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xvmindp vs34, vs34, vs35 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testdminnum_v2f64: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xvmindp vs34, vs34, vs35 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b) + ret <2 x double> %0 +} + +define <2 x double> @testdmaxnum_v2f64(<2 x double> %a, <2 x double> %b) { +; NO-FAST-P9-LABEL: testdmaxnum_v2f64: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xvmaxdp vs34, vs34, vs35 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testdmaxnum_v2f64: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xvmaxdp vs34, vs34, vs35 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b) + ret <2 x double> %0 +} + +define <2 x double> @testdcanonicalize_v2f64(<2 x double> %a) { +; NO-FAST-P9-LABEL: testdcanonicalize_v2f64: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xvmaxdp vs34, vs34, vs34 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testdcanonicalize_v2f64: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xvmaxdp vs34, vs34, vs34 +; NO-FAST-P8-NEXT: blr +entry: + %0 = tail call <2 x double> @llvm.canonicalize.v2f64(<2 x double> %a) + ret <2 x double> %0 +} diff --git a/llvm/test/CodeGen/PowerPC/sink-side-effect.ll b/llvm/test/CodeGen/PowerPC/sink-side-effect.ll index 040c20b..94d2a09 100644 --- a/llvm/test/CodeGen/PowerPC/sink-side-effect.ll +++ b/llvm/test/CodeGen/PowerPC/sink-side-effect.ll @@ -23,7 +23,7 @@ define double @zot(ptr %arg, ptr %arg1, ptr %arg2) { ; CHECK-NEXT: cmpw 4, 3 ; CHECK-NEXT: bge 0, .LBB0_3 ; CHECK-NEXT: # %bb.5: -; CHECK-NEXT: xsmuldp 1, 1, 0 +; CHECK-NEXT: xsmuldp 0, 0, 1 ; CHECK-NEXT: b .LBB0_3 bb: %tmp = load i32, ptr %arg, align 8 diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll index 4904d11..8b4b502 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll @@ -5,46 +5,45 @@ define void @phi2(i32, i32, ptr) local_unnamed_addr { ; CHECK-LABEL: phi2: ; CHECK: # %bb.0: -; CHECK-NEXT: divw 8, 3, 4 +; CHECK-NEXT: divw 7, 3, 4 ; CHECK-NEXT: li 5, 55 ; CHECK-NEXT: li 6, 48 ; CHECK-NEXT: mtctr 3 ; CHECK-NEXT: bdz .LBB0_4 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: divw 9, 8, 4 -; CHECK-NEXT: mullw 7, 8, 4 -; CHECK-NEXT: sub 3, 3, 7 +; CHECK-NEXT: divw 9, 7, 4 +; CHECK-NEXT: mullw 8, 7, 4 +; CHECK-NEXT: sub 3, 3, 8 ; CHECK-NEXT: cmplwi 3, 10 -; CHECK-NEXT: isellt 7, 6, 5 -; CHECK-NEXT: add 3, 7, 3 -; CHECK-NEXT: stbu 3, -1(7) -; CHECK-NEXT: mr 3, 8 +; CHECK-NEXT: isellt 8, 6, 5 +; CHECK-NEXT: add 3, 8, 3 +; CHECK-NEXT: stbu 3, -1(8) ; CHECK-NEXT: bdz .LBB0_3 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: mr 3, 9 -; CHECK-NEXT: mullw 9, 9, 4 -; CHECK-NEXT: divw 10, 3, 4 -; CHECK-NEXT: sub 8, 8, 9 -; CHECK-NEXT: cmplwi 8, 10 -; CHECK-NEXT: isellt 9, 6, 5 -; CHECK-NEXT: add 8, 9, 8 -; CHECK-NEXT: mr 9, 10 -; CHECK-NEXT: stbu 8, -1(7) -; CHECK-NEXT: mr 8, 3 +; CHECK-NEXT: mr 3, 7 +; CHECK-NEXT: mr 7, 9 +; CHECK-NEXT: mullw 10, 9, 4 +; CHECK-NEXT: divw 9, 9, 4 +; CHECK-NEXT: sub 3, 3, 10 +; CHECK-NEXT: cmplwi 3, 10 +; CHECK-NEXT: isellt 10, 6, 5 +; CHECK-NEXT: add 3, 10, 3 +; CHECK-NEXT: stbu 3, -1(8) ; CHECK-NEXT: bdnz .LBB0_2 ; CHECK-NEXT: .LBB0_3: -; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: mr 3, 7 +; CHECK-NEXT: mr 7, 9 ; CHECK-NEXT: b .LBB0_5 ; CHECK-NEXT: .LBB0_4: -; CHECK-NEXT: # implicit-def: $x7 +; CHECK-NEXT: # implicit-def: $x8 ; CHECK-NEXT: .LBB0_5: -; CHECK-NEXT: mullw 4, 8, 4 +; CHECK-NEXT: mullw 4, 7, 4 ; CHECK-NEXT: sub 3, 3, 4 ; CHECK-NEXT: cmplwi 3, 10 ; CHECK-NEXT: isellt 4, 6, 5 ; CHECK-NEXT: add 3, 4, 3 -; CHECK-NEXT: stbu 3, -1(7) +; CHECK-NEXT: stbu 3, -1(8) ; CHECK-NEXT: blr br label %4 diff --git a/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll b/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll new file mode 100644 index 0000000..d0e96e3 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix < %s | \ +; RUN: FileCheck %s + + +define <4 x i8> @backsmith_pure_1(<8 x i32> %0) { +; CHECK-LABEL: backsmith_pure_1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ld r3, L..C0(r2) # %const.0 +; CHECK-NEXT: xxsldwi vs34, vs35, vs35, 1 +; CHECK-NEXT: lxvw4x vs36, 0, r3 +; CHECK-NEXT: vspltb v3, v3, 3 +; CHECK-NEXT: vperm v2, v2, v2, v4 +; CHECK-NEXT: xxland vs34, vs35, vs34 +; CHECK-NEXT: blr +entry: + %shuffle = shufflevector <8 x i32> %0, <8 x i32> zeroinitializer, <4 x i32> <i32 5, i32 6, i32 7, i32 4> + %conv4 = trunc <4 x i32> %shuffle to <4 x i8> + %shift = shufflevector <4 x i8> %conv4, <4 x i8> zeroinitializer, <4 x i32> <i32 3, i32 poison, i32 poison, i32 poison> + %foldExtExtBinop = and <4 x i8> %shift, %conv4 + ret <4 x i8> %foldExtExtBinop +} diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll index 210aee1..d56b1be 100644 --- a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll +++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll @@ -16,9 +16,8 @@ define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind { ; VSX-LABEL: increment_by_one: ; VSX: # %bb.0: -; VSX-NEXT: vspltisw 3, 1 -; VSX-NEXT: vupklsw 3, 3 -; VSX-NEXT: vaddudm 2, 2, 3 +; VSX-NEXT: xxleqv 35, 35, 35 +; VSX-NEXT: vsubudm 2, 2, 3 ; VSX-NEXT: blr ; ; NOVSX-LABEL: increment_by_one: diff --git a/llvm/test/CodeGen/PowerPC/vec_rotate_lw.ll b/llvm/test/CodeGen/PowerPC/vec_rotate_lw.ll new file mode 100644 index 0000000..03b1456 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_rotate_lw.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ +; RUN: FileCheck %s + +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ +; RUN: FileCheck %s + +; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \ +; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ +; RUN: FileCheck %s + +define <4 x i32> @testVRLWMI(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: testVRLWMI: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvrlw v2, v2, v3 +; CHECK-NEXT: blr +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvrlw(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %0 +} diff --git a/llvm/test/CodeGen/PowerPC/vec_rounding.ll b/llvm/test/CodeGen/PowerPC/vec_rounding.ll index 438c8eb..987b2f1 100644 --- a/llvm/test/CodeGen/PowerPC/vec_rounding.ll +++ b/llvm/test/CodeGen/PowerPC/vec_rounding.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: < %s | FileCheck %s --check-prefix=NO-ALTIVEC ; Check vector round to single-precision toward -infinity (vrfim) ; instruction generation using Altivec. @@ -12,6 +14,33 @@ define <2 x double> @floor_v2f64(<2 x double> %p) ; CHECK-NEXT: frim 1, 1 ; CHECK-NEXT: frim 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: floor_v2f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -128(1) +; NO-ALTIVEC-NEXT: std 0, 144(1) +; NO-ALTIVEC-NEXT: .cfi_def_cfa_offset 128 +; NO-ALTIVEC-NEXT: .cfi_offset lr, 16 +; NO-ALTIVEC-NEXT: .cfi_offset f30, -16 +; NO-ALTIVEC-NEXT: .cfi_offset f31, -8 +; NO-ALTIVEC-NEXT: stfd 30, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 31, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 2 +; NO-ALTIVEC-NEXT: bl floor +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl floor +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 2, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: lfd 31, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 30, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 128 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p) ret <2 x double> %t @@ -26,6 +55,51 @@ define <4 x double> @floor_v4f64(<4 x double> %p) ; CHECK-NEXT: frim 3, 3 ; CHECK-NEXT: frim 4, 4 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: floor_v4f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -144(1) +; NO-ALTIVEC-NEXT: std 0, 160(1) +; NO-ALTIVEC-NEXT: .cfi_def_cfa_offset 144 +; NO-ALTIVEC-NEXT: .cfi_offset lr, 16 +; NO-ALTIVEC-NEXT: .cfi_offset f28, -32 +; NO-ALTIVEC-NEXT: .cfi_offset f29, -24 +; NO-ALTIVEC-NEXT: .cfi_offset f30, -16 +; NO-ALTIVEC-NEXT: .cfi_offset f31, -8 +; NO-ALTIVEC-NEXT: stfd 28, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 29, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 29, 2 +; NO-ALTIVEC-NEXT: stfd 30, 128(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 30, 3 +; NO-ALTIVEC-NEXT: stfd 31, 136(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 4 +; NO-ALTIVEC-NEXT: bl floor +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 28, 1 +; NO-ALTIVEC-NEXT: fmr 1, 29 +; NO-ALTIVEC-NEXT: bl floor +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 29, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: bl floor +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl floor +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 4, 1 +; NO-ALTIVEC-NEXT: fmr 1, 28 +; NO-ALTIVEC-NEXT: lfd 31, 136(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 28, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: fmr 2, 29 +; NO-ALTIVEC-NEXT: fmr 3, 30 +; NO-ALTIVEC-NEXT: lfd 30, 128(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 29, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 144 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p) ret <4 x double> %t @@ -38,6 +112,33 @@ define <2 x double> @ceil_v2f64(<2 x double> %p) ; CHECK-NEXT: frip 1, 1 ; CHECK-NEXT: frip 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: ceil_v2f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -128(1) +; NO-ALTIVEC-NEXT: std 0, 144(1) +; NO-ALTIVEC-NEXT: .cfi_def_cfa_offset 128 +; NO-ALTIVEC-NEXT: .cfi_offset lr, 16 +; NO-ALTIVEC-NEXT: .cfi_offset f30, -16 +; NO-ALTIVEC-NEXT: .cfi_offset f31, -8 +; NO-ALTIVEC-NEXT: stfd 30, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 31, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 2 +; NO-ALTIVEC-NEXT: bl ceil +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl ceil +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 2, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: lfd 31, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 30, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 128 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p) ret <2 x double> %t @@ -52,6 +153,51 @@ define <4 x double> @ceil_v4f64(<4 x double> %p) ; CHECK-NEXT: frip 3, 3 ; CHECK-NEXT: frip 4, 4 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: ceil_v4f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -144(1) +; NO-ALTIVEC-NEXT: std 0, 160(1) +; NO-ALTIVEC-NEXT: .cfi_def_cfa_offset 144 +; NO-ALTIVEC-NEXT: .cfi_offset lr, 16 +; NO-ALTIVEC-NEXT: .cfi_offset f28, -32 +; NO-ALTIVEC-NEXT: .cfi_offset f29, -24 +; NO-ALTIVEC-NEXT: .cfi_offset f30, -16 +; NO-ALTIVEC-NEXT: .cfi_offset f31, -8 +; NO-ALTIVEC-NEXT: stfd 28, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 29, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 29, 2 +; NO-ALTIVEC-NEXT: stfd 30, 128(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 30, 3 +; NO-ALTIVEC-NEXT: stfd 31, 136(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 4 +; NO-ALTIVEC-NEXT: bl ceil +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 28, 1 +; NO-ALTIVEC-NEXT: fmr 1, 29 +; NO-ALTIVEC-NEXT: bl ceil +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 29, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: bl ceil +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl ceil +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 4, 1 +; NO-ALTIVEC-NEXT: fmr 1, 28 +; NO-ALTIVEC-NEXT: lfd 31, 136(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 28, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: fmr 2, 29 +; NO-ALTIVEC-NEXT: fmr 3, 30 +; NO-ALTIVEC-NEXT: lfd 30, 128(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 29, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 144 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p) ret <4 x double> %t @@ -64,6 +210,33 @@ define <2 x double> @trunc_v2f64(<2 x double> %p) ; CHECK-NEXT: friz 1, 1 ; CHECK-NEXT: friz 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: trunc_v2f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -128(1) +; NO-ALTIVEC-NEXT: std 0, 144(1) +; NO-ALTIVEC-NEXT: .cfi_def_cfa_offset 128 +; NO-ALTIVEC-NEXT: .cfi_offset lr, 16 +; NO-ALTIVEC-NEXT: .cfi_offset f30, -16 +; NO-ALTIVEC-NEXT: .cfi_offset f31, -8 +; NO-ALTIVEC-NEXT: stfd 30, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 31, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 2 +; NO-ALTIVEC-NEXT: bl trunc +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl trunc +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 2, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: lfd 31, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 30, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 128 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p) ret <2 x double> %t @@ -78,6 +251,51 @@ define <4 x double> @trunc_v4f64(<4 x double> %p) ; CHECK-NEXT: friz 3, 3 ; CHECK-NEXT: friz 4, 4 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: trunc_v4f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -144(1) +; NO-ALTIVEC-NEXT: std 0, 160(1) +; NO-ALTIVEC-NEXT: .cfi_def_cfa_offset 144 +; NO-ALTIVEC-NEXT: .cfi_offset lr, 16 +; NO-ALTIVEC-NEXT: .cfi_offset f28, -32 +; NO-ALTIVEC-NEXT: .cfi_offset f29, -24 +; NO-ALTIVEC-NEXT: .cfi_offset f30, -16 +; NO-ALTIVEC-NEXT: .cfi_offset f31, -8 +; NO-ALTIVEC-NEXT: stfd 28, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 29, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 29, 2 +; NO-ALTIVEC-NEXT: stfd 30, 128(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 30, 3 +; NO-ALTIVEC-NEXT: stfd 31, 136(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 4 +; NO-ALTIVEC-NEXT: bl trunc +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 28, 1 +; NO-ALTIVEC-NEXT: fmr 1, 29 +; NO-ALTIVEC-NEXT: bl trunc +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 29, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: bl trunc +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl trunc +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 4, 1 +; NO-ALTIVEC-NEXT: fmr 1, 28 +; NO-ALTIVEC-NEXT: lfd 31, 136(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 28, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: fmr 2, 29 +; NO-ALTIVEC-NEXT: fmr 3, 30 +; NO-ALTIVEC-NEXT: lfd 30, 128(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 29, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 144 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p) ret <4 x double> %t @@ -107,6 +325,29 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p) nounwind ; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: nearbyint_v2f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -128(1) +; NO-ALTIVEC-NEXT: std 0, 144(1) +; NO-ALTIVEC-NEXT: stfd 30, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 31, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 2 +; NO-ALTIVEC-NEXT: bl nearbyint +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl nearbyint +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 2, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: lfd 31, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 30, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 128 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) ret <2 x double> %t @@ -152,6 +393,45 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p) nounwind ; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: nearbyint_v4f64: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: mflr 0 +; NO-ALTIVEC-NEXT: stdu 1, -144(1) +; NO-ALTIVEC-NEXT: std 0, 160(1) +; NO-ALTIVEC-NEXT: stfd 28, 112(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: stfd 29, 120(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 29, 2 +; NO-ALTIVEC-NEXT: stfd 30, 128(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 30, 3 +; NO-ALTIVEC-NEXT: stfd 31, 136(1) # 8-byte Folded Spill +; NO-ALTIVEC-NEXT: fmr 31, 4 +; NO-ALTIVEC-NEXT: bl nearbyint +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 28, 1 +; NO-ALTIVEC-NEXT: fmr 1, 29 +; NO-ALTIVEC-NEXT: bl nearbyint +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 29, 1 +; NO-ALTIVEC-NEXT: fmr 1, 30 +; NO-ALTIVEC-NEXT: bl nearbyint +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 30, 1 +; NO-ALTIVEC-NEXT: fmr 1, 31 +; NO-ALTIVEC-NEXT: bl nearbyint +; NO-ALTIVEC-NEXT: nop +; NO-ALTIVEC-NEXT: fmr 4, 1 +; NO-ALTIVEC-NEXT: fmr 1, 28 +; NO-ALTIVEC-NEXT: lfd 31, 136(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 28, 112(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: fmr 2, 29 +; NO-ALTIVEC-NEXT: fmr 3, 30 +; NO-ALTIVEC-NEXT: lfd 30, 128(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: lfd 29, 120(1) # 8-byte Folded Reload +; NO-ALTIVEC-NEXT: addi 1, 1, 144 +; NO-ALTIVEC-NEXT: ld 0, 16(1) +; NO-ALTIVEC-NEXT: mtlr 0 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p) ret <4 x double> %t @@ -164,6 +444,11 @@ define <4 x float> @floor_v4f32(<4 x float> %p) ; CHECK: # %bb.0: ; CHECK-NEXT: vrfim 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: floor_v4f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfim 2, 2 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p) ret <4 x float> %t @@ -176,6 +461,12 @@ define <8 x float> @floor_v8f32(<8 x float> %p) ; CHECK-NEXT: vrfim 2, 2 ; CHECK-NEXT: vrfim 3, 3 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: floor_v8f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfim 2, 2 +; NO-ALTIVEC-NEXT: vrfim 3, 3 +; NO-ALTIVEC-NEXT: blr { %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p) ret <8 x float> %t @@ -187,6 +478,11 @@ define <4 x float> @ceil_v4f32(<4 x float> %p) ; CHECK: # %bb.0: ; CHECK-NEXT: vrfip 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: ceil_v4f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfip 2, 2 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p) ret <4 x float> %t @@ -199,6 +495,12 @@ define <8 x float> @ceil_v8f32(<8 x float> %p) ; CHECK-NEXT: vrfip 2, 2 ; CHECK-NEXT: vrfip 3, 3 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: ceil_v8f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfip 2, 2 +; NO-ALTIVEC-NEXT: vrfip 3, 3 +; NO-ALTIVEC-NEXT: blr { %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p) ret <8 x float> %t @@ -210,6 +512,11 @@ define <4 x float> @trunc_v4f32(<4 x float> %p) ; CHECK: # %bb.0: ; CHECK-NEXT: vrfiz 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: trunc_v4f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfiz 2, 2 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p) ret <4 x float> %t @@ -222,6 +529,12 @@ define <8 x float> @trunc_v8f32(<8 x float> %p) ; CHECK-NEXT: vrfiz 2, 2 ; CHECK-NEXT: vrfiz 3, 3 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: trunc_v8f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfiz 2, 2 +; NO-ALTIVEC-NEXT: vrfiz 3, 3 +; NO-ALTIVEC-NEXT: blr { %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p) ret <8 x float> %t @@ -233,6 +546,11 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %p) ; CHECK: # %bb.0: ; CHECK-NEXT: vrfin 2, 2 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: nearbyint_v4f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfin 2, 2 +; NO-ALTIVEC-NEXT: blr { %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p) ret <4 x float> %t @@ -245,6 +563,12 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p) ; CHECK-NEXT: vrfin 2, 2 ; CHECK-NEXT: vrfin 3, 3 ; CHECK-NEXT: blr +; +; NO-ALTIVEC-LABEL: nearbyint_v8f32: +; NO-ALTIVEC: # %bb.0: +; NO-ALTIVEC-NEXT: vrfin 2, 2 +; NO-ALTIVEC-NEXT: vrfin 3, 3 +; NO-ALTIVEC-NEXT: blr { %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) ret <8 x float> %t diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll index 71c3069..08ca1d1 100644 --- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll @@ -5286,16 +5286,16 @@ entry: define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32(<3 x float> %x) #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 -; PC64LE-NEXT: xxswapd 1, 34 +; PC64LE-NEXT: xxswapd 0, 34 +; PC64LE-NEXT: xxsldwi 1, 34, 34, 3 ; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 -; PC64LE-NEXT: mtfprwz 0, 3 -; PC64LE-NEXT: mffprwz 3, 1 +; PC64LE-NEXT: mffprwz 4, 1 +; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI97_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI97_0@toc@l @@ -5311,25 +5311,25 @@ define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32(<3 x float> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3 -; PC64LE9-NEXT: xxswapd 1, 34 +; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: xscvdpsxws 1, 1 ; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: mffprwz 3, 1 -; PC64LE9-NEXT: mtfprwz 1, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1 -; PC64LE9-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: xscvspdpn 1, 1 -; PC64LE9-NEXT: xscvdpsxws 1, 1 -; PC64LE9-NEXT: mffprwz 3, 1 +; PC64LE9-NEXT: xxswapd 0, 34 +; PC64LE9-NEXT: xscvspdpn 0, 0 +; PC64LE9-NEXT: xscvdpsxws 0, 0 +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE9-NEXT: mtvsrwz 34, 3 +; PC64LE9-NEXT: mtfprwz 1, 4 +; PC64LE9-NEXT: addis 4, 2, .LCPI97_0@toc@ha +; PC64LE9-NEXT: xscvspdpn 0, 0 +; PC64LE9-NEXT: addi 4, 4, .LCPI97_0@toc@l +; PC64LE9-NEXT: xscvdpsxws 0, 0 +; PC64LE9-NEXT: mffprwz 5, 0 +; PC64LE9-NEXT: mtfprwz 0, 5 +; PC64LE9-NEXT: xxmrghw 35, 1, 0 +; PC64LE9-NEXT: lxv 0, 0(4) ; PC64LE9-NEXT: xxperm 34, 35, 0 ; PC64LE9-NEXT: blr entry: @@ -5558,11 +5558,11 @@ entry: define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64(<3 x double> %x) #0 { ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xscvdpsxws 0, 1 -; PC64LE-NEXT: xscvdpsxws 1, 2 +; PC64LE-NEXT: xscvdpsxws 0, 2 +; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 -; PC64LE-NEXT: mtfprwz 0, 3 -; PC64LE-NEXT: mffprwz 3, 1 +; PC64LE-NEXT: mffprwz 4, 1 +; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI105_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI105_0@toc@l @@ -5577,19 +5577,19 @@ define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64(<3 x double> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: xscvdpsxws 0, 1 -; PC64LE9-NEXT: xscvdpsxws 1, 2 +; PC64LE9-NEXT: xscvdpsxws 0, 3 ; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: mffprwz 3, 1 -; PC64LE9-NEXT: mtfprwz 1, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI105_0@toc@ha -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xscvdpsxws 1, 3 -; PC64LE9-NEXT: addi 3, 3, .LCPI105_0@toc@l -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: mffprwz 3, 1 +; PC64LE9-NEXT: xscvdpsxws 0, 2 ; PC64LE9-NEXT: mtvsrwz 34, 3 +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: xscvdpsxws 0, 1 +; PC64LE9-NEXT: mtfprwz 1, 4 +; PC64LE9-NEXT: addis 4, 2, .LCPI105_0@toc@ha +; PC64LE9-NEXT: addi 4, 4, .LCPI105_0@toc@l +; PC64LE9-NEXT: mffprwz 5, 0 +; PC64LE9-NEXT: mtfprwz 0, 5 +; PC64LE9-NEXT: xxmrghw 35, 1, 0 +; PC64LE9-NEXT: lxv 0, 0(4) ; PC64LE9-NEXT: xxperm 34, 35, 0 ; PC64LE9-NEXT: blr entry: @@ -5783,16 +5783,16 @@ entry: define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32(<3 x float> %x) #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 -; PC64LE-NEXT: xxswapd 1, 34 +; PC64LE-NEXT: xxswapd 0, 34 +; PC64LE-NEXT: xxsldwi 1, 34, 34, 3 ; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 -; PC64LE-NEXT: mtfprwz 0, 3 -; PC64LE-NEXT: mffprwz 3, 1 +; PC64LE-NEXT: mffprwz 4, 1 +; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI113_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI113_0@toc@l @@ -5808,25 +5808,25 @@ define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32(<3 x float> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3 -; PC64LE9-NEXT: xxswapd 1, 34 +; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: xscvdpuxws 1, 1 ; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: mffprwz 3, 1 -; PC64LE9-NEXT: mtfprwz 1, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI113_0@toc@ha -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1 -; PC64LE9-NEXT: addi 3, 3, .LCPI113_0@toc@l -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: xscvspdpn 1, 1 -; PC64LE9-NEXT: xscvdpuxws 1, 1 -; PC64LE9-NEXT: mffprwz 3, 1 +; PC64LE9-NEXT: xxswapd 0, 34 +; PC64LE9-NEXT: xscvspdpn 0, 0 +; PC64LE9-NEXT: xscvdpuxws 0, 0 +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE9-NEXT: mtvsrwz 34, 3 +; PC64LE9-NEXT: mtfprwz 1, 4 +; PC64LE9-NEXT: addis 4, 2, .LCPI113_0@toc@ha +; PC64LE9-NEXT: xscvspdpn 0, 0 +; PC64LE9-NEXT: addi 4, 4, .LCPI113_0@toc@l +; PC64LE9-NEXT: xscvdpuxws 0, 0 +; PC64LE9-NEXT: mffprwz 5, 0 +; PC64LE9-NEXT: mtfprwz 0, 5 +; PC64LE9-NEXT: xxmrghw 35, 1, 0 +; PC64LE9-NEXT: lxv 0, 0(4) ; PC64LE9-NEXT: xxperm 34, 35, 0 ; PC64LE9-NEXT: blr entry: @@ -6054,11 +6054,11 @@ entry: define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64(<3 x double> %x) #0 { ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xscvdpuxws 0, 1 -; PC64LE-NEXT: xscvdpuxws 1, 2 +; PC64LE-NEXT: xscvdpuxws 0, 2 +; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: mffprwz 3, 0 -; PC64LE-NEXT: mtfprwz 0, 3 -; PC64LE-NEXT: mffprwz 3, 1 +; PC64LE-NEXT: mffprwz 4, 1 +; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI121_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI121_0@toc@l @@ -6073,19 +6073,19 @@ define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64(<3 x double> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: xscvdpuxws 0, 1 -; PC64LE9-NEXT: xscvdpuxws 1, 2 +; PC64LE9-NEXT: xscvdpuxws 0, 3 ; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: mffprwz 3, 1 -; PC64LE9-NEXT: mtfprwz 1, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI121_0@toc@ha -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xscvdpuxws 1, 3 -; PC64LE9-NEXT: addi 3, 3, .LCPI121_0@toc@l -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: mffprwz 3, 1 +; PC64LE9-NEXT: xscvdpuxws 0, 2 ; PC64LE9-NEXT: mtvsrwz 34, 3 +; PC64LE9-NEXT: mffprwz 4, 0 +; PC64LE9-NEXT: xscvdpuxws 0, 1 +; PC64LE9-NEXT: mtfprwz 1, 4 +; PC64LE9-NEXT: addis 4, 2, .LCPI121_0@toc@ha +; PC64LE9-NEXT: addi 4, 4, .LCPI121_0@toc@l +; PC64LE9-NEXT: mffprwz 5, 0 +; PC64LE9-NEXT: mtfprwz 0, 5 +; PC64LE9-NEXT: xxmrghw 35, 1, 0 +; PC64LE9-NEXT: lxv 0, 0(4) ; PC64LE9-NEXT: xxperm 34, 35, 0 ; PC64LE9-NEXT: blr entry: @@ -6269,33 +6269,33 @@ entry: define <3 x float> @constrained_vector_fptrunc_v3f64(<3 x double> %x) #0 { ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xsrsp 0, 1 -; PC64LE-NEXT: xsrsp 1, 2 +; PC64LE-NEXT: xsrsp 0, 3 +; PC64LE-NEXT: xsrsp 2, 2 ; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI129_0@toc@l -; PC64LE-NEXT: xscvdpspn 0, 0 +; PC64LE-NEXT: xsrsp 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xxmrghw 34, 1, 0 -; PC64LE-NEXT: lxvd2x 0, 0, 3 -; PC64LE-NEXT: xxswapd 35, 0 -; PC64LE-NEXT: xsrsp 0, 3 +; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 36, 0 +; PC64LE-NEXT: xxmrghw 34, 2, 1 +; PC64LE-NEXT: lxvd2x 1, 0, 3 +; PC64LE-NEXT: xxswapd 35, 1 ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: xsrsp 0, 1 -; PC64LE9-NEXT: xsrsp 1, 2 +; PC64LE9-NEXT: xsrsp 0, 3 +; PC64LE9-NEXT: xsrsp 2, 2 +; PC64LE9-NEXT: xsrsp 1, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI129_0@toc@l -; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xsrsp 1, 3 -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: xscvdpspn 34, 1 -; PC64LE9-NEXT: xxperm 34, 35, 0 +; PC64LE9-NEXT: xscvdpspn 2, 2 +; PC64LE9-NEXT: xscvdpspn 34, 0 +; PC64LE9-NEXT: xxmrghw 35, 2, 1 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 35, 1 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64( @@ -7142,8 +7142,8 @@ entry: define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 { ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xxswapd 0, 34 -; PC64LE-NEXT: xxsldwi 1, 34, 34, 1 +; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 +; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mtfprwa 0, 3 ; PC64LE-NEXT: mffprwz 3, 1 @@ -7154,7 +7154,7 @@ define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 { ; PC64LE-NEXT: xscvsxdsp 1, 1 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xxmrghw 35, 1, 0 +; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: mfvsrwz 3, 34 ; PC64LE-NEXT: xxswapd 36, 0 @@ -7166,24 +7166,24 @@ define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: li 3, 0 +; PC64LE9-NEXT: li 3, 4 ; PC64LE9-NEXT: vextuwrx 3, 3, 2 ; PC64LE9-NEXT: mtfprwa 0, 3 -; PC64LE9-NEXT: li 3, 4 +; PC64LE9-NEXT: li 3, 0 ; PC64LE9-NEXT: vextuwrx 3, 3, 2 ; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: mtfprwa 1, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI161_0@toc@ha +; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: xscvsxdsp 1, 1 -; PC64LE9-NEXT: addi 3, 3, .LCPI161_0@toc@l +; PC64LE9-NEXT: mtfprwa 2, 3 +; PC64LE9-NEXT: addis 3, 2, .LCPI161_0@toc@ha +; PC64LE9-NEXT: xscvsxdsp 2, 2 ; PC64LE9-NEXT: xscvdpspn 0, 0 +; PC64LE9-NEXT: addi 3, 3, .LCPI161_0@toc@l ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 +; PC64LE9-NEXT: xscvdpspn 34, 2 +; PC64LE9-NEXT: xxmrghw 35, 0, 1 ; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: mfvsrwz 3, 34 -; PC64LE9-NEXT: mtfprwa 1, 3 -; PC64LE9-NEXT: xscvsxdsp 1, 1 -; PC64LE9-NEXT: xscvdpspn 34, 1 ; PC64LE9-NEXT: xxperm 34, 35, 0 ; PC64LE9-NEXT: blr entry: @@ -7225,15 +7225,15 @@ entry: define <3 x float> @constrained_vector_sitofp_v3f32_v3i64(<3 x i64> %x) #0 { ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: mtfprd 0, 3 -; PC64LE-NEXT: mtfprd 1, 4 +; PC64LE-NEXT: mtfprd 0, 4 +; PC64LE-NEXT: mtfprd 1, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI163_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI163_0@toc@l ; PC64LE-NEXT: xscvsxdsp 0, 0 ; PC64LE-NEXT: xscvsxdsp 1, 1 -; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xxmrghw 34, 1, 0 +; PC64LE-NEXT: xscvdpspn 0, 0 +; PC64LE-NEXT: xxmrghw 34, 0, 1 ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 35, 0 ; PC64LE-NEXT: mtfprd 0, 5 @@ -7244,20 +7244,20 @@ define <3 x float> @constrained_vector_sitofp_v3f32_v3i64(<3 x i64> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: mtfprd 0, 3 ; PC64LE9-NEXT: mtfprd 1, 4 +; PC64LE9-NEXT: mtfprd 2, 3 +; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: addis 3, 2, .LCPI163_0@toc@ha -; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: xscvsxdsp 1, 1 +; PC64LE9-NEXT: xscvsxdsp 2, 2 +; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: addi 3, 3, .LCPI163_0@toc@l -; PC64LE9-NEXT: xscvdpspn 0, 0 +; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: mtfprd 1, 5 -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: xscvsxdsp 1, 1 -; PC64LE9-NEXT: xscvdpspn 34, 1 -; PC64LE9-NEXT: xxperm 34, 35, 0 +; PC64LE9-NEXT: xscvdpspn 34, 0 +; PC64LE9-NEXT: xxmrghw 35, 1, 2 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 35, 1 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> @@ -7709,8 +7709,8 @@ entry: define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 { ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i32: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: xxswapd 0, 34 -; PC64LE-NEXT: xxsldwi 1, 34, 34, 1 +; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 +; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mtfprwz 0, 3 ; PC64LE-NEXT: mffprwz 3, 1 @@ -7721,7 +7721,7 @@ define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 { ; PC64LE-NEXT: xscvuxdsp 1, 1 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xxmrghw 35, 1, 0 +; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: mfvsrwz 3, 34 ; PC64LE-NEXT: xxswapd 36, 0 @@ -7733,24 +7733,24 @@ define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i32: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: li 3, 0 +; PC64LE9-NEXT: li 3, 4 ; PC64LE9-NEXT: vextuwrx 3, 3, 2 ; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: li 3, 4 +; PC64LE9-NEXT: li 3, 0 ; PC64LE9-NEXT: vextuwrx 3, 3, 2 ; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: mtfprwz 1, 3 -; PC64LE9-NEXT: addis 3, 2, .LCPI179_0@toc@ha +; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: xscvuxdsp 1, 1 -; PC64LE9-NEXT: addi 3, 3, .LCPI179_0@toc@l +; PC64LE9-NEXT: mtfprwz 2, 3 +; PC64LE9-NEXT: addis 3, 2, .LCPI179_0@toc@ha +; PC64LE9-NEXT: xscvuxdsp 2, 2 ; PC64LE9-NEXT: xscvdpspn 0, 0 +; PC64LE9-NEXT: addi 3, 3, .LCPI179_0@toc@l ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 +; PC64LE9-NEXT: xscvdpspn 34, 2 +; PC64LE9-NEXT: xxmrghw 35, 0, 1 ; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: mfvsrwz 3, 34 -; PC64LE9-NEXT: mtfprwz 1, 3 -; PC64LE9-NEXT: xscvuxdsp 1, 1 -; PC64LE9-NEXT: xscvdpspn 34, 1 ; PC64LE9-NEXT: xxperm 34, 35, 0 ; PC64LE9-NEXT: blr entry: @@ -7792,15 +7792,15 @@ entry: define <3 x float> @constrained_vector_uitofp_v3f32_v3i64(<3 x i64> %x) #0 { ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: mtfprd 0, 3 -; PC64LE-NEXT: mtfprd 1, 4 +; PC64LE-NEXT: mtfprd 0, 4 +; PC64LE-NEXT: mtfprd 1, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI181_0@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI181_0@toc@l ; PC64LE-NEXT: xscvuxdsp 0, 0 ; PC64LE-NEXT: xscvuxdsp 1, 1 -; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 -; PC64LE-NEXT: xxmrghw 34, 1, 0 +; PC64LE-NEXT: xscvdpspn 0, 0 +; PC64LE-NEXT: xxmrghw 34, 0, 1 ; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: xxswapd 35, 0 ; PC64LE-NEXT: mtfprd 0, 5 @@ -7811,20 +7811,20 @@ define <3 x float> @constrained_vector_uitofp_v3f32_v3i64(<3 x i64> %x) #0 { ; ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64: ; PC64LE9: # %bb.0: # %entry -; PC64LE9-NEXT: mtfprd 0, 3 ; PC64LE9-NEXT: mtfprd 1, 4 +; PC64LE9-NEXT: mtfprd 2, 3 +; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: addis 3, 2, .LCPI181_0@toc@ha -; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: xscvuxdsp 1, 1 +; PC64LE9-NEXT: xscvuxdsp 2, 2 +; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: addi 3, 3, .LCPI181_0@toc@l -; PC64LE9-NEXT: xscvdpspn 0, 0 +; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: mtfprd 1, 5 -; PC64LE9-NEXT: lxv 0, 0(3) -; PC64LE9-NEXT: xscvuxdsp 1, 1 -; PC64LE9-NEXT: xscvdpspn 34, 1 -; PC64LE9-NEXT: xxperm 34, 35, 0 +; PC64LE9-NEXT: xscvdpspn 34, 0 +; PC64LE9-NEXT: xxmrghw 35, 1, 2 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 35, 1 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> diff --git a/llvm/test/CodeGen/PowerPC/vector-rotates.ll b/llvm/test/CodeGen/PowerPC/vector-rotates.ll index 2de8804..38e2736 100644 --- a/llvm/test/CodeGen/PowerPC/vector-rotates.ll +++ b/llvm/test/CodeGen/PowerPC/vector-rotates.ll @@ -5,6 +5,9 @@ ; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \ ; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | \ ; RUN: FileCheck --check-prefix=CHECK-P7 %s +; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \ +; RUN: -verify-machineinstrs -mcpu=future < %s | \ +; RUN: FileCheck --check-prefix=CHECK-FUTURE %s define <16 x i8> @rotl_v16i8(<16 x i8> %a) { ; CHECK-P8-LABEL: rotl_v16i8: @@ -23,6 +26,14 @@ define <16 x i8> @rotl_v16i8(<16 x i8> %a) { ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: vrlb v2, v2, v3 ; CHECK-P7-NEXT: blr +; +; CHECK-FUTURE-LABEL: rotl_v16i8: +; CHECK-FUTURE: # %bb.0: # %entry +; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-FUTURE-NEXT: lxv vs35, 0(r3) +; CHECK-FUTURE-NEXT: vrlb v2, v2, v3 +; CHECK-FUTURE-NEXT: blr entry: %b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8> %c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0> @@ -47,6 +58,14 @@ define <8 x i16> @rotl_v8i16(<8 x i16> %a) { ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: vrlh v2, v2, v3 ; CHECK-P7-NEXT: blr +; +; CHECK-FUTURE-LABEL: rotl_v8i16: +; CHECK-FUTURE: # %bb.0: # %entry +; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-FUTURE-NEXT: lxv vs35, 0(r3) +; CHECK-FUTURE-NEXT: vrlh v2, v2, v3 +; CHECK-FUTURE-NEXT: blr entry: %b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16> %c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0> @@ -71,6 +90,14 @@ define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) { ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: vrlw v2, v2, v3 ; CHECK-P7-NEXT: blr +; +; CHECK-FUTURE-LABEL: rotl_v4i32_0: +; CHECK-FUTURE: # %bb.0: # %entry +; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI2_0@toc@ha +; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI2_0@toc@l +; CHECK-FUTURE-NEXT: lxv vs0, 0(r3) +; CHECK-FUTURE-NEXT: xvrlw vs34, vs34, vs0 +; CHECK-FUTURE-NEXT: blr entry: %b = shl <4 x i32> %a, <i32 29, i32 19, i32 17, i32 11> %c = lshr <4 x i32> %a, <i32 3, i32 13, i32 15, i32 21> @@ -94,6 +121,12 @@ define <4 x i32> @rotl_v4i32_1(<4 x i32> %a) { ; CHECK-P7-NEXT: vsubuwm v3, v4, v3 ; CHECK-P7-NEXT: vrlw v2, v2, v3 ; CHECK-P7-NEXT: blr +; +; CHECK-FUTURE-LABEL: rotl_v4i32_1: +; CHECK-FUTURE: # %bb.0: # %entry +; CHECK-FUTURE-NEXT: xxspltiw vs0, 23 +; CHECK-FUTURE-NEXT: xvrlw vs34, vs34, vs0 +; CHECK-FUTURE-NEXT: blr entry: %b = shl <4 x i32> %a, <i32 23, i32 23, i32 23, i32 23> %c = lshr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9> @@ -124,6 +157,14 @@ define <2 x i64> @rotl_v2i64(<2 x i64> %a) { ; CHECK-P7-NEXT: addi r3, r1, -16 ; CHECK-P7-NEXT: lxvd2x vs34, 0, r3 ; CHECK-P7-NEXT: blr +; +; CHECK-FUTURE-LABEL: rotl_v2i64: +; CHECK-FUTURE: # %bb.0: # %entry +; CHECK-FUTURE-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; CHECK-FUTURE-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-FUTURE-NEXT: lxv vs35, 0(r3) +; CHECK-FUTURE-NEXT: vrld v2, v2, v3 +; CHECK-FUTURE-NEXT: blr entry: %b = shl <2 x i64> %a, <i64 41, i64 53> %c = lshr <2 x i64> %a, <i64 23, i64 11> diff --git a/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll b/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll index 9cb2d44..871aab3 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll @@ -145,14 +145,14 @@ declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>) ; CHECK32-NEXT: .align 4 ; CHECK32-NEXT: [[L2_foo:.*]]: # %for.body ; CHECK32-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK32-NEXT: slwi r8, r7, 4 -; CHECK32-NEXT: addic r7, r7, 1 -; CHECK32-NEXT: addze r6, r6 +; CHECK32-NEXT: slwi r8, r6, 4 +; CHECK32-NEXT: addic r6, r6, 1 +; CHECK32-NEXT: addze r7, r7 ; CHECK32-NEXT: lxvx vs2, r4, r8 ; CHECK32-NEXT: xvmaddmsp vs2, vs0, vs1 ; CHECK32-NEXT: stxvx vs2, r3, r8 -; CHECK32-NEXT: xor r8, r7, r5 -; CHECK32-NEXT: or. r8, r8, r6 +; CHECK32-NEXT: xor r8, r6, r5 +; CHECK32-NEXT: or. r8, r8, r7 ; CHECK32-NEXT: bne cr0, [[L2_foo]] ; CHECK32: .foo: |