diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Combine.td | 2 |
2 files changed, 20 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 590a65a..0e07bc4 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -2014,6 +2014,25 @@ void CombinerHelper::applyCombineShlOfExtend(MachineInstr &MI, MI.eraseFromParent(); } +bool CombinerHelper::matchCombineMergeUnmerge(MachineInstr &MI, + Register &MatchInfo) { + GMerge &Merge = cast<GMerge>(MI); + SmallVector<Register, 16> MergedValues; + for (unsigned I = 0; I < Merge.getNumSources(); ++I) + MergedValues.emplace_back(Merge.getSourceReg(I)); + + auto *Unmerge = getOpcodeDef<GUnmerge>(MergedValues[0], MRI); + if (!Unmerge || Unmerge->getNumDefs() != Merge.getNumSources()) + return false; + + for (unsigned I = 0; I < MergedValues.size(); ++I) + if (MergedValues[I] != Unmerge->getReg(I)) + return false; + + MatchInfo = Unmerge->getSourceReg(); + return true; +} + static Register peekThroughBitcast(Register Reg, const MachineRegisterInfo &MRI) { while (mi_match(Reg, MRI, m_GBitcast(m_Reg(Reg)))) diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td index 62493ae..5e2b5b6 100644 --- a/llvm/lib/Target/AArch64/AArch64Combine.td +++ b/llvm/lib/Target/AArch64/AArch64Combine.td @@ -203,6 +203,6 @@ def AArch64PostLegalizerCombinerHelper extractvecelt_pairwise_add, redundant_or, mul_const, redundant_sext_inreg, form_bitfield_extract, rotate_out_of_range, - icmp_to_true_false_known_bits]> { + icmp_to_true_false_known_bits, merge_unmerge]> { let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule"; } |