diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 15 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 1 |
4 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index dab6dbe..4e1dc81 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -426,6 +426,9 @@ def FeatureEnhancedCounterVirtualization : SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", "true", "Enable enhanced counter virtualization extension">; +def FeatureRME : SubtargetFeature<"rme", "HasRME", + "true", "Enable Realm Management Extension">; + //===----------------------------------------------------------------------===// // Architectures. // diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index ea1fbc1..491e7bd 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -183,6 +183,9 @@ protected: bool HasSVE2SHA3 = false; bool HasSVE2BitPerm = false; + // Armv9-A Extensions + bool HasRME = false; + // Future architecture extensions. bool HasETE = false; bool HasTRBE = false; diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 1909e79..8594ec9 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -531,6 +531,14 @@ defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; } //FeatureTLB_RMI +// Armv9-A Realm Management Extention TLBI Instructions +let Requires = ["AArch64::FeatureRME"] in { +defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>; +defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>; +defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>; +defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>; +} + // Armv8.5-A Prediction Restriction by Context instruction options: class PRCTX<string name, bits<4> crm> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; @@ -743,6 +751,13 @@ def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>; def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>; } +// v9a Realm Management Extension registers +let Requires = [{ {AArch64::FeatureRME} }] in { +def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>; +def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>; +def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>; +} + //===---------------------- // Write-only regs //===---------------------- diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index d2a0b1dc..cd7001f 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2917,6 +2917,7 @@ static const struct Extension { {"xs", {AArch64::FeatureXS}}, {"pauth", {AArch64::FeaturePAuth}}, {"flagm", {AArch64::FeatureFlagM}}, + {"rme", {AArch64::FeatureRME}}, // FIXME: Unsupported extensions {"lor", {}}, {"rdma", {}}, |