diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ExpandPseudo.cpp | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAMX.td | 31 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 6 |
3 files changed, 53 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp index 73ca4b0..7544c20 100644 --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -781,7 +781,11 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB, case X86::PTDPBF16PSV: case X86::PTDPFP16PSV: case X86::PTMMULTF32PSV: - case X86::PTTMMULTF32PSV: { + case X86::PTTMMULTF32PSV: + case X86::PTDPBF8PSV: + case X86::PTDPBHF8PSV: + case X86::PTDPHBF8PSV: + case X86::PTDPHF8PSV: { MI.untieRegOperand(4); for (unsigned i = 3; i > 0; --i) MI.removeOperand(i); @@ -801,6 +805,18 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB, case X86::PTTMMULTF32PSV: Opc = X86::TTMMULTF32PS; break; + case X86::PTDPBF8PSV: + Opc = X86::TDPBF8PS; + break; + case X86::PTDPBHF8PSV: + Opc = X86::TDPBHF8PS; + break; + case X86::PTDPHBF8PSV: + Opc = X86::TDPHBF8PS; + break; + case X86::PTDPHF8PSV: + Opc = X86::TDPHF8PS; + break; default: llvm_unreachable("Unexpected Opcode"); diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td index 059bfb4..8191fc4 100644 --- a/llvm/lib/Target/X86/X86InstrAMX.td +++ b/llvm/lib/Target/X86/X86InstrAMX.td @@ -304,6 +304,37 @@ let Predicates = [HasAMXFP8, In64BitMode] in { [(int_x86_tdphf8ps timm:$src1, timm:$src2, timm:$src3)]>; } + + let Constraints = "$src4 = $dst" in { + def PTDPBF8PSV : PseudoI<(outs TILE:$dst), + (ins GR16:$src1, GR16:$src2, GR16:$src3, + TILE:$src4, TILE:$src5, TILE:$src6), + [(set TILE:$dst, + (int_x86_tdpbf8ps_internal GR16:$src1, + GR16:$src2, GR16:$src3, TILE:$src4, + TILE:$src5, TILE:$src6))]>; + def PTDPBHF8PSV : PseudoI<(outs TILE:$dst), + (ins GR16:$src1, GR16:$src2, GR16:$src3, + TILE:$src4, TILE:$src5, TILE:$src6), + [(set TILE:$dst, + (int_x86_tdpbhf8ps_internal GR16:$src1, + GR16:$src2, GR16:$src3, TILE:$src4, + TILE:$src5, TILE:$src6))]>; + def PTDPHBF8PSV : PseudoI<(outs TILE:$dst), + (ins GR16:$src1, GR16:$src2, GR16:$src3, + TILE:$src4, TILE:$src5, TILE:$src6), + [(set TILE:$dst, + (int_x86_tdphbf8ps_internal GR16:$src1, + GR16:$src2, GR16:$src3, TILE:$src4, + TILE:$src5, TILE:$src6))]>; + def PTDPHF8PSV : PseudoI<(outs TILE:$dst), + (ins GR16:$src1, GR16:$src2, GR16:$src3, + TILE:$src4, TILE:$src5, TILE:$src6), + [(set TILE:$dst, + (int_x86_tdphf8ps_internal GR16:$src1, + GR16:$src2, GR16:$src3, TILE:$src4, + TILE:$src5, TILE:$src6))]>; + } } } diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 08f6f43..1bbfd21 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -1080,7 +1080,11 @@ static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, case X86::PTILELOADDRSV: case X86::PTILELOADDRST1V: case X86::PTMMULTF32PSV: - case X86::PTTMMULTF32PSV: { + case X86::PTTMMULTF32PSV: + case X86::PTDPBF8PSV: + case X86::PTDPBHF8PSV: + case X86::PTDPHBF8PSV: + case X86::PTDPHF8PSV: { MachineOperand &MO1 = MI->getOperand(1); MachineOperand &MO2 = MI->getOperand(2); ShapeT Shape(&MO1, &MO2, MRI); |