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-rw-r--r--llvm/lib/Target/Mips/Mips16InstrInfo.cpp17
-rw-r--r--llvm/lib/Target/Mips/Mips16InstrInfo.h7
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.cpp5
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.h23
-rw-r--r--llvm/lib/Target/Mips/MipsSEFrameLowering.cpp49
-rw-r--r--llvm/lib/Target/Mips/MipsSEInstrInfo.cpp49
-rw-r--r--llvm/lib/Target/Mips/MipsSEInstrInfo.h7
7 files changed, 72 insertions, 85 deletions
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index aa94f54..d23ec57 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -37,11 +37,7 @@ using namespace llvm;
#define DEBUG_TYPE "mips16-instrinfo"
Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
- : MipsInstrInfo(STI, Mips::Bimm16), RI(STI) {}
-
-const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
- return RI;
-}
+ : MipsInstrInfo(STI, RI, Mips::Bimm16), RI(STI) {}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
@@ -105,7 +101,6 @@ void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
int64_t Offset,
MachineInstr::MIFlag Flags) const {
DebugLoc DL;
@@ -120,10 +115,12 @@ void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
.addMemOperand(MMO);
}
-void Mips16InstrInfo::loadRegFromStack(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
- int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
- int64_t Offset, MachineInstr::MIFlag Flags) const {
+void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ Register DestReg, int FI,
+ const TargetRegisterClass *RC,
+ int64_t Offset,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.h b/llvm/lib/Target/Mips/Mips16InstrInfo.h
index 1058e8c..4300d08 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.h
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.h
@@ -30,7 +30,7 @@ class Mips16InstrInfo : public MipsInstrInfo {
public:
explicit Mips16InstrInfo(const MipsSubtarget &STI);
- const MipsRegisterInfo &getRegisterInfo() const override;
+ const Mips16RegisterInfo &getRegisterInfo() const { return RI; }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
@@ -56,13 +56,14 @@ public:
void storeRegToStack(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, int64_t Offset,
+ int64_t Offset,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
void loadRegFromStack(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, int64_t Offset,
+
+ int64_t Offset,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index bffdffa..c879c46 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -39,8 +39,9 @@ using namespace llvm;
// Pin the vtable to this file.
void MipsInstrInfo::anchor() {}
-MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
- : MipsGenInstrInfo(STI, Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
+MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI,
+ const MipsRegisterInfo &RI, unsigned UncondBr)
+ : MipsGenInstrInfo(STI, RI, Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
Subtarget(STI), UncondBrOpc(UncondBr) {}
const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h
index 2337ae7..0b90972 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.h
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.h
@@ -55,7 +55,8 @@ public:
BT_Indirect // One indirct branch.
};
- explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
+ explicit MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI,
+ unsigned UncondBrOpc);
MCInst getNop() const override;
@@ -130,7 +131,10 @@ public:
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
- virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
+ const MipsRegisterInfo &getRegisterInfo() const {
+ return static_cast<const MipsRegisterInfo &>(
+ TargetInstrInfo::getRegisterInfo());
+ }
virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
@@ -143,31 +147,28 @@ public:
void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {
- storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags);
+ storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, 0, Flags);
}
void loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
+ Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {
- loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0, Flags);
+ loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, 0, Flags);
}
virtual void
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Register SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
- int64_t Offset,
+ const TargetRegisterClass *RC, int64_t Offset,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;
virtual void loadRegFromStack(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, int64_t Offset,
+ int FrameIndex, const TargetRegisterClass *RC, int64_t Offset,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;
virtual void adjustStackPtr(unsigned SP, int64_t Amount,
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index f08704a..942194c 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -172,7 +172,7 @@ void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
Register VR = MRI.createVirtualRegister(RC);
Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
- TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
+ TII.loadRegFromStack(MBB, I, VR, FI, RC, 0);
BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
.addReg(VR, RegState::Kill);
}
@@ -189,7 +189,7 @@ void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
.addReg(Src, getKillRegState(I->getOperand(0).isKill()));
- TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
+ TII.storeRegToStack(MBB, I, VR, true, FI, RC, 0);
}
void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
@@ -210,9 +210,9 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
DebugLoc DL = I->getDebugLoc();
const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
- TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
+ TII.loadRegFromStack(MBB, I, VR0, FI, RC, 0);
BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
- TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
+ TII.loadRegFromStack(MBB, I, VR1, FI, RC, RegSize);
BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
}
@@ -234,9 +234,9 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
DebugLoc DL = I->getDebugLoc();
BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
- TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
+ TII.storeRegToStack(MBB, I, VR0, true, FI, RC, 0);
BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
- TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
+ TII.storeRegToStack(MBB, I, VR1, true, FI, RC, RegSize);
}
bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
@@ -321,11 +321,9 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC2);
if (!Subtarget.isLittle())
std::swap(LoReg, HiReg);
- TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
- &RegInfo, 0);
- TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
- &RegInfo, 4);
- TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
+ TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, 0);
+ TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, 4);
+ TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, 0);
return true;
}
@@ -385,8 +383,8 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
// We re-use the same spill slot each time so that the stack frame doesn't
// grow too much in functions with a large number of moves.
int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC);
- TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
- TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
+ TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, 0);
+ TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, Offset);
return true;
}
@@ -480,8 +478,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
if (!MBB.isLiveIn(ABI.GetEhDataReg(I)))
MBB.addLiveIn(ABI.GetEhDataReg(I));
TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false,
- MipsFI->getEhDataRegFI(I), RC, &RegInfo,
- Register());
+ MipsFI->getEhDataRegFI(I), RC, Register());
}
// Emit .cfi_offset directives for eh data registers.
@@ -579,8 +576,7 @@ void MipsSEFrameLowering::emitInterruptPrologueStub(
.setMIFlag(MachineInstr::FrameSetup);
STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
- MipsFI->getISRRegFI(0), PtrRC,
- STI.getRegisterInfo(), 0);
+ MipsFI->getISRRegFI(0), PtrRC, 0);
// Fetch and Spill Status
MBB.addLiveIn(Mips::COP012);
@@ -590,8 +586,7 @@ void MipsSEFrameLowering::emitInterruptPrologueStub(
.setMIFlag(MachineInstr::FrameSetup);
STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
- MipsFI->getISRRegFI(1), PtrRC,
- STI.getRegisterInfo(), 0);
+ MipsFI->getISRRegFI(1), PtrRC, 0);
// Build the configuration for disabling lower priority interrupts. Non EIC
// interrupts need to be masked off with zero, EIC from the Cause register.
@@ -657,7 +652,6 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
const MipsSEInstrInfo &TII =
*static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
- const MipsRegisterInfo &RegInfo = *STI.getRegisterInfo();
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
MipsABIInfo ABI = STI.getABI();
@@ -690,8 +684,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
// Insert instructions that restore eh data registers.
for (int J = 0; J < 4; ++J) {
TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J),
- MipsFI->getEhDataRegFI(J), RC, &RegInfo,
- Register());
+ MipsFI->getEhDataRegFI(J), RC, Register());
}
}
@@ -722,17 +715,15 @@ void MipsSEFrameLowering::emitInterruptEpilogueStub(
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
// Restore EPC
- STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
- MipsFI->getISRRegFI(0), PtrRC,
- STI.getRegisterInfo(), Register());
+ STI.getInstrInfo()->loadRegFromStackSlot(
+ MBB, MBBI, Mips::K1, MipsFI->getISRRegFI(0), PtrRC, Register());
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
.addReg(Mips::K1)
.addImm(0);
// Restore Status
- STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
- MipsFI->getISRRegFI(1), PtrRC,
- STI.getRegisterInfo(), Register());
+ STI.getInstrInfo()->loadRegFromStackSlot(
+ MBB, MBBI, Mips::K1, MipsFI->getISRRegFI(1), PtrRC, Register());
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
.addReg(Mips::K1)
.addImm(0);
@@ -795,7 +786,7 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters(
// Insert the spill to the stack frame.
bool IsKill = !IsRAAndRetAddrIsTaken;
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
- TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, I.getFrameIdx(), RC, TRI,
+ TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, I.getFrameIdx(), RC,
Register());
}
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index dbdbb17..a1d0aa0 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -28,11 +28,7 @@ static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
}
MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
- : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI(STI) {}
-
-const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
- return RI;
-}
+ : MipsInstrInfo(STI, RI, getUnconditionalBranch(STI)), RI(STI) {}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
@@ -213,7 +209,6 @@ void MipsSEInstrInfo::storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
int64_t Offset,
MachineInstr::MIFlag Flags) const {
DebugLoc DL;
@@ -239,16 +234,16 @@ void MipsSEInstrInfo::storeRegToStack(MachineBasicBlock &MBB,
Opc = Mips::SDC1;
else if (Mips::FGR64RegClass.hasSubClassEq(RC))
Opc = Mips::SDC164;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v16i8))
Opc = Mips::ST_B;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
- TRI->isTypeLegalForClass(*RC, MVT::v8f16))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v8i16) ||
+ RI.isTypeLegalForClass(*RC, MVT::v8f16))
Opc = Mips::ST_H;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
- TRI->isTypeLegalForClass(*RC, MVT::v4f32))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v4i32) ||
+ RI.isTypeLegalForClass(*RC, MVT::v4f32))
Opc = Mips::ST_W;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
- TRI->isTypeLegalForClass(*RC, MVT::v2f64))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v2i64) ||
+ RI.isTypeLegalForClass(*RC, MVT::v2f64))
Opc = Mips::ST_D;
else if (Mips::LO32RegClass.hasSubClassEq(RC))
Opc = Mips::SW;
@@ -285,10 +280,12 @@ void MipsSEInstrInfo::storeRegToStack(MachineBasicBlock &MBB,
.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
}
-void MipsSEInstrInfo::loadRegFromStack(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
- int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
- int64_t Offset, MachineInstr::MIFlag Flags) const {
+void MipsSEInstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ Register DestReg, int FI,
+ const TargetRegisterClass *RC,
+ int64_t Offset,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
@@ -317,16 +314,16 @@ void MipsSEInstrInfo::loadRegFromStack(
Opc = Mips::LDC1;
else if (Mips::FGR64RegClass.hasSubClassEq(RC))
Opc = Mips::LDC164;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v16i8))
Opc = Mips::LD_B;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
- TRI->isTypeLegalForClass(*RC, MVT::v8f16))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v8i16) ||
+ RI.isTypeLegalForClass(*RC, MVT::v8f16))
Opc = Mips::LD_H;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
- TRI->isTypeLegalForClass(*RC, MVT::v4f32))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v4i32) ||
+ RI.isTypeLegalForClass(*RC, MVT::v4f32))
Opc = Mips::LD_W;
- else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
- TRI->isTypeLegalForClass(*RC, MVT::v2f64))
+ else if (RI.isTypeLegalForClass(*RC, MVT::v2i64) ||
+ RI.isTypeLegalForClass(*RC, MVT::v2f64))
Opc = Mips::LD_D;
else if (Mips::HI32RegClass.hasSubClassEq(RC))
Opc = Mips::LW;
@@ -682,8 +679,8 @@ MipsSEInstrInfo::compareOpndSize(unsigned Opc,
const MCInstrDesc &Desc = get(Opc);
assert(Desc.NumOperands == 2 && "Unary instruction expected.");
const MipsRegisterInfo *RI = &getRegisterInfo();
- unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI));
- unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI));
+ unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0));
+ unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1));
return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
}
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/llvm/lib/Target/Mips/MipsSEInstrInfo.h
index 2b4f55d..5c48ccd 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.h
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.h
@@ -24,7 +24,7 @@ class MipsSEInstrInfo : public MipsInstrInfo {
public:
explicit MipsSEInstrInfo(const MipsSubtarget &STI);
- const MipsRegisterInfo &getRegisterInfo() const override;
+ const MipsSERegisterInfo &getRegisterInfo() const { return RI; }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
@@ -50,13 +50,12 @@ public:
void storeRegToStack(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, int64_t Offset,
+ int64_t Offset,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
void loadRegFromStack(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, int64_t Offset,
+ int FrameIndex, const TargetRegisterClass *RC, int64_t Offset,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
generated by cgit v1.1 at 2025-11-11 08:51:59 +0000