diff options
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index b992988..c5a259b 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -447,6 +447,14 @@ static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); template <typename InsnType> +static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> +static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); @@ -608,12 +616,12 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, template <typename InsnType> static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) { - InsnType Rt = fieldFromInstruction(insn, 16, 5); + InsnType Rs = fieldFromInstruction(insn, 16, 5); InsnType Imm = fieldFromInstruction(insn, 0, 16); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, - Rt))); + Rs))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, - Rt))); + Rs))); MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; @@ -622,12 +630,12 @@ static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Addre template <typename InsnType> static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) { - InsnType Rt = fieldFromInstruction(insn, 21, 5); + InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Imm = fieldFromInstruction(insn, 0, 16); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, - Rt))); + Rs))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, - Rt))); + Rs))); MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; |