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-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp15
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp15
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.h10
-rw-r--r--llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSubtarget.cpp3
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSubtarget.h5
-rw-r--r--llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp4
8 files changed, 30 insertions, 28 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 68f5312..b378ce4 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1886,7 +1886,7 @@ bool BitSimplification::matchHalf(unsigned SelfR,
bool BitSimplification::validateReg(BitTracker::RegisterRef R, unsigned Opc,
unsigned OpNum) {
- auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI);
+ auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum);
auto *RRC = HBS::getFinalVRegClass(R, MRI);
return OpRC->hasSubClassEq(RRC);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index dd343d9..df61226 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1405,7 +1405,7 @@ bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
int FI = I.getFrameIdx();
const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
- HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI, Register());
+ HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, Register());
if (IsKill)
MBB.addLiveIn(Reg);
}
@@ -1470,7 +1470,7 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
MCRegister Reg = I.getReg();
const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
int FI = I.getFrameIdx();
- HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI, Register());
+ HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, Register());
}
return true;
@@ -1814,8 +1814,7 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
.addReg(SrcR, getKillRegState(IsKill))
.addReg(TmpR0, RegState::Kill);
- auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
- HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI, Register());
+ HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, Register());
expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
NewRegs.push_back(TmpR0);
@@ -1844,9 +1843,7 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
.addImm(0x01010101);
- MachineFunction &MF = *B.getParent();
- auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
- HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI, Register());
+ HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, Register());
expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
@@ -2225,7 +2222,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
if (!Bad) {
// If the addressing mode is ok, check the register class.
unsigned OpNum = Load ? 0 : 2;
- auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI);
+ auto *RC = HII.getRegClass(In.getDesc(), OpNum);
RC = getCommonRC(SI.RC, RC);
if (RC == nullptr)
Bad = true;
@@ -2395,7 +2392,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
SrcOp.getSubReg() };
- auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI);
+ auto *RC = HII.getRegClass(SI.getDesc(), 2);
// The this-> is needed to unconfuse MSVC.
Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 55bafde..7682af4 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -118,9 +118,9 @@ const int Hexagon_ADDI_OFFSET_MIN = -32768;
void HexagonInstrInfo::anchor() {}
HexagonInstrInfo::HexagonInstrInfo(const HexagonSubtarget &ST)
- : HexagonGenInstrInfo(ST, Hexagon::ADJCALLSTACKDOWN,
+ : HexagonGenInstrInfo(ST, RegInfo, Hexagon::ADJCALLSTACKDOWN,
Hexagon::ADJCALLSTACKUP),
- Subtarget(ST) {}
+ RegInfo(ST.getHwMode()), Subtarget(ST) {}
namespace llvm {
namespace HexagonFUnits {
@@ -964,7 +964,6 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
Register VReg,
MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
@@ -1009,10 +1008,12 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}
}
-void HexagonInstrInfo::loadRegFromStackSlot(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
- int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
- Register VReg, MachineInstr::MIFlag Flags) const {
+void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ Register DestReg, int FI,
+ const TargetRegisterClass *RC,
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 48adf82..796b978 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -23,6 +23,8 @@
#include <cstdint>
#include <vector>
+#include "HexagonRegisterInfo.h"
+
#define GET_INSTRINFO_HEADER
#include "HexagonGenInstrInfo.inc"
@@ -36,6 +38,7 @@ class MachineOperand;
class TargetRegisterInfo;
class HexagonInstrInfo : public HexagonGenInstrInfo {
+ const HexagonRegisterInfo RegInfo;
const HexagonSubtarget &Subtarget;
enum BundleAttribute {
@@ -47,6 +50,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
public:
explicit HexagonInstrInfo(const HexagonSubtarget &ST);
+ const HexagonRegisterInfo &getRegisterInfo() const { return RegInfo; }
+
/// TargetInstrInfo overrides.
/// If the specified machine instruction is a direct
@@ -183,8 +188,7 @@ public:
/// is true, the register operand is the last use and must be marked kill.
void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
/// Load the specified register of the given register class from the specified
@@ -193,7 +197,7 @@ public:
void loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
+ Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
/// This function is called for all pseudo instructions
diff --git a/llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
index 7cbd81f..54969b2 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
@@ -646,7 +646,7 @@ bool HexagonLoadStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG,
MachineInstr *CombI;
if (Acc != 0) {
const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi);
- const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI);
+ const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0);
Register VReg = MF->getRegInfo().createVirtualRegister(RC);
MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg).addImm(LowerAcc);
NG.push_back(TfrI);
@@ -677,7 +677,7 @@ bool HexagonLoadStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG,
} else {
// Create vreg = A2_tfrsi #Acc; mem[hw] = vreg
const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi);
- const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI);
+ const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0);
Register VReg = MF->getRegInfo().createVirtualRegister(RC);
MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg).addImm(int(Acc));
NG.push_back(TfrI);
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index a3c8a88..66c8b0a 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -76,8 +76,7 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
OptLevel(TM.getOptLevel()),
CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
- RegInfo(getHwMode()), TLInfo(TM, *this),
- InstrItins(getInstrItineraryForCPU(CPUString)) {
+ TLInfo(TM, *this), InstrItins(getInstrItineraryForCPU(CPUString)) {
Hexagon_MC::addArchSubtarget(this, FS);
// Beware of the default constructor of InstrItineraryData: it will
// reset all members to 0.
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index 995f66d..7dfede2 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -100,7 +100,6 @@ private:
// The following objects can use the TargetTriple, so they must be
// declared after it.
HexagonInstrInfo InstrInfo;
- HexagonRegisterInfo RegInfo;
HexagonTargetLowering TLInfo;
HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering;
@@ -122,7 +121,7 @@ public:
}
const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const HexagonRegisterInfo *getRegisterInfo() const override {
- return &RegInfo;
+ return &InstrInfo.getRegisterInfo();
}
const HexagonTargetLowering *getTargetLowering() const override {
return &TLInfo;
@@ -295,6 +294,8 @@ public:
bool useBSBScheduling() const { return UseBSBScheduling; }
bool enableMachineScheduler() const override;
+ bool enableTerminalRule() const override { return true; }
+
// Always use the TargetLowering default scheduler.
// FIXME: This will use the vliw scheduler which is probably just hurting
// compiler time and will be removed eventually anyway.
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index cb88d1a..d39b79a 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -653,7 +653,7 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
const MCInstrDesc& MCID = PacketMI.getDesc();
// First operand is always the result.
- const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI);
+ const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0);
// Double regs can not feed into new value store: PRM section: 5.4.2.2.
if (PacketRC == &Hexagon::DoubleRegsRegClass)
return false;
@@ -866,7 +866,7 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
return false;
const MCInstrDesc& MCID = PI.getDesc();
- const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI);
+ const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0);
if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
return false;
generated by cgit v1.1 at 2025-11-11 08:01:21 +0000