diff options
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 3dc5aff..5d43320 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -1806,7 +1806,7 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) { // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64. if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) || - !(TLI.isOperationLegalOrCustom(ISD::FSUB, VT) || VT.isScalableVector())) + !(TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) || VT.isScalableVector())) return SDValue(); SDLoc DL(Node); |