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| author | Craig Topper <craig.topper@sifive.com> | 2024-09-18 17:24:43 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2024-09-18 18:19:21 -0700 |
| commit | d21a43579e36af4aa90bf541aa8bab33e7500297 (patch) | |
| tree | 007cb4a27071d8482ffd881e3a02860d3680ddf3 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | 615bd9ee60ca213d0e93a7ddc5c1bf48418952e9 (diff) | |
| download | llvm-d21a43579e36af4aa90bf541aa8bab33e7500297.zip llvm-d21a43579e36af4aa90bf541aa8bab33e7500297.tar.gz llvm-d21a43579e36af4aa90bf541aa8bab33e7500297.tar.bz2 | |
[LegalizeVectorOps][RISCV] Don't scalarize FNEG in ExpandFNEG if FSUB is marked Promote.
We have a special check that tries to determine if vector FP
operations are supported for the type to determine whether to
scalarize or not. If FP arithmetic would be promoted, don't unroll.
This improves Zvfhmin codegen on RISC-V.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 3dc5aff..5d43320 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -1806,7 +1806,7 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) { // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64. if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) || - !(TLI.isOperationLegalOrCustom(ISD::FSUB, VT) || VT.isScalableVector())) + !(TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) || VT.isScalableVector())) return SDValue(); SDLoc DL(Node); |