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| author | Alexey Bataev <a.bataev@outlook.com> | 2025-10-31 13:13:58 -0700 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@outlook.com> | 2025-10-31 14:52:19 -0700 |
| commit | 4ac74fc6143b787e9e9ccd088b27ab6fe384b77c (patch) | |
| tree | 0df7190cca0ba2cea0851df7faa131467743303f /llvm | |
| parent | cf829cc11c0db7500bb4222c5c5c22b276a314d9 (diff) | |
| download | llvm-4ac74fc6143b787e9e9ccd088b27ab6fe384b77c.zip llvm-4ac74fc6143b787e9e9ccd088b27ab6fe384b77c.tar.gz llvm-4ac74fc6143b787e9e9ccd088b27ab6fe384b77c.tar.bz2 | |
[SLP][NFC]Add a test with the incorrect minbitwidth in alternate nodes, NFC
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll new file mode 100644 index 0000000..cc2e16e --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll @@ -0,0 +1,38 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-99999 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define float @test(i8 %0) { +; CHECK-LABEL: define float @test( +; CHECK-SAME: i8 [[TMP0:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> <i8 poison, i8 0>, i8 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = mul <2 x i16> [[TMP2]], <i16 2, i16 27> +; CHECK-NEXT: [[TMP4:%.*]] = lshr <2 x i16> [[TMP2]], <i16 2, i16 27> +; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> [[TMP4]], <2 x i32> <i32 0, i32 3> +; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i16> [[TMP5]], i32 0 +; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP9]] to i32 +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i16> [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP7:%.*]] = zext i16 [[TMP10]] to i32 +; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP6]], [[TMP7]] +; CHECK-NEXT: switch i32 [[TMP8]], label %[[EXIT:.*]] [ +; CHECK-NEXT: i32 0, label %[[EXIT]] +; CHECK-NEXT: i32 1, label %[[EXIT]] +; CHECK-NEXT: ] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret float 0.000000e+00 +; +entry: + %1 = sext i8 0 to i32 + %2 = lshr i32 %1, 27 + %3 = sext i8 %0 to i32 + %reass.add.epil = mul i32 %3, 2 + %4 = or i32 %reass.add.epil, %2 + switch i32 %4, label %exit [ + i32 0, label %exit + i32 1, label %exit + ] + +exit: + ret float 0.000000e+00 +} |