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| author | Philip Reames <preames@rivosinc.com> | 2023-10-30 13:21:56 -0700 |
|---|---|---|
| committer | Philip Reames <listmail@philipreames.com> | 2023-10-30 13:35:58 -0700 |
| commit | c92c86f66a72c2a07dce4976ab26446e5f272875 (patch) | |
| tree | dee0fd3f556e3ae8793e07e3addfa85504397d15 /llvm/unittests/CodeGen/MachineInstrTest.cpp | |
| parent | 1abc931d469bca47193efa4d0676776c31438f3e (diff) | |
| download | llvm-c92c86f66a72c2a07dce4976ab26446e5f272875.zip llvm-c92c86f66a72c2a07dce4976ab26446e5f272875.tar.gz llvm-c92c86f66a72c2a07dce4976ab26446e5f272875.tar.bz2 | |
[RISCV] Add test coverage for "zext nneg" [nfc]
This IR feature was recently added in #67982. An upcoming change will
improve our lowering on these examples.
Diffstat (limited to 'llvm/unittests/CodeGen/MachineInstrTest.cpp')
0 files changed, 0 insertions, 0 deletions