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| author | Stelios Ioannou <stelios.ioannou@arm.com> | 2021-05-05 11:02:33 +0100 |
|---|---|---|
| committer | Stelios Ioannou <stelios.ioannou@arm.com> | 2021-05-05 15:15:07 +0100 |
| commit | 3f4bad5eadacfc5322817eaa062dd272b52cfc54 (patch) | |
| tree | ad6079e637538fad0b1400adfb187c98c85133ed /llvm/unittests/CodeGen/MachineInstrTest.cpp | |
| parent | e994e74bca49831eb649e7c67955e9de7a1784b6 (diff) | |
| download | llvm-3f4bad5eadacfc5322817eaa062dd272b52cfc54.zip llvm-3f4bad5eadacfc5322817eaa062dd272b52cfc54.tar.gz llvm-3f4bad5eadacfc5322817eaa062dd272b52cfc54.tar.bz2 | |
[AArch64] Fix for the pre-indexed paired load/store optimization.
This patch fixes an issue where a pre-indexed store e.g.,
STR x1, [x0, #24]! with a store like STR x0, [x0, #8] are
merged into a single store: STP x1, x0, [x0, #24]!
. They shouldn’t be merged because the second store uses
x0 as both the stored value and the address and so it needs to be using the updated x0.
Therefore, it should not be folded into a STP <>pre.
Additionally a new test case is added to verify this fix.
Differential Revision: https://reviews.llvm.org/D101888
Change-Id: I26f1985ac84e970961e2cdca23c590fa6773851a
Diffstat (limited to 'llvm/unittests/CodeGen/MachineInstrTest.cpp')
0 files changed, 0 insertions, 0 deletions