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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 14:23:51 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 14:35:01 +0300 |
| commit | ede0611e792c90acbe528ca7895377195a1bbadf (patch) | |
| tree | 963793435dcbf01273820733398a051650d288eb /llvm/tools/llvm-objdump/llvm-objdump.cpp | |
| parent | eb9a694c1744f6a1608faf7daa79244bd1e45248 (diff) | |
| download | llvm-ede0611e792c90acbe528ca7895377195a1bbadf.zip llvm-ede0611e792c90acbe528ca7895377195a1bbadf.tar.gz llvm-ede0611e792c90acbe528ca7895377195a1bbadf.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=8 interleaving costs
This one required quite a bit of assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/oYWv4cTnK - for intels `Block RThroughput: =10.0`; for ryzens, `Block RThroughput: <=8.0`
So pick cost of `10`.
For store we have:
https://godbolt.org/z/33GMhrsG9 - for intels `Block RThroughput: =12.0`; for ryzens, `Block RThroughput: <=8.0`
So pick cost of `12`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111027
Diffstat (limited to 'llvm/tools/llvm-objdump/llvm-objdump.cpp')
0 files changed, 0 insertions, 0 deletions