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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 14:23:46 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 14:34:47 +0300 |
| commit | eb9a694c1744f6a1608faf7daa79244bd1e45248 (patch) | |
| tree | 06f1a770b20f0414172e8217fe4a4d78c5b1d73a /llvm/tools/llvm-objdump/llvm-objdump.cpp | |
| parent | d3bbe781ea8e6e968ad4be2eb3aa5eedb168a4a8 (diff) | |
| download | llvm-eb9a694c1744f6a1608faf7daa79244bd1e45248.zip llvm-eb9a694c1744f6a1608faf7daa79244bd1e45248.tar.gz llvm-eb9a694c1744f6a1608faf7daa79244bd1e45248.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=4 interleaving costs
This one required quite a bit of assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/Tce3osvcz - for intels `Block RThroughput: =5.0`; for ryzens, `Block RThroughput: <=4.0`
So pick cost of `5`.
For store we have:
https://godbolt.org/z/oc3arEcnE - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=4.0`
So pick cost of `6`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111026
Diffstat (limited to 'llvm/tools/llvm-objdump/llvm-objdump.cpp')
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