diff options
| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 14:23:51 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 14:35:17 +0300 |
| commit | cef0a693b6373764dc5483ef3b4523e68a812972 (patch) | |
| tree | 8860f4c414a95a42693934d0479c90c537960777 /llvm/tools/llvm-objdump/llvm-objdump.cpp | |
| parent | ede0611e792c90acbe528ca7895377195a1bbadf (diff) | |
| download | llvm-cef0a693b6373764dc5483ef3b4523e68a812972.zip llvm-cef0a693b6373764dc5483ef3b4523e68a812972.tar.gz llvm-cef0a693b6373764dc5483ef3b4523e68a812972.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs
This required huge amount of assembly surgery, but i think this is about right.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/z11crMEcj - for intels `Block RThroughput: =20.0`; for ryzens, `Block RThroughput: <=18.0`
So could pick cost of `25`.
For store we have:
https://godbolt.org/z/eqT4ze3j4 - for intels `Block RThroughput: =24.0`; for ryzens, `Block RThroughput: <=16.0`
So we could pick cost of `24`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111031
Diffstat (limited to 'llvm/tools/llvm-objdump/llvm-objdump.cpp')
0 files changed, 0 insertions, 0 deletions