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| author | Xerxes Ranby <xerxes@zafena.se> | 2010-07-22 17:28:34 +0000 |
|---|---|---|
| committer | Xerxes Ranby <xerxes@zafena.se> | 2010-07-22 17:28:34 +0000 |
| commit | ff66cd43c408185c5236a931d6ccee832ee9a3d7 (patch) | |
| tree | 256cf073939f6c848ec6bf8d798715ed5dec757e /llvm/lib | |
| parent | 7609bca74c9bcb056cdb4b0565c2e0b049797fe9 (diff) | |
| download | llvm-ff66cd43c408185c5236a931d6ccee832ee9a3d7.zip llvm-ff66cd43c408185c5236a931d6ccee832ee9a3d7.tar.gz llvm-ff66cd43c408185c5236a931d6ccee832ee9a3d7.tar.bz2 | |
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
llvm-svn: 109125
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMCodeEmitter.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrFormats.td | 2 |
2 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index d5896a3f..93f617d 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -654,6 +654,19 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { switch (Opcode) { default: llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); + case ARM::BX: + case ARM::BMOVPCRX: + case ARM::BXr9: + case ARM::BMOVPCRXr9: { + // First emit mov lr, pc + unsigned Binary = 0x01a0e00f; + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + emitWordLE(Binary); + + // and then emit the branch. + emitMiscBranchInstruction(MI); + break; + } case TargetOpcode::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index ac568e7..74cdd90 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -313,7 +313,7 @@ class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, } class ABXIx2<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> - : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, + : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin, asm, "", pattern>; // BR_JT instructions |