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| author | Nashe Mncube <nashe.mncube@arm.com> | 2024-09-24 11:26:06 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-24 11:26:06 +0100 |
| commit | d4f38f43f5402041dd36977baa459830011d6ac6 (patch) | |
| tree | 207a2985a17c6314525e80ebd5c87763f9e3e09e /llvm/lib | |
| parent | a3cf01d58587d81b184d40091a86d6b8bf92d240 (diff) | |
| download | llvm-d4f38f43f5402041dd36977baa459830011d6ac6.zip llvm-d4f38f43f5402041dd36977baa459830011d6ac6.tar.gz llvm-d4f38f43f5402041dd36977baa459830011d6ac6.tar.bz2 | |
[LLVM][ARM][CodeGen]Define branch instruction alignment for m85 and m7 (#109647)
Branch instruction alignments were not defined for cortex-m85 and
cortex-m7 which misses an optimisation opportunity. With this patch we
see performance improvements as high as 5% on some benchmarks with most
around 1%.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFeatures.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMProcessors.td | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td index 8b0ade5..dc0e86c 100644 --- a/llvm/lib/Target/ARM/ARMFeatures.td +++ b/llvm/lib/Target/ARM/ARMFeatures.td @@ -375,6 +375,9 @@ def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", "Prefer 32-bit alignment for loops">; +def FeaturePrefLoopAlign64 : SubtargetFeature<"loop-align-64", "PrefLoopLogAlignment","3", + "Prefer 64-bit alignment for loops">; + def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "4", "Model MVE instructions as a 1 beat per tick architecture">; diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td index e4e122a0..a66a2c0 100644 --- a/llvm/lib/Target/ARM/ARMProcessors.td +++ b/llvm/lib/Target/ARM/ARMProcessors.td @@ -344,6 +344,7 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, ProcM7, FeatureFPARMv8_D16, + FeaturePrefLoopAlign64, FeatureUseMIPipeliner, FeatureUseMISched]>; @@ -385,6 +386,7 @@ def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline, FeatureDSP, FeatureFPARMv8_D16, FeaturePACBTI, + FeaturePrefLoopAlign64, FeatureUseMISched, HasMVEFloatOps]>; |