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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-04-15 23:09:03 -0400 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-04-19 21:04:33 -0400 |
commit | bc7902f1483c20dd1bf78f7115b3e9c59f8e01cc (patch) | |
tree | 0916500935e75730b3c0b5a36a0c82d9416c84bd /llvm/lib | |
parent | 8591328e15940c5b36d30954fdcc065597dc0d76 (diff) | |
download | llvm-bc7902f1483c20dd1bf78f7115b3e9c59f8e01cc.zip llvm-bc7902f1483c20dd1bf78f7115b3e9c59f8e01cc.tar.gz llvm-bc7902f1483c20dd1bf78f7115b3e9c59f8e01cc.tar.bz2 |
AMDGPU: Remove unused MachineFunctionInfo fields
These were leftovers from a half-implement spill to LDS attempt.
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 5 | ||||
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 11 |
2 files changed, 1 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index cb8b1e9..8cd64e5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -875,10 +875,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, LDSAlignShift = 9; } - unsigned LDSSpillSize = - MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize(); - - ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize; + ProgInfo.LDSSize = MFI->getLDSSize(); ProgInfo.LDSBlocks = alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 1254fbe..03c2cc6 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -335,8 +335,6 @@ template <> struct MappingTraits<SIMachineFunctionInfo> { class SIMachineFunctionInfo final : public AMDGPUMachineFunction { friend class GCNTargetMachine; - Register TIDReg = AMDGPU::NoRegister; - // Registers that may be reserved for spilling purposes. These may be the same // as the input registers. Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG; @@ -382,7 +380,6 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction { std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV; private: - unsigned LDSWaveSpillSize = 0; unsigned NumUserSGPRs = 0; unsigned NumSystemSGPRs = 0; @@ -569,10 +566,6 @@ public: int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI); Optional<int> getOptionalScavengeFI() const { return ScavengeFI; } - bool hasCalculatedTID() const { return TIDReg != 0; }; - Register getTIDReg() const { return TIDReg; }; - void setTIDReg(Register Reg) { TIDReg = Reg; } - unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; } @@ -912,10 +905,6 @@ public: llvm_unreachable("unexpected dimension"); } - unsigned getLDSWaveSpillSize() const { - return LDSWaveSpillSize; - } - const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) { if (!BufferPSV) BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII); |