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| author | Phoebe Wang <phoebe.wang@intel.com> | 2024-09-24 16:46:56 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-24 16:46:56 +0800 |
| commit | 70529b24a30943d46e361d2990268499921e28a2 (patch) | |
| tree | 910e29c26fbc136ab3d3233d53c41025003d86a0 /llvm/lib | |
| parent | eabc8857e77c94a09624c12cc690753f68b87825 (diff) | |
| download | llvm-70529b24a30943d46e361d2990268499921e28a2.zip llvm-70529b24a30943d46e361d2990268499921e28a2.tar.gz llvm-70529b24a30943d46e361d2990268499921e28a2.tar.bz2 | |
[X86][APX] Do not emit {evex} prefix for memory variant (#109759)
This was mistakely changed by #109579, which doesn't match with other
EVEX decoding.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 417f31a..b9ff4a5 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2617,20 +2617,19 @@ defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp>, E multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk, string OpcodeStr, RegisterClass KRC, ValueType vvt, X86MemOperand x86memop, string Suffix = ""> { - let explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in { - let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in - def kk#Suffix : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src), - !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>, - Sched<[WriteMove]>; - def km#Suffix : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src), - !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - [(set KRC:$dst, (vvt (load addr:$src)))]>, - Sched<[WriteLoad]>, NoCD8; - def mk#Suffix : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src), - !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - [(store KRC:$src, addr:$dst)]>, - Sched<[WriteStore]>, NoCD8; - } + let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove], + explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in + def kk#Suffix : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>, + Sched<[WriteMove]>; + def km#Suffix : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set KRC:$dst, (vvt (load addr:$src)))]>, + Sched<[WriteLoad]>, NoCD8; + def mk#Suffix : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(store KRC:$src, addr:$dst)]>, + Sched<[WriteStore]>, NoCD8; } multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk, |