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authorDiana Picus <diana.picus@linaro.org>2016-12-19 14:07:56 +0000
committerDiana Picus <diana.picus@linaro.org>2016-12-19 14:07:56 +0000
commit5a724452a0ed8c7cb1bc828dbf901b8ad8b28019 (patch)
treef484d1e966de5c1a8c0e221fa33847cf65bdf69b /llvm/lib
parent36aa09fa3c45038c832ccd952a6972f89922ea16 (diff)
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[ARM] GlobalISel: Allow i8 and i16 adds
Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMLegalizerInfo.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 6680196..255ea4b 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -25,7 +25,11 @@ using namespace llvm;
ARMLegalizerInfo::ARMLegalizerInfo() {
using namespace TargetOpcode;
+
const LLT p0 = LLT::pointer(0, 32);
+
+ const LLT s8 = LLT::scalar(8);
+ const LLT s16 = LLT::scalar(16);
const LLT s32 = LLT::scalar(32);
setAction({G_FRAME_INDEX, p0}, Legal);
@@ -33,7 +37,8 @@ ARMLegalizerInfo::ARMLegalizerInfo() {
setAction({G_LOAD, s32}, Legal);
setAction({G_LOAD, 1, p0}, Legal);
- setAction({G_ADD, s32}, Legal);
+ for (auto Ty : {s8, s16, s32})
+ setAction({G_ADD, Ty}, Legal);
computeTables();
}