diff options
| author | Simon Wallis <simon.wallis2@arm.com> | 2025-10-24 16:08:14 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-24 16:08:14 +0100 |
| commit | 202bcc4fa1c7d65b29978f063f5aa82010f1d99d (patch) | |
| tree | 61f2a14e9a5cdf2ed932d9e9d78c9c5d536c9911 /llvm/lib | |
| parent | c18c3ccd0b48c4055dfdcdc2ff7514ca8ab3dfae (diff) | |
| download | llvm-202bcc4fa1c7d65b29978f063f5aa82010f1d99d.zip llvm-202bcc4fa1c7d65b29978f063f5aa82010f1d99d.tar.gz llvm-202bcc4fa1c7d65b29978f063f5aa82010f1d99d.tar.bz2 | |
[AArch64] Fix Neoverse-V2 scheduling information for STNT1 (#164780)
Fix 3 cases in the scheduler tables to match the current SWOG,
in section 3.29 SVE Store: change pipeline V to V01.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td index bdde8e3..2387f17 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td @@ -2762,11 +2762,11 @@ def : InstRW<[V2Write_11c_18L01_18V01], (instregex "^ST4[BHWD]_IMM$")>; def : InstRW<[V2Write_11c_18L01_18S_18V01], (instregex "^ST4[BHWD]$")>; // Non temporal store, scalar + imm -def : InstRW<[V2Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>; +def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STNT1[BHWD]_ZRI$")>; // Non temporal store, scalar + scalar -def : InstRW<[V2Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>; -def : InstRW<[V2Write_2c_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>; +def : InstRW<[V2Write_2c_1L01_1S_1V01], (instrs STNT1H_ZRR)>; +def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STNT1[BWD]_ZRR$")>; // Scatter non temporal store, vector + scalar 32-bit element size def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^STNT1[BHW]_ZZR_S")>; |