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author | Reid Spencer <rspencer@reidspencer.com> | 2006-12-24 00:40:59 +0000 |
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committer | Reid Spencer <rspencer@reidspencer.com> | 2006-12-24 00:40:59 +0000 |
commit | 193df25eb9e7d8887921a0010a3e6b3699efb7cc (patch) | |
tree | d9f3263590676362b23226e43dc50b2d327bf33c /llvm/lib | |
parent | 910f23f7d729ea105dd70326f3dacd10d7a8a346 (diff) | |
download | llvm-193df25eb9e7d8887921a0010a3e6b3699efb7cc.zip llvm-193df25eb9e7d8887921a0010a3e6b3699efb7cc.tar.gz llvm-193df25eb9e7d8887921a0010a3e6b3699efb7cc.tar.bz2 |
For PR1066:
Fix this by ensuring that a bitcast is inserted to do sign switching. This
is only temporarily needed as the merging of signed and unsigned is next
on the SignlessTypes plate.
llvm-svn: 32757
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Transforms/Scalar/InstructionCombining.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp index d0e74c1f..592e61d 100644 --- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp @@ -2002,8 +2002,14 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) { if (CU->getZExtValue() == SI->getType()->getPrimitiveSizeInBits()-1) { // Ok, the transformation is safe. Insert AShr. - return new ShiftInst(Instruction::AShr, SI->getOperand(0), - CU, SI->getName()); + // FIXME: Once integer types are signless, this cast should be + // removed. + Value *ShiftOp = SI->getOperand(0); + if (ShiftOp->getType() != I.getType()) + ShiftOp = InsertCastBefore(Instruction::BitCast, ShiftOp, + I.getType(), I); + return new ShiftInst(Instruction::AShr, ShiftOp, CU, + SI->getName()); } } } |