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| author | Craig Topper <craig.topper@intel.com> | 2018-04-06 16:16:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-06 16:16:48 +0000 |
| commit | f0d042619b0411bf2c211e61a3dbd3ea0ceb7c49 (patch) | |
| tree | 35a4a8e20a305f2e2126bbb85b2afc960952a995 /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | f131b60049abce734f32dc1469718aaf462687ee (diff) | |
| download | llvm-f0d042619b0411bf2c211e61a3dbd3ea0ceb7c49.zip llvm-f0d042619b0411bf2c211e61a3dbd3ea0ceb7c49.tar.gz llvm-f0d042619b0411bf2c211e61a3dbd3ea0ceb7c49.tar.bz2 | |
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
Summary:
This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.
Apparently we were inconsistent about whether the store has latency or not thus the test changes.
I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.
Reviewers: RKSimon, andreadb
Reviewed By: andreadb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45351
llvm-svn: 329416
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions