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| author | Craig Topper <craig.topper@intel.com> | 2018-04-06 16:16:46 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-06 16:16:46 +0000 |
| commit | f131b60049abce734f32dc1469718aaf462687ee (patch) | |
| tree | 2b08006c26573736c183a1dffa95d2fe7ef1f695 /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | 22d25a08ae4432ebc783e208e59a62d64d8dcb10 (diff) | |
| download | llvm-f131b60049abce734f32dc1469718aaf462687ee.zip llvm-f131b60049abce734f32dc1469718aaf462687ee.tar.gz llvm-f131b60049abce734f32dc1469718aaf462687ee.tar.bz2 | |
[X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell/Haswell/Skylake scheduler model.
Even those the address was calculated for the load, its calculated again for the store.
llvm-svn: 329415
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions