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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:15:49 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:20:11 +0300 |
| commit | a5113e9445ae024af5ba2084917c9fd115407efc (patch) | |
| tree | 2c3edbd0770a062881700d6fede9787e947d43ce /llvm/lib/Transforms/Utils/Local.cpp | |
| parent | 70c90cc5bdffe4a21e7537689ccfb958f0cb13bd (diff) | |
| download | llvm-a5113e9445ae024af5ba2084917c9fd115407efc.zip llvm-a5113e9445ae024af5ba2084917c9fd115407efc.tar.gz llvm-a5113e9445ae024af5ba2084917c9fd115407efc.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=2 VF=16 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/Y1E7qnjz8 - for intels `Block RThroughput: =9.0`; for ryzens, `Block RThroughput: <=3.5`
So pick cost of `9`.
For store we have:
https://godbolt.org/z/Y1E7qnjz8 - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `4`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110506
Diffstat (limited to 'llvm/lib/Transforms/Utils/Local.cpp')
0 files changed, 0 insertions, 0 deletions