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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:15:37 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:18:29 +0300 |
| commit | 70c90cc5bdffe4a21e7537689ccfb958f0cb13bd (patch) | |
| tree | 3b826e6b4bf3b07c00d1bd9e6c9300eda0b51c67 /llvm/lib/Transforms/Utils/Local.cpp | |
| parent | 49e532aa52593921a5c4bf67fe3f170027df6f18 (diff) | |
| download | llvm-70c90cc5bdffe4a21e7537689ccfb958f0cb13bd.zip llvm-70c90cc5bdffe4a21e7537689ccfb958f0cb13bd.tar.gz llvm-70c90cc5bdffe4a21e7537689ccfb958f0cb13bd.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=2 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/e5YE99a4P - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =2.0`
So pick cost of `6`.
For store we have:
https://godbolt.org/z/3vM4KsE1n - for intels `Block RThroughput: =3.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `3`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110505
Diffstat (limited to 'llvm/lib/Transforms/Utils/Local.cpp')
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