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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:15:58 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:21:12 +0300 |
| commit | 7424deb7433180ecb1c4722259f151c5c252be64 (patch) | |
| tree | c3291396ffb3a74224b489aecf96d7033bba4af3 /llvm/lib/Transforms/Utils/Local.cpp | |
| parent | a5113e9445ae024af5ba2084917c9fd115407efc (diff) | |
| download | llvm-7424deb7433180ecb1c4722259f151c5c252be64.zip llvm-7424deb7433180ecb1c4722259f151c5c252be64.tar.gz llvm-7424deb7433180ecb1c4722259f151c5c252be64.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=2 VF=32 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/q6GbK89br - for intels `Block RThroughput: =18.0`; for ryzens, `Block RThroughput: <=7.0`
So pick cost of `18`.
For store we have:
https://godbolt.org/z/Yzfoo5TnW - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=4.0`
So pick cost of `8`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110507
Diffstat (limited to 'llvm/lib/Transforms/Utils/Local.cpp')
0 files changed, 0 insertions, 0 deletions