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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:15:25 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 14:15:25 +0300 |
| commit | 49e532aa52593921a5c4bf67fe3f170027df6f18 (patch) | |
| tree | aa1e5f9208b89f51d873690fd855bab1b7b7d14d /llvm/lib/Transforms/Utils/Local.cpp | |
| parent | 354ded67b30d0f8115dde2f0bbed260d6f4d1b3d (diff) | |
| download | llvm-49e532aa52593921a5c4bf67fe3f170027df6f18.zip llvm-49e532aa52593921a5c4bf67fe3f170027df6f18.tar.gz llvm-49e532aa52593921a5c4bf67fe3f170027df6f18.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=2 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/1j3nf3dro - for intels `Block RThroughput: =2.0`; for ryzens, `Block RThroughput: <=1.0`
So pick cost of `2`.
For store we have:
https://godbolt.org/z/4n1zvP37j - for intels `Block RThroughput: =1.0`; for ryzens, `Block RThroughput: <=0.5`
So pick cost of `1`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110504
Diffstat (limited to 'llvm/lib/Transforms/Utils/Local.cpp')
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