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| author | sstwcw <f0gukp2nk@protonmail.com> | 2023-05-07 05:12:20 +0000 |
|---|---|---|
| committer | sstwcw <f0gukp2nk@protonmail.com> | 2023-05-07 05:13:04 +0000 |
| commit | df722b01246de56a1d3c6f5b1e7aaa881c39f642 (patch) | |
| tree | ca32f86838d21e49cc5dcff149154c8378437fee /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | e12428557a4545c0bd1b277dac2d5b56cae3c156 (diff) | |
| download | llvm-df722b01246de56a1d3c6f5b1e7aaa881c39f642.zip llvm-df722b01246de56a1d3c6f5b1e7aaa881c39f642.tar.gz llvm-df722b01246de56a1d3c6f5b1e7aaa881c39f642.tar.bz2 | |
[clang-format] Don't indent Verilog `begin` keyword on its own line
When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D149657
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions