[clang-format] Recognize Verilog edge identifiers

Previously the event expression would be misidentified as a port list.
A line break would be added after the comma.  The events can be
separated with either a comma or the `or` keyword, and a line break
would not be inserted if the `or` keyword was used.  We changed the
behavior of the comma to match the `or` keyword.

Before:
```
always @(posedge x,
         posedge y)
  x <= x;
always @(posedge x or posedge y)
  x <= x;
```

After:
```
always @(posedge x, posedge y)
  x <= x;
always @(posedge x or posedge y)
  x <= x;
```

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149561

0 files changed, 0 insertions, 0 deletions