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authorThomas Lively <tlively@google.com>2018-08-28 18:49:47 +0000
committerThomas Lively <tlively@google.com>2018-08-28 18:49:47 +0000
commitadb6da10b81d35008178826adfc678275e776c9d (patch)
tree720368cb7c8633489860e9eb12a71eb6d2253d26 /llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
parent88d99a09a2ff0ce63003bcad87250c814aa02a10 (diff)
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[WebAssembly][NFC] Document stackifier tablegen backend
Summary: Add comments to help readers avoid having to read tablegen backends to understand the code. Also remove unecessary breaks from the output. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51371 llvm-svn: 340864
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp9
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
index 0a58b9f..3dca75d 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
@@ -285,8 +285,13 @@ static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) {
static unsigned regInstructionToStackInstruction(unsigned OpCode) {
// For most opcodes, this function could have been implemented as "return
// OpCode + 1", but since table-gen alphabetically sorts them, this cannot be
- // guaranteed (see e.g. BR and BR_IF), so we table-gen a giant switch
- // statement instead.
+ // guaranteed (see e.g. BR and BR_IF). Instead we use a giant switch statement
+ // generated by a custom TableGen backend (WebAssemblyStackifierEmitter.cpp)
+ // that emits switch cases of the form
+ //
+ // case WebAssembly::RegisterInstr: return WebAssembly::StackInstr;
+ //
+ // for every pair of equivalent register and stack instructions.
switch (OpCode) {
default:
llvm_unreachable(