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| author | Nishant Patel <nishant.b.patel@intel.com> | 2025-09-01 13:56:02 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-01 13:56:02 -0700 |
| commit | fdfc751d39f81f5e0befc898d3fc1994ea655d07 (patch) | |
| tree | 7dc018be68d35a76b70a43b17705c2ec276c6fb0 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | a7224dc188bb131a4c51b33104e8090ccaad3250 (diff) | |
| download | llvm-fdfc751d39f81f5e0befc898d3fc1994ea655d07.zip llvm-fdfc751d39f81f5e0befc898d3fc1994ea655d07.tar.gz llvm-fdfc751d39f81f5e0befc898d3fc1994ea655d07.tar.bz2 | |
[MLIR][XeGPU] Distribute load_gather/store_scatter op from Wg To Sg (#154420)
This PR adds distribution patterns for scatter ops (LoadGather and
StoreScatter) with offsets.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions